Monitoring system based on APB bus protocol
By introducing a status monitoring unit, dynamic CRC check, and multi-level error warning unit into the APB bus protocol, the problems of misjudgment in anomaly detection and difficulty in fault diagnosis in the prior art are solved, realizing real-time monitoring and reliability assurance of bus transactions, and improving the system's fault location efficiency and security.
Patent Information
- Application Number
- CN202510967643.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-07
AI Technical Summary
The existing APB bus protocol has the problem of misjudging or missing detection when anomalies are detected, lacks hierarchical error handling capabilities, and cannot provide detailed context of timeout events, making fault diagnosis difficult, especially posing safety risks in high reliability scenarios.
Design a monitoring system based on the APB bus protocol, including a status monitoring unit, a dynamic CRC check engine unit, and a multi-level error warning unit. The system tracks the bus transmission stage through a five-state machine, performs dynamic CRC check and identifies abnormal data, supports 16/32-bit configurable polynomials and input/output bit reversal, achieves single-cycle byte processing, and locks the fault address.
It enables real-time monitoring and reliability assurance of bus transactions, accurately and quickly locates errors, shortens fault diagnosis time, enhances system robustness and maintainability, provides differentiated processing capabilities, and improves the overall resilience and security of the system.
Smart Images
Figure CN120909869A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a monitoring system based on an APB (Advanced Peripheral Bus) bus protocol. BACKGROUND
[0002] In a conventional APB bus protocol, the system mainly relies on the slave device to actively report the PSLVERR signal or the master device to poll the PREADY state through software to detect exceptions. However, if the slave device cannot actively send PSLVERR due to hardware failure (such as deadlock), the master device will not be able to perceive the timeout, resulting in permanent blocking of the bus. In addition, the software polling scheme relies on a fixed cycle threshold and cannot dynamically adapt to the response time of different slave devices (such as low-speed sensors and high-speed memories), which is prone to false positives or false negatives.
[0003] The existing technical solution only supports terminating transmission and interrupt reporting, lacks hierarchical error handling capability (such as fault isolation or data recording), and cannot provide detailed context (such as timeout time) of timeout events, making it difficult to troubleshoot faults. The passive response mechanism and single processing strategy pose significant safety hazards in high-reliability scenarios such as automotive electronics and industrial control. SUMMARY
[0004] The present application provides a monitoring system based on an APB bus protocol, which solves the problem of only supporting terminating transmission and interrupt reporting in the prior art, lacking hierarchical error handling capability, and being unable to provide detailed context of timeout events, making it difficult to troubleshoot faults. The monitoring system based on the APB bus protocol completely transmits the APB signal, and mainly realizes real-time monitoring and reliability assurance of bus transactions.
[0005] The present application provides a monitoring system based on an APB bus protocol, which is arranged between a master device and a slave device. The module includes a state monitoring unit, a dynamic CRC check engine unit, and a multi-level error warning unit. The state monitoring unit is configured to track the bus transmission phase through a five-state machine. The dynamic CRC check engine unit is configured to support 16 / 32-bit configurable polynomials and input / output bit inversion to obtain an updated CRC value, realizing single-cycle byte processing. The multi-level error warning unit is configured to identify abnormal data in the slave device according to the updated CRC value and lock the fault address corresponding to the abnormal data.
[0006] In one possible implementation, the bus transmission phase is tracked through a five-state machine, which includes: IDLE state→SETUP state: triggered by the APB master selection signal PSEL_M, and the PADDR / PWRITE is stable; SETUP state→ACCESS_MONITOR state: forced single-cycle transition, locking the PWDATA / PADDR signal and setting the PENABLE_M high; ACCESS_MONITOR state→CRC_CHECK state: entered when the APB slave ready signal PREADY_S is valid; ACCESS_MONITOR state→ERROR_HANDLING state: triggered when the timeout counter reaches the preset threshold value TIMEOUT_CYCLES; CRC_CHECK state→ERROR_HANDLING state: triggered when the CRC check value is not equal to 0xFFFF; ERROR_HANDLING state→IDLE state: return to the idle state after completing error handling.
[0007] In a possible implementation, the IDLE state→SETUP state strictly follows the APB4 single-cycle SETUP phase protocol; The enable signal PENABLE_M is generated at the state transition edge and remains until the ACCESS_MONITOR state ends.
[0008] In a possible implementation, the CRC_CHECK state→ERROR_HANDLING state, the trigger condition of state transition is that the count value of the timeout timer is the same as the preset value.
[0009] In a possible implementation, the 16 / 32-bit configurable polynomial and input / output bit inversion are supported, and single-cycle byte processing is implemented, including: The current input data and the 16-bit current CRC value input are input into the dynamic CRC check engine unit; The current CRC value is data-separated to obtain a high 8-bit CRC value and a low 8-bit CRC value; The high 8-bit CRC value is subjected to bitwise XOR operation with the input data to obtain an 8-bit index value; According to the 8-bit index value, the preset CRC calculation table is accessed to obtain a 16-bit polynomial value; The low 8-bit CRC value is left shifted by 8 bits, and the low bits are filled with zeros to obtain a left shift result; The left shift result is subjected to bitwise XOR operation with the 16-bit polynomial value to obtain an updated CRC value, and the updated CRC value is output after a single clock cycle.
[0010] In a possible implementation, the identifying abnormal data in the slave device according to the updated CRC value and locking a fault address corresponding to the abnormal data comprises a three-level error priority judgment logic submodule and an address latching circuit submodule; The three-level error priority judgment logic submodule is configured to perform a misplacement type judgment according to the updated CRC value. The address latching circuit submodule is configured to capture a current transmission address PADDR_M to an error_addr register in an ERROR_HANDLING state.
[0011] In a possible implementation, the three-level error comprises: The highest priority is a slave device hardware error signal PSLVERR_S. The second priority is a CRC check failure error. The lowest priority is a transmission timeout error.
[0012] In a possible implementation, the state monitoring unit is connected with the master device through PSEL_M, PADDR_M, PWRITE_M and PWDATA_M signal interfaces. The state monitoring unit is connected with the slave device through PREADY_S, PRDATA_S and PSLVERR_S signal interfaces.
[0013] In a possible implementation, when the execution instruction of the dynamic CRC check engine unit is a write operation, the bus data in the PWDATA_M interface is checked. When the execution instruction of the dynamic CRC check engine unit is a read operation, the bus data in the PRDATA_S interface is checked. The bit width is adaptively checked according to the APB data bus width.
[0014] One or more technical solutions provided in the application have at least the following technical effects or advantages: The application provides the context of error occurrence by the state monitoring unit through the five-state machine to accurately track each stage of bus transmission; the dynamic CRC check engine unit supports 16-bit or 32-bit configurable polynomials and input / output bit inversion, is compatible with various communication protocols, and can realize single-cycle byte processing, completes the CRC calculation of one byte in each clock cycle, efficiently guarantees the real-time performance and integrity of data transmission, and accurately detects data bit errors caused by noise, interference or hardware failure; the multi-level error early warning unit can not only identify abnormal data based on the CRC check result and state information, but also immediately locks the specific fault address corresponding to the abnormal data. The three work together to significantly improve the reliability of data transmission, realize accurate and rapid positioning of errors, shorten the fault diagnosis and debugging time, and enhance the maintainability of the system; meanwhile, the real-time monitoring and rapid error response capability are guaranteed, and the system is allowed to take measures before the error causes serious consequences; the multi-level early warning mechanism also supports differential processing according to the error severity and address importance, improves the overall resilience, fault tolerance capability and safety of the system; and finally, the robustness and diagnosability of the system are comprehensively enhanced. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 A monitoring system based on the APB bus protocol is provided for the embodiment of the application. Figure 2 A working flowchart of the monitoring system based on the APB bus protocol is provided for the embodiment of the application. DETAILED DESCRIPTION
[0016] The technical solutions in the embodiments of the application will be described clearly and completely in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.
[0017] A monitoring system based on the APB bus protocol is provided for the embodiment of the application. Figure 1 The module includes a state monitoring unit, a dynamic CRC check engine unit and a multi-level error early warning unit.
[0018] The state monitoring unit is used to track the bus transmission stage according to the five-state machine.
[0019] Specifically, in the state monitoring unit, the bus transmission stage is tracked according to the five-state machine, including: IDLE state→SETUP state: triggered by the APB master device selection signal PSEL_M, and PADDR / PWRITE is stable; Here, IDLE state→SETUP state, strictly follow the APB4 single-cycle SETUP phase protocol; enable signal PENABLE_M is generated at the state transition edge and kept until the end of ACCESS_MONITOR state.
[0020] SETUP state→ACCESS_MONITOR state: forced single-cycle transition, lock PWDATA / PADDR signals and set high enable signal PENABLE_M; ACCESS_MONITOR state→CRC_CHECK state: enter when APB slave ready signal PREADY_S is valid; ACCESS_MONITOR state→ERROR_HANDLING state: triggered when the timeout counter reaches the preset threshold TIMEOUT_CYCLES; CRC_CHECK state→ERROR_HANDLING state: triggered when the CRC check value is not equal to 0xFFFF; Here, CRC_CHECK state→ERROR_HANDLING state, the trigger condition of state transition is that the count value of the timeout timer is the same as the preset value.
[0021] ERROR_HANDLING state→IDLE state: return to idle state after completing error handling.
[0022] Here, the state monitoring unit is connected with the master device through PSEL_M, PADDR_M, PWRITE_M, PWDATA_M signal interfaces; and is connected with the slave device through PREADY_S, PRDATA_S, PSLVERR_S signal interfaces.
[0023] For example, IDLE state represents no transmission activity; SETUP state represents address establishment phase; ACCESS_MONITOR state represents data transmission monitoring; CRC_CHECK state represents data integrity check; ERROR_HANDLING state represents error handling. Compared with the three-state switching of APB bus access, the module adopts five-state switching, adds two states of ACCESS_MONITOR and CRC_CHECK to realize real-time monitoring of the transmission process, and improves the stability of access.
[0024] (1) DLE→SETUP; Trigger condition: slave enable signal PSEL_M is valid (APB transmission start flag); IDLE: initialization state, the system is in this state after module reset or standby state, the system is not working in this state, SETUP: start state, the system monitors the PSEL_M signal to determine whether the master device sends a read / write request to the slave device.
[0025] (2) SETUP→ACCESS_MONITOR; Trigger condition: SETUP state lasts only 1 clock cycle by default, and state transition is performed.
[0026] Explanation: According to the APB bus protocol, the shortest read / write cycle of APB is two clock cycles, and the PENABLE signal of the APB bus is pulled high at the second clock cycle. Then the bus must keep PADDR, PSEL, and PWRITE unchanged. Transmission will only last for one cycle, and if the slave device cannot respond in time, this state will also be extended. Therefore, in the ACCESS_MONITOR state, the system will monitor the handshake signal pready and start the timeout timer.
[0027] (3) ACCESS_MONITOR→ERROR_HANDLING; Trigger condition: when the timeout counter reaches the maximum value TIMEOUT_CYCLES, state transition is performed.
[0028] Explanation: When the slave device does not send the handshake signal pready_s for a long time, and the timeout counter reaches the set value, it indicates that the slave device does not respond, and the next state is entered to notify the master device and prevent bus deadlock.
[0029] (4) ACCESS_MONITOR→CRC_CHECK; Trigger condition: when pready_s is detected from the slave device, enter CRC_CHECK state.
[0030] Explanation: When the pready_s signal of the slave device is detected, it indicates that the slave device responds normally, and the system will perform CRC check on the transmitted data.
[0031] (5) CRC_CHECK→IDLE; Trigger condition: CRC check passes and transitions to IDLE state; Explanation: 8-bit parallel lookup table method is used to realize high-speed CRC calculation; (6) CRC_CHECK→ERROR_HANDLING; Trigger condition: CRC value is not equal to 0xFFFF to trigger error handling; Explanation: CRC verification fails, which may be due to data error during transmission.
[0032] (7) ERROR HANDLING → IDLE; Trigger condition: according to the different monitoring results, after processing, automatically switch to IDLE state Description: in this state, the system outputs the following three signals and automatically jumps to the IDLE state, including the err signal, the err_type[2:0] signal, and the err_addr[31:0] signal.
[0033] No error in transmission: err=0, err_type=3’b0, err_addr=32’b0.
[0034] Hardware error: err=1, err_type=3’b100, err_addr=32’b0, this error is PSLVERR_S issued from the slave device, indicating that the slave device has a hardware error, and this error has the highest priority.
[0035] A dynamic CRC check engine unit is configured to support 16 / 32-bit configurable polynomials and input / output bit inversion, and obtain an updated CRC value to realize single-cycle byte processing.
[0036] Specifically, in the dynamic CRC check engine unit, 16 / 32-bit configurable polynomials and input / output bit inversion are supported to realize single-cycle byte processing, including: (1) inputting current input data and a 16-bit current CRC value into the dynamic CRC check engine unit; (2) separating the current CRC value to obtain a high 8-bit CRC value and a low 8-bit CRC value; (3) performing bitwise XOR operation on the high 8-bit CRC value and the input data to obtain an 8-bit index value; (4) accessing a preset CRC calculation table according to the 8-bit index value to obtain a 16-bit polynomial value; (5) left shifting the low 8-bit CRC value by 8 bits, and filling the low bits with zeros to obtain a left shift result; (6) performing bitwise XOR operation on the left shift result and the 16-bit polynomial value to obtain an updated CRC value, and outputting the updated CRC value after a single clock cycle.
[0037] For example, an 8-bit parallel table lookup method is used to realize high-speed CRC calculation, the high 8 bits are XORed with data index, the low 8 bits are updated by table lookup (single-cycle completion), single-cycle byte processing is realized, REFIN / REFOUT bit inversion mode is supported, 12 kinds of international standards such as CRC-16 / CRC-32 are compatible, the check range covers the full data bit width of PWDATA / PRDATA, and the error detection rate is >99.99%.
[0038] CRC check error: err=1, err_type=3'b010, err_addr=paddr, when the crc error occurs, the current address is recorded automatically and sent to the master device, which is convenient for further debug.
[0039] Timeout error: err=1, err_type=3'b001, err_addr=32'b0, indicating that the slave device has not responded for a long time, and if the master device does not reset the slave device, the system will be locked.
[0040] Multi-level error warning unit, for identifying abnormal data in the slave device according to the updated CRC value, and locking the fault address corresponding to the abnormal data.
[0041] In the multi-level error warning unit, the abnormal data in the slave device is identified according to the updated CRC value, and the fault address corresponding to the abnormal data is locked, including a three-level error priority determination logic submodule and an address latch circuit submodule.
[0042] The three-level error priority determination logic submodule is used to determine the error type according to the updated CRC value; here, the three-level error includes: the highest priority: slave device hardware error signal PSLVERR_S; the secondary priority: CRC check failure error; the lowest priority: transmission timeout error.
[0043] The address latch circuit submodule is used to capture the current transmission address PADDR_M to the error_addr register in the ERROR_HANDLING state.
[0044] For example, see Figure 2 , which is a flowchart of the APB state monitoring unit.
[0045] (1) IDLE→SETUP; Trigger condition: master device strobe signal PSEL_M is valid (APB transmission start flag); Protocol constraint: keep PADDR / PWRITE stable (meet the requirements of APB4 address establishment stage); (2) SETUP→ACCESS_MONITOR; Forced conversion: APB4 two-stage transmission rule (SETUP state lasts only one clock cycle); Signal retention: PENABLE_M is set high, and PWDATA / PADDR signals are locked; (3) ACCESS_MONITOR state branch; Normal path: enter CRC_CHECK (complete data transmission) when PREADY_S is valid; Abnormal path: timeout counter reaches TIMEOUT_CYCLES (prevent bus deadlock); (4) CRC_CHECK verification decision; Failure path: trigger error handling (data integrity verification) when the CRC value is not equal to 0xFFFF; Success path: return to IDLE after passing the verification (comply with the APB transmission end rule); (5) ERROR_HANDLING recovery mechanism; Error classification: preferentially handle PSLVERR_S hardware errors, then CRC errors, and finally timeout errors; Address locking: record the fault address error_addr.
[0046] Hardware error (PSLVERR) > data error > transmission timeout.
[0047] The application is a monitoring system for the APB bus protocol, which is an intermediate layer between the master device and the slave device, and completely transmits the APB signal, mainly realizing real-time monitoring and reliability guarantee of the bus transaction. It includes: 1) accurately tracking the bus transmission stage through a five-state state machine, strictly following the APB protocol timing specification; 2) integrating a dynamic CRC check engine, supporting 16 / 32-bit configurable polynomials and input / output bit inversion, realizing single-cycle byte processing capability; 3) multi-level error handling mechanism, which can identify three types of exceptions of slave device error (PSLVERR), transmission timeout and data verification failure, and lock the fault address (error_addr) to assist debugging; the module is suitable for high reliability scenes such as automotive electronics and industrial control. The five-state state machine includes: IDLE state, SETUP state, ACCESS_MONITOR state, CRC_CHECK state and ERROR_HANDLING state.
[0048] The application realizes the whole life cycle monitoring of the APB bus transmission by integrating a dynamic CRC check engine and a five-state finite state machine control system, which can improve the data transmission reliability by up to 99.99% compared with the traditional scheme, and the three-level error grading mechanism (hardware error > CRC verification failure > timeout error) improves the fault location efficiency. The parametric design supports dynamic configuration of key indicators such as CRC polynomial and timeout threshold, is compatible with APB full protocol version and CCITT check standard, and provides end-to-end security for high reliability scenes such as automotive electronics and industrial control.
[0049] The various embodiments in this specification are described in a progressive manner, and the same or similar parts among the various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. The whole or part of the present application can be used in a variety of general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like.
[0050] The above examples are only used to illustrate the technical solutions of the present application, and are not limited to the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or part or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the present application.
Claims
1. A monitoring system based on APB bus protocol, arranged between a master device and a slave device, characterized in that, The application relates to a state monitoring unit, a dynamic CRC check engine unit and a multi-stage error warning unit. The state monitoring unit is used for tracking bus transmission stages through a five-state machine. The dynamic CRC check engine unit is used for supporting 16 / 32-bit configurable polynomials and input / output bit inversion, obtaining an updated CRC value and realizing single-cycle byte processing. The multi-stage error warning unit is used for identifying abnormal data in the slave device according to the updated CRC value and locking a fault address corresponding to the abnormal data. The state monitoring unit is used for tracking bus transmission stages through a five-state machine.
2. The APB bus protocol based monitoring system of claim 1, wherein, IDLE state -> SETUP state: the APB master device selects a communication signal PSEL_M to be valid, and keeps PADDR / PWRITE stable; SETUP state -> ACCESS_MONITOR state: forced single-cycle conversion, locking PWDATA / PADDR signals and setting high the enable signal PENABLE_M; ACCESS_MONITOR state -> CRC_CHECK state: when the APB slave device readiness signal PREADY_S is valid, entering; ACCESS_MONITOR state -> ERROR_HANDLING state: when the timeout counter reaches the preset threshold value TIMEOUT_CYCLES, triggering; CRC_CHECK state -> ERROR_HANDLING state: when the CRC check value is not equal to 0xFFFF, triggering; ERROR_HANDLING state -> IDLE state: returning to the idle state after completing error processing. The IDLE state -> SETUP state strictly follows the APB4 single-cycle SETUP stage protocol; 3. The APB bus protocol based monitoring system of claim 2, wherein, The enable signal PENABLE_M is generated at the state conversion edge and kept until the ACCESS_MONITOR state ends. The CRC_CHECK state -> ERROR_HANDLING state: the triggering condition of state conversion is that the count value of the timeout timer is the same as the preset value.
4. The APB bus protocol based monitoring system of claim 2, wherein, The 16 / 32-bit configurable polynomials and input / output bit inversion are supported to realize single-cycle byte processing, which comprises the following steps:
5. The APB bus protocol based monitoring system of claim 1, wherein, inputting current input data and a 16-bit current CRC value into the dynamic CRC check engine unit; performing data separation on the current CRC value to obtain a high 8-bit CRC value and a low 8-bit CRC value; performing bitwise XOR operation on the high 8-bit CRC value and the input data to obtain an 8-bit index value; accessing a preset CRC table according to the 8-bit index value to obtain a 16-bit polynomial value; left shifting the low 8-bit CRC value by 8 bits and filling the low bits with zeros to obtain a left shift result; performing bitwise XOR operation on the left shift result and the 16-bit polynomial value to obtain an updated CRC value, and outputting the updated CRC value after a single clock cycle. The multi-stage error warning unit is used for identifying abnormal data in the slave device according to the updated CRC value and locking a fault address corresponding to the abnormal data, which comprises a three-stage error priority determination logic submodule and an address latching circuit submodule.
6. The APB bus protocol based monitoring system of claim 1, wherein, The third-level error priority determination logic submodule is configured to determine the error type according to the updated CRC value. The address latch circuit submodule is configured to capture the current transmission address PADDR_M to the error_addr register in the ERROR_HANDLING state.
7. The APB bus protocol based monitoring system of claim 6, wherein, The third-level error includes: The highest priority: a slave hardware error signal PSLVERR_S; The second priority: a CRC check failure error; The lowest priority: a transmission timeout error.
8. The APB bus protocol based monitoring system of claim 1, wherein, The state monitoring unit is connected with the master device through a PSEL_M, PADDR_M, PWRITE_M and PWDATA_M signal interface. The state monitoring unit is connected with the slave device through a PREADY_S, PRDATA_S and PSLVERR_S signal interface.
9. The APB bus protocol based monitoring system of claim 8, wherein, When the execution instruction of the dynamic CRC check engine unit is a write operation, the bus data in the PWDATA_M interface is checked. When the execution instruction of the dynamic CRC check engine unit is a read operation, the bus data in the PRDATA_S interface is checked. The bit width is adaptively checked according to the APB data bus width.