Digital circuit standard unit level temperature prediction method and storage medium

Abstract

The invention discloses a digital circuit standard cell level temperature prediction method and a storage medium. The method comprises the following steps: S1, calculating equivalent thermal resistance of each standard cell in a standard cell library in each input state; s2, calculating according to each equivalent thermal resistance and power consumption information of a corresponding standard unit in a standard unit library in a corresponding input state to obtain standard unit temperature rise information so as to form a ThermalLib; s3, after the integration of the circuit is completed, and layout and wiring are carried out, an EDA power consumption analysis tool calls the ThermalLib so as to retrieve and output temperature rise data delta T of each standard unit in the circuit; and S4, based on the output temperature rise data, generating a standard unit-level heat map in combination with circuit layout information. And calculating the heat dissipation capability of the standard cell in different input states according to the actual current path and the heating transistor. According to the method, the overestimation heat dissipation capability can be avoided, and the accuracy of digital circuit temperature evaluation is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit thermal management technology, and in particular to a method for predicting temperature at the standard cell level in digital circuits and a storage medium. Background Technology

[0002] With the continuous development and technological advancement of the integrated circuit industry, the integration density of integrated circuits has been continuously increasing, a trend that has directly led to a significant increase in power density. Just as... Figure 1 As shown, with the continuous shrinking of technology nodes, both dynamic power and leakage power in digital circuits exhibit a sustained upward trend. This power increase makes thermal management issues increasingly severe. Especially in modern advanced processes, three-dimensional devices such as FinFETs and gate-all-agent transistors (GAAs) are widely used. While improving performance, they face more complex heat dissipation challenges due to their thermally limited geometry and materials. [1-3] With the adoption of these new devices, the thermal problems of digital integrated circuits have become increasingly prominent. [4-7] Severe thermal problems not only degrade system performance but can also have a profound impact on the long-term reliability of circuits. Excessively high temperatures accelerate transistor degradation, further leading to circuit malfunction. Particularly in high-power-density regions, heat accumulation can cause localized overheating, affecting circuit stability and lifespan. Furthermore, overheating can induce thermal cycling stress, causing physical damage to interconnects or other sensitive components, and in some cases, even permanent device failure.

[0003] With the ever-escalating thermal challenges in digital circuits, accurate temperature assessment is becoming increasingly important, yet also increasingly difficult. The temperature assessment process typically requires a difficult trade-off between accuracy and efficiency. Overemphasizing computational efficiency may sacrifice the accuracy of temperature predictions, leading to significant errors in identifying hotspots and locating temperature distributions, thus affecting the reliability and validity of the final results.

[0004] To address this challenge, existing circuit temperature estimation methods employ various strategies. HotSpot, for example, uses a compact thermal model to predict function block-level temperatures. This method offers relatively fast computational results. [8] Additionally, Florian Klemme et al. developed a circuit temperature analysis method that generates detailed thermal maps at the standard cell level using traditional electronic design automation (EDA) tools. This method obtains thermal information through library characterization. [9] .

[0005] HotSpot uses a compact thermal model to predict the temperature at the functional block level, which can provide thermal analysis results in a short time. Although it has a significant advantage in efficiency, due to its coarse-grained processing method, it often introduces larger errors in determining peak temperature and hotspot location. The accumulation of such errors can lead to inaccurate prediction of temperature distribution, affecting the reliability of thermal analysis results, especially in applications that require accurate identification of local hotspots and optimization of heat dissipation design, insufficient accuracy can cause problems that cannot be ignored.

[0006] B. Vermeersch et al. realized this limitation and proved through research that using a more fine-grained analysis method can significantly improve the accuracy of temperature prediction

[10] By performing thermal simulation at a finer level, the variation of temperature distribution can be captured more accurately, especially in predicting peak temperature and hotspots in critical areas. This method can effectively compensate for the shortcomings of coarse-grained models in high-precision demand scenarios, providing more reliable support for accurate thermal management and system optimization.

[0007] At the same time, the circuit temperature analysis method proposed by Florian Klemme et al. Although it can provide standard cell-level fine-grained temperature prediction, it still faces a more serious problem of computational complexity. Since the thermal reservoir in this method is realized through the characterization of the library, a large number of characterizations are needed to generate the corresponding thermal reservoir when evaluating the temperature under different process, temperature, and voltage (PTV) angles, which not only has a large amount of calculation, but also puts higher requirements on the real-time and efficiency of the design. Although this method is superior to coarse-grained methods in terms of accuracy, it still has a large limitation, affecting the feasibility in actual applications.

[0008] Therefore, how to ensure high accuracy while improving computational efficiency has become an important issue in the field of digital circuit temperature evaluation.

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[0010] [2] M. Choi et al., “Fast Prediction of Spatio-Temporal Temperature Profiles in FinFET Arrays via Numerical and Machine-Learning Approaches” in 2024 International Electron Devices Meeting (IEDM), 2024.

[0011] [3] V. A. Chhabria and S. S. Sapatnekar, “Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs,” in 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA: IEEE, Mar. 2019, pp. 235-240. doi: 10.1109 / ISQED.2019.8697786.

[0012] [4] A. J. Gabourie, C. A. Polanco, C. J. McClellan, H. Su, and M. Malakoutian, “AI-Accelerated Atoms-to-Circuits Thermal Simulation Pipeline for Integrated Circuit Design” in 2024 International Electron Devices Meeting (IEDM), 2024.

[0013] [5] M. Pedram and S. Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,” Proc. IEEE, vol. 94, no. 8, pp. 1487-1501, Aug. 2006, doi: 10.1109 / JPROC.2006.879797.

[0014] [6] L. Zhu and S. K. Lim, “INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps,” in 2023 60th ACM / IEEE Design Automation Conference (DAC), San Francisco, CA, USA: IEEE, Jul. 2023, pp. 1-4. doi: 10.1109 / DAC.56929.2023.10247666.

[0015] [7] M. M. Sabry Aly et al., “Energy-Efficient Abundant-Data Computing: The N3XT 1,000x,” Computer, vol. 48, no. 12, pp. 24-33, Dec. 2015, doi: 10.1109 / MC.2015.376.

[0016] [8] M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, and S. Velusamy, “HotSpot: a dynamic compact thermal model at the processor-architecture level,” Microelectronics Journal, vol. 34, no. 12, pp. 1153-1165, Dec. 2003, doi: 10.1016 / S0026-2692(03)00206-4.

[0017] [9] F. Klemme, S. Salamin, and H. Amrouch, “Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDATool Flows,” in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium: IEEE, Apr. 2023, pp. 1-6. doi: 10.23919 / DATE.56975.2023.10137162.

[0018]

[10] B. Vermeersch et al.,“Multiscale Thermal Impact of BSPDN:SoCHotspot Challenges and Partial Mitigation”in 2024 International Electron Devices Meeting (IEDM), 2024. SUMMARY

[0019] With the rapid development of integrated circuit technology, the integration of digital circuits in size and function is constantly improving, and the power density in the circuit is increasing sharply, leading to increasingly serious thermal management problems. In this context, how to efficiently and accurately predict the temperature at the standard cell level of digital circuits has become a key technical challenge. In the prior art, although there are some temperature evaluation methods that can solve this problem to some extent, most of the methods have obvious contradictions between accuracy and efficiency, and sacrificing accuracy to improve efficiency may lead to significant errors in temperature prediction, especially in the accurate positioning of hot spots and peak temperatures.

[0020] Therefore, the present application proposes a digital circuit standard cell level temperature prediction method, which is based on the traditional EDA power consumption analysis process and standard cell library, and creates a thermal library by defining the equivalent thermal resistance of the input state dependence of the standard cell. The average or dynamic standard cell level thermal analysis can be performed in the traditional power consumption analysis process, and the dual optimization of high accuracy and high efficiency is realized in the standard cell level temperature evaluation, providing a more reliable and accurate technical solution for thermal management in digital circuit design.

[0021] To achieve the above object, the technical scheme provided by the present application is as follows:

[0022] A digital circuit standard cell level temperature prediction method, comprising:

[0023] S1. Calculate the equivalent thermal resistance of each standard cell in the standard cell library under each input state;

[0024] S2. Calculate the standard cell temperature rise information according to each equivalent thermal resistance and the power consumption information of the corresponding standard cell in the standard cell library under the corresponding input state, to form a thermal library Thermal_Lib;

[0025] S3. After the synthesis and layout of the circuit, the thermal library Thermal_Lib is called by the EDA power consumption analysis tool to retrieve and output the temperature rise data ΔT of each standard cell in the circuit;

[0026] S4. Based on the output temperature rise data, generate a standard cell level thermal map in combination with the circuit layout information.

[0027] The further improvement of the present application is that the type of the input state includes flip combination, non-flip combination and static combination.

[0028] For the input state of static combination, the equivalent thermal resistance of the standard cell includes leakage type equivalent thermal resistance R th,leakage leakage type equivalent thermal resistance R th,leakage is obtained by SPICE simulation of the standard cell under the input state of static combination;

[0029] For the input state of flip combination, the equivalent thermal resistance of the standard cell includes short circuit type equivalent thermal resistance R th,internal and switch type equivalent thermal resistance R th,switching ; the short circuit type equivalent thermal resistance R th,internal is obtained by setting the output load capacitance of the standard cell to zero and performing SPICE simulation under the input state of flip combination; the switch type equivalent thermal resistance R th,switching is obtained by setting the output load capacitance of the standard cell to the maximum load capacitance in the standard cell library power consumption lookup table and performing SPICE simulation under the input state of flip combination;

[0030] For the input state of non-flip combination, the equivalent thermal resistance of the standard cell only includes short circuit type equivalent thermal resistance R th,internal ; the short circuit type equivalent thermal resistance R th,internal is obtained by setting the output load capacitance of the standard cell to zero and performing SPICE simulation under the input state of flip combination.

[0031] The further improvement of the present application is that the process of performing SPICE simulation of the standard cell under the predetermined input state includes the following steps:

[0032] simulating the power consumption of each transistor in the standard cell under the predetermined input state by a SPICE simulation tool;

[0033] setting a power consumption threshold, and taking the transistors in the standard cell with power consumption greater than the power consumption threshold as active transistors;

[0034] identifying the type of each active transistor, for an N-type transistor, its thermal resistance is recorded as R th,n ; for a P-type transistor, its thermal resistance is recorded as R th,p ;

[0035] calculating the equivalent thermal resistance of the standard cell under the predetermined input state, and the equivalent thermal resistance is the parallel combination of the thermal resistances of the active transistors.

[0036] The further improvement of the present application is that in step S2:

[0037] for the input state of static combination, the leakage type equivalent thermal resistance Rth,leakage multiplying the leakage power consumption of the standard cell in the standard cell library, to obtain standard cell temperature rise information of the standard cell under the input state, and replacing the corresponding leakage power consumption in the standard cell library with the standard cell temperature rise information;

[0038] For the input state of the flip-flop combination, the short-circuit equivalent thermal resistance R th,internal multiplying the short-circuit power consumption of the standard cell in the standard cell library to obtain short-circuit temperature rise information, multiplying the switch equivalent thermal resistance R th,switching obtaining switch temperature rise information by multiplying the switch power consumption, and combining the short-circuit temperature rise information and the switch temperature rise information into total temperature rise under the flip-flop combination, and replacing the short-circuit power consumption lookup table under the input state of the flip-flop combination in the standard cell library;

[0039] For the input state of the non-flip-flop combination, the short-circuit equivalent thermal resistance R th,internal multiplying the short-circuit power consumption of the standard cell in the standard cell library to obtain short-circuit temperature rise information, and replacing the short-circuit power consumption lookup table under the input state of the non-flip-flop combination in the standard cell library.

[0040] A further improvement of the present application is that the leakage power consumption and the short-circuit power consumption are obtained by table lookup in the standard cell library.

[0041] A further improvement of the present application is that in step S3, for the circuit netlist satisfying the timing and power consumption constraints, the average power consumption analysis or the time-varying power consumption analysis is performed on the netlist by the power consumption analysis tool in the EDA tool to obtain average temperature rise data or time-varying temperature rise data of each standard cell.

[0042] A further improvement of the present application is that for the time-varying temperature rise data, the modified time-varying temperature rise data is obtained after convolution with the thermal response function.

[0043] A further improvement of the present application is that step S3 further includes thermal coupling correction.

[0044] A further improvement of the present application is that step S4 includes: parsing the standard cell layout file and the processed temperature rise data, and generating an average or dynamic temperature distribution heat map based on the physical coordinates and area information of the standard cell, to reflect the temperature distribution characteristics of the circuit in the spatial dimension.

[0045] The present application also provides a storage medium, characterized in that the storage medium stores a plurality of instructions; the instructions are suitable for being loaded and executed by a processor to perform the method according to any one of claims 1 to 9.

[0046] The beneficial technical effects of the present application include:

[0047] 1) Higher accuracy: The thermal dissipation capability of standard cells under different input states is calculated according to the actual current path and the heating transistor. This method can avoid overestimating the thermal dissipation capability and improve the accuracy of digital circuit temperature evaluation. The consideration of temperature data during the heating / cooling process and the calculation of the thermal coupling of standard cells improve the accuracy of digital circuit temperature evaluation in time and space, respectively.

[0048] 2) Finer granularity: Fine-grained temperature evaluation is implemented at the standard cell level, effectively determining the hot spot location of the standard cell, thereby obtaining more accurate results.

[0049] 3) Fully compatible with existing EDA processes and tools: By multiplying the power consumption information in the standard cell library with the equivalent thermal resistance value related to the input state, it is replaced by a thermal library containing standard cell temperature rise (ΔT) information, which can be directly used by existing EDA processes, power consumption analysis tools, etc.

[0050] 4) Easy migration to thermal evaluation of other standard cell libraries: In addition to the step of performing batch SPICE simulation to determine the actual heating transistor, the process of generating a thermal library of a standard cell library under new process, voltage and temperature conditions only needs to call the above SPICE simulation results, without the need for a complex characterization process. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 A schematic diagram showing that both dynamic power consumption and leakage power consumption continue to rise with technology nodes in digital circuits;

[0052] Figure 2 A schematic diagram showing the varying paths of short-circuit current and switching current for an XNOR gate under different input states;

[0053] Figure 3 A detailed framework of the method proposed in the present application;

[0054] Figure 4 A schematic diagram of a standard cell in Thermal_Lib;

[0055] Figure 5 A dynamic temperature processing;

[0056] Figure 6 A relationship between the degree of thermal coupling and the distance of the standard cell;

[0057] Figure 7 A riscv circuit layout diagram for verifying the present application;

[0058] Figure 8 A mean temperature distribution heat map; (a) uses the refined thermal analysis method proposed in the present application, and (b) uses the traditional parallel thermal resistance model (control group);

[0059] Figure 9 (a) is the number of standard cells in the thermal coupling range; (b) is the temperature rise value of the standard cell caused by thermal coupling. DETAILED DESCRIPTION

[0060] The present application is described below by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the specification. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0061] The present application provides a digital circuit standard cell level temperature prediction method and storage medium. The method simulates the power consumption of all transistors in the standard cell under different input states, determines the equivalent thermal resistance related to the input state based on the simulation results, and generates a thermal library combined with the power consumption information in the standard cell library. Unlike traditional complex library characterization methods, the technical solution of the present application can achieve fine prediction of the standard cell level temperature without complex library characterization.

[0062] The working state of the transistor in the standard cell will change with different input conditions. For example, when different input states cause the output port of the standard cell to change levels, the short-circuit current path may change. Similarly, the current (switching current) path of the standard cell charging and discharging the load capacitor (C load ) may also change. Figure 2 The above problem is illustrated by taking an XNOR gate as an example: when the input end of the standard cell is as shown in (a) and (b), the short-circuit current flows through transistors M5, M6, M7, M8 (a) and M0, M2, M3 (b), respectively, and the switching current flows through transistors M5, M6 (a) and M4 (b), respectively, to charge C Figure 2 . Figure 2 Figure 2 Figure 2 Figure 2 load Therefore, the short-circuit power consumption caused by the short-circuit current, the switching power consumption caused by charging and discharging the load capacitor, and the number of transistors generating these power consumptions all change with the input state.

[0063] ​​​​Furthermore, different input states in static condition affect the three-terminal voltage of the transistors, which in turn causes the leakage power of the transistors to change. Therefore, the short-circuit power, switching power or leakage power does not distribute evenly among all the transistors in a standard cell. Due to thermal isolation among the transistors, only the transistors that generate power contribute to heat dissipation. The thermal resistance of a standard cell is closely related to the input states - different input states affect the number of transistors in a standard cell that generate power, which in turn affects the heat dissipation capability of the standard cell, i.e. the thermal resistance. If all the transistors are assumed to generate heat, the self-heating effect of a standard cell is underestimated.

[0064] A standard cell library contains power consumption information of the cells for power analysis in EDA flow. A power analysis tool retrieves the leakage power and short-circuit power of a standard cell in different input states, and calculates the switching power according to the toggle rate of the circuit. Specifically, the standard cell library contains the following power consumption information: static power of a standard cell when its input signals do not toggle (a lookup value related to input states); short-circuit power when input signals toggle and cause output to toggle (a 7x7 lookup table depending on input states, transition time and C load of the standard cell); short-circuit power when input signals toggle but do not cause output to toggle (a 7x1 lookup table depending on input states and transition time). Finally, the tool in the prior art reports the three parts of power and the total power. In addition, the temperature rise ΔT of a standard cell can be calculated by formula (1):

[0065] ΔT = Power * R th (1)

[0066] where Power is the power consumption, and R th is the overall thermal resistance of a standard cell in the prior art.

[0067] Based on the above background, the present embodiment multiplies the power consumption information of each input state in the original standard cell library (denoted as Power_Lib) with the equivalent thermal resistance of the corresponding standard cell, to obtain the temperature rise ΔT of the standard cell in the state. Then ΔT replaces the corresponding power consumption information in Power_Lib to obtain Thermal_Lib. In this way, Thermal_Lib contains the temperature rise information of a standard cell in each input state, and can be retrieved and analyzed by the existing power analysis software.

[0068] Figure 3 The framework of the method of the present application is shown. The colored boxes indicate the parts built on the basis of the conventional EDA flow. By using a SPICE simulation tool, the power consumption of each transistor in a standard cell in different input states is simulated to determine the equivalent thermal resistance R th,equIt is worth noting that the equivalent thermal resistance R th,equ The Thermal_Lib generation process for Power_Lib under different PVT (frequency, voltage and temperature). This is because, although using different libraries, the function of the standard cell remains unchanged, and the number of transistors involved in heat dissipation does not change. By multiplying the equivalent thermal resistance with the power consumption under the corresponding input state in Power_Lib, Thermal_Lib can be obtained.

[0069] In the circuit design process, Power_Lib is used for synthesis, layout and routing. When temperature analysis is performed, the EDA power analysis tool will use the Thermal_Lib proposed in the present application. Unlike traditional methods, the report file reports ΔT rather than power consumption. In addition, by combining circuit layout information, a heat map at the standard cell level can also be generated, providing a more intuitive heat distribution. The method of obtaining equivalent thermal resistance and generating Thermal_Lib will be described in detail below.

[0070] Method for obtaining equivalent thermal resistance of standard cell under different input states:

[0071] Generate SPICE simulation files for all input states of all standard cells and perform simulation. Standard cell power consumption can be divided into three categories: short-circuit power consumption, switching power consumption and leakage power consumption, corresponding to three different equivalent thermal resistances R th,equ : internal equivalent thermal resistance R th,internal , switching equivalent thermal resistance R th,switching and leakage equivalent thermal resistance R th,leakage . The input states of the standard cell are also divided into three categories:

[0072] Flip combination: input signal flips and can make the output state flip;

[0073] Non-flip combination: input signal flips but cannot make the output state flip;

[0074] Static combination: input signal does not flip.

[0075] Among them: internal equivalent thermal resistance R th,internal , switching equivalent thermal resistance R th,switching need to be determined under the flip input of the standard cell, and leakage type equivalent thermal resistance R th,leakageThis needs to be determined under static input conditions. For each input state toggling combination that causes the output to flip, when simulating short-circuit power consumption, the output load capacitance of the standard cell is set to zero to ensure that only short-circuit current exists. When simulating switching power consumption, the maximum load capacitance from the standard cell library power lookup table is applied to the standard cell, making the switching power consumption during capacitor charging and discharging much higher than the short-circuit power. For each input state toggling combination that does not cause the output to flip, when simulating short-circuit power consumption, the output load capacitance of the standard cell is set to zero to ensure that only short-circuit current exists. For each static input state combination where the output does not flip, leakage power consumption can be simulated. By performing SPICE simulation, three power consumption values ​​for all transistors in the standard cell under different input states are obtained.

[0076] Referring to the algorithm flow shown in Table-1 (Algorithm 1), in this embodiment, the process of performing SPICE simulation on the standard unit under a predetermined input state includes the following steps:

[0077] (1) Selecting a power threshold: First, set a reasonable power threshold to distinguish between active and inactive transistors. All transistors with power consumption exceeding this threshold will be identified as active transistors and responsible for heat dissipation. The power consumption contribution of these active transistors will be considered in the thermal analysis.

[0078] (2) Identify active transistors: Based on each power consumption file (short-circuit power consumption, switching power consumption and leakage power consumption), the script will traverse the transistors in each input state and determine whether they are active transistors based on whether their power consumption exceeds the threshold.

[0079] (3) Classify transistor types: The identified active transistors are classified by type, usually into N-type transistors and P-type transistors. This helps to consider the thermal resistance contribution of different types of transistors when calculating the equivalent thermal resistance.

[0080] (4) Calculate the equivalent thermal resistance: Based on the thermal resistance of the active transistor, calculate the equivalent thermal resistance under this condition. For an N-type transistor, the thermal resistance is denoted as R. th,n For a P-type transistor, the thermal resistance is denoted as R. th,p By treating the thermal resistances of these transistors as a parallel combination, the equivalent thermal resistance in this state is finally obtained.

[0081] Algorithm 1Flow of obtaining Rth,eff

[0082]

[0083] The following is based on Figure 4 Using the AND gate shown as an example, this section describes the process of obtaining the hot library Thermal_Lib. Figure 4 This explains how to obtain R th,equHow to generate Thermal_Lib from Power_Lib. Leakage power in Power_Lib is a look-up value, which only depends on the input state. By multiplying the leakage power in each static state with the corresponding R th,leakage and the state, the transition time and C load in the Power_Lib, which depends on the state and the transition time. load The total ΔT caused by the dynamic power is calculated from the formula In this embodiment, the ΔT caused by the two kinds of power is combined into one look-up table, which represents the total ΔT caused by the dynamic power. In the non-flip combinations where the input port flip does not trigger the output port flip, only the short-circuit power exists. This part of the short-circuit power is provided by a 7x1 look-up table in the Power_Lib, which depends on the state and the transition time.

[0084] Figure 4 Fig. 4 shows a schematic diagram of a standard cell in the Thermal_Lib, which indicates how the Thermal_Lib represents the thermal information, including the ΔT from the leakage power, the short-circuit power and the switching power. The red text represents the thermal information replacing the original power information.

[0085] The use of the Thermal_Lib and the processing of the thermal data:

[0086] For a digital circuit that has been designed, after the circuit synthesis and layout routing by calling the Power_Lib, the circuit netlist that meets the timing and power constraints can be generated. In the traditional EDA flow, the Thermal_Lib is called by the power analysis tool to perform the average power analysis or the time-varying power analysis on the netlist. Specifically, the power analysis tool retrieves the ΔT from the Thermal_Lib based on the input state, and outputs the average temperature rise data ΔT or the time-varying temperature rise data ΔT data according to the user's requirements.

[0087] In the average mode, the power analysis tool generates the average temperature rise data ΔT report file of each standard cell within the simulation time; in the time-varying mode, the time-varying temperature rise data ΔT waveform file of each standard cell is output. The above files provide the temperature information of the standard cell in different working states. In order to improve the accuracy of the temperature data in the time and space dimensions, the following temperature data processing steps are further performed:

[0088] (1) Modeling of the temperature rise and fall process of the dynamic temperature

[0089] In the time-varying mode, the dynamic temperature data output by the power consumption analysis tool is the product of power consumption and equivalent thermal resistance at each time point, but it does not consider the temperature transient response caused by thermal inertia. Since the temperature change of the standard cell lags behind the power consumption change (determined by the thermal time constant), convolution operation needs to be performed on the dynamic power consumption data and the thermal response function to accurately represent the temperature rise and fall process. Figure 5 By comparing the original dynamic temperature data, the thermal response function and the temperature curve after convolution correction, the accuracy improvement of the method in the time dimension is verified.

[0090] (2) To improve the spatial accuracy of temperature distribution, the thermal crosstalk effect of adjacent standard cells needs to be considered. Based on the finite element simulation results in the literature

[11] , the effective action range of thermal coupling and the distance-coupling coefficient relationship are defined (see Figure 6 ). If standard cell B is within the thermal coupling range of standard cell A, the coupling coefficient is determined according to the distance between them, and the temperature rise of B is proportionally added to the temperature rise of A to quantify the thermal coupling effect.

[0091]

[11] Haifeng Chen et al., “Self-Adapting Power Density Sampling for On-Chip Thermal Prediction with Transistor Level Granularity,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 14, no. 8, pp. 1413-1421, Aug. 2024, doi: 10.1109 / TCPMT.2024.3436595.

[0092] To visually present the temperature characteristics of the circuit, the standard cell layout file and the processed temperature rise data are analyzed by script, and based on the physical coordinates and area information of the cells, average or dynamic temperature distribution heat maps are generated. This heat map can clearly reflect the temperature distribution characteristics of the circuit in the spatial dimension.

[0093] The core of this technical solution is to establish a thermal library by proposing a standard cell state-dependent equivalent thermal resistance, and then use traditional EDA processes for thermal analysis and prediction of digital circuits. This solution combines power consumption data with thermal resistance to provide an accurate temperature prediction framework, which helps to optimize circuit thermal management and improve circuit reliability. Other alternative solutions include using libraries of different technology nodes or different PDKs to establish thermal libraries, using different power consumption analysis tools to use thermal libraries, and any form of post-processing of thermal data output by power consumption analysis tools.

[0094] To verify the effectiveness of the method, a RISC-V architecture is designed and implemented using the ASAP7 standard cell library. Figure 7 The physical layout of the architecture is shown. If all transistors in the standard cell are assumed to participate in heat dissipation, it will lead to overestimation of the cooling capacity of the cell (underestimation of the equivalent thermal resistance). Therefore, the parallel value of the thermal resistance of all transistors in the standard cell is taken as the equivalent thermal resistance (control group model) in this embodiment, and compared with the method of the application.

[0095] As Figure 8 (b) shows the temperature distribution under the control group model, which is systematically underestimated due to not considering the non-uniform heat dissipation characteristics of transistors. After using the method of the application ( Figure 8 a), by accurately modeling the thermal coupling effect at the transistor level, the ΔT of each standard cell increases to varying degrees. This result confirms the limitations of the traditional parallel thermal resistance model in heat dissipation evaluation, and the significant improvement of the application in thermal analysis accuracy.

[0096] To quantify the impact of thermal coupling on temperature evaluation, Figure 9 (a) shows the number distribution of thermal coupling of adjacent cells on each standard cell. In this embodiment, a single standard cell is subjected to the thermal coupling effect of up to 7 adjacent cells. Figure 9 (b) shows the temperature correction results considering the thermal coupling effect; experimental data show that the thermal coupling effect leads to a maximum temperature increase of 3K in the standard cell.

[0097] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be included in the claims of the application.

Claims

1. A digital circuit standard cell level temperature prediction method, characterized by, The method comprises the following steps: S1. Calculate the equivalent thermal resistance of each standard cell in the standard cell library under each input state; S2. Calculate the standard cell temperature rise information according to the equivalent thermal resistance and the power consumption information of the corresponding standard cell in the standard cell library under the corresponding input state, to form a thermal library Thermal_Lib; S3. After the synthesis and layout of the circuit are completed, the thermal library Thermal_Lib is called by an EDA power consumption analysis tool to retrieve and output the temperature rise data ΔT of each standard cell in the circuit; S4. Based on the output temperature rise data, the standard cell level thermal map is generated in combination with the circuit layout information.

2. The method of claim 1, wherein the temperature prediction is based on a temperature of a digital circuit standard cell library. The types of input states include flip combinations, non-flip combinations, and static combinations. For the input state of static combination, the equivalent thermal resistance of the standard cell includes a leakage-type equivalent thermal resistance R th,leakage ; the leakage-type equivalent thermal resistance R th,leakage is obtained by means of SPICE simulation of the standard cell in the input state of static combination; For the input state of the flip-flop combination, the equivalent thermal resistance of the standard cell includes a short-circuit equivalent thermal resistance R th,internal and a switching equivalent thermal resistance R th,switching ; the short-circuit equivalent thermal resistance R th,internal is obtained by setting the output load capacitance of the standard cell to zero and performing SPICE simulation under the input state of the flip-flop combination; the switching equivalent thermal resistance R th,switching is obtained by setting the output load capacitance of the standard cell to the maximum load capacitance in the standard cell library power consumption lookup table and performing SPICE simulation under the input state of the flip-flop combination; For input states of non-flipped combinations, the equivalent thermal resistance of the standard cell includes a short-circuit equivalent thermal resistance R th,internal ; a short-circuit equivalent thermal resistance R th,internal is obtained by setting the output load capacitance of the standard cell to zero and performing a SPICE simulation at input states of flipped combinations.

3. The method for predicting temperature at the standard unit level of a digital circuit according to claim 2, characterized in that, The process of SPICE simulation of the standard cell under a predetermined input state comprises the following steps: Through a SPICE simulation tool, the power consumption of each transistor in the standard cell under a predetermined input state is simulated; A power consumption threshold is set, and the transistors in the standard cell with power consumption greater than the power consumption threshold are regarded as active transistors; The type of each active transistor is identified, with the thermal resistance noted as R th,n for an N-type transistor, and R th,p for a P-type transistor. The equivalent thermal resistance of the standard cell under the predetermined input state is calculated, and the equivalent thermal resistance is the parallel combination of the thermal resistances of the active transistors.

4. The method of claim 2, wherein the temperature prediction is based on a temperature of a digital circuit standard cell library. In step S2: For the input state of static combination, the leakage equivalent thermal resistance R th,leakage The leakage power consumption of the standard cell in the standard cell library is multiplied by the standard cell temperature rise information of the standard cell under the input state, and the standard cell temperature rise information is used to replace the corresponding leakage power consumption in the standard cell library. For the input state of the flip-flop combination, the short-circuit equivalent thermal resistance R th,internal The short-circuit temperature rise information is obtained by multiplying the short-circuit power consumption of the standard cell in the standard cell library, the switch equivalent thermal resistance R th,switchin The switch temperature rise information is obtained by multiplying the switch power consumption; the total temperature rise under the flip-flop combination is obtained by combining the short-circuit temperature rise information and the switch temperature rise information, and the short-circuit power consumption lookup table of the corresponding flip-flop combination input state in the standard cell library is replaced; For non-flip combination input states, short-circuit equivalent thermal resistance R th,internal The short-circuit temperature rise information is multiplied by the short-circuit power consumption of the standard cell in the standard cell library to replace the short-circuit power consumption lookup table of the corresponding non-flip combination input state in the standard cell library.

5. The method of claim 4, wherein the temperature prediction is based on a temperature of a digital circuit standard cell library. 5 The leakage power consumption and short-circuit power consumption are obtained by table lookup in the standard cell library.

6. The method of claim 1, wherein, In step S3, for the circuit netlist meeting the timing and power consumption constraints, the thermal library Thermal_Lib is called by the power consumption analysis tool in the EDA tool to perform average power consumption analysis or time-varying power consumption analysis on the netlist, to obtain the average temperature rise data or time-varying temperature rise data of each standard cell.

7. The method of claim 6, wherein the temperature prediction is based on a temperature of a digital circuit standard cell library. For time-varying temperature rise data, the modified time-varying temperature rise data is obtained after convolution with a thermal response function.

8. The method of claim 6, wherein the temperature prediction is based on a temperature of a digital circuit standard cell library. Step S3 also includes thermal coupling correction.

9. The method of claim 1, wherein the method is a digital circuit standard cell level temperature prediction method. Step S4 includes: parsing the standard cell layout file and the processed temperature rise data, generating an average or dynamic temperature distribution thermal map based on the physical coordinates and area information of the standard cell, to reflect the temperature distribution characteristics of the circuit in the spatial dimension.

10. A storage medium, characterized by The memory stores a plurality of instructions; the instructions are suitable for being loaded and executed by the processor to perform the method according to any one of claims 1 to 9.

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