Modularized superconducting quantum chip and processing method thereof

Abstract

The invention discloses a modular superconducting quantum chip and a method thereof, and belongs to the technical field of quantum computing, the modular superconducting quantum chip comprises at least two superconducting quantum network modules, and each superconducting quantum network module comprises a superconducting quantum bit configured with a quantum bit reading cavity and a control line; the floating capacitance adjustable coupler is provided with a floating capacitance reading cavity and a Z line; the coplanar waveguide impedance matcher is a coplanar waveguide cavity with a half wavelength, one end of the coplanar waveguide impedance matcher is in capacitive coupling with the floating capacitance adjustable coupler, and the other end of the coplanar waveguide impedance matcher is connected to a superconducting coaxial cable; the superconductive coaxial cable is connected with two adjacent quantum network modules, and superconductive quantum bits in different modules are indirectly coupled through the floating ground capacitance adjustable coupler; the quantum bit interconnection structure has the beneficial effects that by using the design of the floating ground capacitance adjustable coupler and the coplanar waveguide impedance matcher, the coupling loss between quantum bits is effectively reduced, so that the quantum bits on different chips can be efficiently interconnected with low loss.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and more particularly, to a modular superconducting quantum chip and a processing method thereof. BACKGROUND

[0002] In recent years, the research and development of quantum computing has entered an unprecedented stage of rapid development. Quantum computing is based on the principles of quantum mechanics and uses quantum bits (qubits) for information processing. Compared with traditional computers, quantum computing can exhibit extremely powerful computing power when solving certain problems. With the continuous exploration of quantum computing technology, quantum computing models based on different physical systems have emerged, including trapped ions, single atoms, diamond color centers, semiconductor quantum dots, quantum optics chips, and superconducting quantum circuit systems. These different systems have their own advantages and disadvantages, but superconducting quantum circuits have gradually become the main development direction in the field of quantum computing due to their advantages in process maturity, scalability, and operation speed.

[0003] The superconducting quantum circuit system is based on the manufacturing process of the traditional semiconductor industry and combines the characteristics of superconducting materials to achieve very fast and low-energy quantum bit operations. Superconducting quantum bits have high fidelity and long coherence time, and operate at high speed, which makes them have great potential in the practical application of quantum computing. In recent years, some top international research teams have released a number of superconducting quantum chips with a large scale. In 2019, Google released a 53-bit superconducting quantum chip that successfully demonstrated quantum superiority. In 2021, a team from the University of Science and Technology of China released a 66-bit superconducting quantum chip (Zuchongzhi 1.0), in 2022, a team from Zhejiang University released a 110-bit superconducting quantum chip (Mogang No. 1, Tianmu No. 1), and in 2023, IBM released a 433-bit superconducting quantum chip. These achievements mark the great progress of the superconducting quantum circuit system in the field of quantum computing.

[0004] Despite this, as the number of quantum bits continues to increase, the design and manufacture of superconducting quantum chips face a series of new challenges. Especially when the number of quantum bits expands to dozens or even hundreds, the physical space of the superconducting chip has become extremely crowded. The arrangement of superconducting quantum bits, couplers, control lines, and other devices inside the chip is very dense, causing serious line crosstalk, signal interference, and electromagnetic noise, which affects the accuracy and stability of quantum computing. In addition, as the number of quantum bits increases, the manufacturing and packaging process of the chip becomes increasingly complex, requiring higher technical levels to ensure the performance and reliability of the chip in a low-temperature environment.

[0005] Currently, most superconducting quantum chips rely on the design concept of two-dimensional integrated circuits, but this design faces a serious scalability bottleneck as the number of qubits increases. The mutual interference between circuits, the limitation of information transmission speed, and the high precision requirement of qubit operation make the existing superconducting quantum chips face many challenges. Under the existing system, as the number of qubits increases, the power consumption of the chip, the reliability of signal transmission, and the interconnection coupling between qubits may be severely affected. SUMMARY

[0006] In order to overcome the shortcomings of the prior art, a modular superconducting quantum chip and a method thereof effectively reduce the coupling loss between qubits by using the design of a floating ground capacitance adjustable coupler and a coplanar waveguide impedance matcher, and improve the transmission efficiency of signals through structural optimization, so that qubits on different chips can be interconnected efficiently and with low loss. In addition, the optimization of packaging and manufacturing processes makes the superconducting quantum chip suitable for large-scale integration and long-term stable operation, with high experimental reliability.

[0007] The technical scheme adopted by the application to solve the technical problems is: a modular superconducting quantum chip, improved in that it comprises: at least two superconducting quantum network modules, each of which comprises: a superconducting qubit configured with a qubit reading cavity for reading the state of the qubit, a control line for manipulating the superconducting qubit, the control line comprising an XY line and a Z line; a floating ground capacitance adjustable coupler connected to the superconducting qubit through capacitive coupling, the floating ground capacitance adjustable coupler further being configured with a floating ground capacitance reading cavity and a Z line for manipulating the floating ground capacitance adjustable coupler; a coplanar waveguide impedance matcher, which is a coplanar waveguide cavity with a wavelength of one-half, one end of which is capacitively coupled to the floating ground capacitance adjustable coupler, and the other end is connected to a superconducting coaxial cable; the superconducting coaxial cable connects two adjacent quantum network modules, and through the indirect coupling effect of the floating ground capacitance adjustable coupler, the superconducting qubits in different modules are interconnected to build a modular quantum network.

[0008] In the above structure, the floating ground capacitance adjustable coupler is arranged in a floating ground form, and its two ends are respectively connected to the superconducting qubit and the impedance matcher.

[0009] In the above structure, the effective coupling strength between the superconducting qubit and the floating ground capacitance adjustable coupler, the coplanar waveguide impedance matcher, and the superconducting coaxial cable is: ; ; ;

[0010] wherein (i,j=1,3,4) are the equivalent capacitance matrix of the floating-capacitor tunable coupler, , are the frequencies of the superconducting quantum bit and the floating-capacitor tunable coupler, respectively; is the frequency corresponding to the standing wave mode of the selected superconducting coaxial cable.

[0011] In the above structure, the eigenfrequency of the coplanar waveguide impedance matcher is consistent with the standing wave mode frequency of the superconducting coaxial cable, and the coupling end points of the coplanar waveguide impedance matcher and the superconducting coaxial cable are located at the voltage peaks to minimize current loss.

[0012] In the above structure, the impedance matcher is connected to the external superconducting coaxial cable through wire bonding.

[0013] The application also provides a processing method of a modular superconducting quantum chip, which is improved in that it comprises the following steps: S10: selecting a sapphire substrate as the substrate of the chip; S20: depositing a superconducting material on the sapphire substrate to form the circuit structure of the superconducting quantum bit, the floating-capacitor tunable coupler and the coplanar waveguide impedance matcher; S30: connecting the superconducting circuit using a superconducting quantum chip processing technology, wherein the superconducting quantum chip processing technology comprises an air bridge technology; S40: packaging the superconducting quantum chip in a sample box with a superconducting coaxial cable welded thereon, and connecting each control line on the superconducting quantum chip to the external superconducting coaxial cable through wire bonding; S50: performing low-temperature testing on the packaged superconducting quantum chip to verify the coupling efficiency and stability of the chip in a low-temperature environment.

[0014] Further, the specific steps of step S40 are as follows: S401: connecting the processed superconducting quantum chip to the connection end of the external superconducting coaxial cable through wire bonding technology; S402: bonding with suitable conductive materials to ensure good connection of the control lines and power lines of the superconducting quantum chip to the external circuit; S403: packaging the connection end of the external coaxial cable to ensure that the chip does not interfere with the external connection.

[0015] Further, in step S20, the superconducting material deposited on the surface of the substrate is an aluminum superconducting material.

[0016] Further, the specific steps of the step S50 are: S501: Put the packaged superconducting quantum chip into a low-temperature environment for testing at a temperature close to absolute zero; S502: Measure the coupling strength between the superconducting quantum bit and the floating ground capacitor adjustable coupler, and the coupling strength between the superconducting coaxial cable standing wave mode and the superconducting quantum bit; S503: Verify whether the designed quantum chip meets the stability, low energy consumption and high coupling efficiency of the quantum bit according to the experimental results.

[0017] The beneficial effects of the present application are: through the use of the design of the floating ground capacitor adjustable coupler and the coplanar waveguide impedance matcher, the coupling loss between the quantum bits is effectively reduced, and the transmission efficiency of the signal is improved through structure optimization, so that the quantum bits on different chips can be interconnected efficiently and with low loss. In addition, the optimization of packaging and manufacturing process makes the superconducting quantum chip suitable for large-scale integration and long-term stable operation, and has high experimental reliability. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural principle diagram of a modular superconducting quantum chip of the present application; Figure 2 is a flowchart of a processing method of a modular superconducting quantum chip of the present application; Figure 3 is an equivalent circuit model diagram of a modular superconducting quantum chip of the present application; Figure 4 is a connection mode diagram of a modular superconducting quantum chip of the present application through a superconducting coaxial cable. DETAILED DESCRIPTION

[0019] The present application will be further described below in combination with the drawings and examples.

[0020] The concept, specific structure and technical effects of the present application will be described clearly and completely in combination with the embodiments and drawings, so as to fully understand the purpose, features and effects of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In addition, all the coupling / connection relations involved in the patent do not mean that the components are directly connected, but that a better coupling structure can be composed by adding or reducing coupling accessories according to the specific implementation situation. The technical features in the present application can be combined interactively without conflict.

[0021] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0022] In addition, if the embodiments of the present application involve descriptions such as "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. Secondly, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0023] Referring to Figure 1 As shown in the drawings, the present application provides a modular superconducting quantum chip, comprising: At least two superconducting quantum network modules, each of the quantum network modules comprising: A superconducting quantum bit configured with a quantum bit reading cavity for reading the state of the quantum bit, a control line for manipulating the superconducting quantum bit, the control line comprising an XY line and a Z line; A floating ground capacitor adjustable coupler connected to the superconducting quantum bit in a capacitive coupling manner, the floating ground capacitor adjustable coupler further configured with a floating ground capacitor reading cavity, and a Z line for manipulating the floating ground capacitor adjustable coupler; A coplanar waveguide impedance matcher, which is a coplanar waveguide cavity with a wavelength of one-half, one end of which is capacitively coupled to the floating ground capacitor adjustable coupler, and the other end is connected to a superconducting coaxial cable; The superconducting coaxial cable connects two adjacent quantum network modules, and through the indirect coupling effect of the floating ground capacitor adjustable coupler, the superconducting quantum bits in different modules are interconnected to build a modular quantum network.

[0024] In Figure 1 , ① represents a superconducting quantum bit, ② represents a floating ground capacitor adjustable coupler, ③ represents a coplanar waveguide impedance matcher, ④ represents a quantum bit reading cavity, and ⑤ represents a floating ground capacitor reading cavity.

[0025] In the present application, by dividing into multiple independent quantum network modules, the number of qubits can be easily expanded without the need to redesign the entire chip. This modular design can reduce the congestion and complexity of circuit layout when the system size increases, thereby effectively avoiding the problems of circuit crosstalk and signal interference caused by the increase in the number of qubits. Each module can work independently, and the interconnection between modules is realized through a standardized connection method, which makes the expansion of the chip more convenient and flexible. The coplanar waveguide impedance matcher used can effectively improve the transmission efficiency of the signal. The coplanar waveguide cavity structure of the coplanar waveguide helps to reduce signal reflection loss, providing a more stable signal transmission path to ensure efficient and lossless transmission of signals from the quantum network module to the superconducting coaxial cable. Especially when dealing with large-scale qubits, this efficient signal transmission can significantly reduce noise and signal attenuation, thereby improving the performance of the entire quantum computing system. Using superconducting coaxial cables to connect adjacent modules and implementing quantum bit interconnection between modules through floating ground capacitive adjustable couplers can not only ensure efficient coupling between quantum bits, but also maximize the loss and noise caused by the signal transmission path. This way, the quantum bits between different modules can interact with each other with low delay and stability, which is particularly important in quantum computing processes and directly affects the speed and accuracy of computation.

[0026] Further, the floating ground capacitive adjustable coupler is arranged in a floating ground form, and the two ends thereof are connected with the superconducting quantum bit and the impedance matcher respectively. The floating ground form of the floating ground capacitive adjustable coupler means that there is no direct connection between the center electrode and the ground electrode, and this structure effectively reduces the conduction of electromagnetic noise. Through such a design, the interference of the quantum bit with the external signal source is minimized, ensuring the high fidelity and accuracy of the quantum bit operation. Quantum computing is extremely sensitive to noise, so the influence of noise on the state of the quantum bit can be reduced through the floating ground design, thereby improving the stability of the quantum computing system. As an important component for coupling between modules, the floating ground capacitive adjustable coupler can dynamically adjust the coupling strength between modules. By adjusting the capacitance value of the coupler, the interaction between quantum bits can be accurately controlled, thereby optimizing the coherence and interconnection performance of the quantum bits. Especially in modular design, due to the large physical space distribution of each module, the floating ground capacitive adjustable coupler provides an efficient and adjustable coupling means between modules, which can avoid the energy transmission loss and crosstalk problems that may occur in traditional coupling methods.

[0027] In the present embodiment, as Figure 3 and Figure 4As shown, the coplanar waveguide cavity CPW (Coplanar Waveguide) is a transmission line structure, usually composed of two strip electrodes and a coplanar ground electrode. It is mainly used for the transmission of microwave signals, and its application in quantum computing is mainly used for signal transmission, control of quantum bits, and measurement of quantum bit states. Its characteristics are that it can realize low-loss signal transmission at high frequencies, and the structure is compact. The intrinsic frequency of the coplanar waveguide impedance matching device is consistent with the standing wave mode frequency of the superconducting coaxial cable, and the coupling end points of the coplanar waveguide impedance matching device and the superconducting coaxial cable are located at the voltage wave peak to minimize current loss.

[0028] CPW+cable+CPW structure refers to a transmission path composed of two coplanar waveguides (CPW) and a superconducting coaxial cable (equivalent superconducting coaxial cable). Specifically: CPW: Coplanar waveguide is the internal circuit part for signal transmission in the chip. It is connected to the floating ground capacitance adjustable coupler at one end and to the external superconducting coaxial cable at the other end. cable (superconducting coaxial cable): This superconducting coaxial cable connects the signal transmission path between two different modules, and it can effectively transmit microwave signals and maintain high-quality signal transmission. The superconducting coaxial cable usually has low transmission loss and is commonly used in quantum computing. CPW: At the other end of the external superconducting coaxial cable, a coplanar waveguide is also needed to receive and process the signal, ensuring that the signal can be smoothly transmitted from one module to another. The CPW+cable+CPW structure is equivalent to connecting to external devices (such as superconducting coaxial cables) through two CPWs and a cable, thereby forming a complete signal channel. It can efficiently connect quantum bits of different modules and ensure the stability and quality of signal transmission. This design not only optimizes the coupling between quantum bits, but also improves the scalability and computing power of quantum computers by adjusting the capacitance and inductance characteristics of the transmission path.

[0029] Further, the impedance matching device and its connected superconducting coaxial cable are equivalent to an open-circuit half-wavelength resonant cavity with its own capacitance and inductance, thereby constructing an equivalent circuit model.

[0030] Based on the equivalent circuit model, circuit quantization derivation is performed to obtain the specific calculation form of the coupling strength between quantum devices, including the coupling energy between superconducting quantum bits and superconducting coaxial cables, between superconducting quantum bits and floating ground capacitance adjustable couplers, and between superconducting coaxial cables and floating ground capacitance adjustable couplers.

[0031] In this example, the superconducting quantum bits and the equivalent superconducting cable are both grounded, and only the floating ground capacitance adjustable coupler is floating, so we set up four magnetic flux nodes The magnetic flux through the SQUID loop is The Lagrangian can be expressed as

[0032]

[0033] .

[0034] where is the Josephson junction energy, we assume that the capacitances of the two plates of the floating capacitance tunable coupler to ground are equal, , is the equivalent inductance of the equivalent superconducting coaxial cable. Define a new magnetic flux variable and a new conjugate variable , , and The corresponding Hamiltonian is

[0035] The capacitance matrix is

[0036] where , , , keep the modes represented by , and The Hamiltonian can be expressed as

[0037] where represents the Cooper pair logarithm, is the charging energy, , and are the coupling energies between the quantum bit and the equivalent superconducting coaxial cable, the quantum bit and the floating capacitance tunable coupler, and the equivalent superconducting coaxial cable and the floating capacitance tunable coupler, respectively.

[0038] The effective coupling strength between the superconducting quantum bit and the floating capacitance tunable coupler, the coplanar waveguide impedance matcher and the superconducting coaxial cable is ; ; ; where (i,j=1,3,4) is the equivalent capacitance matrix of the floating capacitance tunable coupler, , These are the frequencies of the superconducting quantum bit and the floating capacitive tunable coupler, respectively. It is the frequency corresponding to the standing wave mode of the selected superconducting coaxial cable.

[0039] like Figure 4 As shown, the effective coupling strength of the entire model constructed from the structure of the floating-ground capacitor adjustable coupler is calculated by the following formula:

[0040]

[0041] in , (j=q, m).

[0042] Based on the above derivation, the overall Hamiltonian of the chip containing two superconducting quantum network modules can be expressed as:

[0043] in , These are the creation and annihilation operators for superconducting qubits; , These are the generation and annihilation operators for floating-ground capacitor adjustable couplers; , These are the generation and annihilation operators in the m-th standing wave mode of an equivalent superconducting coaxial cable; , These are the eigenfrequency of the superconducting quantum bit and the floating-ground capacitive tunable coupler, respectively. It is the free spectral layer of the equivalent superconducting coaxial cable standing wave mode; M is the standing wave mode included in the simulation.

[0044] like Figure 2 As shown, the present invention also provides a method for fabricating a modular superconducting quantum chip, comprising the following steps: S10: Select sapphire substrate as the chip substrate; S20: Deposit superconducting material on the sapphire substrate to form a circuit structure of superconducting quantum bits, floating capacitive adjustable couplers, and coplanar waveguide impedance matching devices; S30: Using superconducting quantum chip fabrication technology to realize the connection of superconducting circuits: wherein, the superconducting quantum chip fabrication technology includes air bridge technology; S40: The superconducting quantum chip is packaged in a sample box with a superconducting coaxial cable welded on it. The various control lines on the superconducting quantum chip are connected to the external superconducting coaxial cable by wire bonding. S50: Perform low-temperature testing on the packaged superconducting quantum chip to verify the coupling efficiency and stability of the chip in a low-temperature environment.

[0045] Sapphire substrate is a commonly used material for superconducting quantum chips, which has excellent thermal stability and high mechanical strength, and can provide a stable platform. The high thermal conductivity of sapphire ensures that heat can be effectively transferred from the chip to the outside at low temperatures, maintaining the stability of the low-temperature environment. The surface flatness of the sapphire substrate is good, which can provide a defect-free foundation to ensure uniform deposition of superconducting materials and avoid manufacturing defects of quantum bits and other circuit components.

[0046] In step S20, the superconducting material deposited on the substrate surface is aluminum superconducting material. By depositing superconducting material on the sapphire substrate, key circuit components such as superconducting quantum bits, floating ground capacitance adjustable couplers, and coplanar waveguide impedance matchers can be formed. Using appropriate superconducting material (aluminum) can ensure efficient operation of the circuit at low temperature, with low resistance and high coherence time. By connecting superconducting circuits through air bridge technology, the problem of contact resistance caused by direct welding can be effectively avoided. Air bridge technology not only ensures low loss of superconducting connections, but also reduces the impact of physical contact points on quantum bit coherence.

[0047] Further, the specific steps of step S40 are: S401: Connect the processed superconducting quantum chip to the connection end of the external superconducting coaxial cable through wire bonding technology; S402: Use appropriate conductive materials for bonding to ensure good connection of the control lines and power lines of the superconducting quantum chip to the external circuit; S403: Package the connection end of the external coaxial cable to ensure that the chip does not interfere with external connections.

[0048] The superconducting quantum chip needs to be connected to the external superconducting coaxial cable through wire bonding technology for its control signal line, sensor line, power line, etc. Wire bonding is a precise connection technology that usually connects the chip with external circuits through metal wires (such as gold wires). The purpose of this step is to ensure that the chip can receive external signals and also feedback information to external devices. The wire bonding of the chip needs to be connected to the connection end of the superconducting coaxial cable. The superconducting coaxial cable is used for the input of control signals and the output of measurement signals, ensuring that the signals of the quantum chip can effectively interact with the outside. During wire bonding, it is necessary to ensure that the resistance of the connection point is as small as possible to avoid current loss or signal reflection and reduce noise interference. In addition, the bonding needs to be stable to prevent the chip from having poor contact or loosening in subsequent operations, affecting the stability of the quantum bits and the accuracy of quantum computing. The packaging here not only aims to physically protect, but also needs to ensure the stability of the signal transmission channel. During the packaging process, it is necessary to ensure that there is no external electromagnetic interference affecting the transmission of signals, and to avoid external noise entering the quantum system and interfering with the operation or measurement of quantum bits. The packaging material needs to have good electromagnetic shielding performance to reduce the influence of signal reflection, crosstalk or other electromagnetic noise.

[0049] Further, the specific steps of step S50 are: S501: Place the packaged superconducting quantum chip in a low-temperature environment and test it at a temperature close to absolute zero; S502: Measure the coupling strength between the superconducting quantum bits and the floating ground capacitor adjustable coupler, and the coupling strength between the superconducting coaxial cable standing wave mode and the superconducting quantum bits; S503: Verify whether the designed quantum chip meets the stability of quantum bits, low energy consumption and high coupling efficiency according to the experimental results.

[0050] Low-temperature testing is a standard testing procedure in quantum computing, as quantum computing is usually carried out under low-temperature conditions. At this temperature, the resistance of superconducting materials is almost zero, and the coherence of quantum bits and the stability of energy states are fully verified. Quantum chips, especially superconducting quantum bits, work at very low temperatures (close to absolute zero, usually around 10 millikelvin) to reduce thermal noise and increase the coherence time of quantum states. Testing at low temperatures can ensure the stability of the chip in the actual working environment.

[0051] In this embodiment, on the basis of the above-mentioned modular superconducting quantum chip, first of all, we selected a sapphire substrate as the substrate of the superconducting quantum modular superconducting quantum chip. This substrate is a commonly used material in the manufacture of superconducting quantum modular superconducting quantum chips at present, and has good thermal stability and mechanical strength. Based on the design drawing, we made it according to the standard superconducting quantum modular superconducting quantum chip processing flow, including air bridge technology, to ensure that each component can be effectively connected and work stably. After processing, the modular superconducting quantum chip is packaged in a sample box, and a 15-centimeter-long aluminum (Al) coaxial cable is welded. We have specially treated the Al superconducting coaxial cable: The outer conductor of the Al superconducting coaxial cable is connected to the ground of the sample box to ensure the stability of the ground potential.

[0052] The internal center conductor is cut open by a blade to expose the center conductor part, facilitating connection in the subsequent wire bonding process.

[0053] Each control line of the modular superconducting quantum chip is connected to the cable through Al wire bonding technology. In particular, the ground wire of the modular superconducting quantum chip is connected to the ground wire of the sample box, and the pad end of the impedance matching device is connected to the exposed end of the cable.

[0054] After packaging, we get a modular sample. The same packaging process is also applied to the other end of the sample box, which is also welded with a 15-centimeter-long aluminum (Al) coaxial cable.

[0055] The packaged modular superconducting quantum chip sample is placed in the 10mK working temperature zone of the dilution refrigerator for low-temperature testing. The measurement results are as follows: The frequency of the superconducting quantum bit is about 3.5 GHz at the highest point.

[0056] The frequency of the floating ground capacitance adjustable coupler is about 6.5 GHz at the highest point.

[0057] The free spectral range of the Al superconducting coaxial cable is about 450 MHz.

[0058] The coupling strength between the superconducting quantum bit and the floating ground capacitance adjustable coupler can reach about 90 MHz.

[0059] The coupling between the floating ground capacitance adjustable coupler and the modes of the Al cable also shows strong coupling characteristics, especially the coupling strength between the 12th standing wave mode and the floating ground capacitance adjustable coupler is about 32 MHz.

[0060] The coupling between the superconducting quantum bit and the Al superconducting coaxial cable reaches about 8 MHz through the action of the floating ground capacitance adjustable coupler.

[0061] Through the above tests, we verify the performance of the modular superconducting quantum chip in a low-temperature environment and ensure the stability of the coupling between quantum bits and the frequency characteristics. This provides a foundation for subsequent quantum bit gate operations, quantum entanglement experiments, etc. Through this processing and testing, the performance in a low-temperature environment is verified. The test results show that the frequency, coupling strength and operation stability of the chip meet the expectations, indicating that the performance of the chip has good symmetry and stability.

[0062] The application has the beneficial effects that: by using the design of the floating ground capacitance adjustable coupler and the coplanar waveguide impedance matcher, the coupling loss between quantum bits is effectively reduced, and the transmission efficiency of the signal is improved through structure optimization, so that the quantum bits on different chips can be efficiently and low-loss interconnected. In addition, the optimization of the packaging and manufacturing process makes the superconducting quantum chip suitable for large-scale integration and long-term stable operation, and has high experimental reliability.

[0063] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application. These equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A modular superconducting quantum chip, characterized by, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

2. The modular superconducting quantum chip of claim 1, wherein, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

3. The modular superconducting quantum chip of claim 1, wherein, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. ； ； ； wherein (i,j = 1,3,4) the equivalent capacitance matrix of the floating-capacitor tunable coupler, , are the frequencies of the superconducting qubit and the floating-capacitor tunable coupler, respectively; is the standing wave mode corresponding frequency of the selected superconducting coaxial cable.

4. The modular superconducting quantum chip of claim 1, wherein, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

5. The modular superconducting quantum chip of claim 1, wherein, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

6. A method of processing a modular superconducting quantum chip as claimed in any one of claims 1-5, characterized in that, The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

7. The method of claim 6, wherein the plurality of superconducting qubits are fabricated on a plurality of substrates, and the plurality of substrates are bonded together to form the superconducting quantum chip. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

8. The method of claim 6, wherein the plurality of superconducting qubits are fabricated on a plurality of substrates, and the plurality of substrates are bonded together to form the superconducting quantum chip. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method.

9. The method of claim 6, wherein the superconducting quantum chip is a modular superconducting quantum chip. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. 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The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting quantum chip and a superconducting quantum chip processing method. The application relates to a superconducting

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