SOC chip, bridging integrated chip and DRAM
By introducing a memory repair module into the SOC chip and the bridging integrated chip, the fault status of DRAM memory cells is detected and remapped, which solves the problem of ineffective use caused by memory cell failure in DRAM, and realizes the effective utilization of DRAM and the improvement of system performance.
Patent Information
- Application Number
- CN202511024988.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-07
AI Technical Summary
Faulty memory cells in DRAM render them unusable, and traditional system-on-a-chip (SoC) cannot effectively utilize DRAM interface modules.
By introducing a storage repair module into the SOC chip and the bridging integrated chip, the physical address of the normal state cell is remapped after detecting the fault status of the DRAM storage cell, thereby realizing the repair and effective utilization of the storage cell.
This enables the efficient utilization of DRAM memory cells, improves system performance and stability, and ensures fast and efficient data transmission.
Smart Images
Figure CN120913623A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage unit repair, and particularly relates to a SOC chip, a bridge integrated chip and a DRAM. BACKGROUND
[0002] DRAM (Dynamic Random Access Memory) is a kind of semiconductor memory, and the main principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The storage units in the DRAM have certain distribution differences in quality and reliability, and the distribution is caused by the randomness of manufacturing process, material defects, thermal stress, and design tolerance and the like.
[0003] The DRAM interface module involved in the traditional system-on-chip includes a double data rate controller and a double data rate physical layer, and when data read / write operation is performed on the DRAM, if there is a faulty storage unit in the DRAM memory chip, the DRAM cannot be effectively used. SUMMARY
[0004] The main purpose of the present application is to provide a SOC chip, a bridge integrated chip and a DRAM, which aims to solve the problem that the storage unit in the DRAM is faulty, resulting in the problem that the DRAM cannot be effectively used.
[0005] To achieve the above purpose, the present application provides a SOC chip, which is electrically connected with a DRAM, and the SOC chip comprises:
[0006] a first control circuit;
[0007] a storage repair module, which is electrically connected with the first control circuit and the DRAM respectively; the storage repair module is configured to detect the fault of the storage unit of the DRAM after power-on, and confirm the physical address of the storage unit in the fault state; based on the physical address of the storage unit in the fault state, the physical address of the storage unit in the normal state in the DRAM is remapped and output to the first control circuit.
[0008] In an embodiment, the SOC chip further comprises:
[0009] a first DRAM interface;
[0010] a first DDR conversion circuit, a first end of the first DDR conversion circuit being electrically connected with the first DRAM interface; the first DDR conversion circuit is used for signal conversion;
[0011] a first DDR controller, a first end of the first DDR controller being electrically connected with the first control circuit, and a second end of the first DDR controller being electrically connected with a second end of the first DDR conversion circuit; the first DDR controller is used for accessing data.
[0012] The storage repair module is arranged in the first DDR controller.
[0013] In an embodiment, the storage repair module is specifically configured to:
[0014] acquire the functional parameter of each storage unit in the DRAM, and confirm the working state of each storage unit according to the functional parameter of each storage unit;
[0015] based on the working state of each storage unit, screen the storage unit in the fault state and the storage unit in the normal state, and confirm the physical address of the storage unit in the fault state and the storage unit in the normal state;
[0016] according to the physical address of the storage unit in the fault state and the storage unit in the normal state, perform removal processing on the storage unit in the fault state, reorder the physical address of the storage unit in the normal state, acquire the physical address of the storage unit in the normal state in the DRAM, and output to the SOC chip.
[0017] In an embodiment, the step of acquiring the functional parameter of each storage unit in the DRAM, and confirming the working state of each storage unit according to the functional parameter of each storage unit is specifically:
[0018] acquire the functional parameter of each storage unit in the DRAM, in the case that the functional parameter of each storage unit is within a preset parameter range, confirm that the working state of each storage unit is the normal state; and in the case that the functional parameter of the storage unit is outside the preset parameter range, confirm that the working state of the storage unit is the fault state.
[0019] In an embodiment, the SOC chip further comprises a first CPU, and the first control circuit is the first CPU.
[0020] The application further provides a bridge integrated chip, which is electrically connected with an SOC chip and a DRAM respectively, and comprises:
[0021] a second control circuit;
[0022] a storage repair module electrically connected with the second control circuit; the storage repair module is configured to, after power-on, perform fault detection on the storage units of the DRAM, and confirm the physical addresses of the storage units in a fault state; based on the physical addresses of the storage units in the fault state, remap the physical addresses of the storage units in a normal state in the DRAM, and output to the second control circuit.
[0023] In an embodiment, the bridge integrated chip further comprises:
[0024] a second DRAM interface for connecting a DRAM;
[0025] a second DDR conversion circuit, a first end of the second DDR conversion circuit being electrically connected with the second DRAM interface; the second DDR conversion circuit being configured to convert signals;
[0026] a second DDR controller, a first end of the second DDR controller being electrically connected with the second control circuit, and a second end of the second DDR controller being electrically connected with a second end of the second DDR conversion circuit; the second DDR controller being configured to access data;
[0027] The storage repair module is arranged in the second DDR controller.
[0028] In an embodiment, the storage repair module is specifically configured to:
[0029] obtain the functional parameters of each storage unit in the DRAM, and confirm the working state of each storage unit according to the functional parameters of each storage unit;
[0030] based on the working state of each storage unit, screen the storage units in a fault state and the storage units in a normal state, and confirm the physical addresses of the storage units in the fault state and the storage units in the normal state;
[0031] According to the physical addresses of the storage units in the fault state and the storage units in the normal state, the storage units in the fault state are removed, and the physical addresses of the storage units in the normal state are reordered to obtain the physical addresses of the storage units in the normal state in the DRAM, and output to the second control circuit.
[0032] In an embodiment, the step of obtaining the functional parameters of each storage unit in the DRAM, and confirming the working state of each storage unit according to the functional parameters of each storage unit is specifically:
[0033] Obtaining the function parameter of each memory cell in the DRAM, and if the function parameter of each memory cell is within the preset parameter range, the working state of each memory cell is confirmed to be normal; if the function parameter of the memory cell is outside the preset parameter range, the working state of the memory cell is confirmed to be a fault state.
[0034] The application also provides a DRAM, which comprises the bridge integrated chip according to any one of the above.
[0035] The application can effectively solve the problem of the failure of the memory cell in the DRAM and the problem of the ineffective use of the DRAM by arranging the corresponding control circuit and the storage repair module in the SOC chip, the bridge integrated chip or the DRAM. The SOC chip comprises a first control circuit and a storage repair module, which are electrically connected with the DRAM. The storage repair module is configured to detect the fault of the memory cell of the DRAM and confirm the physical address of the memory cell in the fault state after power-on. The physical address of the memory cell in the normal state in the DRAM is remapped based on the physical address of the memory cell in the fault state and output to the first control circuit. Thus, the repair of the memory cell in the DRAM is realized by the first control circuit and the storage repair module when the SOC chip is electrically connected with the DRAM, so as to realize the effective use of the DRAM. BRIEF DESCRIPTION OF DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on the drawings shown.
[0037] Figure 1 The figure is a module schematic diagram of the SOC chip of the present application;
[0038] Figure 2 The figure is a module schematic diagram of an embodiment of the SOC chip of the present application;
[0039] Figure 3 The figure is a module schematic diagram of the bridge integrated chip of the present application;
[0040] Figure 4 The figure is a module schematic diagram of an embodiment of the bridge integrated chip of the present application.
[0041] Explanation of reference signs:
[0042] 10, SOC chip; 11, first control circuit; 12, storage repair module; 13, first DRAM interface; 14, first DDR conversion circuit; 15, first DDR controller; 20, bridge integrated chip; 21, second controller; 23, second DRAM interface; 24, second DDR conversion circuit; 25, second DDR controller; 30, DRAM.
[0043] The objectives, functional characteristics and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION
[0044] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0045] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indications also change accordingly.
[0046] In addition, the descriptions of “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is also not within the protection scope required by the present application.
[0047] DRAM (Dynamic Random Access Memory) is a kind of semiconductor memory, and the main principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The storage units inside the DRAM have certain distribution differences in quality and reliability, and such distribution is caused by the randomness of manufacturing process, material defects, thermal stress, and design tolerance and other factors.
[0048] The traditional system-level chip involves a DRAM interface module including a double data rate controller and a double data rate physical layer. When reading and writing data from the DRAM, if there is a faulty memory cell in the DRAM memory chip, the DRAM cannot be effectively used.
[0049] To solve the above problems, with reference to Figure 1 The application provides a SOC chip 10 used for electrical connection with a DRAM 30, the SOC chip 10 comprising:
[0050] a first control circuit 11;
[0051] a memory repair module 12 electrically connected with the first control circuit 11 and the DRAM 30 respectively; the memory repair module 12 is configured to detect faults of memory cells of the DRAM 30 after power-on, and confirm physical addresses of memory cells in a fault state; based on the physical addresses of the memory cells in the fault state, the physical addresses of memory cells in a normal state in the DRAM 30 are remapped and output to the first control circuit 11.
[0052] It can be understood that the SOC chip 10 is an integrated circuit that integrates all components of a computer or other electronic system onto a single chip. In addition to the central processor, the SOC may also include a graphics processing unit, a memory controller, a communication module, a multimedia processing unit, a sensor interface, and other peripheral interfaces, etc. Among them, the SOC chip 10 is usually electrically connected with the DRAM 30 to provide a fast and efficient temporary data storage solution to meet the needs of the central processor and other components when processing data. During the computing process, the central processor needs to read and write data quickly. Compared with hard disks or other types of storage devices, the DRAM 30 provides faster data access speed, which helps to improve the overall performance of the system. In addition, modern operating systems often run multiple applications and services at the same time. Enough DRAM 30 can allow more application data to be loaded into memory, reducing frequent data exchange due to insufficient memory, thereby improving multi-task processing efficiency. And for the SOC integrated with a graphics processing unit, connecting to the external DRAM 30 can significantly speed up the graphics rendering process, providing a smoother experience for applications such as games, video playback, or professional graphics design. Finally, the SOC design uses high-speed interface technology (such as LPDDR4, LPDDR5, etc.) to connect the DRAM 30, ensuring that data can be quickly and stably transmitted between the processor and the memory, supporting high-bandwidth demand applications. When the CPU, GPU or NPU accesses the DRAM 30 address through the DDR controller and the DDR conversion circuit, it is a continuous address space, such as 0x0000~0x6FFF, etc. If one or more cell addresses in a continuous address space are faulty, the running computation or data will be incorrect, causing the system to be unable to run or crash and other abnormal situations.
[0053] In the embodiment, the first control circuit 11 can be implemented by a micro CPU or the like control processor. The first control circuit 11 reads and executes the instructions in the storage repair module 12 by being electrically connected to the storage repair module 12 and the storage repair module 12 being electrically connected to the DRAM 30, so that the storage repair module 12 detects the storage units in the DRAM 30. After the SOC chip 10 is powered on, the first control circuit 11 reads and executes the instructions stored in the storage repair module 12, so as to detect each storage unit in the DRAM 30, and then confirm the faulty storage units in the DRAM 30. Wherein, by confirming the physical addresses of the storage units in the faulty state, the physical addresses of the storage units in the DRAM 30 are remapped to confirm the physical addresses of the storage units in the normal state, so that the first control circuit 11 feeds back the remapped physical addresses of the storage units to the SOC chip 10, so that the SOC chip 10 can effectively use the DRAM 30 when being electrically connected to the DRAM 30.
[0054] Further, the storage repair module 12 is specifically configured to:
[0055] obtain the function parameters of each storage unit in the DRAM 30, and confirm the working state of each storage unit according to the function parameters of each storage unit;
[0056] based on the working state of each storage unit, screen the storage units in the faulty state and the storage units in the normal state, and confirm the physical addresses of the storage units in the faulty state and the storage units in the normal state;
[0057] According to the physical addresses of the storage units in the faulty state and the storage units in the normal state, the storage units in the faulty state are removed, and the physical addresses of the storage units in the normal state are reordered to obtain the physical addresses of the storage units in the normal state in the DRAM 30, and output to the SOC chip 10.
[0058] In the embodiment, the storage repair module 12 is controlled by the first control circuit 11 to apply voltage and current to the storage unit and measure the response to detect the functionality of each storage unit in the DRAM 30 by powering on the SOC chip 10. It can be understood that the corresponding parameter range is preset in the storage repair module 12, so that the functionality of each storage unit in the DRAM 30 is detected, and each storage unit in the DRAM 30 is classified according to the preset parameter range. Specifically, the read-write operation test can be performed to verify whether the storage unit can correctly store and retrieve data. If a storage unit cannot correctly perform these basic operations, it is determined to be faulty.
[0059] Optionally, the step of acquiring the functional parameters of each storage unit in the DRAM 30 and confirming the working state of each storage unit according to the functional parameters of each storage unit is specifically:
[0060] The functional parameters of each storage unit in the DRAM 30 are acquired, and in the case that the functional parameters of each storage unit are within the preset parameter range, the working state of each storage unit is confirmed to be normal; and in the case that the functional parameters of the storage unit are outside the preset parameter range, the working state of the storage unit is confirmed to be a fault state.
[0061] In the embodiment, the functionality of each storage unit is tested to obtain the corresponding functional parameters of each storage unit, and the working state of each storage unit is confirmed by comparing the functional parameters of each storage unit with the preset parameter range. The preset parameter range can be set according to actual use requirements. For example, in a working environment with high requirements for the performance of the DRAM 30, a relatively strict preset parameter range is used. It can be understood that in the embodiment, the working state of the storage unit in the DRAM 30 can be defined according to actual use requirements. In the case that the storage unit in the DRAM 30 cannot meet the actual use requirements, the storage unit that cannot meet the use requirements is identified as a fault state, that is, the preset parameter range is set relatively strictly to meet the corresponding use requirements. The functional parameters of the plurality of storage units in the DRAM 30 are compared with the preset parameter range to identify the storage units within the preset parameter range as normal.
[0062] Optionally, the function parameters of the memory cells can also be judged whether they reach the preset parameter range by testing the length of time that the memory cells can maintain their charge states without refreshing. It can be understood that a shorter retention time can indicate that there is a leakage or other problems in the capacitor, thereby affecting the persistence of data storage. Secondly, by the case that the current flows from the power supply of the memory cell to the ground or adjacent circuit in an ideal completely isolated state, a larger leakage current can be caused by manufacturing defects or poor insulation due to material aging, which can cause the charge to flow out faster, thereby shortening the charge retention time and possibly causing data loss or errors. By the corresponding preset parameter range, it can be judged whether each memory cell in the DRAM 30 meets the corresponding use requirements, and the memory cells that cannot meet the use requirements are all identified as a fault state.
[0063] In the present embodiment, the memory cells identified as a fault state are screened out and the physical addresses of the memory cells in a fault state are identified. It needs to be understood that in the DRAM 30, the physical address of the memory cell is mainly used to uniquely identify and access the location of each memory cell. The physical address allows the system to accurately locate to a specific memory cell. Since the memory cells in the DRAM 30 are organized in a two-dimensional matrix form (rows and columns), the physical address is usually decomposed into a row address (Row Address) and a column address (Column Address) to facilitate access to a specific memory cell. In order to perform a read or write operation of data, the processor or memory controller needs to know the exact location to be accessed. By providing the correct physical address, the system can accurately find the target memory cell and perform the corresponding operation. Therefore, in order to ensure the accurate identification of the memory cells in the DRAM 30 identified as being in a fault state, the physical address of each memory cell in a fault state needs to be identified in order to facilitate subsequent remapping, thereby realizing the subsequent use of the memory cells in the DRAM 30. The first control circuit 11 remaps the physical address of the memory cells in the DRAM 30 through the storage repair module 12, thereby removing the memory cells in the DRAM 30 in a fault state. In addition, the first control circuit 11 is also electrically connected with the CPU in the SOC, thereby outputting the remapped physical address of the memory cells in the DRAM 30 to the CPU in the SOC chip 10, so that the SOC can stably and effectively use the DRAM 30 to meet the demand of the SOC chip 10 for fast and efficient temporary data storage.
[0064] By adopting the mode that the corresponding control circuit and the storage repair module 12 are arranged in the SOC chip 10, the problem that the storage unit in the DRAM 30 fails and the DRAM 30 cannot be effectively used can be effectively solved. The SOC chip 10 comprises: a first control circuit 11; a storage repair module 12, which is electrically connected with the first control circuit 11 and the DRAM 30; the storage repair module 12 is configured to detect the fault of the storage unit of the DRAM 30 after power-on, and confirm the physical address of the storage unit in the fault state; based on the physical address of the storage unit in the fault state, the physical address of the storage unit in the normal state in the DRAM 30 is remapped and output to the first control circuit 11. Thus, when the SOC chip 10 is electrically connected with the DRAM 30, the repair of the storage unit in the DRAM 30 is realized through the first control circuit 11 and the storage repair module 12, so as to realize the effective use of the DRAM 30.
[0065] Reference Figure 2 In an embodiment of the present application, the SOC chip 10 further comprises:
[0066] a first DRAM 30 interface 13;
[0067] a first DDR conversion circuit 14, a first end of the first DDR conversion circuit 14 being electrically connected with the first DRAM 30 interface 13; the first DDR conversion circuit 14 is used for signal conversion;
[0068] a first DDR controller 15, a first end of the first DDR controller 15 being electrically connected with the first control circuit 11, and a second end of the first DDR controller 15 being electrically connected with a second end of the first DDR conversion circuit 14; the first DDR controller 15 is used for data access;
[0069] The storage repair module 12 is arranged in the first DDR controller 15.
[0070] In the embodiment, the first DRAM 30 interface 13 can be realized as a trace on a printed circuit board corresponding to a DRAM 30 chip to realize effective connection of the SOC chip 10 and the DRAM 30. The interface connection includes an address bus, a data bus, a control signal, a clock signal, and a clock enable signal, etc. The first DDR conversion circuit 14 can be realized by a DDR PHY, which is responsible for realizing the functions of the physical layer of the DDR interface, including signal transmission and reception, clock generation and synchronization, voltage level conversion, and providing an interface that meets the electrical characteristics required by the DDR memory module. The design of the DDR PHY must consider signal integrity and electromagnetic compatibility, etc. to ensure stability and reliability under high-speed data transmission. The first DDR controller 15 is responsible for processing the logic units of all communication protocol related tasks. It manages high-level functions such as command scheduling, address generation, data flow control, etc. The DDR controller ensures that the CPU or other host devices can interact with the DDR memory in the correct way, including read and write operation execution, timing, and data integrity verification, etc.
[0071] Optionally, in the embodiment, the first control circuit 11 can be realized by a first CPU in the SOC, that is, the storage repair unit multiplexes the first CPU in the SOC to realize the execution of program instructions and the processing of data in the storage repair unit, thereby avoiding the cost of additionally setting a CPU. In addition, this way can also enable the SOC chip 10 to more quickly, stably and accurately confirm the physical address of the storage unit remapping in the DRAM 30. Because, at this time, the first CPU in the SOC chip 10 does not need to interact with the additional first control circuit 11 to confirm the data.
[0072] Reference Figure 3 The application further provides a bridge integrated chip 20, which is used for being electrically connected with the SOC chip 10 and the DRAM 30 respectively, and includes:
[0073] a second control circuit;
[0074] a storage repair module 12, which is electrically connected with the second control circuit; the storage repair module 12 is configured to, after power-on, detect the storage unit of the DRAM 30 for failure, and confirm the physical address of the storage unit in a failure state; remap the physical address of the storage unit in a normal state in the DRAM 30 based on the physical address of the storage unit in the failure state, and output to the second control circuit.
[0075] In the embodiment, the second control circuit can be implemented by a micro CPU or the like control processor. The second control circuit is electrically connected with the storage repair module 12, and the storage repair module 12 is electrically connected with the DRAM 30, so as to read and execute the instructions in the storage repair module 12, so that the storage repair module 12 detects the storage units in the DRAM 30. After the bridge integrated chip 20 is powered on, the instructions stored in the storage repair module 12 are read and executed by the second control circuit, so as to detect each storage unit in the DRAM 30, and then confirm the storage units in the DRAM 30 that are in a fault state. The physical addresses of the storage units in the fault state are confirmed, and the physical addresses of the storage units in the DRAM 30 are remapped to confirm the physical addresses of the storage units in the normal state, so that the first control circuit 11 feeds back the physical addresses of the remapped storage units to the second control circuit. The second control circuit is electrically connected with the SOC chip 10, so that the SOC chip 10 can effectively use the DRAM 30 when the SOC chip 10 is electrically connected with the bridge integrated chip 20, and the bridge integrated chip 20 is electrically connected with the DRAM 30.
[0076] Further, the storage repair module 12 is specifically configured to:
[0077] obtain the function parameters of each storage unit in the DRAM 30, and confirm the working state of each storage unit according to the function parameters of each storage unit;
[0078] based on the working state of each storage unit, screen the storage units in the fault state and the storage units in the normal state, and confirm the physical addresses of the storage units in the fault state and the storage units in the normal state;
[0079] According to the physical addresses of the storage units in the fault state and the storage units in the normal state, the storage units in the fault state are removed, and the physical addresses of the storage units in the normal state are reordered to obtain the physical addresses of the storage units in the normal state in the DRAM 30, and output to the second control circuit.
[0080] In this embodiment, by powering on the bridging integrated chip 20, the storage repair module 12, under the control of the second control circuit, applies voltage and current to the storage cells and measures the response to detect the functionality of each storage cell in the DRAM 30. It is understood that the storage repair module 12 has preset parameter ranges, thereby classifying the working state of each storage cell in the DRAM 30 according to the preset parameter ranges while detecting the functionality of each storage cell. Specifically, read / write operation tests can be performed to verify whether the storage cell can correctly store and retrieve data. If a storage cell cannot correctly perform these basic operations, it is considered to be faulty.
[0081] Optionally, the step of obtaining the functional parameters of each memory cell in the DRAM 30 and confirming the working state of each memory cell based on the functional parameters of each memory cell specifically includes:
[0082] The functional parameters of each storage cell in the DRAM 30 are obtained. If the functional parameters of each storage cell are within the preset parameter range, the working state of each storage cell is confirmed to be normal. If the functional parameters of a storage cell are outside the preset parameter range, the working state of the storage cell is confirmed to be faulty.
[0083] In this embodiment, functional tests are performed on each storage cell to obtain its corresponding functional parameters. By comparing the functional parameters of each storage cell with preset parameter ranges, the normal operating status of each storage cell can be confirmed. The preset parameter range can be set according to actual usage requirements. For example, in environments with high performance requirements for DRAM30, a relatively strict preset parameter range is used. It is understood that in this embodiment, the operating status of the storage cells in DRAM30 can be defined according to actual usage requirements. If a storage cell in DRAM30 fails to meet actual usage requirements, this failure can be identified as a fault state; that is, the preset parameter range is set relatively strictly to meet the corresponding usage requirements. By testing the functional parameters of multiple storage cells in DRAM30, storage cells whose functional parameters are within the preset parameter range are identified as being in a normal state.
[0084] Optionally, the function parameters of the memory cells can also be compared with the pre-set parameter range by testing the length of time the memory cells can maintain their charge state without refresh. It can be understood that a shorter retention time can indicate that the capacitor has a leakage or other problems, thereby affecting the persistence of data storage. Secondly, a larger leakage current can be caused by manufacturing defects or poor insulation due to material aging, which can cause the charge to dissipate faster, thereby shortening the charge retention time and possibly causing data loss or errors, by the case of current flowing from the power supply of the memory cell to the ground or adjacent circuits in an ideally completely isolated state. By comparing the corresponding pre-set parameter range, it can be determined whether each memory cell in the DRAM 30 meets the corresponding use requirements, and the memory cells that cannot meet the use requirements are all identified as a fault state.
[0085] In this embodiment, the memory cells identified as a fault state are screened out and the physical addresses of the memory cells in a fault state are identified. It should be understood that in the DRAM 30, the physical address of the memory cell is mainly used to uniquely identify and access the location of each memory cell. The physical address allows the system to accurately locate to a specific memory cell. Since the memory cells in the DRAM 30 are organized in a two-dimensional matrix form (rows and columns), the physical address is usually decomposed into a row address (Row Address) and a column address (Column Address) to facilitate access to a specific memory cell. In order to perform a read or write operation of data, the processor or memory controller needs to know the exact location to be accessed. By providing the correct physical address, the system can accurately find the target memory cell and perform the corresponding operation. Therefore, in order to ensure the accurate identification of the memory cells in the DRAM 30 identified as being in a fault state, the physical address of each memory cell in a fault state needs to be identified in order to facilitate subsequent remapping, thereby realizing the subsequent use of the memory cells in the DRAM 30. The second control circuit remaps the physical address of the memory cells in the DRAM 30 through the storage repair module 12, thereby removing the memory cells in the DRAM 30 in a fault state. In addition, the second control circuit is also electrically connected with the SOC chip 10, thereby outputting the remapped physical address of the memory cells in the DRAM 30 to the SOC chip 10, so that the SOC chip 10 can stably and effectively use the DRAM 30 to meet the demand of the SOC chip 10 for fast and efficient temporary data storage.
[0086] By adopting the mode that the corresponding second control circuit and the storage repair module 12 are arranged in the bridge integrated chip 20, the problem that the storage unit in the DRAM 30 fails and the DRAM 30 cannot be effectively used can be effectively solved. The bridge integrated chip 20 comprises: a second control circuit; a storage repair module 12, which is electrically connected with the second control circuit and the DRAM 30; the storage repair module 12 is configured to detect the storage unit of the DRAM 30 for failure after power-on, and confirm the physical address of the storage unit in the failure state; based on the physical address of the storage unit in the failure state, the physical address of the storage unit in the normal state in the DRAM 30 is remapped and output to the second control circuit. Thus, when the SOC chip 10 is electrically connected with the DRAM 30, the storage unit in the DRAM 30 is repaired through the bridge integrated chip 20, so as to realize the effective use of the DRAM 30.
[0087] Reference Figure 4 In an embodiment of the present application, the bridge integrated chip 20 further comprises:
[0088] A second DRAM 30 interface 23, which is used for connecting the DRAM 30;
[0089] A second DDR conversion circuit 24, a first end of the second DDR conversion circuit 24 being electrically connected with the second DRAM 30 interface 23; the second DDR conversion circuit 24 is used for signal conversion;
[0090] A second DDR controller 25, a first end of the second DDR controller 25 being electrically connected with the second control circuit, and a second end of the second DDR controller 25 being electrically connected with a second end of the second DDR conversion circuit 24; the second DDR controller 25 is used for data access;
[0091] The storage repair module 12 is arranged in the second DDR controller 25.
[0092] In the embodiment, the second DRAM 30 interface 23 can be realized as a trace on a printed circuit board corresponding to the DRAM 30 chip to realize the effective connection of the bridge integrated chip 20 and the DRAM 30. The interface connection includes an address bus, a data bus, a control signal, a clock signal, a clock enable signal, and the like. The first DDR conversion circuit 14 can be realized as a DDR PHY, which is responsible for realizing the physical layer function of the DDR interface, including signal transmission and reception, clock generation and synchronization, voltage level conversion, and providing an interface meeting the electrical characteristics required by the DDR memory module. The design of the DDR PHY must consider signal integrity and electromagnetic compatibility and the like to ensure stability and reliability under high-speed data transmission. The first DDR controller 15 is a logic unit responsible for processing all communication protocol-related tasks. It manages high-level functions such as command scheduling, address generation, data flow control, and the like. The DDR controller ensures that the CPU or other host devices can interact with the DDR memory in the correct manner, including read and write operation execution, timing, and data integrity verification, and the like.
[0093] The application further provides a DRAM, which comprises the bridge integrated chip according to any one of the above embodiments. It can be understood that the bridge integrated chip is arranged on the DRAM. It is worth noting that since the DRAM of the application is based on the bridge integrated chip described above, the embodiments of the DRAM of the application include all the technical solutions of all the embodiments of the bridge integrated chip described above, and the technical effects achieved are also completely the same, which will not be described here.
[0094] The above only describes the preferred embodiments of the application, and does not limit the patent scope of the application. Any equivalent structural transformation based on the inventive concept of the application, or direct / indirect application in other related technical fields is included in the patent protection scope of the application.
Claims
1. A SOC chip, characterized by, The SOC chip is electrically connected with the DRAM, and the SOC chip comprises: a first control circuit; a storage repair module, which is electrically connected with the first control circuit and the DRAM respectively; the storage repair module is configured to perform fault detection on the storage units of the DRAM after power-on, and to confirm the physical addresses of the storage units in a fault state; based on the physical addresses of the storage units in the fault state, the physical addresses of the storage units in a normal state in the DRAM are remapped and output to the first control circuit.
2. The SOC chip of claim 1, wherein, The SOC chip further comprises: a first DRAM interface; a first DDR conversion circuit, a first end of which is electrically connected with the first DRAM interface; the first DDR conversion circuit is used for signal conversion; a first DDR controller, a first end of which is electrically connected with the first control circuit, and a second end of which is electrically connected with a second end of the first DDR conversion circuit; the first DDR controller is used for data access; wherein the storage repair module is arranged in the first DDR controller.
3. The SOC chip of claim 1, wherein, The storage repair module is specifically configured to: obtain the functional parameters of each storage unit in the DRAM, and confirm the working state of each storage unit according to the functional parameters of each storage unit; based on the working state of each storage unit, screen the storage units in a fault state and the storage units in a normal state, and confirm the physical addresses of the storage units in the fault state and the storage units in the normal state; according to the physical addresses of the storage units in the fault state and the storage units in the normal state, perform removal processing on the storage units in the fault state, reorder the physical addresses of the storage units in the normal state, so as to obtain the physical addresses of the storage units in the normal state in the DRAM, and output to the SOC chip.
4. The SOC chip of claim 3, wherein, The step of obtaining the functional parameters of each storage unit in the DRAM and confirming the working state of each storage unit according to the functional parameters of each storage unit is specifically: obtain the functional parameters of each storage unit in the DRAM, and in the case that the functional parameters of each storage unit are within a preset parameter range, confirm that the working state of each storage unit is in a normal state; in the case that the functional parameters of the storage unit are outside the preset parameter range, confirm that the working state of the storage unit is in a fault state.
5. The SOC chip of any one of claims 1 to 4, wherein, The SOC chip further comprises a first CPU, and the first control circuit is the first CPU.
6. A bridge integrated chip, comprising: The bridge integrated chip is electrically connected with the SOC chip and the DRAM respectively, and the bridge integrated chip comprises: a second control circuit; a storage repair module electrically connected with the second control circuit; the storage repair module is configured to, after power-on, perform fault detection on the storage units of the DRAM, and confirm the physical addresses of the storage units in a fault state; based on the physical addresses of the storage units in the fault state, remap the physical addresses of the storage units in a normal state in the DRAM, and output to the second control circuit.
7. The bridge integrated chip of claim 6, wherein, The bridge integrated chip further comprises: a second DRAM interface for connecting a DRAM; a second DDR conversion circuit, a first end of which is electrically connected with the second DRAM interface; the second DDR conversion circuit is used for signal conversion; a second DDR controller, a first end of which is electrically connected with the second control circuit, and a second end of which is electrically connected with a second end of the second DDR conversion circuit; the second DDR controller is used for data access; wherein the storage repair module is arranged in the second DDR controller.
8. The bridge integrated chip of claim 6, wherein, The storage repair module is specifically configured to: obtain the functional parameters of each storage unit in the DRAM, and confirm the working state of each storage unit according to the functional parameters of each storage unit; based on the working state of each storage unit, screen the storage units in a fault state and the storage units in a normal state, and confirm the physical addresses of the storage units in the fault state and the storage units in the normal state; according to the physical addresses of the storage units in the fault state and the storage units in the normal state, perform removal processing on the storage units in the fault state, reorder the physical addresses of the storage units in the normal state, to obtain the physical addresses of the storage units in the normal state in the DRAM, and output to the second control circuit.
9. The bridge integrated chip of claim 8, wherein, The step of obtaining the functional parameters of each storage unit in the DRAM, and confirming the working state of each storage unit according to the functional parameters of each storage unit is specifically: obtain the functional parameters of each storage unit in the DRAM, and confirm the working state of each storage unit according to the functional parameters of each storage unit; in the case that the functional parameters of each storage unit are within a preset parameter range, confirm that the working state of each storage unit is a normal state; 10. A DRAM, comprising: in the case that the functional parameters of the storage unit are outside the preset parameter range, confirm that the working state of the storage unit is a fault state. The DRAM comprises the bridge integrated chip according to any one of claims 6 to 9.