Controller of power electronic device and power electronic device

Abstract

The invention provides a controller of a power electronic device and the power electronic device, and relates to the technical field of power electronics. Comprising a digital signal processor (DSP) and a field programmable gate array (FPGA), the DSP is used for generating a PWM signal and outputting the PWM signal to the FPGA, and the FPGA is used for outputting the PWM signal to a transistor in a primary circuit of the power electronic device; the DSP is also used for outputting a software fault signal to the FPGA when detecting that the power electronic device has a software fault; the FPGA is also used for triggering a hardware fault signal under the condition of detecting that the power electronic device has a hardware fault, and is used for stopping outputting the PWM signal to a transistor in the primary circuit according to the hardware fault signal and / or the software fault signal; according to the power electronic device controller, through cooperative work of the DSP and the FPGA, the real-time performance of fault processing of the power electronic device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a controller of a power electronic device and the power electronic device. BACKGROUND

[0002] The power electronic device uses semiconductor power devices such as IGBT (Insulated Gate Bipolar Transistor) to realize efficient conversion and precise control of electric energy. Its main functions include voltage, current or frequency regulation, supporting AC (Alternating Current) / DC (Direct Current) rectification, DC / AC inversion and DC / DC conversion and other energy conversion forms.

[0003] In the prior art, the power electronic device uses DSP (Digital Signal Processor) / MCU (Microcontroller Unit) as the core, and through current transformers and voltage transformers and other sensors, the current and voltage signals in the power system are collected in real time, and after signal conditioning and analog-to-digital conversion, the DSP is used to perform high-speed digital signal processing tasks such as filtering and FFT (Fast Fourier Transform) analysis, or the MCU is responsible for control logic and simple data processing, so as to realize rapid detection and analysis of fault characteristics.

[0004] However, in the prior art, the power electronic device collects signals by means of sensors and processes to realize fault feature detection and analysis, but because the sampling rate of the DSP / MCU is not high, the control period and the sampling rate are the same frequency, resulting in low data acquisition frequency, which leads to poor real-time performance of the power electronic device fault processing. SUMMARY

[0005] The embodiments of the present application provide a controller of a power electronic device and the power electronic device, to solve the problem of poor real-time performance of the power electronic device fault processing.

[0006] In a first aspect, the embodiments of the present application provide a controller of a power electronic device, comprising: a digital signal processor DSP and a field programmable gate array FPGA;

[0007] The DSP is configured to generate a PWM signal and output the PWM signal to the FPGA, and the FPGA is configured to output the PWM signal to a transistor in a primary circuit of the power electronic device.

[0008] The DSP is also configured to output a software fault signal to the FPGA when a software fault is detected in the power electronic device;

[0009] The FPGA is also configured to trigger a hardware fault signal when a hardware fault is detected in the power electronic device, and to stop outputting the PWM signal to the transistor in the primary circuit according to the hardware fault signal and / or the software fault signal.

[0010] In one possible implementation, the DSP includes a software fault detection module and a PWM generation module; the FPGA includes a PWM output module, a fault signal processing module, a pulse blocking module, and a hardware fault detection module;

[0011] The PWM generation module is configured to generate a PWM signal and transmit the PWM signal to the PWM output module; the software fault detection module is configured to output a software fault signal to the FPGA when a software fault is detected in the power electronic device;

[0012] The PWM output module is configured to output the PWM signal to the transistor in the primary circuit; the hardware fault detection module is configured to output a hardware fault signal to the fault signal processing module when a hardware fault is detected in the power electronic device; the fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module when a software fault signal and / or a hardware fault signal is received; and the pulse blocking module is configured to control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit in response to the pulse blocking signal.

[0013] In one possible implementation, a hardware comparison circuit is further included;

[0014] The hardware comparison circuit is configured to compare an electrical signal of a primary circuit of the power electronic device with a reference signal, and output a comparison result signal to the hardware fault detection module;

[0015] The hardware fault detection module is configured to determine whether a hardware fault exists in the power electronic device according to the comparison result signal.

[0016] In one possible implementation, the FPGA further includes a PWM pass-through detection module;

[0017] The PWM pass-through detection module is configured to output a PWM pass-through fault signal to the fault signal processing module when it is detected that the PWM signal output by the PWM output module causes the transistors of the upper and lower bridge arms to pass through;

[0018] The fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module when the PWM pass-through fault signal is received.

[0019] In a possible implementation, the PWM generation module is further configured to output a PWM enable signal to the pulse blocking module.

[0020] The pulse blocking module is configured to control the PWM output module to output the PWM signal to a transistor in the primary circuit when the PWM enable signal is in an enabled state, and control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit when the PWM enable signal is in a disabled state.

[0021] In a possible implementation, the system further comprises an analog quantity conditioning circuit and an analog-digital conversion circuit; the FPGA further comprises an analog quantity sampling module and a bus read-write logic module; and the DSP further comprises a bus read-write module.

[0022] The analog quantity conditioning circuit is configured to perform voltage conversion on an electrical signal of the primary circuit.

[0023] The analog-digital conversion circuit is configured to perform analog-digital conversion on the electrical signal subjected to voltage conversion.

[0024] The analog quantity sampling module is configured to sample a signal output by the analog-digital conversion circuit.

[0025] The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the bus read-write module according to a preset period.

[0026] In a possible implementation, the system further comprises a data bus; and the bus read-write logic module and the bus read-write module perform data transmission through the data bus.

[0027] The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the data bus according to the preset period, trigger a synchronization signal to the bus read-write module, and release control over the read-write permission of the data bus.

[0028] The bus read-write module is configured to read the signal sampled by the analog quantity sampling module from the data bus after obtaining the read-write permission of the data bus.

[0029] In a possible implementation, the system further comprises a memory.

[0030] The fault signal processing module is configured to trigger a fault saving signal to the bus read-write logic module when any fault signal is received.

[0031] The bus read-write logic module is configured to transmit the signal sampled by the analog sampling module to the memory through the data bus in response to the fault saving signal.

[0032] In a possible implementation, the PWM output module is configured to output the PWM signal to a transistor in the primary circuit after adding a dead time.

[0033] In a second aspect, an embodiment of the present application provides an electric power electronic device, and the electric power electronic device comprises the controller provided in the above.

[0034] The controller of the electric power electronic device provided in the embodiments of the present application comprises a digital signal processor (DSP) and a field programmable gate array (FPGA). The DSP is configured to generate a pulse width modulation (PWM) signal and output the PWM signal to the FPGA. The FPGA is configured to output the PWM signal to a transistor in a primary circuit of the electric power electronic device. The DSP is further configured to output a software fault signal to the FPGA when detecting that the electric power electronic device has a software fault. The FPGA is further configured to trigger a hardware fault signal when detecting that the electric power electronic device has a hardware fault, and to stop outputting the PWM signal to the transistor in the primary circuit according to the hardware fault signal and / or the software fault signal. The controller of the electric power electronic device cooperates with the DSP and the FPGA to improve the real-time performance of fault processing of the electric power electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0036] Figure 1 A structural schematic diagram of the controller of the electric power electronic device provided in the embodiments of the present application;

[0037] Figure 2 A structural schematic diagram of the electric power electronic device provided in the embodiments of the present application.

[0038] The above-described accompanying drawings have shown the specific embodiments of the present application, and the following will have a more detailed description. These accompanying drawings and the written description are not intended to limit the scope of the concept of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0039] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, like reference numerals refer to like elements unless indicated otherwise. The implementations described in the following exemplary embodiments are not meant to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0040] Power electronics devices can efficiently realize power conversion and precise control by virtue of the powerful performance of semiconductor power devices (such as IGBT). They have a wide range of functions, can flexibly adjust voltage, current or frequency, and widely support various energy conversion forms such as AC / DC rectification, DC / AC inversion and DC / DC conversion.

[0041] In the prior art, power electronics devices usually use DSP / MCU as the core control unit. With the help of various sensors such as current transformers and voltage transformers, it can real-time and accurately collect current and voltage signals in the power system. The collected signals will go through a series of processing procedures, including signal conditioning and analog-to-digital conversion, to ensure that the quality and format of the signals meet the subsequent processing requirements. Then, DSP is used to perform high-speed digital signal processing tasks such as filtering, or MCU is responsible for control logic and simple data processing work, so as to achieve rapid detection and analysis of fault characteristics, and provide protection for stable operation of power electronics devices.

[0042] However, in the prior art, the sampling rate of DSP / MCU is relatively low, and the control period and the sampling rate are kept at the same frequency, which greatly limits the data acquisition frequency and cannot timely and comprehensively obtain the operation information of the power system, resulting in poor real-time performance of the power electronics device fault processing.

[0043] To solve the above problems, the controller of the power electronics device provided by the present application takes digital signal processor (DSP) and field programmable gate array (FPGA) as the core components, builds a cooperative working mechanism, DSP is responsible for generating PWM (Pulse Width Modulation) signal and outputting to FPGA, and then FPGA transmits the signal to the transistor in the primary circuit to realize control; at the same time, DSP is given the ability to detect software faults and output software fault signals to FPGA, and FPGA is given the ability to detect hardware faults and trigger hardware fault signals, and finally FPGA stops PWM signal output according to hardware or software fault signals. The power electronics device controller works cooperatively with DSP and FPGA, which improves the real-time performance of the power electronics device fault processing.

[0044] The technical solutions of the present application and how the technical solutions solve the above technical problems will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described again in some examples. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0045] Figure 1 The structural schematic diagram of the controller of the power electronic device provided by the present application is shown in FIG. 1, which is a controller of a power electronic device, comprising a digital signal processor (DSP) and a field programmable gate array (FPGA). Figure 1

[0046] The DSP is used to generate a PWM signal and output the PWM signal to the FPGA, and the FPGA is used to output the PWM signal to a transistor in a primary circuit of the power electronic device.

[0047] The DSP is also used to output a software fault signal to the FPGA when a software fault of the power electronic device is detected.

[0048] The FPGA is also used to trigger a hardware fault signal when a hardware fault of the power electronic device is detected, and to stop outputting the PWM signal to the transistor in the primary circuit according to the hardware fault signal and / or the software fault signal.

[0049] The digital signal processor (DSP) is a microprocessor specially used for efficient processing of digital signals.

[0050] The field programmable gate array (FPGA) is a semiconductor device that can configure hardware logic through programming, which is composed of a large number of programmable logic units, interconnection resources and special modules inside.

[0051] The DSP is the control core of the power electronic device, responsible for calculating key parameters such as duty cycle, frequency and phase of the PWM signal. The DSP adjusts the PWM waveform in real time based on the control algorithm of the power electronic device (such as SVPWM (Space Vector Pulse Width Modulation) or SPWM (Sinusoidal Pulse Width Modulation)) to meet the accurate regulation requirements of voltage, current or power.

[0052] ​The PWM signal generated by the DSP is transmitted to the FPGA through the GPIO (General Purpose Input / Output). The FPGA uses its programmable hardware logic to further process the received PWM signal, such as: dead time insertion: prevents the short circuit of the upper and lower bridge arm transistors, ensures safe switching. Multi-channel PWM signal synchronization: coordinates the timing of multiple switching tubes, improves the stability of power electronic devices. Fault protection: real-time detection of abnormal signals such as overcurrent and overvoltage, and blocking PWM output.

[0053] The PWM signal optimized by the FPGA is finally sent to the primary circuit of the power electronic device through an isolation driving circuit (such as an optocoupler), which controls the switching state of the power transistor (such as IGBT). The parallel processing capability and nanosecond-level response speed of the FPGA enable it to accurately control high-frequency switching actions, ensuring efficient conversion of electrical energy.

[0054] When the DSP runs the control algorithm (such as state detection) of the power electronic device, it will detect the running state of the power electronic device in real time. When a software anomaly (such as algorithm calculation overflow) is detected, the DSP will immediately trigger the internal fault handling program to generate a software fault signal.

[0055] After detecting the software fault, the DSP transmits the fault signal to the FPGA in real time through a high-speed digital interface (such as GPIO). After receiving the fault signal from the DSP, the FPGA immediately intervenes in the hardware protection mechanism, such as: blocking PWM output: forcibly closes all driving signals to prevent power devices from being damaged due to control anomalies.

[0056] The FPGA directly detects key hardware signals of the power electronic device through hardware logic, such as: overcurrent / overvoltage signals: abnormal values from current / voltage sensors, triggered after comparison or ADC threshold determination. Temperature overrun: detects power device overheating through temperature sensor digital interface or analog signal.

[0057] The controller of the power electronic device provided in the application comprises: a digital signal processor DSP and a field programmable gate array FPGA; the DSP is used to generate a PWM signal and output the PWM signal to the FPGA, and the FPGA is used to output the PWM signal to a transistor in a primary circuit of the power electronic device; the DSP is also used to output a software fault signal to the FPGA when a software fault of the power electronic device is detected; the FPGA is also used to trigger a hardware fault signal when a hardware fault of the power electronic device is detected, and to stop outputting the PWM signal to the transistor in the primary circuit according to the hardware fault signal and / or the software fault signal; the power electronic device controller cooperates with the DSP and the FPGA to improve the real-time performance of the fault handling of the power electronic device.

[0058] In an alternative implementation, the DSP includes a software fault detection module and a PWM generation module; the FPGA includes a PWM output module, a fault signal processing module, a pulse blocking module and a hardware fault detection module;

[0059] The PWM generation module is configured to generate a PWM signal and transmit the PWM signal to the PWM output module; the software fault detection module is configured to output a software fault signal to the FPGA in the case that a software fault of the power electronic device is detected;

[0060] The PWM output module is configured to output the PWM signal to a transistor in a primary circuit; the hardware fault detection module is configured to output a hardware fault signal to the fault signal processing module in the case that a hardware fault of the power electronic device is detected; the fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module in the case that the software fault signal and / or the hardware fault signal is received; and the pulse blocking module is configured to control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit in response to the pulse blocking signal.

[0061] The software fault detection module is an intelligent fault management power electronic device with multi-source cooperation, which detects software algorithm faults (such as overvoltage, overcurrent, etc. digital filter signal) and hardware fault flags uploaded by the FPGA (triggered by GPIO interruption) of the power electronic device in real time. A "double-channel verification mechanism" (software algorithm verification + hardware signal review) is adopted, and when the fault is confirmed, a dynamic blocking instruction (enable signal hardware zero) is sent to the PWM generation module and a fault code with a time stamp is transmitted to the FPGA fault processing module through a high-speed serial port.

[0062] The PWM generation module is a precise pulse control unit based on a hardware timer, which generates PWM pulse signals through an embedded PWM controller (such as ePWM (Enhanced Pulse Width Modulator)). The module can generate high-precision driving signals with adjustable frequency (1 kHz-1 MHz), accurate duty cycle (0-100%) and controllable phase in real time, and integrates core functions such as dead time insertion, fast fault shutdown and synchronous triggering. The generated PWM pulse signal is transmitted to the FPGA for subsequent processing through a high-speed GPIO interface, and the PWM enable signal is used as a global switch control signal, which can dynamically respond to the blocking instruction of the software fault detection module to achieve fast shutdown.

[0063] PWM output module is a hardware-level signal conditioning unit, which directly receives the PWM pulses sent by the PWM generation module of DSP through dedicated digital logic, and performs the key dead-time insertion operation: for falling edge signals, it uses straight-through output to ensure fast turn-off, while for rising edge signals, it applies a preset dead-time (e.g. 50ns-5μ adjustable) through a programmable delay counter (step precision up to 5ns) to ensure that the driving signals of upper and lower bridge power devices (e.g. IGBT) strictly avoid the risk of overlapping conduction.

[0064] The fault signal processing module receives and processes software fault flags (e.g. algorithm overflow) from DSP and local hardware fault detection signals (e.g. overcurrent, overvoltage comparator outputs) in real time through parallel digital logic. When any fault flag is detected as valid, an asynchronous blocking signal is immediately sent to the PWM output module through dedicated wiring.

[0065] The pulse blocking module receives two types of key input signals in real time through a dual-channel detection mechanism: the PWM enable signal of DSP (high level valid) and the fault trigger signal of the fault processing module. When either condition is met, i.e. the DSP enable signal is invalid (low level) or the fault signal is valid (high level), an asynchronous blocking signal is immediately sent to the PWM output module through a dedicated hardware path, forcing all PWM output channels to be turned off within 50ns.

[0066] The hardware fault detection module is an anti-interference detection unit based on edge triggering, which captures the rising edge of the input fault signal (e.g. overcurrent / overvoltage comparator output) in real time through a comparator, and uses a jitter prevention processing mechanism (including clock synchronization sampling, continuous period verification and minimum pulse width filtering) to eliminate transient interference. After confirming a valid fault edge (duration > 100ns), the module transmits the shaped fault pulse to the fault signal processing module through a low-delay path (< 20ns), while recording the precise timestamp of the fault trigger, ensuring the reliable transmission and timing traceability of the hardware fault signal.

[0067] The PWM generation module of DSP transmits signals to the PWM output module of FPGA through the GPIO port for subsequent conditioning and driving; at the same time, the software fault detection module in DSP continuously monitors the algorithm running state (e.g. data overflow, communication anomaly, etc.), and when a software fault is detected, it immediately outputs a software fault signal to the fault processing module of FPGA through the interrupt pin or dedicated digital interface, triggering the protection mechanism of the power electronic device to block the PWM output, ensuring the safe operation of the power electronic device.

[0068] The PWM output module is responsible for outputting the regulated PWM signal (including dead time) to the power transistor (such as IGBT) in the primary circuit to control its switching action; the hardware fault detection module detects the circuit state (such as overcurrent, overvoltage) in real time, and immediately sends a hardware fault signal to the fault signal processing module when a hardware fault is detected; after receiving the software fault signal (from the DSP) and / or the hardware fault signal, the fault signal processing module generates a pulse blocking signal through priority arbitration and transmits it to the pulse blocking module; the module immediately forces all channels of the PWM output module to shut down with nanosecond-level response, ensuring that the power transistor stops working immediately, thereby achieving fast and safe protection of the hardware.

[0069] In an optional implementation, the controller further comprises a hardware comparison circuit;

[0070] The hardware comparison circuit is configured to compare the electrical signal of the primary circuit of the power electronic device with the reference signal and output a comparison result signal to the hardware fault detection module;

[0071] The hardware fault detection module is configured to determine whether the power electronic device has a hardware fault according to the comparison result signal.

[0072] The hardware comparison circuit is an analog protection unit based on a high-speed voltage comparator, which compares the current / voltage signal output by the analog quantity conditioning circuit (converted into a standard voltage U) with a precise reference voltage (set by a voltage stabilizer or a DAC (Digital-to-Analog Converter)) in real time; when it is detected that U exceeds the preset threshold, the circuit outputs a digital high-level fault signal, and uses a hysteresis comparison design to prevent signal jitter and false triggering, and its output directly drives the hardware fault detection module of the FPGA.

[0073] The hardware comparison circuit collects the electrical signal (such as the collector current of IGBT or the DC bus voltage) of the primary circuit in real time through a high-speed voltage comparator, and compares it with the reference voltage after converting it into a voltage signal; when it is detected that the electrical signal exceeds the safety threshold, the circuit outputs a digital comparison result signal (high / low level), which is directly sent to the hardware fault detection module of the FPGA through optical coupling isolation or differential transmission, thereby providing a bottom-level fast protection channel for the power electronic device that does not depend on software processing, and ensuring that the power device can be quickly turned off at the hardware level under dangerous working conditions such as overcurrent and overvoltage.

[0074] The hardware fault detection module detects the comparison result signal from the hardware comparison circuit in real time through dedicated hardware logic, determines an effective hardware fault when a continuously effective overrun signal (such as a high level duration > 500 ns) is detected, and generates a fault identification signal with a time stamp through a priority encoder.

[0075] In an optional implementation, the FPGA further includes a PWM pass-through detection module.

[0076] The PWM pass-through detection module is configured to output a PWM pass-through fault signal to the fault signal processing module when it is detected that the PWM signal output by the PWM output module causes the transistors of the upper and lower bridge arms to pass through.

[0077] The fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module when the PWM pass-through fault signal is received.

[0078] The PWM pass-through detection module is a real-time safety detection unit based on hardware logic, which detects the upper and lower bridge arm drive signals sent by the DSP in real time through a high-speed timing analysis circuit. When it is identified that the complementary PWM signals have a risk of overlapping conduction (insufficient dead time or abnormal edges), the module immediately triggers the protection mechanism: forcibly blocks all PWM channels through a dedicated hardware path; and feeds back a fault signal to the DSP.

[0079] The PWM pass-through detection module is a hardware protection unit based on nanosecond-level timing analysis, which monitors the upper and lower bridge arm drive signals generated by the PWM output module in real time through a high-speed digital comparator. When it is detected that the complementary PWM signals have a dangerous state such as insufficient dead time, edge overlap, or abnormal synchronization, which may cause IGBT pass-through short circuit, the module immediately outputs a PWM pass-through fault signal with a phase marker to the fault signal processing module, and ensures that the signal transmission is not affected by the FPGA logic delay through a hardware interlocking mechanism.

[0080] After receiving the PWM pass-through fault signal transmitted by the PWM pass-through detection module, the fault signal processing module immediately starts the highest priority hardware protection process, and outputs a pulse blocking signal to the pulse blocking module through a dedicated hardware link; the signal will bypass the conventional logic arbitration and directly trigger the asynchronous reset end of the pulse blocking module, ensuring that all PWM channels are forcibly turned off within the critical time before the upper and lower bridge arm power tubes (such as IGBT) pass through and short circuit, and automatically recording the accurate time stamp and corresponding phase information of the pass-through event.

[0081] In an optional implementation, the PWM generation module is further configured to output a PWM enable signal to the pulse blocking module.

[0082] The pulse blocking module is configured to control the PWM output module to output the PWM signal to the transistor in the primary circuit when the PWM enable signal is in an enabled state, and control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit when the PWM enable signal is in a disabled state.

[0083] The PWM generation module of the DSP outputs a PWM enable signal (high / low level programmable configuration) to the pulse blocking module of the FPGA through a special control pin, which serves as a global switch control flag for the PWM output: when the enable signal is valid (such as high level), the PWM signal is allowed to be normally transmitted, and when a module internal fault or a protection instruction is received, the enable signal is immediately set to an invalid state (such as pulled down to 0V), and the pulse blocking action is triggered through a hardware direct connection path, realizing seamless cooperation with the FPGA protection power electronic device.

[0084] The pulse blocking module, as the final hardware switch for the PWM output, controls the power path by real-time detection of the PWM enable signal state (high level enabled / low level disabled) sent by the DSP: when the enable signal is in a valid high level, the module releases the blocking to allow the PWM output module to transmit the processed driving signal to the primary circuit power transistor (such as IGBT); once the enable signal becomes low level (including active control instruction or fault triggering), the module immediately activates the hardware blocking logic to cut off the output of all PWM channels to the power device, which not only supports normal software PWM start-stop control, but also ensures nanosecond-level synchronization with the fault protection power electronic device in emergency.

[0085] In an optional implementation, the controller further comprises an analog quantity conditioning circuit and an analog-digital conversion circuit; the FPGA further comprises an analog quantity sampling module and a bus read-write logic module; the DSP further comprises a bus read-write module;

[0086] The analog quantity conditioning circuit is configured to perform voltage conversion on the electrical signal of the primary circuit;

[0087] The analog-digital conversion circuit is configured to perform analog-digital conversion on the electrical signal subjected to the voltage conversion;

[0088] The analog quantity sampling module is configured to sample the signal output by the analog-digital conversion circuit;

[0089] The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the bus read-write module according to a preset period.

[0090] Among them, the analog quantity conditioning circuit is a high-precision signal conversion and conditioning unit, and its core function is to convert the high voltage / current signal (such as bus voltage, power tube current) in the primary loop into a weak current signal (such as 0-3.3V voltage range) through a sensor interface (Hall effect or shunt) and a signal conditioning chain (including precision operational amplifier, voltage divider network and filter circuit).

[0091] The analog-to-digital conversion circuit (ADC circuit) is a high-precision signal digitizing unit, which converts the standardized weak current signal (0-3.3V range) output by the analog quantity conditioning circuit into a digital signal through a high-speed ADC chip; through SPI or parallel bus, the digital quantity is transmitted to DSP / FPGA in real time, providing accurate data input for closed-loop control and fault diagnosis, and is a bridge connecting analog signals and digital processing power electronic devices.

[0092] The analog quantity sampling module is a periodic data acquisition and transmission unit, which is triggered by a hardware timer and reads digital signals (such as 16-bit conversion results of three-phase current / voltage) from a multi-channel ADC module synchronously according to a preset sampling period (such as 100μs).

[0093] The bus read-write logic module is a multifunctional data management hub, and its core functions include: generating a synchronous signal (such as 1kHz) through a hardware counter, triggering the GPIO interrupt of the DSP when the counter overflows, and transferring the bus control right; using the DMA (Direct Memory Access) channel to package the latest sampling data (such as three-phase current / voltage) into a data frame and transmit it to the DSP in real time through the parallel bus; integrating a double-buffer storage architecture, which writes the sampling data into the SRAM (Static Random-Access Memory) in a loop during normal operation, activates the fault snapshot function immediately when a fault flag is set, saves the waveform data (including timestamp and fault type) before and after the fault, and ensures that critical data is not lost through hardware priority logic, providing nanosecond-level response data collaboration management capability for power electronic devices.

[0094] The bus read-write module of the DSP is a hardware-level data communication control unit, which manages the access permission and transmission timing of the data bus through a programmable state machine. After receiving the cycle trigger signal of the bus read-write logic module of the FPGA, the module immediately starts the bus arbitration protocol: first, it acquires the bus control right (waiting time < 100 ns), then it reads the analog sampling data from the SRAM or buffer register according to the predefined data frame format (including address, sample value, CRC check), and transmits the data packet to the DSP through the high-speed parallel bus; after the transmission is completed, it automatically releases the bus and feeds back the status flag.

[0095] In an optional implementation, the controller further comprises a data bus; the bus read-write logic module and the bus read-write module perform data transmission through the data bus.

[0096] The bus read-write logic module is configured to transmit the signal sampled by the analog sampling module to the data bus according to a preset period, trigger a synchronization signal to the bus read-write module of the DSP, and release the control of the read-write permission of the data bus.

[0097] The bus read-write module of the DSP is configured to read the signal sampled by the analog sampling module from the data bus after acquiring the read-write permission of the data bus.

[0098] The data bus is a high-speed digital communication channel that can transmit analog sampling data, control instructions and status information in real time, and is the core data transmission framework for building a distributed power electronic control power electronic device.

[0099] In an optional implementation, the controller further comprises a memory.

[0100] The fault signal processing module is configured to trigger a fault saving signal to the bus read-write logic module in the case of receiving any fault signal.

[0101] The bus read-write logic module is configured to transmit the signal sampled by the analog sampling module to the memory through the data bus in response to the fault saving signal.

[0102] The memory is a digital information storage unit, which uses a high-speed volatile memory chip (such as SRAM / SDRAM (Synchronous Dynamic Random-Access Memory, Synchronous Dynamic Random-Access Memory)), is connected with the processor (DSP / FPGA) through the data bus, and is used for buffering real-time sampling data (such as ADC conversion results) or storing power electronic device parameters (such as fault records). The module integrates an address decoder, a read-write controller and an error checking mechanism, supports nanosecond-level access delay and million-time erasing and writing life, and is a key hardware basis for guaranteeing the execution of the control algorithm and the historical data tracing.

[0103] The fault signal processing module sends a fault save signal to the bus read-write logic module through a dedicated hardware link immediately upon detecting any one of a software fault signal, a hardware fault signal, or a PWM pass-through fault signal.

[0104] Upon receiving the fault save signal sent by the fault signal processing module, the DSP bus read-write logic module immediately suspends regular data transmission and initiates a high-priority fault storage process: real-time signals (such as three-phase current and voltage ADC sampling values at the time of fault occurrence) in the analog quantity sampling module buffer register are packaged into a fault data frame along with a timestamp, and then written into a specified address region of the memory in DMA mode, with a CRC check code automatically attached to ensure the integrity and traceability of critical fault data.

[0105] In an optional implementation, the PWM output module is configured to output the PWM signal to a transistor in the primary circuit after adding a dead time.

[0106] The PWM output module is responsible for hardware-level conditioning of the PWM signal generated by the DSP to ensure safe switching of power devices (such as IGBTs). The core function of this module is to insert a dead time to prevent short circuit caused by signal overlap of upper and lower bridge arm transistors.

[0107] Specific implementation of dead time insertion: falling edge pass-through: for turn-off signals (falling edge), the PWM output module adopts a pass-through output strategy to ensure that the power device can be quickly turned off and reduce switching loss. Rising edge delay: for turn-on signals (rising edge), the module applies a user-set dead time (typical value 50ns~5μs adjustable) through a programmable counter to ensure that the drive signals of complementary bridge arms are not turned on at the same time.

[0108] The PWM output module is built-in with a high-precision timer. The module detects the timing of the PWM signal in real time and can trigger hardware-level protection in case of abnormality to ensure safe operation of the power electronic device. Finally, the conditioned PWM signal is output to the power transistor of the primary circuit to achieve efficient and reliable switching control.

[0109] Figure 2 The structure diagram of the controller of the power electronic device provided in the present application is shown in FIG. 1, and the power electronic device provided in the present application comprises the controller as any one of the above. Figure 2 The structure diagram of the controller of the power electronic device provided in the present application is shown in FIG. 1, and the power electronic device provided in the present application comprises the controller as any one of the above.

[0110] A power electronic device (such as inverter, rectifier or motor driver) integrates a high-performance controller which adopts a DSP+FPGA collaborative architecture: DSP is responsible for algorithm generation and system-level control, FPGA implements hardware-level signal processing and nanosecond-level protection, both of which are interconnected through bus and GPIO, forming a control system which takes into account flexibility and real-time performance.

[0111] Through the multi-level fault protection system (including software detection, hardware comparison and PWM pass-through detection) and the precise PWM management module (dead zone control and dynamic blocking) of the controller, the device can respond to abnormal conditions such as overcurrent and overvoltage within μs, ensuring the safe operation of power devices.

[0112] The power electronic device significantly improves dynamic response speed (fault handling <1 μs) and reliability thanks to the hardware acceleration capability (FPGA implements signal conditioning) and the layered protection mechanism (software / hardware / PWM pass-through triple protection) of the controller.

[0113] Finally, it should be noted that: after considering the specification and practicing the invention disclosed herein, other embodiments of the invention will be easily conceived by those skilled in the art. The invention is intended to cover any variations, uses or adaptations of the invention which follow the general principles of the invention and include common knowledge or conventional technical means in the art which are not disclosed by the invention, and is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the invention is only limited by the appended claims.

Claims

1. A controller of a power electronic device, characterized by, The application relates to a power electronic device, comprising: a digital signal processor (DSP) and a field programmable gate array (FPGA); the DSP is configured to generate a pulse width modulation (PWM) signal and output the PWM signal to the FPGA, and the FPGA is configured to output the PWM signal to a transistor in a primary circuit of the power electronic device; the DSP is further configured to output a software fault signal to the FPGA when a software fault of the power electronic device is detected; the FPGA is further configured to trigger a hardware fault signal when a hardware fault of the power electronic device is detected, and to stop outputting the PWM signal to the transistor in the primary circuit according to the hardware fault signal and / or the software fault signal.

2. The controller of claim 1, wherein, The DSP comprises a software fault detection module and a PWM generation module, and the FPGA comprises a PWM output module, a fault signal processing module, a pulse blocking module and a hardware fault detection module; the PWM generation module is configured to generate a PWM signal and transmit the PWM signal to the PWM output module; the software fault detection module is configured to output a software fault signal to the FPGA when a software fault of the power electronic device is detected; the PWM output module is configured to output the PWM signal to the transistor in the primary circuit; the hardware fault detection module is configured to output a hardware fault signal to the fault signal processing module when a hardware fault of the power electronic device is detected, the fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module when a software fault signal and / or a hardware fault signal is received, and the pulse blocking module is configured to control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit in response to the pulse blocking signal.

3. The controller of claim 2, wherein, The application further comprises a hardware comparison circuit; the hardware comparison circuit is configured to compare an electrical signal of the primary circuit of the power electronic device with a reference signal and output a comparison result signal to the hardware fault detection module; the hardware fault detection module is configured to determine whether a hardware fault exists in the power electronic device according to the comparison result signal.

4. The controller of claim 2, wherein, The FPGA further comprises a PWM pass-through detection module; the PWM pass-through detection module is configured to output a PWM pass-through fault signal to the fault signal processing module when it is detected that the PWM signal output by the PWM output module causes the transistors of upper and lower bridge arms to pass through; the fault signal processing module is configured to output a pulse blocking signal to the pulse blocking module when the PWM pass-through fault signal is received.

5. The controller of claim 2, wherein, The PWM generation module is further configured to output a PWM enable signal to the pulse blocking module. The pulse blocking module is configured to control the PWM output module to output the PWM signal to a transistor in the primary circuit when the PWM enable signal is in an enabled state, and control the PWM output module to stop outputting the PWM signal to the transistor in the primary circuit when the PWM enable signal is in a disabled state.

6. The controller of claim 2, wherein, The analog quantity conditioning circuit and the analog-digital conversion circuit are further included; the analog quantity sampling module and the bus read-write logic module are further included in the FPGA; and the bus read-write module is further included in the DSP. The analog quantity conditioning circuit is configured to perform voltage conversion on an electrical signal of the primary circuit. The analog-digital conversion circuit is configured to perform analog-digital conversion on the electrical signal subjected to voltage conversion. The analog quantity sampling module is configured to sample a signal output by the analog-digital conversion circuit. The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the bus read-write module according to a preset period.

7. The controller of claim 6, wherein, Further comprising: a data bus; the bus read-write logic module and the bus read-write module perform data transmission through the data bus; The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the data bus according to the preset period, trigger a synchronization signal to the bus read-write module, and release the control on the read-write permission of the data bus; The bus read-write module is configured to read the signal sampled by the analog quantity sampling module from the data bus after obtaining the read-write permission of the data bus.

8. The controller of claim 7, wherein, Further comprising: a memory; The fault signal processing module is configured to trigger a fault saving signal to the bus read-write logic module when receiving any fault signal; The bus read-write logic module is configured to transmit the signal sampled by the analog quantity sampling module to the memory through the data bus in response to the fault saving signal.

9. The controller of claim 2, wherein, The PWM output module is configured to output the PWM signal to the transistor in the primary circuit after adding a dead time.

10. A power electronic device, characterized by The controller according to any one of claims 1-9 is included.

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