Bidirectional programmable direct-current power supply system and control method

Abstract

The invention provides a bidirectional programmable direct-current power supply system and a control method, and belongs to the technical field of direct-current power supplies, the bidirectional programmable direct-current power supply system comprises a loop competition control module and a parallel operation capacity expansion module, the loop competition control module comprises three independent control loops of a voltage loop (CV), a current loop (CC) and a power loop (CP), the output end of each loop is connected to a window comparator group, and the judgment threshold range of the window comparator group is-8V to + 8V; the parallel operation capacity expansion module comprises a host signal transmission channel, a slave signal receiving channel and a shared bus (Vshare +), and synchronous transmission of control signals between the host and the slave is controlled through a relay. According to the invention, through a hardware competition mechanism, the window comparator group and the field effect transistor control unit, the software criterion delay is eliminated, the response speed of mode switching is greatly improved, the demand change of the output mode can be responded more timely and accurately, the system operation efficiency is optimized, and the CPU resource occupation is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of direct current power supply, in particular to a bidirectional programmable direct current power supply system and a control method. BACKGROUND

[0002] In the field of bidirectional programmable direct current power supply, the traditional power supply system has deficiencies in mode switching response speed and device power expansion. In mode switching, the response delay caused by relying on software criteria affects the timeliness and accuracy of power output; in device power expansion, it is difficult to achieve seamless expansion, and the flexibility of the system is limited. In addition, noise interference in signal transmission process, high-frequency ripple, overvoltage risk, and line loss voltage drop and impact current during parallel operation also pose challenges to the stability, accuracy and reliability of the power supply system.

[0003] Therefore, a bidirectional programmable direct current power supply system and a control method are proposed. SUMMARY

[0004] The present application aims to solve the problems raised in the background art and provides a bidirectional programmable direct current power supply system and a control method.

[0005] The specific technical solutions are as follows:

[0006] A bidirectional programmable direct current power supply system comprises:

[0007] Loop competition control module: containing voltage loop (CV), current loop (CC), power loop (CP) three independent control loops, the output end of each loop is connected to the window comparator group, and the determination threshold value of the window comparator group is-8V to +8V;

[0008] Parallel expansion module: containing master signal transmission channel, slave signal receiving channel and shared bus (Vshare+), and the synchronous transmission of control signals between master and slave devices is controlled by relays.

[0009] The bidirectional programmable direct current power supply system described above, wherein the loop competition control module comprises:

[0010] The voltage loop (CV) comprises operational amplifier U23B (TL084ID), voltage dividing resistors R204 (5.8k) and R205 (3.3k), feedback resistor R206 (380R), compensation capacitors C108 (100nF) and C157 (100nF); wherein REF_5V is input to the positive input terminal of U23B after being divided by R204 and R205, and the output of U23B is connected to the subsequent circuit through R206;

[0011] The current loop (CC) comprises an operational amplifier U19B (TL084ID), an input resistor R84 (4.7k), and a feedback resistor R86 (33k); wherein the LTC2755_B_LIMIT signal is input to the inverting input terminal of U19B through R84, the +7.926V reference signal is input to the non-inverting input terminal of U19B, and the output of U19B is connected to the gate of field effect transistor Q2 (BSS138).

[0012] The power loop (CP) comprises an operational amplifier U19C (TL084ID), an input resistor R83 (4.7k), and a feedback resistor R85 (33k), which are in a mirror-symmetrical connection relationship with the current loop.

[0013] The bidirectional programmable DC power supply system further comprises a field effect transistor control unit, which comprises:

[0014] Q17 (BSS138), Q2 (BSS138), and Q1 (BSS308PE) respectively receive output signals of the loops, and determine whether they are in the range of -8V-8V through a comparator to control the output of the pull-up circuit to the CPU.

[0015] The bidirectional programmable DC power supply system further comprises a field effect transistor control unit, which comprises:

[0016] The main machine signal transmission channel comprises an operational amplifier U24B (ADA4075-2ARZ), an input resistor R91 (51k), a feedback resistor R92 (1k), balance resistors R94 (51k) and R95 (1k), and a compensation capacitor C99 (33pF); wherein the main machine outer loop signal Vctrl is input to the non-inverting input terminal of U24B through R91, Vshare- is input to the inverting input terminal of U24B through R94, and the output of U24B is transmitted to the relay K1 through R92 and R95.

[0017] The relay K1 (G5V-1 / 2V1A) is driven by field effect transistor Q15 (BSS138), and its on-off is controlled by the CPU, which is used to connect the Vmaster signal and the Vshare+ bus.

[0018] The bidirectional programmable DC power supply system further comprises an anti-interference circuit, which comprises:

[0019] A common-mode suppression inductor L1 (B82793C0475N265), clamping diodes D8 (T2ZMB18) and D9 (T2ZMB18), damping resistors R102 (680R) and R103 (680R), and filter capacitors C101 (1uF) and C98 (470pF) are connected in parallel between the Vshare+ bus and the ground wire.

[0020] The bidirectional programmable DC power supply system, wherein the output logic of the window comparator group is:

[0021] When the voltage loop output is 0-4V, the corresponding comparator output low level, triggering the pull-up circuit to high CV flag signal;

[0022] When the current loop or power loop output exceeds ±8V, the comparator output high level, CC / CP flag signal is pulled to low level.

[0023] The bidirectional programmable DC power supply system, wherein the working process of the parallel expansion module comprises:

[0024] The CPU controls Q15 conduction according to the set number of parallel machines, so that the main machine relay K1 is attracted, and the Vmaster signal is output to the Vshare+ bus;

[0025] The slave machine receives the signal through the Vshare+ bus and controls the local relay to be attracted, so that Vslave is connected with Vshare+, realizing the main machine outer loop signal control of the slave machine inner loop.

[0026] The application also provides a bidirectional programmable DC power supply control method applied to the bidirectional programmable DC power supply system, comprising the following steps:

[0027] Loop competition control step: real-time monitoring of each loop output voltage, if the CV loop output is in the range of 0-4V and the CC / CP loop output exceeds ±8V, it is determined as constant voltage mode;

[0028] Parallel machine synchronization step: the main machine transmits the outer loop signal Vctrl to the Vshare+ bus after proportional amplification, and the slave machine obtains the signal through the bus and injects the inner loop given value.

[0029] The bidirectional programmable DC power supply control method, wherein it further comprises:

[0030] Line loss compensation step: inserting an adjustable gain operational amplifier in the parallel machine signal transmission path, dynamically increasing the output gain of the main machine according to the wire resistance to offset the pressure drop.

[0031] The bidirectional programmable DC power supply control method, wherein it further comprises:

[0032] Interference suppression step: a magnetic ring is connected in series in the Vshare+ bus, and an RC filter network (C101, R102) is connected in parallel to the ground to absorb high-frequency ripple.

[0033] The application has the following beneficial effects:

[0034] 1. Mode switching response aspect: through the hardware competition mechanism, the window comparator group and the field effect tube control unit are utilized, the software criterion delay is eliminated, the response speed of mode switching is greatly improved, the demand change of output mode can be responded more timely and accurately, the system operation efficiency is optimized, and the CPU resource occupation is reduced.

[0035] 2. Equipment power expansion aspect: the parallel expansion module realizes seamless expansion of equipment power, improves the system flexibility, and can flexibly expand the current, power level and the like of the power supply equipment according to actual needs. Meanwhile, through active compensation of line loss voltage drop and suppression of parallel machine impact current, the current sharing accuracy of multi-machine parallel connection is improved, and the precise synchronization of master and slave equipment is realized.

[0036] 3. Signal transmission stability aspect: the low noise characteristic of the operational amplifier in the parallel expansion module improves the parallel machine signal transmission quality and reduces noise interference; the anti-interference circuit effectively suppresses high-frequency ripple, limits the risk of bus overvoltage, protects the safety of the rear-stage circuit, enhances the electromagnetic compatibility and anti-transient impact capability of the system, and guarantees stable and reliable operation of the power supply system. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A novel loop competition circuit architecture diagram of a bidirectional programmable direct current power supply is provided for the embodiments of the present application.

[0038] Figure 2 A voltage loop (CV) circuit diagram is provided for the embodiments of the present application.

[0039] Figure 3 A current loop (CC) circuit diagram is provided for the embodiments of the present application.

[0040] Figure 4 A power loop (CP) circuit diagram is provided for the embodiments of the present application.

[0041] Figure 5 A parallel expansion module circuit diagram is provided for the embodiments of the present application.

[0042] Figure 6 A parallel anti-interference circuit diagram is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0043] The technical solutions of the present application will be further described below by combining the drawings and through specific embodiments.

[0044] Among them, the drawings are only used for illustrative description, and the representation is only a schematic diagram, not a physical diagram, and cannot be understood as a limitation on the present patent; in order to better illustrate the embodiments of the present application, some components of the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some known structures and their descriptions in the drawings can be omitted.

[0045] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only used for exemplary illustration and cannot be understood as a limitation of the present patent, for those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0046] In the description of the present application, unless otherwise explicitly specified and limited, if the term "connection" and the like indicating the connection relationship between components appears, the term should be interpreted broadly, for example, it can be a fixed connection, or a detachable connection, or integrated; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the internal communication of two components or the interaction relationship between two components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0047] Embodiment 1

[0048] The bidirectional programmable DC power supply system provided by the present embodiment is shown in the following figure, wherein: Figures 1-4

[0049] Figure 1 : Novel loop competition circuit architecture diagram of bidirectional programmable DC power supply

[0050] Description:

[0051] The overall architecture of the loop competition control module is shown in the following figure, which includes three independent control loops of voltage loop (CV), current loop (CC) and power loop (CP), and the output ends of each loop are connected to a window comparator group (threshold range -8V~+8V).

[0052] Core logic: through the comparator, it is determined in real time whether the output of each loop is in the effective interval (-8V~+8V), and the hardware competition mechanism (pull-up / pull-down signal) is triggered, and finally the CPU reads the loop state (CV / CC / CP mode).

[0053] Figure 2 : Circuit diagram of voltage loop (CV)

[0054] Description:

[0055] ​Core components: op-amp U23B (TL084ID), voltage divider resistors R204 (6.8kΩ) and R205 (unlabeled, presumably used in conjunction with R204 for voltage division), feedback resistor R206 (unlabeled), compensation capacitors C108 (100nF) and C157 (100nF).

[0056] Signal path:

[0057] REF_5V is input to the positive input terminal of U23B after being divided by R204 and R205, forming a voltage set signal.

[0058] The output of U23B is fed back to the negative input terminal through R206, forming a closed-loop control; at the same time, it is output to the subsequent comparator for determining whether it is within the 0-4V valid range.

[0059] Design points: voltage divider resistors and compensation capacitors suppress temperature drift and improve the accuracy of constant voltage mode.

[0060] Figure 3 : Current loop (CC) circuit diagram

[0061] Explanation:

[0062] Core components: op-amp U19B (TL084ID), input resistor R84 (4.7kΩ), feedback resistor R86 (33kΩ), and field-effect transistor Q2 (BSS138).

[0063] Signal path:

[0064] LTC2755_B_LIMIT signal (current set) is input to the negative input terminal of U19B through R84, and +7.926V reference voltage is input to the positive input terminal.

[0065] The output of U19B drives the gate of Q2 to control the current loop output; at the same time, it is output to the comparator to determine whether it exceeds the ±8V range.

[0066] Symmetry design: mirror symmetry with power loop (CP) (e.g., R83 / R85 corresponding to R84 / R86), ensuring consistent loop gain.

[0067] Figure 4 : Power loop (CP) circuit diagram

[0068] Explanation:

[0069] Core components: op-amp U19C (TL084ID), input resistor R83 (4.7kΩ), feedback resistor R85 (33kΩ), and field-effect transistor Q1 (BSS308PE).

[0070] Signal path:

[0071] LTC2755_D_LIMIT signal (power given) through R83 input U19C input, +7.926V reference voltage input positive input.

[0072] U19C output drive Q1 gate, control power ring output; output to the comparator, determine whether to exceed the interval of ±8V.

[0073] With the current loop relationship: mirror symmetry design, to ensure the balance of double loop control, to avoid competition oscillation.

[0074] Figure 5 : parallel expansion module circuit diagram

[0075] Description:

[0076] Host signal transmission channel:

[0077] Op-amp U24B (ADA4075-2ARZ), input resistance R91 (51kΩ), feedback resistance R92 (1kΩ), balance resistance R94 (51kΩ), R95 (1kΩ), compensation capacitor C99 (33pF).

[0078] Host outer ring signal Vctrl through R91 input U24B positive input, Vshare- through R94 input negative input, U24B output through R92, R95 proportional amplification after the generation of Vmaster signal.

[0079] Control unit:

[0080] Field effect transistor Q15 (BSS138) drive relay K1 (G5V-1 / 2V1A), CPU control K1 attraction, Vmaster signal access Vshare+ bus.

[0081] Slave synchronization: slave through Vshare+ bus to receive Vmaster signal, through the local relay connected to Vslave, realize the host outer ring control of the slave inner ring.

[0082] Figure 6 : parallel anti-interference circuit diagram

[0083] Description:

[0084] Core components:

[0085] Common mode suppression inductance L1 (B82793C0475N265), clamp diode D8 / D9 (T2ZMB18), damping resistance R102 / R103 (680Ω), filter capacitor C101 (1μF), C98 (470pF).

[0086] Anti-interference mechanism:

[0087] High-frequency filter: L1 and C98 form a π-type network to suppress high-frequency ripple of Vshare+ bus.

[0088] Overvoltage protection: D8 / D9 clamps the bus voltage within ±18V to prevent surge impact.

[0089] Low-frequency filter: C101 and R102 / R103 absorb low-frequency noise to improve signal stability.

[0090] SUMMARY OF DRAWINGS

[0091] Figures 1-4 : Around the loop competition control module, show three independent loop circuit structure, element parameters and signal flow, highlight the hardware competition mechanism and anti-interference design.

[0092] Figures 5-6 : Focus on and machine expansion module, presents the master-slave signal transmission path, relay control logic and anti-interference circuit details, embodies seamless expansion and stability optimization.

[0093] OVERALL EFFECT: Through the diagram, the circuit topology, element connection relationship and key technical points (such as symmetry design, proportional amplification, filter protection, etc.) are presented intuitively to assist understanding of the hardware implementation scheme of the present application.

[0094] The bidirectional programmable DC power supply system comprises a loop competition control module and a parallel machine expansion module, wherein:

[0095] The loop competition control module comprises three independent control loops of voltage loop (CV), current loop (CC) and power loop (CP), and the output ends of the loops are connected to a window comparator group, and the determination threshold range of the window comparator group is-8V to +8V.

[0096] The parallel machine expansion module comprises a master signal transmission channel, a slave signal receiving channel and a shared bus (Vshare+), and the synchronization transmission of control signals between the master and slave devices is realized through the relay control.

[0097] Through the hardware competition mechanism, the software criterion delay is eliminated, the mode switching response speed is significantly improved, the device power is seamlessly expanded, and the system flexibility is greatly improved.

[0098] Specifically, in the present embodiment, in the loop competition control module:

[0099] The voltage loop (CV) comprises an operational amplifier U23B (TL084ID), voltage dividing resistors R204 (5.8k) and R205 (3.3k), a feedback resistor R206 (380R), and compensation capacitors C108 (100nF) and C157 (100nF); wherein the REF_5V is input to the positive input terminal of U23B after being divided by R204 and R205, and the output of U23B is connected to the subsequent circuit through R206;

[0100] The current loop (CC) comprises an operational amplifier U19B (TL084ID), an input resistor R84 (4.7k), and a feedback resistor R86 (33k); wherein the LTC2755_B_LIMIT signal is input to the inverting input terminal of U19B through R84, the +7.926V reference is input to the non-inverting input terminal of U19B, and the output of U19B is connected to the gate of field effect transistor Q2 (BSS138).

[0101] The power loop (CP) comprises an operational amplifier U19C (TL084ID), an input resistor R83 (4.7k), and a feedback resistor R85 (33k), which are mirror-symmetrically connected.

[0102] The voltage dividing resistors (R204 / R205) and the compensation capacitors (C108 / C157) cooperate to effectively suppress the temperature drift of the voltage loop and improve the precision of the constant voltage mode; the current loop and the power loop are mirror-designed (R84 / R86 and R83 / R85 are symmetric), which ensures the consistency of the current / power loop gain and avoids the imbalance of the dual-loop control.

[0103] Specifically, in the embodiment, the field effect transistor control unit further comprises:

[0104] Q17 (BSS138), Q2 (BSS138), and Q1 (BSS308PE) respectively receive the output signals of the loops, determine whether they are in the range of -8V-8V through the comparator, and control the output of the pull-up circuit to the CPU.

[0105] The field effect transistors (Q17 / Q2 / Q1) form a fast switching array, which greatly reduces the signal transmission delay and speeds up the loop state determination; the combination of BSS138 / BSS308PE enhances the driving capability and prevents the comparator from being damaged by overload.

[0106] Specifically, in the embodiment, in the parallel expansion module:

[0107] The host signal transmission channel comprises an operational amplifier U24B (ADA4075-2ARZ), an input resistor R91 (51k), a feedback resistor R92 (1k), balanced resistors R94 (51k) and R95 (1k), and a compensation capacitor C99 (33pF); wherein the host outer ring signal Vctrl is input to the positive input end of U24B through R91, Vshare- is input to the negative input end of U24B through R94, and the output of U24B is transmitted to the relay K1 through R92 and R95;

[0108] The relay K1 (G5V-1 / 2V1A) is driven by the field effect transistor Q15 (BSS138), and is controlled by the CPU to be turned on and turned off, and is used for connecting the Vmaster signal and the Vshare+ bus.

[0109] The low-noise characteristic (4nV / √Hz) of the operational amplifier U24B (ADA4075-2ARZ) significantly improves the parallel machine signal transmission quality and reduces noise interference; the relay direct connection scheme reduces the software transfer link, shortens the parallel machine establishment time, and improves the dynamic response performance of the system.

[0110] Specifically, in the embodiment, the anti-interference circuit comprises:

[0111] The common-mode suppression inductor L1 (B82793C0475N265), the clamping diodes D8 (T2ZMB18) and D9 (T2ZMB18), the damping resistors R102 (680R) and R103 (680R), the filter capacitors C101 (1uF) and C98 (470pF) are connected in parallel between the Vshare+ bus and the ground wire.

[0112] The inductor L1 and the capacitor C98 constitute a π-type filter, effectively suppress high-frequency ripple, and improve the output stability; the clamping diodes (D8 / D9) limit the bus overvoltage peak within ±18V, reliably limit the bus overvoltage risk, and protect the safety of the subsequent circuit.

[0113] Specifically, in the embodiment, the output logic of the window comparator group is:

[0114] When the voltage loop output is 0-4V, the corresponding comparator output low level, trigger pull-up circuit set high CV flag signal;

[0115] When the current loop or power loop output exceeds ±8V, the comparator output high level, CC / CP flag signal is pulled down to low level.

[0116] The -8V~+8V window comparator sets a safety margin (voltage loop 4V<8V), completely eliminates the critical oscillation phenomenon, avoids the CPU mode misjudgment; the pull-down failure protection mechanism avoids the CPU misreading (such as the CC loop exceeding 14V, which is forced to be pulled down), provides a failure protection mechanism, and enhances the system robustness.

[0117] Specifically, in the embodiment, the working process of the parallel expansion module includes:

[0118] The CPU controls the Q15 conduction according to the set number of parallel machines, so that the host relay K1 is attracted, and the Vmaster signal is output to the Vshare+ bus;

[0119] The slave receives the signal through the Vshare+ bus and controls the local relay to be attracted, so that Vslave is connected with Vshare+, realizing the master outer ring signal control of the slave inner ring.

[0120] Active compensation of line loss voltage drop, improve the precision of multi-machine parallel current; realize the precise synchronization of master and slave equipment, and suppress the parallel machine impact current.

[0121] Embodiment 2

[0122] The embodiment provides a bidirectional programmable DC power supply control method, applied to the bidirectional programmable DC power supply system provided in embodiment 1, and includes the following steps:

[0123] S1: loop competition control step: real-time monitoring of each loop output voltage, if the CV loop output is in the range of 0-4V and the CC / CP loop output exceeds ±8V, it is determined that it is in constant voltage mode, the hardware priority criterion mode competes, greatly reduces the CPU resource occupation, and optimizes the system operation efficiency.

[0124] S2: parallel machine synchronization step: the host transmits the outer ring signal Vctrl to the Vshare+ bus after proportional amplification, and the slave obtains the signal through the bus and injects the inner ring given value, the bus signal is transmitted by proportional amplification, so as to ensure that the slave accurately tracks the host and maintains the output consistency.

[0125] S3: line loss compensation step: an adjustable gain operational amplifier is inserted in the parallel machine signal transmission path, the host output gain is dynamically increased according to the wire resistance to offset the voltage drop, the influence of dynamic offset wire voltage drop is compensated, and the long-distance parallel machine precision is guaranteed; temperature-resistance model adaptive adjustment, adaptive to environmental changes, and keep the compensation effectiveness in all working conditions.

[0126] S4: interference suppression step: a magnetic ring is connected in series on the Vshare+ bus, and an RC filter network (C101, R102) is connected in parallel to the ground to absorb high-frequency ripple, the magnetic ring+RC filter combination significantly reduces the conducted interference and improves the electromagnetic compatibility of the system; the clamping diode absorbs EFT4kV surge, effectively absorbs the surge energy, and enhances the anti-transient impact capability.

[0127] In summary, the working principle of the bidirectional programmable DC power supply system provided in the embodiment is as follows:

[0128] Loop competition control module: voltage loop (CV), current loop (CC), power loop (CP) as three independent control loop, each through a specific op-amp, resistor, capacitor and other components to form a circuit. In the voltage loop, REF_5V is input to the positive input terminal of the op-amp after being divided by the voltage dividing resistor, and the output of the op-amp is connected to the next stage circuit after being connected by the feedback resistor. The voltage dividing resistor and the compensation capacitor cooperate to suppress temperature drift. In the current loop, a specific signal is input to the negative input terminal of the op-amp through the input resistor, and the reference voltage is input to the positive input terminal. The output of the op-amp controls the field effect transistor. The power loop is designed in mirror symmetry with the current loop. The outputs of the loops are connected to the window comparator group. The comparator group determines whether the outputs of the loops are in the threshold range of -8V to +8V, and then outputs high or low level to the CPU through the field effect transistor to control the pull-up circuit, thereby determining the output mode of the power supply.

[0129] Parallel expansion module: the main signal transmission channel uses op-amp, resistor, capacitor and other components to transmit the main outer loop signal Vctrl to the relay after proportional amplification processing. The CPU controls the field effect transistor according to the set number of parallel machines to drive the relay to attract and output the Vmaster signal to the Vshare+ bus. The slave machine receives the signal through the Vshare+ bus and controls the local relay to attract, so that Vslave is connected to Vshare+, realizing the control of the main outer loop signal on the slave inner loop. At the same time, the common mode suppression inductor, clamping diode, damping resistor, filter capacitor and other elements in the anti-interference circuit work together to suppress high frequency ripple, limit overvoltage spikes and ensure stable signal transmission.

[0130] Workflow

[0131] 1. Loop competition control process: real-time monitoring of the output voltage of voltage loop (CV), current loop (CC) and power loop (CP). When the voltage loop output is 0-4V and the current loop and power loop outputs exceed ±8V, the corresponding comparator output is low, triggering the pull-up circuit to set the CV flag signal high, determining the constant voltage mode. If the current loop or power loop output exceeds ±8V, the comparator output is high, and the CC / CP flag signal is pulled down to low, thereby determining the output mode of the power supply.

[0132] 2. Parallel expansion process: first, the CPU controls the field effect transistor Q15 to conduct according to the set number of parallel machines, so that the main relay K1 is attracted to output the Vmaster signal to the Vshare+ bus; then, the slave machine receives the signal through the Vshare+ bus and controls the local relay to attract, so that Vslave is connected to Vshare+, realizing the control of the main outer loop signal on the slave inner loop. During the parallel process, line loss compensation is performed by inserting an adjustable gain op-amp, and interference suppression is performed by using a magnetic ring and an RC filter network.

[0133] The above merely preferred embodiments of the present application and are not intended to limit the embodiments and protection scope of the present application. Those skilled in the art should be able to understand that any equivalent substitutions and obvious changes made according to the present application description and drawings should be included in the protection scope of the present application.

Claims

1. A bidirectional programmable DC power supply system, characterized by, Comprise: Loop competition control module: contains voltage loop (CV), current loop (CC), power loop (CP) three independent control loop, each loop output end is connected to the window comparator group, the determination threshold value range of the window comparator group is -8V to +8V; Parallel expansion module: contains master signal transmission channel, slave signal receiving channel and shared bus (Vshare+), the synchronization transmission of control signal between master and slave devices is controlled by relay.

2. The bidirectional programmable DC power supply system of claim 1, wherein, In the loop competition control module: The voltage loop (CV) contains operational amplifier U23B (TL084ID), voltage dividing resistors R204 (5.8k) and R205 (3.3k), feedback resistor R206 (380R), compensation capacitors C108 (100nF) and C157 (100nF); wherein REF_5V is input to the positive input terminal of U23B after being divided by R204 and R205, and the output of U23B is connected to the subsequent circuit through R206; The current loop (CC) contains operational amplifier U19B (TL084ID), input resistor R84 (4.7k), feedback resistor R86 (33k); wherein the LTC2755_B_LIMIT signal is input to the inverting input terminal of U19B through R84, and the +7.926V reference is input to the non-inverting input terminal of U19B, and the output of U19B is connected to the gate of field effect transistor Q2 (BSS138); The power loop (CP) contains operational amplifier U19C (TL084ID), input resistor R83 (4.7k), feedback resistor R85 (33k), which is mirror-symmetrical connected with the current loop.

3. The bidirectional programmable DC power supply system of claim 2, wherein, It also includes a field effect transistor control unit, which includes: Q17 (BSS138), Q2 (BSS138), Q1 (BSS308PE), respectively receiving the output signals of each loop, determining whether they are in the range of -8V~8V through the comparator, and controlling the output of the pull-up circuit to the CPU.

4. The bidirectional programmable DC power supply system of claim 1, wherein, In the parallel expansion module: The master signal transmission channel contains operational amplifier U24B (ADA4075-2ARZ), input resistor R91 (51k), feedback resistor R92 (1k), balance resistor R94 (51k) and R95 (1k), compensation capacitor C99 (33pF); wherein the master outer loop signal Vctrl is input to the positive input terminal of U24B through R91, Vshare- is input to the inverting input terminal of U24B through R94, and the output of U24B is transmitted to relay K1 through R92 and R95; The relay K1 (G5V-1 / 2V1A) is driven by field effect transistor Q15 (BSS138), and its on-off is controlled by CPU, which is used to connect Vmaster signal and Vshare+ bus.

5. The bidirectional programmable DC power supply system of claim 4, wherein, It also includes an anti-interference circuit, which contains: Common-mode rejection inductance L1 (B82793C0475N265), clamping diodes D8 (T2ZMB18) and D9 (T2ZMB18), damping resistors R102 (680R) and R103 (680R), filter capacitors C101 (1uF) and C98 (470pF) are connected in parallel between the Vshare+ bus and ground.

6. The bidirectional programmable DC power supply system of claim 1, wherein, The output logic of the window comparator group is: When the voltage loop output is 0-4V, the corresponding comparator output is low, triggering the pull-up circuit to set the CV flag signal high; When the current loop or power loop output exceeds ±8V, the comparator output is high, and the CC / CP flag signal is pulled low.

7. The bidirectional programmable DC power supply system of claim 1, wherein, The working process of the parallel expansion module includes: The CPU controls Q15 to be on according to the set number of parallel machines, so that the main machine relay K1 is attracted, and the Vmaster signal is output to the Vshare+ bus; The slave machine receives the signal through the Vshare+ bus and controls the local relay to be attracted, so that Vslave is connected with Vshare+, realizing the control of the main machine outer loop signal on the slave machine inner loop.

8. A bidirectional programmable DC power supply control method applied to any of the bidirectional programmable DC power supply systems of claims 1-7, characterized in that, The method includes the following steps: Loop competition control step: real-time monitoring of each loop output voltage, if the CV loop output is in the range of 0-4V and the CC / CP loop output exceeds ±8V, it is determined as constant voltage mode; Parallel machine synchronization step: the main machine transmits the outer loop signal Vctrl to the Vshare+ bus after proportional amplification, and the slave machine obtains the signal through the bus and injects the inner loop given value.

9. The bidirectional programmable DC power supply control method of claim 8, wherein, Further comprising: Line loss compensation step: insert an adjustable gain operational amplifier in the parallel machine signal transmission path, dynamically increase the output gain of the main machine according to the wire resistance to offset the pressure drop.

10. The bidirectional programmable DC power supply control method of claim 9, wherein, Further comprising: Interference suppression step: series magnetic ring in Vshare+ bus, and parallel RC filter network (C101, R102) to ground to absorb high frequency ripple.

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