Low-distortion pulse generator

Abstract

The invention provides a low-distortion pulse generator which comprises a transistor MP1, an S pole of the transistor MP1 is used for connecting a high-voltage power supply end, and a D pole of the transistor MP1 is used for connecting a transducer; the first level translator is used for driving the G pole of the transistor MP1 so as to apply a voltage pulse with a rising edge to the transducer; s poles of the transistor MN1 and the transistor MP1 are grounded, and D poles of the transistor MN1 and the transistor MP1 are connected with a transducer; the second level shifter is used for driving the G pole of the transistor MP2 so as to apply a voltage pulse with a falling edge to the transducer; and the level shifter is used for adjusting the voltage difference VGS between the grid electrode and the source electrode of the transistor so as to realize the time adjustment of the rising edge or the falling edge of the voltage pulse. According to the invention, the voltage difference VGS between the grid electrode and the source electrode of the transistor is adjusted through the level translator to realize the time adjustment of the rising edge or the falling edge of the voltage pulse, so that the slew rates of different edges are adjusted, and the waveform distortion is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of medical ultrasound imaging, in particular, to a low-distortion pulse generator. BACKGROUND

[0002] In the field of ultrasound imaging, ultrasound harmonic imaging (UHI) is an ultrasound imaging technique based on the principle of nonlinear acoustics. By receiving the harmonic signals generated by the tissue or contrast agent (usually multiples of the frequency of the incident ultrasound wave), a higher quality image is provided.

[0003] Considering the imaging advantages brought by harmonic imaging, mainstream ultrasound imaging systems will support the function of harmonic imaging. These imaging systems will be connected to a one-dimensional array using a long wire, usually 8 to 128 array elements. The transmitter is usually integrated in the host of the ultrasound imaging, so it can provide sufficient area and power consumption. However, in a large-scale two-dimensional transducer array, the transducer array elements usually exceed one thousand or even ten thousand, and each transducer array element needs a corresponding transmitter driver. Therefore, the area and power consumption are very limited, and how to realize a low-distortion transmitter under the limitation of limited area and power consumption is a great challenge. In addition, due to the process deviation in the semiconductor process manufacturing process and the temperature change in the chip working process, the transmitters of different channels will have performance differences, thereby affecting the final imaging quality.

[0004] The core of ultrasound harmonic imaging is to receive the harmonic signals generated by the target medium (such as tissue or contrast agent), rather than the harmonic signals from the transmitter. If the transmitter circuit introduces too much nonlinear distortion when generating the fundamental wave signal, these pseudo-harmonic signals will mix into the received signal, reducing the image quality. Therefore, there is an urgent need for a low-distortion transmitter circuit. SUMMARY

[0005] In view of the defects in the prior art, the purpose of the present application is to provide a low-distortion pulse generator.

[0006] The low-distortion pulse generator provided by the present application comprises: a transistor MP1, the S pole of the transistor MP1 is used to connect a high-voltage power supply end, and the D pole is used to connect a transducer; a first level converter, used to drive the G pole of the transistor MP1, so as to realize the application of a voltage pulse with a rising edge to the transducer; a transistor MN1, the S pole of the transistor MP1 is used to connect the ground, and the D pole is used to connect the transducer; a second level converter, used to drive the G pole of the transistor MP2, so as to realize the application of a voltage pulse with a falling edge to the transducer; The level converter is configured to adjust a voltage difference VGS between the gate and the source of the transistor to achieve the time adjustment of the rising edge or the falling edge of the voltage pulse.

[0007] Preferably, further comprising: A transistor MN2, an S pole of the transistor MN2 is configured to be connected to a low-voltage power supply end, and a D pole of the transistor MN2 is configured to be connected to the transducer; A third level converter configured to drive a G pole of the transistor MN2 to achieve the voltage pulse with the falling edge applied to the transducer; A transistor MP2, an S pole of the transistor MP2 is configured to be connected to the ground, and a D pole of the transistor MP2 is configured to be connected to the transducer; A fourth level converter configured to drive a G pole of the transistor MN2 to achieve the voltage pulse with the rising edge applied to the transducer.

[0008] Preferably, further comprising: A diode D1, a positive pole of the diode D1 is configured to be connected to the transducer, and a negative pole of the diode D1 is configured to be connected to the D pole of the transistor MN1; A diode D2, a negative pole of the diode D2 is configured to be connected to the transducer, and a positive pole of the diode D2 is configured to be connected to the D pole of the transistor MP2.

[0009] Preferably, the first level converter comprises: An adjustable current source ITRIM1; A first two-stage current mirror configured to amplify the current generated by the adjustable current source ITRIM1 by X1 times; A resistor R3 configured to perform voltage drop on the amplified current to serve as VGS of the transistor MP1, VGS being a voltage difference between the G pole and the S pole.

[0010] Preferably, the first level converter comprises: A current source ITRIM1 configured to output a current with a first value; A current mirror transistor MN3, an S pole of the current mirror transistor MN3 is configured to be connected to a high-voltage source, and a G pole of the current mirror transistor MN3 is configured to be connected to a D pole; A current mirror transistor A current mirror transistor MN4, an S pole of the current mirror transistor MN4 is configured to be connected to the high-voltage source, and a G pole of the current mirror transistor MN4 is configured to be connected to the G pole of the current mirror transistor MN3; A current mirror transistor MP3, an S pole of the current mirror transistor MP3 is configured to be connected to the ground, a D pole of the current mirror transistor MP3 is configured to be connected to the D pole of the current mirror transistor MN4, and a G pole of the current mirror transistor MP3 is configured to be connected to the D pole; A current mirror transistor MP5, an S pole of the current mirror transistor MP5 is configured to be connected to the ground, and a G pole of the current mirror transistor MP5 is configured to be connected to the G pole of the current mirror transistor MP3; a resistor R3, one end of which is connected to a high voltage source and the other end of which is connected to an output port Vout, a voltage stabilizing diode D3, which is connected in parallel with the resistor R3; a transistor MP4, the S pole of which is connected to the D pole of the current mirror transistor MP5, the G pole of which is connected to an input port Vin, and the D pole of which is connected to the other end of the resistor R3; a transistor MP6, the S pole of which is connected to ground, and the D pole of which is connected to the S pole of the transistor MP4; a NAND gate, the output of which is connected to the G pole of the transistor MP6, the first input of which is used to input a TRIM_EN signal, and the other input of which is used to input Vin.

[0011] Preferably, the second level shifter comprises: an adjustable current source ITRIM2; a second two-stage current mirror, which is used to amplify the current generated by the adjustable current source ITRIM1 by a factor of X2; a resistor R4, which is used to perform voltage drop on the amplified current, so as to serve as VGS of the transistor MN1, VGS being the voltage difference between the G pole and the S pole.

[0012] Preferably, the second level shifter comprises: a current source ITRIM2, which is configured to output a current of a second value; a current mirror transistor MN5, the S pole of which is connected to a high voltage source, and the G pole of which is connected to the D pole; a current mirror transistor MN6, the S pole of which is connected to a high voltage source, and the G pole of which is connected to the G pole of the current mirror transistor MN5; a current mirror transistor MP7, the S pole of which is connected to ground, the D pole of which is connected to the D pole of the current mirror transistor MN6, and the G pole of which is connected to the D pole; a current mirror transistor MP8, the S pole of which is connected to ground, and the G pole of which is connected to the G pole of the current mirror transistor MP7; a resistor R4, one end of which is connected to a high voltage source, and the other end of which is connected to the D pole of the current mirror transistor MP8; a transistor MN7, the S pole of which is connected to a high voltage source, the G pole of which is used to input a TRIM_EN signal, and the D pole of which is connected to the other end of the resistor R4; an inverter, the input of which is used to receive a signal Vin, the output of which is used to output a signal Vout, the positive power supply end of which is connected to the other end of the resistor R4, and the negative power supply end of which is connected to ground.

[0013] Preferably, the first level shifter comprises a current stabilizing circuit; the current stabilizing circuit comprises: a resistive voltage divider for generating a reference voltage; an operational amplifier for making the voltage across resistor R0 equal to the reference voltage through negative feedback, forming a constant current I; a third two-stage current mirror for amplifying the constant current I by X3 times and providing it to resistor R3 of the first level shifter.

[0014] Preferably, the current stabilizing circuit comprises: a resistor R1, one end of which is connected to a high voltage source; a resistor R2, one end of which is connected to the other end of the resistor R1; an operational amplifier, the positive input terminal of which is connected to the other end of the resistor R1; a resistor R0, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end is grounded; a current mirror transistor MN8, the S pole of which is used to connect a high voltage source, and the G pole is connected to the D pole; a current mirror transistor MN9, the S pole of which is connected to the D pole of the current mirror transistor MN9, and the G pole is connected to the D pole; a transistor MP14, the S pole of which is connected to one end of the resistor R0, the G pole is connected to the output terminal of the operational amplifier, and the D pole is connected to the D pole of the current mirror transistor MN9; a current mirror transistor MN10, the S pole of which is used to connect a high voltage source, and the G pole is connected to the G pole of the current mirror transistor MN8; a current mirror transistor MN11, the S pole of which is connected to the D pole of the current mirror transistor MN10, and the G pole is connected to the G pole of the current mirror transistor MN9; a current mirror transistor MP9, the D pole of which is connected to the D pole of the current mirror transistor MN11, and the G pole is connected to the D pole; a current mirror transistor MP10, the D pole of which is connected to the S pole of the current mirror transistor MP9, the G pole is connected to the D pole, and the S pole is grounded; a current mirror transistor MP12, the G pole of which is connected to the G pole of the current mirror transistor MP9; a current mirror transistor MP13, the G pole of which is connected to the G pole of the current mirror transistor MP10, the D pole is connected to the S pole of the current mirror transistor MP12, and the S pole is grounded.

[0015] Preferably, the first level converter further comprises: a resistor R3, one end of the resistor R3 is connected to a high voltage source, the other end is connected to an output port Vout, a voltage stabilizing diode D3 connected in parallel with the resistor R3; a transistor MP11, the D pole of the transistor MP11 is connected to the other end of the resistor R3, the S pole is connected to the D pole of the current mirror transistor MP12, and the G pole is used to receive a signal Vin.

[0016] Compared with the prior art, the present application has the following beneficial effects: The present application adjusts the time of the rising edge or the falling edge of the voltage pulse by adjusting the voltage difference VGS between the gate and the source of the transistor through the level converter, thereby adjusting the size of the slew rate of different edges and reducing waveform distortion. The present application realizes a high-voltage DMOS switch control voltage independent of temperature and semiconductor process deviation through the current stabilizing circuit, thereby improving the slew rate adjustment efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings. Other features, objects and advantages of the present application will become more apparent through reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings: Figure 1 a schematic diagram of an ideal three-stage pulse with a period of T in an embodiment of the present application; Figure 2 a schematic diagram of a low-distortion pulse generator in an embodiment of the present application; Figure 3 a circuit diagram of a low-to-high current-regulated level converter in an embodiment of the present application; Figure 4 a circuit diagram of a low-voltage current-regulated level converter in an embodiment of the present application; Figure 5 a current-regulated level converter for a current-regulated level converter in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The application will be described in detail below with specific examples. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be pointed out that, for those skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made. These are within the scope of the application.

[0019] The terms "first", "second", "third", "fourth" and the like in the description and claims of the application and above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so construed can be interchanged, such that, for example, without departing from the scope of the embodiments of the application described herein, an embodiment of the application described herein can be carried out in an order other than the one illustrated or described herein. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or apparatus that comprises a list of steps or units not necessarily limited to those explicitly listed, but can include other not expressly listed or inherent to such processes, methods, products or apparatus.

[0020] The technical solutions of the application will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some examples.

[0021] The technical solutions of the application and how the technical solutions of the application solve the above technical problems will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some examples. The embodiments of the application will be described below with reference to the drawings.

[0022] Figure 1 A schematic diagram of an ideal three-stage pulse with a period of T in an embodiment of the application is shown in FIG. 1, which includes two rising edges and two falling edges. An ideal three-stage pulse has no second harmonic component. In actual situations, due to the mismatch of rising and falling edges, a second harmonic component appears in the pulse, resulting in waveform distortion. Figure 1

[0023] Therefore, in order to reduce the second harmonic component and waveform distortion, the high-voltage transmitting circuit needs to match the rising and falling edges of the waveform when generating the transmitting pulse.

[0024] Figure 2 A schematic diagram of a low-distortion pulse generator in an embodiment of the application is shown in FIG. 2, which includes: Figure 2 ​​Transistor MP1, S pole of which is used to connect high voltage power supply end, D pole of which is used to connect transducer; First level converter, which is used to drive G pole of transistor MP1, so as to realize voltage pulse with rising edge applied to transducer; Transistor MN1, S pole of which is used to connect ground, D pole of which is used to connect transducer; Second level converter, which is used to drive G pole of transistor MP2, so as to realize voltage pulse with falling edge applied to transducer; The level converter is used to adjust voltage difference VGS between gate and source of the transistor, so as to realize time adjustment of the rising edge or the falling edge of the voltage pulse.

[0025] Transistor MN2, S pole of which is used to connect low voltage power supply end, D pole of which is used to connect transducer; Third level converter, which is used to drive G pole of transistor MN2, so as to realize voltage pulse with falling edge applied to transducer; Transistor MP2, S pole of which is used to connect ground, D pole of which is used to connect transducer; Fourth level converter, which is used to drive G pole of transistor MN2, so as to realize voltage pulse with rising edge applied to transducer; Diode D1, positive pole of which is used to connect the transducer, negative pole of which is connected to D pole of the transistor MN1; Diode D2, negative pole of which is used to connect the transducer, positive pole of which is connected to D pole of the transistor MP2.

[0026] As Figure 2 shown, the transistor MP1, transistor MN1, transistor MN2 and transistor MP2 adopt field effect transistor DMOS. 4 high voltage DMOS are driven by 4 level converters. When the high voltage DMOS is opened, the transmitting circuit charges and discharges the load, so as to generate Figure 1 three-stage pulse shown, the charging and discharging current provided by the DMOS determines the size of the rising and falling time in the pulse.

[0027] When the high voltage DMOS is opened and works in the saturation region, the current passing through is: (1) Wherein, W / L is the width to length ratio of the MOS, μ is the electron mobility, Cox is the oxide layer capacitance, VG is the gate voltage, VT is the threshold voltage, VS is the source voltage, and VGS is the voltage difference between the gate and the source; Wherein, the electron mobility of DMOS, the oxide layer capacitance Cox and the threshold voltage VT will change with the semiconductor manufacturing process and the chip working temperature. In most cases, the load of the high-voltage transmitting circuit is a capacitor, therefore, the pressure swing rate of the output pulse is: (2) As can be seen from formula (2), the pressure swing rate of the output pulse can be achieved by adjusting the gate and source voltage difference VGS of DMOS. If the VGS of the four DMOS in the middle can be regulated respectively, Figure 2 then the time of the four rising and falling edges of the output pulse can be matched, and the waveform distortion can be effectively reduced.

[0028] Figure 3 The circuit diagram of the low-to-high voltage current-regulated level shifter in the embodiment of the present application is shown in FIG. 1, which comprises: Figure 3 a first level shifter, a second level shifter, and a third level shifter. an adjustable current source ITRIM1; a first two-stage current mirror for amplifying the current generated by the adjustable current source ITRIM1 by X1 times; a resistor R3 for voltage drop of the amplified current, so as to serve as the VGS of the transistor MP1, VGS being the voltage difference between the gate and the source.

[0029] In the embodiment of the present application, the first two-stage current mirror first amplifies the current by M times, and then amplifies the current by N times, the value of M being any value between 1 and 5, such as 1, the value of N being any value between 40 and 100, such as 50, and the value of X1 being M×N.

[0030] More specifically, the first level shifter comprises: a current source ITRIM1 configured to output a current of a first value; a current mirror transistor MN3, the S pole of the current mirror transistor MN3 being configured to be connected to a high-voltage source, and the G pole being connected to the D pole; a current mirror transistor MN4, the S pole of the current mirror transistor MN4 being configured to be connected to the high-voltage source, and the G pole being connected to the G pole of the current mirror transistor MN3; a current mirror transistor MP3, the S pole of the current mirror transistor MP3 being configured to be grounded, the D pole being connected to the D pole of the current mirror transistor MN4, and the G pole being connected to the D pole; a current mirror transistor MP5, the S pole of the current mirror transistor MP5 being configured to be grounded, and the G pole being connected to the G pole of the current mirror transistor MP3; a resistor R3, one end of the resistor R3 being configured to be connected to the high-voltage source, and the other end being connected to an output port Vout, a voltage stabilizing diode D3 connected in parallel with the resistor R3; A transistor MP4, whose S pole is connected to the D pole of the current mirror transistor MP5, whose G pole is connected to the input port Vin, and whose D pole is connected to the other end of the resistor R3; A transistor MP6, whose S pole is connected to ground, and whose D pole is connected to the S pole of the transistor MP4; A NAND gate, whose output is connected to the G pole of the transistor MP6, and whose first input is used to input the TRIM_EN signal, and whose other input is used to input Vin.

[0031] In the embodiment of the present application, the high voltage source connected to the S pole of the current mirror transistor MN3 and the S pole of the current mirror transistor MN4 is VDD -- 5V high voltage source. The high voltage source connected to one end of the resistor R3 is VDD — HV high voltage source. The VDD — The HV high voltage source can be set to be higher than VDD -- 5V high voltage source, such as 20V high voltage source, 40V high voltage source or 60V high voltage source.

[0032] In the embodiment of the present application, the adjustable current source ITRIM1 provides a plurality of times of amplification to the resistor R3 through two-stage current mirror, such as 50 times of amplification. Figure 3 The Vout in the Figure 2 is connected to the gate of the transistor MP1 in the Figure 3 . Therefore, the VGS of the transistor MP1 is equal to the voltage across the resistor R3 in the

[0033] . By adjusting the current flowing through the resistor R3, the size of VGS can be freely adjusted. (3) wherein the TRIM_EN signal is used to turn off the current mirror.

[0034] Figure 4 is the circuit diagram of the low-voltage current-regulated level shifter in the embodiment of the present application, as shown in Figure 4 , The second level shifter comprises: An adjustable current source ITRIM2; A second two-stage current mirror, used to amplify the current generated by the adjustable current source ITRIM1 by X2 times; A resistor R4, used to perform voltage drop on the amplified current, so as to serve as the VGS of the transistor MN1, and VGS is the voltage difference between the G pole and the S pole.

[0035] In the embodiment of the present application, the second two-stage current mirror first amplifies the current by M times, and then amplifies the current by N times, wherein M is any value between 1 and 5, such as 1; N is any value between 40 and 100, such as 50; and X2 is M×N.

[0036] More specifically, the second level converter comprises: a current source ITRIM2 configured to output a second value of current; a current mirror transistor MN5, wherein the S pole of the current mirror transistor MN5 is connected to a high voltage source, and the G pole is connected to the D pole; a current mirror transistor MN6, wherein the S pole of the current mirror transistor MN6 is connected to the high voltage source, and the G pole is connected to the G pole of the current mirror transistor MN5; a current mirror transistor MP7, wherein the S pole of the current mirror transistor MP7 is connected to ground, the D pole is connected to the D pole of the current mirror transistor MN6, and the G pole is connected to the D pole; a current mirror transistor MP8, wherein the S pole of the current mirror transistor MP8 is connected to ground, and the G pole is connected to the G pole of the current mirror transistor MP7; a resistor R4, wherein one end of the resistor R4 is connected to the high voltage source, and the other end is connected to the D pole of the current mirror transistor MP8; a transistor MN7, wherein the S pole of the transistor MN7 is connected to the high voltage source, the G pole is configured to input a TRIM_EN signal, and the D pole is connected to the other end of the resistor R4; an inverter, wherein the input end of the inverter is configured to receive a signal Vin, the output end of the inverter is configured to output a signal Vout, the positive electrode of the power supply end of the inverter is connected to the other end of the resistor R4, and the negative electrode of the power supply end of the inverter is connected to ground.

[0037] In the embodiment of the present application, the high voltage source connected to the S pole of the transistor MN7, the S pole of the current mirror transistor MN5, and the S pole of the current mirror transistor MN6 is VDD -- 5V high voltage source. -- 5V high voltage source.

[0038] However, in the semiconductor process, the resistance value of the resistor is greatly affected by process deviation and temperature change. Therefore, even Figure 3 and Figure 4 the level converter can adjust the size of VGS, and the change of the resistance value will affect the size of the final output waveform swing, thereby affecting the waveform distortion. Using Figure 5 the constant current circuit shown in the figure can effectively reduce the influence of the change of the resistance value.

[0039] Figure 5 FIG. 1 is a circuit diagram of a constant current circuit for a current-regulated level converter in an embodiment of the present application.Figure 5 As shown, the first level converter comprises a constant current circuit; the constant current circuit comprises: a resistive voltage dividing network for generating a reference voltage; an operational amplifier for making the voltage across resistor R0 equal to the reference voltage through negative feedback, forming a constant current I; a third two-stage current mirror for amplifying the constant current I by X3 times and providing it to resistor R3 of the first level converter.

[0040] In the embodiment of the present application, the third two-stage current mirror first amplifies the current by M times and then amplifies the current by N times, the value of M is any value between 1 and 5, such as 1, the value of N is any value between 40 and 100, such as 50, and the value of X3 is M×N.

[0041] More specifically, the constant current circuit comprises: resistor R1, one end of which is connected to a high voltage source; resistor R2, one end of which is connected to the other end of resistor R1; an operational amplifier, the positive input terminal of which is connected to the other end of resistor R1; resistor R0, one end of which is connected to the inverting input terminal of the operational amplifier and the other end of which is grounded; current mirror transistor MN8, the S pole of which is used to connect the high voltage source and the G pole of which is connected to the D pole; current mirror transistor MN9, the S pole of which is connected to the D pole of current mirror transistor MN9 and the G pole of which is connected to the D pole; transistor MP14, the S pole of which is connected to one end of resistor R0, the G pole of which is connected to the output terminal of the operational amplifier, and the D pole of which is connected to the D pole of current mirror transistor MN9; current mirror transistor MN10, the S pole of which is used to connect the high voltage source and the G pole of which is connected to the G pole of current mirror transistor MN8; current mirror transistor MN11, the S pole of which is connected to the D pole of current mirror transistor MN10 and the G pole of which is connected to the G pole of current mirror transistor MN9; current mirror transistor MP9, the D pole of which is connected to the D pole of current mirror transistor MN11 and the G pole of which is connected to the D pole; current mirror transistor MP10, the D pole of which is connected to the S pole of current mirror transistor MP9, the G pole of which is connected to the D pole, and the S pole of which is grounded; A current mirror transistor MP12, a G pole of the current mirror transistor MP12 is connected with a G pole of the current mirror transistor MP9; A current mirror transistor MP13, a G pole of the current mirror transistor MP13 is connected with a G pole of the current mirror transistor MP10, a D pole is connected with an S pole of the current mirror transistor MP12, and an S pole is grounded.

[0042] In the embodiment of the present application, a high voltage source connected with an S pole of the current mirror transistor MN8 and an S pole of the current mirror transistor MN10 is VDD -- 5V high voltage source. A high voltage source connected with one end of the resistor R1 is VDD -- 5V high voltage source.

[0043] The first level converter further comprises: A resistor R3, one end of the resistor R3 is used for connecting a high voltage source, and the other end is connected with an output port Vout, A voltage stabilizing diode D3, which is connected with the resistor R3 in parallel; A transistor MP11, a D pole of the transistor MP11 is connected with the other end of the resistor R3, an S pole is connected with a D pole of the current mirror transistor MP12, and a G pole is used for receiving a signal Vin.

[0044] As Figure 5 As shown in the figure, a reference voltage Vref is generated by the resistance voltage division of R1 and R2, and the voltage between the two ends of the resistor R0 is also equal to Vref through the negative feedback formed by the operational amplifier. The current flowing through the resistor R0 is provided to the resistor R3 in the level converter through the current mirror, and the required voltage drop is formed. The VGS of the driving DMOS can be adjusted by adjusting the ratio N of the current mirror.

[0045] (4) As formula 4, therefore, if the resistance types of the resistor R0 and the resistor R3 are the same and can be well matched in the layout, Figure 5 The current stabilizing circuit in the formula 4 can provide the VGS which is independent of temperature and process deviation.

[0046] In the embodiment of the present application, the time adjustment of the rising edge or the falling edge of the voltage pulse is realized by adjusting the voltage difference VGS between the gate and the source of the transistor through the level converter, so that the size adjustment of the slew rate of different edges is realized, and the waveform distortion is reduced. The high voltage DMOS switch control voltage which is independent of temperature and semiconductor process deviation is realized through the current stabilizing circuit, and the slew rate adjustment efficiency is improved.

[0047] The various embodiments described in this specification are intended to be illustrative of the invention and do not limit the scope of the invention. Although specific embodiments have been described herein, many variations and modifications are possible. For example, the order in which steps of a method are performed can be modified. Additionally, features from different embodiments can be combined. Accordingly, the disclosure is not limited to these specific embodiments disclosed, but instead has scope as set out in the appended claims and their equivalents.

[0048] The specific embodiments of the present application have been described. It is to be understood that the application is not limited to the specific embodiments described and that modifications can be made to these embodiments without parting from the spirit and scope of the application.

Claims

1. A low-distortion pulse generator, characterized by, Comprising: a transistor MP1, the S pole of which is used to connect a high-voltage power supply end, and the D pole of which is used to connect a transducer; a first level converter for driving the G pole of the transistor MP1 to achieve the application of a voltage pulse with a rising edge to the transducer; a transistor MN1, the S pole of which is used to connect to ground, and the D pole of which is used to connect the transducer; a second level converter for driving the G pole of the transistor MP2 to achieve the application of a voltage pulse with a falling edge to the transducer; the level converter is used to adjust the voltage difference VGS between the gate and the source of the transistor to achieve the time adjustment of the rising edge or the falling edge of the voltage pulse.

2. The low-distortion pulse generator of claim 1, wherein, Further comprising: a transistor MN2, the S pole of which is used to connect a low-voltage power supply end, and the D pole of which is used to connect the transducer; a third level converter for driving the G pole of the transistor MN2 to achieve the application of a voltage pulse with a falling edge to the transducer; a transistor MP2, the S pole of which is used to connect to ground, and the D pole of which is used to connect the transducer; a fourth level converter for driving the G pole of the transistor MN2 to achieve the application of a voltage pulse with a rising edge to the transducer.

3. The low distortion pulse generator of claim 1, wherein, Further comprising: a diode D1, the anode of which is used to connect the transducer, and the cathode of which is connected to the D pole of the transistor MN1; a diode D2, the cathode of which is used to connect the transducer, and the anode of which is connected to the D pole of the transistor MP2.

4. The low distortion pulse generator of claim 1, wherein, The first level converter comprises: an adjustable current source ITRIM1; a first two-stage current mirror for amplifying the current generated by the adjustable current source ITRIM1 by X1 times; a resistor R3 for voltage drop on the amplified current to serve as VGS of the transistor MP1, VGS being the voltage difference between the G pole and the S pole.

5. The low distortion pulse generator of claim 4, wherein, The first level converter comprises: a current source ITRIM1 configured to output a current of a first value; a current mirror transistor MN3, the S pole of which is used to connect a high-voltage source, the G pole of which is connected to the D pole, and the D pole of which is connected to one end of the current source ITRIM1, the other end of the current source ITRIM1 being connected to ground; a current mirror transistor a current mirror transistor MN4, the S pole of which is used to connect a high-voltage source, and the G pole of which is connected to the G pole of the current mirror transistor MN3; a current mirror transistor MP3, the S pole of which is used to connect to ground, the D pole of which is connected to the D pole of the current mirror transistor MN4, and the G pole of which is connected to the D pole; a current mirror transistor MP5, the S pole of which is used to connect to ground, and the G pole of which is connected to the G pole of the current mirror transistor MP3; a resistor R3, one end of which is used to connect a high-voltage source, and the other end of which is connected to an output port Vout, a voltage stabilizing diode D3 connected in parallel with the resistor R3; a transistor MP4, the S pole of which is connected to the D pole of the current mirror transistor MP5, the G pole of which is connected to an input port Vin, and the D pole of which is connected to the other end of the resistor R3; a transistor MP6, the S pole of which is used to connect to ground, and the D pole of which is connected to the S pole of the transistor MP4; A NAND gate, an output terminal of the NAND gate is connected to a G terminal of the transistor MP6, a first input terminal is used for inputting a TRIM_EN signal, and another input terminal is used for inputting Vin.

6. The low distortion pulse generator of claim 1, wherein, The second level converter comprises: An adjustable current source ITRIM2; A second two-stage current mirror, used for amplifying a current generated by the adjustable current source ITRIM1 by X2 times; A resistor R4, used for voltage drop of the amplified current, so as to serve as VGS of the transistor MN1, VGS being a voltage difference between a G terminal and an S terminal.

7. The low distortion pulse generator of claim 6, wherein, The second level converter comprises: A current source ITRIM2, configured to output a current of a second value; A current mirror transistor MN5, an S terminal of the current mirror transistor MN5 is used for connecting a high-voltage source, and a G terminal is connected to a D terminal; A current mirror transistor MN6, an S terminal of the current mirror transistor MN6 is used for connecting the high-voltage source, and a G terminal is connected to a G terminal of the current mirror transistor MN5; A current mirror transistor MP7, an S terminal of the current mirror transistor MP7 is used for grounding, a D terminal is connected to a D terminal of the current mirror transistor MN6, and a G terminal is connected to a D terminal; A current mirror transistor MP8, an S terminal of the current mirror transistor MP8 is used for grounding, and a G terminal is connected to a G terminal of the current mirror transistor MP7; A resistor R4, one end of the resistor R4 is used for connecting the high-voltage source, and the other end is connected to a D terminal of the current mirror transistor MP8; A transistor MN7, an S terminal of the transistor MN7 is connected to the high-voltage source, a G terminal is used for inputting the TRIM_EN signal, and a D terminal is connected to the other end of the resistor R4; An inverter, an input terminal of the inverter is used for receiving a signal Vin, an output terminal of the inverter is used for outputting a signal Vout, a positive electrode of a power supply terminal of the inverter is connected to the other end of the resistor R4, and a negative electrode of the power supply terminal is grounded.

8. The low distortion pulse generator of claim 1, wherein, The first level converter comprises a constant current circuit; the constant current circuit comprises: A resistor voltage dividing network, used for generating a reference voltage; An operational amplifier, used for making a voltage between two ends of a resistor R0 equal to the reference voltage through negative feedback, so as to form a constant current I; A third two-stage current mirror, used for amplifying the constant current I by X3 times, and then providing the amplified constant current to a resistor R3 of the first level converter.

9. The low distortion pulse generator of claim 8, wherein, The constant current circuit comprises: A resistor R1, one end of the resistor R1 is connected to a high-voltage source; A resistor R2, one end of the resistor R2 is connected to the other end of the resistor R1; An operational amplifier, a positive input terminal of the operational amplifier is connected to the other end of the resistor R1; A resistor R0, one end of the resistor R0 is connected to an inverting input terminal of the operational amplifier, and the other end is grounded; A current mirror transistor MN8, an S terminal of the current mirror transistor MN8 is used for connecting the high-voltage source, and a G terminal is connected to a D terminal; A current mirror transistor MN9, an S terminal of the current mirror transistor MN9 is connected to a D terminal of the current mirror transistor MN8, and a G terminal is connected to a D terminal; A transistor MP14, an S terminal of the transistor MP14 is connected to one end of the resistor R0, a G terminal is connected to an output terminal of the operational amplifier, and a D terminal is connected to a D terminal of the current mirror transistor MN9; A current mirror transistor MN10, an S terminal of the current mirror transistor MN10 is used for connecting the high-voltage source, and a G terminal is connected to a G terminal of the current mirror transistor MN8; a current mirror transistor MN11, whose S pole is connected to the D pole of the current mirror transistor MN10, and whose G pole is connected to the G pole of the current mirror transistor MN9; a current mirror transistor MP9, whose D pole is connected to the D pole of the current mirror transistor MN11, and whose G pole is connected to the D pole; a current mirror transistor MP10, whose D pole is connected to the S pole of the current mirror transistor MP9, whose G pole is connected to the D pole, and whose S pole is grounded; a current mirror transistor MP12, whose G pole is connected to the G pole of the current mirror transistor MP9; a current mirror transistor MP13, whose G pole is connected to the G pole of the current mirror transistor MP10, whose D pole is connected to the S pole of the current mirror transistor MP12, and whose S pole is grounded.

10. The low distortion pulse generator of claim 9, wherein, The first level shifter further comprises: a resistor R3, one end of which is connected to a high-voltage source, and the other end of which is connected to an output port Vout, a voltage stabilizing diode D3, which is connected in parallel with the resistor R3; a transistor MP11, whose D pole is connected to the other end of the resistor R3, whose S pole is connected to the D pole of the current mirror transistor MP12, and whose G pole is used to receive a signal Vin.

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