Relay adjustment circuit for an endoscope and endoscope

Abstract

The application provides a relay adjusting circuit of an endoscope and the endoscope. The relay adjusting circuit is provided with an input interface, a clock buffer, an input impedance adjusting module, an output matching adjusting module and an output interface. The input end of the clock buffer is electrically connected with the input interface. The input impedance adjusting module is connected with the input end and the grounding end of the clock buffer in parallel. The output matching adjusting module is electrically connected with the output end of the clock buffer. The output interface is electrically connected with the output matching adjusting module. The clock buffer is used for receiving a first clock driving signal adjusted by the input impedance adjusting module, enhancing the driving capacity of the adjusted first clock driving signal, obtaining a second clock driving signal and outputting the second clock driving signal. The output matching adjusting module is used for adjusting the signal peak value of the second clock driving signal, outputting a third clock driving signal with identifiable high and low level properties, and then compensating the signal attenuation formed by long-distance transmission and improving the accuracy of image acquisition.

Description

Technical Field

[0001] This application relates to the field of CMOS image sensor endoscopes, and more particularly to a relay adjustment circuit and an endoscope. Background Technology

[0002] As an important medical diagnostic and treatment tool, one of the core performance indicators of an endoscope system is image display quality. In current long-probe endoscope systems, the image signal transmission path is typically quite long, requiring two long transmission lines: "probe image sensor – handpiece" and "main unit – handpiece." During image signal transmission, the integrity of the clock signal (XCLK) is crucial, directly affecting the accuracy of image sensor data acquisition and the quality of the final displayed image.

[0003] To address signal attenuation during long-distance transmission, current technology involves adding resistors to the clock or image output signal lines on the endoscope's mainboard for signal conditioning. This improves the image quality acquired by the image sensor upon receiving the clock signal. However, with the increasing number of endoscope manufacturers and the expanding application scenarios, there are significant differences in the design of control mainboards on the market. More importantly, to adapt to different scenario requirements, the transmission line length connecting the handle and the endoscope probe varies from 1 meter to 4 meters. Clock signals experience significant loss during long-distance transmission; the longer the transmission line, the greater the signal attenuation, resulting in sluggish edges and a sharp decrease in driving capability. When the transmission line is too long, resistor adjustment alone is insufficient to compensate for the signal quality degradation at the far end. Deterioration in clock signal quality can lead to sampling timing errors or unstable data acquisition by the image sensor, ultimately manifesting as blurry, jittery, striped noise, or even signal interruption in the image on the display screen, severely impacting the accuracy and reliability of diagnosis. Summary of the Invention

[0004] The purpose of this application is to at least solve one of the technical problems existing in the prior art, and to provide a relay adjustment circuit and endoscope for an endoscope, which can effectively compensate for the clock signal attenuation caused by long-distance transmission, significantly improve the accuracy of image acquisition and the image quality of the display end, and enable the system to be widely compatible with transmission lines of different specifications from 1m to 4m, thereby enhancing the adaptability and flexibility of the product.

[0005] To achieve the above objectives, a first aspect of this application provides a relay adjustment circuit for an endoscope, comprising:

[0006] The input interface is used to connect to the control board of the endoscope and receive the first clock drive signal output by the control board.

[0007] The clock buffer's input terminal is electrically connected to the input interface;

[0008] The input impedance adjustment module is connected in parallel to the input terminal of the clock buffer and the ground terminal.

[0009] The output matching adjustment module is electrically connected to the output terminal of the clock buffer.

[0010] The output interface is electrically connected to the output matching and adjustment module.

[0011] The input impedance adjustment module is used to adjust the input impedance of the clock buffer so that the load capacity of the clock buffer matches the driving capacity of the first clock drive signal.

[0012] The clock buffer is used to receive the first clock drive signal transmitted from the input interface and adjusted by the input impedance adjustment module, and to enhance the driving capability of the adjusted first clock drive signal to obtain the second clock drive signal and output it.

[0013] The output matching adjustment module is used to adjust the peak-to-peak value of the second clock drive signal to output a third clock drive signal with identifiable high and low level characteristics;

[0014] The output interface is used to transmit a third clock drive signal to the endoscope's image sensor.

[0015] Furthermore, in some embodiments, the relay regulation circuit also includes:

[0016] The first analog grounding interface is electrically connected to the grounding terminals of the input impedance adjustment module and the clock buffer, respectively. The first analog grounding interface is used to connect to the control board of the endoscope to ground the clock buffer and the input impedance adjustment module.

[0017] The second analog grounding interface is electrically connected to the output matching adjustment module. The second analog grounding interface is used to connect to the control board of the endoscope to ground the output matching adjustment module.

[0018] Furthermore, in some embodiments, the input impedance adjustment module includes a first resistor, one end of which is electrically connected to the input terminal of the clock buffer, and the other end of which is electrically connected between the ground terminal of the clock buffer and the first analog ground interface.

[0019] Furthermore, in some embodiments, the value of the first resistor ranges from 1kΩ to 10kΩ.

[0020] Furthermore, in some embodiments, the output matching adjustment module includes a second resistor and a first capacitor;

[0021] One end of the second resistor is electrically connected to the output of the clock buffer, and the other end of the second resistor is electrically connected to the output interface.

[0022] The first terminal of the first capacitor is electrically connected between the second resistor and the output terminal of the clock buffer, or the first terminal of the first capacitor is electrically connected between the second resistor and the output interface.

[0023] The second terminal of the first capacitor is electrically connected to the second analog ground interface.

[0024] Furthermore, in some embodiments, the value of the second resistor ranges from 10Ω to 1.5KΩ, and the value of the first capacitor ranges from 10pF to 200pF.

[0025] Furthermore, in some embodiments, the aforementioned relay regulation circuit further includes:

[0026] The third resistor is connected in series between the output matching adjustment module and the output interface. The third resistor is used to absorb the reflected signal corresponding to the image sensor transmitted through the output interface.

[0027] Furthermore, in some embodiments, the operating voltage of the clock buffer is equal to the operating voltage of the image sensor, and the input / output frequency of the clock buffer is greater than the frequency of the first clock drive signal.

[0028] Furthermore, in some embodiments, the clock buffer operates at a voltage of 3.3V.

[0029] To achieve the above objectives, a second aspect of this application provides an endoscope, comprising:

[0030] The handle includes a control terminal interface circuit, a probe terminal interface circuit, and a relay adjustment circuit for the endoscope as described in the first aspect above. The input interface of the relay adjustment circuit is electrically connected to the control terminal interface circuit, and the output interface of the relay adjustment circuit is electrically connected to the probe terminal interface circuit.

[0031] The control motherboard is connected to the control terminal interface circuit via a transmission line. The control motherboard is used to transmit the first clock drive signal to the controller.

[0032] The probe includes an image sensor, which is connected to the interface circuit transmission line at the detection end.

[0033] The image sensor is used to receive the third clock drive signal obtained after signal enhancement by the relay conditioning circuit, and to acquire endoscopic images based on the third clock drive signal.

[0034] According to an embodiment of this application, an endoscope relay adjustment circuit and an endoscope have at least the following beneficial effects: By integrating a dedicated clock buffer inside the endoscope handle, the attenuated motherboard clock signal after long-distance transmission can be effectively reshaped and its driving capability enhanced, completely solving the core problem of signal edge sluggishness and insufficient driving capability caused by the change in transmission line length from 1m to 4m, ensuring that the signal still maintains complete waveform characteristics when transmitted to the remote probe; at the same time, by introducing an input impedance adjustment module, a flexible parallel impedance network enables the input impedance of the relay circuit to be precisely matched with the clock signal driving capability output by motherboards from different manufacturers and with different designs, effectively suppressing signal reflection and improving the integrity of front-end signal reception and system compatibility; furthermore, the output matching adjustment module can further enhance the signal strength of the enhanced clock signal. By finely adjusting the amplitude (peak-to-peak value) of the clock signal, it can output a stable high and low level clock signal that strictly meets the image sensor recognition requirements (e.g., 0.8V~2.0V), fundamentally ensuring the accuracy of image data acquisition timing. Secondly, as an independent intermediate drive node located in the handle, this relay circuit greatly expands the adaptability of the endoscope system. The same host platform can flexibly adapt to probes with different cable lengths, significantly reducing the overall design change costs and complexity caused by cable specification upgrades, and enhancing the product's adaptability and flexibility. Finally, by thoroughly improving the quality of the clock signal in the relay stage, this solution directly improves the stability of the image sensor's acquired data, ultimately presenting a clear, stable, ghosting-free, and jitter-free high-quality image on the display, significantly enhancing the reliability of medical diagnosis or industrial inspection and improving the user experience.

[0035] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0037] The present application will be further described below with reference to the accompanying drawings and embodiments;

[0038] Figure 1 This is a schematic diagram of an optional relay adjustment circuit for an endoscope provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of a second optional relay adjustment circuit for an endoscope provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of a third optional relay adjustment circuit for an endoscope provided in the embodiments of this application;

[0041] Figure 4 This is a schematic diagram of a fourth optional relay adjustment circuit for an endoscope provided in the embodiments of this application;

[0042] Figure 5 This is a fifth optional schematic diagram of the relay adjustment circuit of the endoscope provided in the embodiments of this application;

[0043] Figure 6 This is a schematic diagram of an optional control terminal interface circuit for an endoscope provided in an embodiment of this application;

[0044] Figure 7 This is an optional schematic diagram of the probe end interface circuit of the endoscope provided in the embodiments of this application.

[0045] Reference numerals: Input interface 10, Clock buffer 20, Input impedance adjustment module 30, First resistor 31, Output matching adjustment module 40, Second resistor 41, First capacitor 42, Output interface 50, First analog ground interface 60, Second analog ground interface 70, Control terminal interface circuit 80, Detection terminal interface circuit 90. Detailed Implementation

[0046] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0047] In the description of this application, the use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features. It should be understood that such use of data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0049] To address signal attenuation during long-distance transmission, current technology involves adding resistors to the clock or image output signal lines on the endoscope's mainboard for signal conditioning. This improves the image quality acquired by the image sensor upon receiving the clock signal. However, with the increasing number of endoscope manufacturers and the expanding application scenarios, there are significant differences in the design of control mainboards on the market. More importantly, to adapt to different scenario requirements, the transmission line length connecting the handle and the endoscope probe varies from 1 meter to 4 meters. Clock signals experience significant loss during long-distance transmission; the longer the transmission line, the greater the signal attenuation, resulting in sluggish edges and a sharp decrease in driving capability. When the transmission line is too long, resistor adjustment alone is insufficient to compensate for the signal quality degradation at the far end. Deterioration in clock signal quality can lead to sampling timing errors or unstable data acquisition by the image sensor, ultimately manifesting as blurry, jittery, striped noise, or even signal interruption in the image on the display screen, severely impacting the accuracy and reliability of diagnosis.

[0050] Based on this, the present application provides a relay adjustment circuit and endoscope for an endoscope, which can effectively compensate for the clock signal attenuation caused by long-distance transmission, significantly improve the accuracy of image acquisition and the image quality of the display end, and enable the system to be widely compatible with transmission lines of different specifications from 1m to 4m, thereby enhancing the adaptability and flexibility of the product.

[0051] Therefore, the embodiments of this application will be further described below with reference to the accompanying drawings.

[0052] Reference Figure 1 As shown, Figure 1 This is an optional schematic diagram of the relay adjustment circuit of an endoscope provided in the embodiments of this application. The relay adjustment circuit of the endoscope includes an input interface 10, a clock buffer 20, an input impedance adjustment module 30, an output matching adjustment module 40, and an output interface 50. The input terminal of the clock buffer 20 is electrically connected to the input interface 10. The input impedance adjustment module 30 is connected in parallel to the input terminal and the ground terminal of the clock buffer 20. The output matching adjustment module 40 is electrically connected to the output terminal of the clock buffer 20. The output interface 50 is electrically connected to the output matching adjustment module 40.

[0053] The input interface 10 is used to connect to the control board of the endoscope and receive the first clock drive signal XCLK output by the control board. The input impedance adjustment module 30 is used to adjust the input impedance of the clock buffer 20 so that the load capacity of the clock buffer 20 matches the driving capacity of the first clock drive signal XCLK.

[0054] The clock buffer 20 is used to receive the first clock drive signal XCLK transmitted from the input interface 10 and adjusted by the input impedance adjustment module 30, and enhance the driving capability of the adjusted first clock drive signal XCLK to obtain the second clock drive signal and output it; wherein, the output matching adjustment module 40 is used to adjust the peak-to-peak value of the second clock drive signal to output a third clock drive signal S_XCLK with identifiable high and low level characteristics; the output interface 50 is used to transmit the third clock drive signal S_XCLK to the image sensor of the endoscope.

[0055] It should be noted that the operating voltage of the clock buffer 20 is equal to the operating voltage of the image sensor, and the input / output frequency of the clock buffer 20 is greater than the frequency of the first clock drive signal XCLK.

[0056] In one possible embodiment, the clock buffer 20 operates at a voltage of 3.3V.

[0057] The clock buffer 20 is one of the key components of this application. Adding the clock buffer 20 to the endoscope handle offers two advantages. First, due to differences in the control motherboard designs of various endoscope manufacturers, the high and low levels of the first clock drive signal XCLK output by the motherboard vary. Inserting the clock buffer 20 at the endoscope handle ensures that the output clock signal has fixed high and low levels and good falling and rising edges. Second, as the clock connection length increases, the load capacitance of the connection increases, leading to greater delay. Without the clock buffer 20, the parasitic capacitance along the entire transmission line increases, resulting in significant signal delay. Inserting the clock buffer 20 at the handle's connection plate reduces the circuit's load capacitance, thereby increasing the driving capability of the clock drive signal XCLK.

[0058] It is worth noting that, in this embodiment, by integrating a dedicated clock buffer 20 inside the endoscope handle, the attenuated motherboard clock signal after long-distance transmission can be effectively reshaped and its driving capability enhanced. This completely solves the core problem of signal edge sluggishness and insufficient driving capability caused by the variation in transmission line length from 1m to 4m, ensuring that the signal maintains complete waveform characteristics when transmitted to the remote probe. Simultaneously, by introducing an input impedance adjustment module 30, a flexible parallel impedance network enables the input impedance of the relay circuit to accurately match the driving capability of clock signals output from motherboards of different manufacturers and designs, effectively suppressing signal reflection and improving the integrity of front-end signal reception and system compatibility. Furthermore, the output matching adjustment module 40 adjusts the amplitude (peak value) of the enhanced clock signal. The fine adjustment of the peak value enables the output of a clock signal with stable high and low levels that strictly meets the image sensor recognition requirements (e.g., 0.8V~2.0V), fundamentally ensuring the accuracy of image data acquisition timing. Secondly, as an independent intermediate drive node located in the handle, this relay circuit greatly expands the adaptability of the endoscope system. The same host platform can flexibly adapt to probes with different cable lengths, significantly reducing the overall design change costs and complexity caused by cable specification upgrades, and enhancing the product's adaptability and flexibility. Finally, by thoroughly improving the quality of the clock signal in the relay stage, this solution directly improves the stability of the image sensor's acquired data, ultimately presenting a clear, stable, ghosting-free, and jitter-free high-quality image on the display, significantly enhancing the reliability of medical diagnosis or industrial inspection and improving the user experience.

[0059] In one possible embodiment, the relay adjustment circuit further includes a first analog ground interface 60 and a second analog ground interface 70. The first analog ground interface 60 is electrically connected to the ground terminals of the input impedance adjustment module 30 and the clock buffer 20, respectively. The second analog ground interface 70 is electrically connected to the output matching adjustment module 40. The first analog ground interface 60 is used to connect to the control board of the endoscope to ground the clock buffer 20 and the input impedance adjustment module 30. The second analog ground interface 70 is used to connect to the control board of the endoscope to ground the output matching adjustment module 40.

[0060] It should be noted that, in this embodiment, by setting up independent first analog grounding interface 60 and second analog grounding interface 70, the physical separation of the input and output circuit grounding paths is achieved. This innovative design forms a complete and isolated analog signal grounding system: the first analog grounding interface 60 directly leads the grounding terminals of the clock buffer 20 and the input impedance adjustment module 30 back to the control motherboard grounding reference point, ensuring that the input stage signal is referenced to the motherboard ground plane, effectively avoiding potential deviation and noise interference caused by inconsistent grounding paths; the second analog grounding interface 70 provides an independent, low-impedance dedicated grounding return path for the output matching adjustment module 40, enabling the enhanced clock signal to be amplitude adjusted and output with a clean reference plane, completely blocking the coupling interference of the large current of the output stage to the sensitive input grounding circuit during the return process. This separated grounding architecture significantly improves the common-mode noise immunity and system stability of the entire relay drive circuit, ensuring that the rising / falling edges of the clock signal remain steep and clean after long-distance transmission, and that the high and low level amplitudes are accurately and stably within the image sensor recognition threshold of 0.8V~2.0V, thereby greatly improving the integrity and reliability of signal transmission. Meanwhile, this design enhances the compatibility and adaptability of the relay circuit to different motherboard designs and grounding layouts, providing a crucial foundation for the endoscope system to adapt to various long probes ranging from 1 to 4 meters in length and ultimately present jitter-free, distortion-free high-definition images on the display end.

[0061] Furthermore, the input impedance adjustment module 30 includes a first resistor 31, one end of which is electrically connected to the input terminal of the clock buffer 20, and the other end of which is electrically connected between the ground terminal of the clock buffer 20 and the first analog ground interface 60. In one possible embodiment, the value of the first resistor 31 is in the range of 1kΩ to 10kΩ.

[0062] It should be noted that, in this embodiment, a precisely controllable input impedance matching network is constructed by directly connecting the first resistor 31 in the input impedance adjustment module 30 between the input terminal of the clock buffer 20 and the first analog ground interface 60. This design eliminates the dependence of the input loop impedance adjustment on the common ground plane on the PCB board, instead allowing it to trace back directly to the clean reference ground of the motherboard through an independent analog ground interface, effectively avoiding noise interference and potential fluctuations introduced by the common ground impedance. The resistance value of the first resistor 31 can be precisely configured according to the driving capability of different motherboard clock signals, ensuring optimal matching between the input impedance and the signal source. This avoids both excessively high impedance leading to increased signal reflection and excessively low impedance causing overloading of the preceding motherboard driver circuit. This precise impedance matching not only significantly improves the signal-to-noise ratio and signal integrity at the clock signal input, ensuring that the clock buffer 20 can receive input signals with clear edges and stable levels, but also enhances compatibility with motherboard designs from different manufacturers. This allows the relay circuit to stably adapt to motherboards with various output characteristics, laying a solid foundation for subsequent signal enhancement and transmission.

[0063] Furthermore, refer to Figure 1 or Figure 2 The above, Figure 2 This is a schematic diagram of a second optional relay adjustment circuit for an endoscope provided in this application embodiment. The output matching adjustment module 40 includes a second resistor 41 and a first capacitor 42. One end of the second resistor 41 is electrically connected to the output terminal of the clock buffer 20, and the other end of the second resistor 41 is electrically connected to the output interface 50. Figure 1 It can be seen that the first terminal of the first capacitor 42 is electrically connected between the second resistor 41 and the output interface 50, and the second terminal of the first capacitor 42 is electrically connected to the second analog ground interface 70. From Figure 2 It is known that the first end of the first capacitor 42 is electrically connected between the second resistor 41 and the output end of the clock buffer 20, and the second end of the first capacitor 42 is electrically connected to the second analog ground interface 70. Placing the first capacitor 42 in front of the second resistor 41 and electrically connecting it to the output end of the clock buffer 20 enables the output matching adjustment module 40 to better suppress signal reflection.

[0064] It should be noted that this embodiment of the application constructs a highly efficient and reliable signal conditioning and output network by employing a collaborative design of a second resistor 41 and a first capacitor 42 in the output matching and adjustment module 40. The second resistor 41 is connected in series between the output terminal of the clock buffer 20 and the output interface 50, which not only plays a role in impedance matching and effectively suppresses signal reflection, but also acts as a current-limiting resistor to protect the output stage circuit. The first capacitor 42 is connected in parallel between the output terminal of the clock buffer 20 and the second analog ground interface 70, forming an RC filter network with the second resistor 41, which can effectively filter out high-frequency harmonic noise and power supply noise of the clock signal, significantly purifying the output signal waveform. This structure precisely controls the amplitude and driving capability of the output signal through the second resistor 41, and provides a clean high-frequency ground path through the first capacitor 42. The two work together to ensure that the output third clock drive signal S_XCLK has a steep rising / falling edge and a stable peak-to-peak value. In particular, by directly connecting the ground terminal of the first capacitor 42 to the independent second analog ground interface 70, rather than a common ground plane, the path of output stage noise to interfere with the front-end circuit through ground coupling is completely blocked, greatly improving the anti-interference capability of the system. This design ensures that the high and low levels of the output clock signal are stably maintained within the ideal range of 0.8-2.0V, guaranteeing that image sensors at the ends of transmission lines of different lengths (1-4 meters) can receive a complete and reliable clock signal. This significantly improves image acquisition quality and display stability, while also enhancing the system's adaptability and compatibility with probes of different line lengths.

[0065] It is worth noting that the second resistor 41 and the first capacitor 42 form an RC filter network. When the second clock drive signal output from the clock buffer 20 is matched by the RC filter network, the output third clock drive signal S_XCLK provides a high-quality clock signal for the endoscope's image sensor. In this output matching adjustment module 40, appropriate values ​​for the second resistor 41 and the first capacitor 42 need to be selected. If the value of the first capacitor 42 is too large, the peak-to-peak value of the output clock signal will be small after the circuit reaches steady state, and the image sensor will not be able to effectively acquire data. Conversely, the value of the first capacitor 42 should not be too small. If the value of the first capacitor 42 is too small, it only smooths out the signal edges and cannot effectively adjust the peak-to-peak value of the clock signal, affecting the acquired image quality.

[0066] Taking all factors into consideration, the value of the second resistor 41 is in the range of 10Ω to 1.5KΩ, and the value of the first capacitor 42 is in the range of 10pF to 200pF.

[0067] Meanwhile, in the embodiment of this application, the parasitic capacitance of the wire itself can also be taken into account in the output matching adjustment module 40, referring to... Figure 3 As shown, Figure 3This is a schematic diagram of a third optional relay adjustment circuit for an endoscope provided in this application embodiment, in which the first capacitor 42 can be removed independently. Alternatively, refer to... Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of a fourth optional relay adjustment circuit for an endoscope provided in the embodiments of this application. Figure 5 This is a fifth optional schematic diagram of the relay adjustment circuit of the endoscope provided in the embodiments of this application. In the embodiments of this application, the first resistor 31 can also be removed separately. Therefore, circuits formed by changing their implementation without departing from the technical principles of this application should also fall within the protection scope of this application.

[0068] Furthermore, the aforementioned relay adjustment circuit also includes a third resistor, which is connected in series between the output matching adjustment module 40 and the output interface 50. The third resistor is used to absorb the reflected signal corresponding to the image sensor transmitted through the output interface 50.

[0069] It should be noted that this embodiment constructs a highly efficient reflected signal absorption network by connecting a third resistor in series between the output matching adjustment module 40 and the output interface 50. This resistor can effectively suppress and absorb signal reflection waves caused by transmission line impedance mismatch, preventing reflected signals from forming standing waves or causing signal overshoot / undershoot in the transmission channel, significantly improving signal integrity. The precise matching between the third resistor and the characteristic impedance of the transmission line allows signal energy to be effectively transferred to the remote load instead of being reflected back to the source, ensuring the clarity and stability of the clock signal waveform. This design is particularly suitable for application scenarios with transmission lines of different lengths, and can adaptively eliminate impedance mismatch problems caused by changes in line length, greatly enhancing the system's compatibility with various probes. By suppressing reflection interference, this structure ensures that the third clock drive signal S_XCLK transmitted to the image sensor has accurate and stable high and low level timing, thereby reducing image jitter, ghosting, or data acquisition errors caused by signal reflection, significantly improving the stability and reliability of the display image quality. At the same time, this solution does not require complex active circuits, achieving efficient signal conditioning with simple passive components, reducing system cost and design complexity.

[0070] A second aspect of this application also provides an endoscope, which includes: a handle, a control motherboard, and a probe. The control motherboard is connected to a control terminal interface circuit 80 via a transmission line. The control motherboard is used to transmit a first clock drive signal to the handle. The probe includes an image sensor, which is connected to a probe terminal interface circuit 90 via a transmission line. The image sensor is used to receive a third clock drive signal obtained after signal enhancement by a relay adjustment circuit, and to acquire endoscopic images based on the third clock drive signal.

[0071] Among them, reference Figure 6 and Figure 7 As shown, Figure 6 This is a schematic diagram of an optional control interface circuit for an endoscope provided in an embodiment of this application. Figure 7 This is an optional schematic diagram of the probe end interface circuit of the endoscope provided in the embodiments of this application. The handle includes a control end interface circuit 80, a probe end interface circuit 90, and the aforementioned relay adjustment circuit of the endoscope. The input interface 10 in the relay adjustment circuit is electrically connected to the control end interface circuit 80, and the output interface 50 in the relay adjustment circuit is electrically connected to the probe end interface circuit 90.

[0072] It should be noted that the endoscope in this embodiment integrates a dedicated relay adjustment circuit inside the endoscope handle, constructing a complete signal enhancement and conditioning system, thus fundamentally improving the quality of clock signal transmission. This relay circuit is cleverly positioned at a critical transmission node between the control motherboard and the probe image sensor. Its input interface 10 connects to the control end interface circuit 80 to receive the attenuated first clock drive signal from the motherboard, and its output interface 50 connects to the probe end interface circuit 90 to output an enhanced third clock drive signal to the remote image sensor. This architecture allows the relay circuit to precisely compensate for signal attenuation caused by transmission lines of different lengths (1-4 meters), significantly enhancing signal driving capability through the clock buffer 20, ensuring that the signal maintains its complete waveform characteristics even at the longest transmission distance. The input impedance adjustment module 30 achieves perfect matching with the output characteristics of different motherboards, while the output matching adjustment module 40 finely adjusts the signal amplitude through an RC network, stabilizing the high and low voltage difference of the output clock signal within the ideal recognition range of 0.8-2.0V. In particular, the independent dual-ground interface design completely eliminates grounding interference, and the series-connected third resistor effectively absorbs reflected signals, further ensuring the integrity of signal transmission. Ultimately, this solution enables the image sensor to obtain a stable, clean, and timing-accurate clock signal, completely resolving issues such as image jitter, blurring, and stripe interference caused by long-distance transmission, significantly improving image quality at the display end. Simultaneously, it allows the same endoscope system to be compatible with probe transmission lines of different specifications, greatly enhancing the product's adaptability and application range, and providing more reliable visual assurance for medical diagnosis.

[0073] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0074] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0075] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0076] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0077] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0078] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0079] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0080] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0081] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0082] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0083] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A relay adjustment circuit for an endoscope, characterized in that, The endoscope handle, used inside, includes: An input interface is used to connect to the control board of the endoscope and receive the first clock drive signal output by the control board. A clock buffer, the input terminal of which is electrically connected to the input interface; An input impedance adjustment module is connected in parallel to the input terminal and the ground terminal of the clock buffer. An output matching adjustment module is electrically connected to the output terminal of the clock buffer. An output interface, which is electrically connected to the output matching adjustment module; The first analog grounding interface is electrically connected to the grounding terminals of the input impedance adjustment module and the clock buffer, respectively. The first analog grounding interface is used to connect the control board of the endoscope to ground the clock buffer and the input impedance adjustment module. The second analog grounding interface is electrically connected to the output matching adjustment module. The second analog grounding interface is used to connect the control board of the endoscope to ground the output matching adjustment module. The input impedance adjustment module is used to adjust the input impedance of the clock buffer so that the load capacity of the clock buffer matches the driving capacity of the first clock drive signal. The clock buffer is used to receive the first clock drive signal transmitted from the input interface and adjusted by the input impedance adjustment module, and to enhance the driving capability of the adjusted first clock drive signal to obtain a second clock drive signal and output it. The output matching adjustment module is used to adjust the peak-to-peak value of the second clock drive signal to output a third clock drive signal with identifiable high and low level characteristics; The output interface is used to transmit the third clock drive signal to the image sensor of the endoscope.

2. The relay regulation circuit according to claim 1, characterized in that, The input impedance adjustment module includes a first resistor, one end of which is electrically connected to the input terminal of the clock buffer, and the other end of which is electrically connected between the ground terminal of the clock buffer and the first analog ground interface.

3. The relay regulation circuit according to claim 2, characterized in that, The value of the first resistor is in the range of 1kΩ to 10kΩ.

4. The relay regulation circuit according to claim 1, characterized in that, The output matching adjustment module includes a second resistor and a first capacitor; One end of the second resistor is electrically connected to the output terminal of the clock buffer, and the other end of the second resistor is electrically connected to the output interface; The first terminal of the first capacitor is electrically connected between the second resistor and the output terminal of the clock buffer, or the first terminal of the first capacitor is electrically connected between the second resistor and the output interface; The second terminal of the first capacitor is electrically connected to the second analog ground interface.

5. The relay regulation circuit according to claim 4, characterized in that, The value of the second resistor ranges from 10Ω to 1.5KΩ, and the value of the first capacitor ranges from 10pF to 200pF.

6. The relay regulation circuit according to claim 1, characterized in that, Also includes: A third resistor is connected in series between the output matching adjustment module and the output interface. The third resistor is used to absorb the reflected signal corresponding to the image sensor transmitted through the output interface.

7. The relay regulation circuit according to claim 1, characterized in that, The operating voltage of the clock buffer is equal to the operating voltage of the image sensor, and the input / output frequency of the clock buffer is greater than the frequency of the first clock drive signal.

8. The relay regulation circuit according to claim 7, characterized in that, The clock buffer operates at a voltage of 3.3V.

9. An endoscope, characterized in that, include: The handle includes a control terminal interface circuit, a probe terminal interface circuit, and a relay adjustment circuit for an endoscope as described in any one of claims 1 to 8. The input interface of the relay adjustment circuit is electrically connected to the control terminal interface circuit, and the output interface of the relay adjustment circuit is electrically connected to the probe terminal interface circuit. A control motherboard is connected to the control terminal interface circuit via a transmission line. The control motherboard is used to transmit a first clock drive signal to the handle. A probe, which includes an image sensor, is connected to the transmission line of the detection end interface circuit. The image sensor is used to receive the third clock drive signal obtained after signal enhancement by the relay adjustment circuit, and to acquire endoscopic images based on the third clock drive signal.

Images