Three-dimensional embedded non-volatile memory, manufacturing method, chip, device, apparatus

Abstract

The application relates to a three-dimensional embedded nonvolatile memory, a manufacturing method, a chip, an apparatus and a device, wherein a plurality of self-selecting memories are contained in each storage layer through vertical stacking of multiple storage layers, so that the vertically stacked three-dimensional architecture can integrate more self-selecting memories in a unit area, the storage capacity is improved to meet high-density storage requirements, such as the storage requirements of a large language model, support in-memory computing and near-memory computing, and have high-bandwidth, low-delay matrix vector multiplication acceleration capability; the self-selecting memory can realize self-selecting storage when reaching an opening voltage, avoid additional area overhead caused by the introduction of a transistor, reduce the area of a single memory, simplify the structure of the storage layer, and improve the integration of the memory.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional embedded non-volatile memory, its fabrication method, chip, device, and equipment. Background Technology

[0002] With the rapid development of fields such as the Internet of Things, artificial intelligence, and data centers, higher demands are being placed on the density, speed, energy efficiency, and integration of memory. For example, edge inference tasks require storage capacity (storage density) within a certain area, but the on-chip integrated static random access memory (SRAM) has limited capacity, requiring the loading of weights from off-chip dynamic random access memory (DRAM). This results in significant energy consumption. Storing the weights on-chip can greatly improve energy efficiency and bandwidth.

[0003] Resistive Random Access Memory (RRAM) offers advantages such as non-volatility, low power consumption, and compatibility with CMOS back-end processes, making it a promising candidate for weighted memory applications. However, the current mainstream RRAM architecture is a 1T1R architecture (one transistor and one resistive random access cell), which faces bottlenecks in both array miniaturization and 3D integration, limiting its large-scale 3D integration in storage or in-memory computing systems. Summary of the Invention

[0004] Therefore, it is necessary to provide a three-dimensional embedded non-volatile memory, manufacturing method, chip, device, or equipment to address the problems in the existing technology.

[0005] In a first aspect, this application provides a three-dimensional embedded non-volatile memory, which is integrated with a logic chip; the three-dimensional embedded non-volatile memory includes multiple vertically stacked storage layers;

[0006] Each of the storage layers includes:

[0007] A first selection line extends along a first direction and is spaced out along a second direction;

[0008] The second selection line extends along the second direction and is spaced apart along the first direction, and the first direction intersects the second direction;

[0009] The self-selection memory is disposed at the intersection of the first selection line and the second selection line, along the vertical direction, and the self-selection memory is located between the first selection line and the second selection line. Each self-selection memory includes at least one functional layer.

[0010] Optionally, adjacent storage layers in the vertical direction may share either the first selection line or the second selection line.

[0011] Optionally, when adjacent storage layers share the first selection line, the self-selection memories in the same column are independently addressed and operated through different second selection lines;

[0012] When adjacent storage layers share the second selection line, the self-selection memories in the same row are independently addressed and operated through different first selection lines.

[0013] Optionally, the self-selection memory includes a first functional layer and a second functional layer stacked in a vertical direction, wherein one of the first functional layer and the second functional layer is a gating layer and the other is a resistive switching layer;

[0014] The resistive switching layer can reversibly switch between a high-resistivity state and a low-resistivity state to store data;

[0015] The gating layer is used to control the on / off state of current in the self-selection memory, so as to conduct the current path of the selected self-selection memory during read / write operations.

[0016] Optionally, the material of the gate layer includes at least one of niobium oxide and vanadium oxide;

[0017] The resistive switching layer is made of at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0018] Optionally, the self-selecting memory further includes at least one auxiliary function layer, which is selected from at least one of the following:

[0019] A heat transfer layer is disposed between the first functional layer and the second functional layer, wherein the thermal conductivity of the heat transfer layer is less than that of the resistive switching layer;

[0020] A barrier layer is disposed between the functional layer and the first selection line to form a barrier with the first selection line, or it is disposed between the functional layer and the second selection line to form a barrier with the second selection line;

[0021] A buffer layer is disposed between the functional layer and the barrier layer, wherein the electron affinity of the buffer layer is between the functional layer and the barrier layer;

[0022] A first electrode layer and a second electrode layer, wherein the first electrode layer is disposed between the first functional layer and the first selection line, and the second electrode layer is disposed between the second functional layer and the second selection line;

[0023] A diffusion barrier layer is in contact with the first selection line, or the diffusion barrier layer is in contact with the second selection line.

[0024] Optionally, the three-dimensional embedded non-volatile memory further includes:

[0025] A sidewall passivation layer covers the sidewalls of the self-selecting memory;

[0026] A conductive plug is disposed on the top surface of the self-selection memory, and the self-selection memory is connected to the first selection line or the second selection line above it through the conductive plug.

[0027] In a second aspect, this application provides an edge chip, including a substrate and a logic chip integrated on the substrate, as well as a three-dimensional embedded non-volatile memory as described in the first aspect.

[0028] The three-dimensional embedded non-volatile memory is disposed on the logic chip, or the three-dimensional embedded non-volatile memory and the logic chip are respectively disposed on the substrate.

[0029] Thirdly, this application provides an electronic device including a three-dimensional embedded non-volatile memory as described in the first aspect, or including an edge chip as described in the second aspect.

[0030] Fourthly, this application provides a method for fabricating a three-dimensional embedded non-volatile memory, comprising:

[0031] Multiple first selection lines are formed on the substrate, the first selection lines extending along a first direction and spaced apart along a second direction;

[0032] A plurality of self-selection memories are formed on the side of the first selection line away from the substrate, and the self-selection memories are arrayed along the first direction and the second direction; the self-selection memories include a functional layer;

[0033] Multiple second selection lines are formed on the side of the self-select memory away from the first selection line. The second selection lines extend along the second direction and are spaced apart along the first direction. The multiple first selection lines, the multiple self-select memories, and the multiple second selection lines form a storage layer.

[0034] The steps of forming multiple first selection lines, forming multiple self-selecting memories, and forming multiple second selection lines are repeatedly performed to form a vertically stacked multi-layer memory layer.

[0035] Optionally, forming the storage layer includes:

[0036] A first selective material layer and a functional stack are formed on the substrate, wherein the functional stack includes at least a first functional layer and a second functional layer.

[0037] The functional stack and the first selected material layer are etched to form a first trench extending along the first direction, dividing the first selected material layer into multiple first selection lines;

[0038] A second selective material layer is formed to cover the top surface of the functional stack;

[0039] The second selective material layer and the functional stack are etched to form a second trench extending along the second direction, dividing the second selective material layer into multiple second selection lines; the first trench and the second trench divide the functional stack into multiple self-selection memories; one of the first functional layer and the second functional layer of the self-selection memory is a resistive switching layer and the other is a gated layer.

[0040] Optionally, forming the storage layer includes:

[0041] A first selective material layer is formed on the substrate, and the first selective material layer is etched to form a plurality of first selective lines;

[0042] A functional stack is formed, the functional stack covering the top surface of the first selected material layer, the functional stack including at least a first functional layer and a second functional layer;

[0043] The functional stack is patterned and etched to form a plurality of self-select memory layers on the side of the first selection line away from the substrate; one of the first functional layer and the second functional layer of the self-select memory layer is a resistive switching layer and the other is a gated layer;

[0044] A second selection material layer is formed on the side of the self-selection memory away from the first selection line, and the second selection material layer is etched to form multiple second selection lines.

[0045] Optionally, adjacent storage layers in the vertical direction may share either the first selection line or the second selection line.

[0046] Optionally, the substrate is a logic chip on which CMOS circuitry is formed.

[0047] The three-dimensional embedded non-volatile memory, fabrication method, chip, device, and equipment of this application utilize a vertically stacked multi-layer storage architecture. Each storage layer contains multiple self-selecting memories, allowing for the integration of more self-selecting memories within a unit area. This increases storage capacity to meet high-density storage requirements, such as those for large language models on the edge or in the cloud. It supports in-memory and near-memory computations and features high-bandwidth, low-latency matrix-vector multiplication acceleration capabilities. The self-selecting memories can achieve self-selection storage when the turn-on voltage is reached, eliminating the need for additional gating devices. This reduces the footprint of a single self-selecting memory, simplifies the storage layer structure, and improves the integration density of the memory. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A three-dimensional topology circuit diagram of a three-dimensional embedded non-volatile memory provided in one embodiment;

[0050] Figure 2a This is a schematic diagram of the three-dimensional structure of a three-dimensional embedded non-volatile memory provided in one embodiment;

[0051] Figure 2b A cross-sectional view of a three-dimensional embedded non-volatile memory provided in one embodiment;

[0052] Figure 3a This is a schematic diagram of the structure of a self-selecting memory provided in one embodiment;

[0053] Figure 3b This is a schematic diagram of the structure of a self-selecting memory provided in another embodiment;

[0054] Figure 3c This is a schematic diagram of the structure of a self-selecting memory provided in yet another embodiment;

[0055] Figure 3d This is a schematic diagram of the self-selection memory provided in the fourth embodiment;

[0056] Figure 3e This is a schematic diagram of the self-selection memory provided in the fifth embodiment;

[0057] Figure 3f This is a schematic diagram of the self-selection memory provided in the sixth embodiment;

[0058] Figure 4 This is a block diagram of an edge chip provided in one embodiment;

[0059] Figure 5a This is a schematic diagram of the edge chip structure provided in one embodiment;

[0060] Figure 5b This is a schematic diagram of the edge chip structure provided in another embodiment;

[0061] Figure 5c This is a schematic diagram of the edge chip structure provided in one embodiment;

[0062] Figure 5d This is a schematic diagram of the edge chip structure provided in another embodiment;

[0063] Figure 5e This is a schematic diagram of the edge chip provided in another embodiment;

[0064] Figure 5f This is a schematic diagram of the edge chip provided in the fourth embodiment;

[0065] Figure 5g This is a schematic diagram of the edge chip provided in the fifth embodiment;

[0066] Figure 5h This is a schematic diagram of the edge chip provided in the sixth embodiment;

[0067] Figure 6 This is a process flow diagram of a method for fabricating a three-dimensional embedded non-volatile memory provided in one embodiment;

[0068] Figure 7 This is a process flow diagram of a method for fabricating a three-dimensional embedded non-volatile memory provided in one embodiment;

[0069] Figure 8 This is a schematic diagram of the structure after forming the first selected material layer and the functional stack in one embodiment;

[0070] Figure 9 This is a schematic diagram of the structure after the first trench is formed, provided in one embodiment;

[0071] Figure 10 This is a schematic diagram of the structure after the first dielectric layer is filled into the first trench, as provided in one embodiment;

[0072] Figure 11 This is a schematic diagram of the structure after forming the second selective material layer in one embodiment;

[0073] Figure 12This is a schematic diagram of the structure after forming the second trench with the second selection line and the self-selection memory in one embodiment;

[0074] Figure 13 This is a schematic diagram of the structure after the second dielectric layer is filled into the second trench, as provided in one embodiment;

[0075] Figure 14 A process flow diagram of a method for fabricating a three-dimensional embedded non-volatile memory provided in another embodiment;

[0076] Figure 15 This is a schematic diagram of the structure after the first selected material layer is formed in one embodiment;

[0077] Figure 16 This is a schematic diagram of the structure after the first selection line is formed in one embodiment;

[0078] Figure 17 This is a schematic diagram of the structure after the functional layers are formed in one embodiment;

[0079] Figure 18 This is a schematic diagram of the structure after the self-selection memory is formed in one embodiment;

[0080] Figure 19 This is a schematic diagram of the structure after filling the space between the self-selecting memories with a second dielectric layer in one embodiment;

[0081] Figure 20 This is a schematic diagram of the structure after the second selection line is formed in one embodiment;

[0082] Figure 21 This is a schematic diagram of the structure after the protective layer is formed on the first selection line in another embodiment;

[0083] Figure 22 This is a schematic diagram of the structure after removing the protective layer on the first selection line and forming a diffusion barrier layer on the first selection line in another embodiment;

[0084] Figure 23 This is a schematic diagram of the structure after the functional stack is formed in another embodiment;

[0085] Figure 24 This is a schematic diagram of the structure after the self-selection memory is formed in another embodiment;

[0086] Figure 25 This is a schematic diagram of the structure after filling the space between the self-selecting memories in another embodiment;

[0087] Figure 26 This is a schematic diagram of the structure after the second selection line is formed in another embodiment;

[0088] Figure 27This is a schematic diagram of the structure after an insulating layer is formed covering the sidewall of the self-select memory in one embodiment;

[0089] Figure 28 This is a schematic diagram of the structure after the third dielectric layer is formed in one embodiment;

[0090] Figure 29 This is a schematic diagram of the structure after the second dielectric layer covers the third dielectric layer in one embodiment;

[0091] Figure 30 This is a schematic diagram of the structure after forming a through-hole to expose the top surface of the self-select memory in one embodiment;

[0092] Figure 31 This is a schematic diagram of the structure after the conductive plug is formed in one embodiment;

[0093] Figure 32 This is a schematic diagram of the structure after the bit line comes into contact with the conductive plug in one embodiment.

[0094] Explanation of reference numerals in the attached figures:

[0095] 1. Three-dimensional embedded non-volatile memory; 2. Logic chip; 3. Edge chip; 4. Substrate; 5. Carrier board; 6. Intermediate layer; 7. Solder block; 10. Storage layer; 11. First select line; 111. First select material layer; 12. Self-select memory; 120. Functional stack; 121. First functional layer; 122. Second functional layer; 123. Heat transfer layer; 124. Barrier layer; 125. Buffer layer; 126. First electrode layer; 127. Second electrode layer; 128. Diffusion barrier Layer; 13, Second Select Line; 131, Second Select Material Layer; 141, First Dielectric Layer; 142, Second Dielectric Layer; 151, First Trench; 152, Second Trench; 16, Protective Layer; 17, Sidewall Passivation Layer; 171, Insulating Layer; 172, Third Dielectric Layer; 18, Conductive Plug; 20, Peripheral Circuit; 30, Drive Circuit; 31, First Drive Transistor; 32, Second Drive Transistor; 8, Rewiring Layer; X, First Direction; Y, Second Direction; Z, Vertical Direction. Detailed Implementation

[0096] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0097] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0098] Currently, in 1T1R architecture resistive random access memory (IRRAM), each resistive switching cell requires an independent transistor as a selection device, resulting in a large footprint for a single IRRAM. The large transistor footprint and the need for complex multi-layer metal wiring for vertical interconnection make three-dimensional integration of 1T1R architecture IRRAM difficult, hindering its ability to meet high-density storage requirements.

[0099] In related solutions, diodes, bidirectional threshold switches (OTS selectors), or wire-type selectors are used to replace transistors to form self-selection memories. However, diodes suffer from unipolar operation and insufficient driving capability. OTS (Ovonic Threshold Switching Selector) is a nonlinear resistive switching device based on chalcogenide materials (such as Ge-Sb-Te, GeSe, etc.). Chalcogenide materials suffer from inherent elemental segregation leading to insufficient durability, performance fluctuations, and poor thermal stability, making it difficult to meet the practical requirements of edge-side non-volatile memories. Wire-type selectors have long relaxation times, resulting in long turn-off times.

[0100] Furthermore, to meet the back-end fabrication process requirements for CMOS logic circuits, thermal budget compatibility and material compatibility must be satisfied. The tolerance range of CMOS back-end of line (BEOL) processes (below 400°C) is limited. For example, the crystallization temperature of bidirectional threshold switching (OTS) transistors is low; high-temperature annealing can cause the OTS transistors to crystallize and lose their threshold switching characteristics. On the other hand, to improve the performance of some transistors, multi-element doping or easily diffused metal electrodes such as silver (Ag) may be introduced during the process. These materials have poor compatibility with the back-end processes of CMOS logic circuits, making process integration difficult and hindering the integration of resistive random access memory (RRAM) with CMOS logic circuits.

[0101] In view of this, this application provides a three-dimensional embedded non-volatile memory, a fabrication method, a chip, an apparatus, and a device. The three-dimensional embedded non-volatile memory is integrated with a logic chip. The fabrication process of this application's three-dimensional embedded non-volatile memory does not require high-temperature annealing and does not introduce too many new elements. It is compatible with CMOS logic processes and materials and can be directly integrated in the back-end of standard logic processes. Furthermore, this application's three-dimensional embedded non-volatile memory, through multi-layer stacking, can provide high-density on-chip integrated non-volatile memory for edge devices. For example, using a 40nm node CMOS process, under the constraints of back-end metal layer height and metal linewidth, stacking 5 layers of single-bit non-volatile memory cells can achieve ≥90Mb / mm². 2 The array density is high. This three-dimensional embedded non-volatile memory can be used not only as an embedded memory but also as a standalone storage device. As a standalone storage device, the limitations on inter-layer height and linewidth can be relaxed, allowing for higher storage densities. For example, using a single exposure with a 16nm CMOS process or a double exposure with a 45nm CMOS process, stacking four layers of non-volatile memory cells can achieve ≥2000Mb / mm². 2 The array density of this application increases with the number of stacked layers and the miniaturization of process nodes, extending to more advanced logic processes. Storage density can be further increased by storing multiple bits of information in each non-volatile memory cell. Furthermore, matrix-vector multiplication calculations can be accelerated in in-memory or near-memory computations, reducing the efficiency and energy consumption of artificial intelligence (AI) data stream transmission by providing high read bandwidth and latency. Threshold-adjustable neuron arrays can also be implemented to achieve large-scale three-dimensional integrated neuronal circuits, improving the energy efficiency of neuromorphic computing.

[0102] According to an exemplary embodiment, this application provides a three-dimensional embedded non-volatile memory 1, which is integrated with a logic chip 2; see reference Figure 1 , Figure 2a , Figure 2bAs shown, the three-dimensional embedded non-volatile memory 1 includes multiple vertically stacked storage layers 10, and the number of storage layers 10 is at least two. For example, the three-dimensional embedded non-volatile memory 1 may include two storage layers 10, three storage layers 10, four storage layers 10 or more. Each storage layer 10 includes a first selection line 11, a self-selection memory 12, and a second selection line 13 arranged sequentially along the vertical direction Z. The first selection line 11 extends along the first direction X and is spaced along the second direction Y. The second selection line 13 extends along the second direction Y and is spaced along the first direction X. The first direction X and the second direction Y intersect. The vertical direction Z is perpendicular to the plane containing the first direction X and the second direction Y, and the first direction X and the second direction Y are not parallel. The self-selection memory 12 is located at the intersection of the first selection line 11 and the second selection line 13. Along the vertical direction Z, the self-selection memory 12 is located between the first selection line 11 and the second selection line 13. One of the first selection line 11 and the second selection line 13 can be a word line WL and the other can be a bit line BL. One end of the self-selection memory 12 is connected to the first selection line 11 and the other end is connected to the second selection line 13. Each self-selection memory 12 includes at least one functional layer. When the self-selection memory 12 reaches the turn-on voltage, it can realize self-selection storage.

[0103] The aforementioned three-dimensional embedded non-volatile memory 1 uses a vertically stacked multi-layer storage layer 10, with each storage layer 10 containing multiple self-selecting memories 12. This vertically stacked architecture can integrate more self-selecting memories 12 within a unit area, increasing storage capacity to meet high-density storage requirements, such as the storage requirements of large language models. It supports Processing-in-Memory (PIM) and Processing Near Memory (PNM) computations, and has high-bandwidth, low-latency matrix-vector multiplication acceleration capabilities. The self-selecting memories 12 can achieve self-selected storage when the turn-on voltage is reached, without the need for additional gating devices (such as transistors) to be integrated with them, reducing the area occupied by a single self-selecting memory 12, simplifying the structure of the storage layer 10, and improving the integration of the memory.

[0104] The fabrication of the aforementioned three-dimensional embedded non-volatile memory 1 does not require steps such as high-temperature annealing that may damage CMOS logic circuits. At the same time, it reduces the need to introduce materials that are incompatible with CMOS processes, thereby reducing the difficulty of integration with CMOS processes. This makes the three-dimensional embedded non-volatile memory 1 compatible with CMOS processes, and the aforementioned three-dimensional embedded non-volatile memory 1 can achieve homogeneous integration with CMOS logic circuits.

[0105] In some embodiments, refer to Figure 1 , Figure 2a , Figure 2bAs shown, adjacent memory layers 10 in the vertical direction Z share either a first selection line 11 or a second selection line 13. That is, along the vertical direction Z (third direction), the first selection line 11 of adjacent memory layers 10 is the same conductive layer, or the second selection line 13 of adjacent memory layers 10 is the same conductive layer. It can be understood that along the vertical direction Z (third direction), a memory layer 10 can share the first selection line 11 with an adjacent memory layer 10, while another adjacent memory layer 10 can share the second selection line 13. This reduces process steps, improves manufacturing efficiency, and lowers product costs.

[0106] In some embodiments, refer to Figure 1 , Figure 2a , Figure 2b As shown, when adjacent storage layers 10 share the first selection line 11, the self-selection memories 12 in the same column are independently addressed and operated through different second selection lines 13. When reading data from the self-selection memories 12 of the target storage layer 10, by applying a read voltage to the shared first selection line 11 and simultaneously applying an enable voltage to the second selection line 13 of the target layer, while keeping the second selection lines 13 of other layers closed, data can be read from the self-selection memories 12 of the target column in the target layer without interfering with the memories of other layers.

[0107] In other embodiments, when reading data from the selectable memory 12 of the target layer storage layer 10, a 1 / 2 bias method can be used. A working voltage Vdd is applied to the first selection line 11 where the selected selectable memory 12 is located, and 1 / 2 Vdd is applied to the first selection line 11 where the remaining unselected selectable memories 12 in the same layer are located. The second selection line 13 is grounded, and 1 / 2 Vdd is applied to the second selection line 13 where the remaining unselected selectable memories 12 in the same layer are located. In this way, only the selected selectable memory 12 is biased to Vdd, while the remaining selectable memories 12 in the same row are biased to 1 / 2 Vdd (1 / 2 Vdd < turn-on voltage V). th The remaining self-selectable memories 12 in the same layer are biased to 0V. The first selection line 11 and the second selection line 13 of the adjacent layer are turned off. Multiple rows can be opened simultaneously, and multiple self-selectable memories 12 can be selected to improve parallelism.

[0108] Reference Figure 1 , Figure 2a , Figure 2bAs shown, when adjacent storage layers 10 share the second selection line 13, the self-selection memories 12 in the same row are independently addressed and operated through different first selection lines 11. When reading data from the self-selection memories 12 of the target storage layer 10, by applying a read voltage to the shared second selection line 13 and simultaneously applying an enable voltage to the first selection line 11 of the target layer, while keeping the first selection lines 11 of other layers closed, data can be read from the self-selection memories 12 of the target column in the target layer without interfering with the memories of other layers. This ensures that each self-selection memory 12 can be accurately addressed and operated.

[0109] In this embodiment, adjacent storage layers 10 share a selection line and achieve independent addressing, allowing flexible selection of the self-selection memory 12 to operate on a specific layer, row, or column. During data updates, only the layer containing the self-selection memory 12 that needs modification can be operated on, without large-scale read / write operations on the entire storage layer 10, thus improving the efficiency of data operations. At the same time, this design is conducive to memory capacity expansion. The storage capacity and density can be increased by increasing the number of storage layers 10 in the vertical Z direction. The newly added layers can share the selection line with the existing layers without affecting the original addressing and operation methods.

[0110] In some embodiments, refer to Figure 1 , Figure 2a , Figure 2b As shown, the self-selection memory 12 includes a first functional layer 121 and a second functional layer 122 stacked along the vertical direction Z. One of the first functional layer 121 and the second functional layer 122 is a gating layer and the other is a resistive switching layer. The resistive switching layer can reversibly switch between a high-resistance state and a low-resistance state to store data. The gating layer is used to control the current flow in the self-selection memory so as to conduct the current path of the selected self-selection memory 12 during read and write operations.

[0111] In this embodiment, the gating and resistive switching functions are integrated into the same self-select memory 12 through different functional layers, which reduces the complexity of the device structure and connection, reduces the manufacturing difficulty, and is compatible with CMOS process. The self-select memory 12 adopts a stacked structure of the first functional layer 121 and the second functional layer 122 in the vertical Z direction, which makes full use of the vertical third dimension, which is conducive to reducing the area of ​​the self-select memory 12. More self-select memories 12 can be integrated in a unit area, thus improving the storage density.

[0112] In this embodiment, the resistance ratio of the high-resistivity state to the low-resistivity state of the resistive switching layer is ≥2. The leakage current density of the gate layer in the non-conductive state is ≤10. -3 MA / cm², the turn-on voltage of the gate layer in the conducting state is ≤3.5V.

[0113] The gating layer can quickly respond to read / write operation signals, rapidly turning the current path on or off to select a specific self-selected memory 12 for read / write operations. This improves the stability and reliability of data read / write operations, reduces the probability of data errors, and enhances the anti-interference capability of the three-dimensional embedded non-volatile memory 1. During read / write operations, the gating layer can control the current to flow only through the selected self-selected memory 12, preventing current leakage in unselected memories, improving information reading accuracy, and reducing power consumption. Since the three-dimensional embedded non-volatile memory 1 integrates a large number of self-selected memories 12, the gating layer restricts power consumption to only the selected self-selected memories 12, reducing power consumption during standby and read / write operations, thus improving the memory's battery life and heat dissipation performance.

[0114] In this embodiment, suitable materials can be selected according to the functional requirements of the gate layer and the resistive switching layer. The gate layer can be made of materials with good current control characteristics and fast response speed, while the resistive switching layer can be made of materials with stable resistive switching performance and long durability.

[0115] In some embodiments, the material of the gate layer includes at least one of niobium oxide and vanadium oxide. In the gate layer, these materials can respond quickly to voltage signals, enabling precise control of current flow by the gate layer.

[0116] The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide. These materials possess abundant oxygen vacancies and defect states in the resistive switching layer. Under the influence of an electric field, oxygen ions or oxygen vacancies migrate, allowing the resistance of the resistive switching layer to reversibly switch between high and low resistance states. This results in good reliability and durability, meeting the requirements for long-term data storage in the resistive switching layer.

[0117] In this way, by reasonably setting the materials of the gate layer and the resistive switching layer of the self-selection memory 12 to match the materials of the gate layer and the resistive switching layer, the self-selection memory 12 has a self-rectification effect. It will form a potential barrier at the interface of the gate layer and the resistive switching layer. Under the action of forward voltage, the current can pass through the potential barrier relatively easily; while under the action of reverse voltage, the potential barrier will increase significantly, hindering the current from passing through, thereby realizing the self-rectification characteristic. It can effectively suppress the leakage current generated by the self-selection memory 12, reduce the storage errors caused by leakage current, and suppress the additional power consumption generated by leakage current. In this embodiment, the three-dimensional embedded non-volatile memory 1 integrates the self-rectification self-selection memory 12 in three dimensions, which can further reduce the spacing between the self-selection memories 12, thereby reducing the overall size of the memory and increasing the storage density.

[0118] For example, the resistive switching layer is made of tantalum oxide and the gate layer is made of niobium oxide. This can further improve the self-rectification capability of the self-selection memory 12 and suppress leakage current generated by the self-selection memory 12.

[0119] In some embodiments, the gate layer may be doped with dopant elements to improve its stability and electrical properties. For example, the dopant elements in the gate layer may include one or more elements such as aluminum, copper, titanium, zirconium, nitrogen, and silicon.

[0120] In some embodiments, the self-selection memory 12 further includes at least one auxiliary functional layer, which is stacked perpendicularly to the first functional layer 121 and the second functional layer 122. At least one auxiliary functional layer may be disposed between the first functional layer 121 and the second functional layer 122, or between the first functional layer 121 and the first selection line 11; or between the second functional layer 122 and the second selection line 13. The auxiliary functional layer is selected from at least one of the following: a heat transfer layer 123, a barrier layer 124, a buffer layer 125, a first electrode layer 126, a second electrode layer 127, or a diffusion barrier layer 128.

[0121] In some embodiments, refer to Figure 3a The self-select memory 12 also includes a heat transfer layer 123, which is disposed between the first functional layer 121 and the second functional layer 122. The thermal conductivity of the heat transfer layer 123 is lower than that of the resistive switching layer. Thus, during read / write operations, when the gate layer conducts current, the resistive switching layer generates heat, and the heat transfer layer 123 restricts heat dissipation, allowing the gate layer to quickly rise to the turn-on temperature, thereby reducing the turn-on voltage (V) of the self-select memory 12. th The self-select memory 12 enables self-selection of memory. In non-read / write states, the gate layer shuts off current, and the heat transfer layer 123 further reduces the impact of heat on other functional layers, improving memory stability. Simultaneously, the heat transfer layer 123 enhances the thermal stability of the gate layer, delaying temperature decrease and reducing the overall write and read voltages of the self-select memory 12. Furthermore, the heat transfer layer 123 prevents material diffusion between the gate layer and the resistive switching layer from causing performance degradation of the self-select memory 12, thus improving its reliability and performance stability.

[0122] For example, the material of the heat transfer layer 123 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide. The heat transfer layer 123 can be a single-layer structure or a multi-layer structure.

[0123] In some embodiments, refer to Figures 3b-3d The self-select memory 12 also includes a barrier layer 124, which is disposed between the functional layer and the first selection line 11 to form a barrier with the first selection line 11, or disposed between the functional layer and the second selection line 13 to form a barrier with the second selection line 13. The barrier layer 124 and the selection line connected thereto form a Schottky barrier or a tunneling barrier. In this way, the current of the self-select memory 12 is limited by the barrier. During read and write operations, when a suitable voltage is applied, electrons can tunnel through or cross the barrier to enable current conduction; while in the non-read / write state or when a reverse voltage is applied, the barrier will impede the flow of electrons, thereby cutting off the current path and improving the reliability of the selection function of the self-select memory 12.

[0124] For example, the material of barrier layer 124 can be selected to have a high dielectric constant (greater than 3.9) and a wide bandgap. For example, the material of barrier layer 124 includes neodymium oxide (NdO). x ), Strontium oxide (SrO) x germanium oxide (GeO) x lanthanum oxide (LaO) x ), hafnium oxide (HfO) x Gallium oxide (GaO) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), silicon dioxide (SiO) x ), Ytterbium oxide (YbO) x ) or magnesium oxide (MgO) x At least one of the following.

[0125] In some embodiments, refer to Figure 3c , Figure 3d The self-select memory 12 also includes a buffer layer 125, which is disposed between the functional layer and the barrier layer 124. The electron affinity of the buffer layer 125 is between the functional layer and the barrier layer 124. The electron affinity of the buffer layer 125 is also between the gate layer and the barrier layer 124. The buffer layer 125 buffers the difference in electron affinity between the gate layer and the barrier layer 124, avoiding performance fluctuations caused by excessive differences in electron affinity between the gate and barrier layers 124. The buffer layer 125 can reduce the voltage drop across the barrier layer 124, preventing the barrier layer 124 from being broken down by high voltage drops, reducing the risk of leakage current, and improving the stability and reliability of device performance.

[0126] For example, the material of buffer layer 125 may include titanium oxide (TiO2). x Nickel oxide (NiO) x ), zinc oxide (ZnO) x ), chromium oxide (CrO) x ), molybdenum oxide (MoO) x ), tungsten oxide (WO)x ), Bismuth oxide (BiO) x ), antimony oxide (SbO) x Indium oxide (InO) x ), Vanadium oxide (VO) x ), niobium oxide (NbO) x ), manganese oxide (MnO) x ), neodymium oxide (NdO) x ), Strontium oxide (SrO) x germanium oxide (GeO) x lanthanum oxide (LaO) x ), hafnium oxide (HfO) x Gallium oxide (GaO) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), silicon dioxide (SiO) x ), Ytterbium oxide (YbO) x ) or magnesium oxide (MgO) x At least one of the following.

[0127] The material of the buffer layer 125 has good interface properties, which can reduce the interface states and defect states between the functional layer and the barrier layer 124, reduce the scattering and recombination probability of electrons at the interface, and improve the electron transport efficiency.

[0128] In some embodiments, refer to Figure 26 The self-select memory 12 also includes a first electrode layer 126 and a second electrode layer 127. The first electrode layer 126 is disposed between the first functional layer 121 and the first selection line 11, and the second electrode layer 127 is disposed between the second functional layer 122 and the second selection line 13. The first electrode layer 126 and the second electrode layer 127 reduce the contact resistance between the functional layer and the selection line.

[0129] For example, the material of the first electrode layer 126 may include at least one of niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), yttrium (Ir), yttrium oxide (IrO2), indium tin oxide (ITO), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), titanium aluminum nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), and copper (Cu). The first electrode layer 126 may be a single-layer structure or a multi-layer structure.

[0130] The material selection range for the second electrode layer 127 is the same as that for the first electrode layer 126, and will not be repeated here.

[0131] In some embodiments, refer to Figure 26 The self-select memory 12 also includes a diffusion barrier layer 128, which is in contact with the first select line 11 or the second select line 13. Thus, the diffusion barrier layer 128 can be disposed between the self-select memory 12 and the first select line 11 or between the self-select memory 12 and the second select line 13. The diffusion barrier layer 128 can effectively prevent the diffusion of metal atoms under high temperature or electric field, prevent mutual contamination between the select line and the self-select memory 12, improve the stability and reliability of the memory, and extend the service life of the memory.

[0132] For example, the material of the diffusion barrier layer 128 is selected from at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten carbide (WC).

[0133] In some embodiments, such as Figure 3e , Figure 3f As shown, the three-dimensional embedded non-volatile memory 1 also includes a sidewall passivation layer 17, which covers the sidewall of the self-select memory 12. The sidewall passivation layer 17 is used to enhance the electrical isolation performance between adjacent devices, reduce the risk of short circuits between adjacent devices, and improve the leakage current problem of the self-select memory 12.

[0134] The sidewall passivation layer 17 can be a single-layer structure or a multi-layer structure sequentially covering the sidewalls of the self-select memory 12. In one embodiment, as shown in 3e, the sidewall passivation layer 17 is a single-layer structure, and the material of the sidewall passivation layer 17 may include at least one of silicon oxide, silicon nitride, or aluminum oxide. In another embodiment, as shown in 3f, the sidewall passivation layer 17 includes an insulating layer 171 and a third dielectric layer 172 sequentially covering the sidewalls of the self-select memory 12. The material of the insulating layer 171 may include at least one of silicon oxide, silicon nitride, or aluminum oxide, and the material of the third dielectric layer 172 may include silicon oxide.

[0135] like Figure 3e , Figure 3f As shown, the three-dimensional embedded non-volatile memory 1 also includes a conductive plug 18, which is disposed on the top surface of the self-select memory 12. The self-select memory 12 is connected to the first select line 11 or the second select line 13 above it via the conductive plug 18. The sidewall passivation layer 17 may also cover part of the top surface of the self-select memory 12, and the conductive plug 18 passes through the sidewall passivation layer 17 to contact the top surface of the self-select memory 12 to connect the self-select memory 12 to the first select line 11 or the second select line 13 above it.

[0136] In some embodiments, when the height of the self-selection memory 12 is less than the height difference required by the process between the first selection line 11 and the second selection line 13, a conductive plug 18 is formed on the self-selection memory 12 to increase the height of the self-selection memory 12 so that the height of the self-selection memory 12 meets the height difference required by the process between the first selection line 11 and the second selection line 13.

[0137] In some embodiments, refer to Figure 1 Combined with reference Figures 5a-5h As shown, the three-dimensional embedded non-volatile memory 1 also includes peripheral circuitry 20 and driving circuitry 30.

[0138] The peripheral circuit 20 is used to receive instructions and data sent by external devices, and to read data from the memory and transmit it to the external system, enabling data interaction between the three-dimensional embedded non-volatile memory 1 and external devices.

[0139] The driving circuit 30 is used to generate corresponding control signals according to the instructions received by the peripheral circuit 20. The driving circuit 30 controls the working state of each component in the storage layer 10 (such as the first selection line 11, the self-selection memory 12, and the second selection line 13) to realize data writing, reading and erasing operations.

[0140] In this embodiment, refer to Figure 1 Combined with reference Figures 5a-5h As shown, the driving circuit 30 includes multiple driving transistors, including a first driving transistor 31 and a second driving transistor 32. Each first driving transistor 31 is connected to a first selection line 11 and is used to control the voltage applied to the first selection line 11. Each second driving transistor is connected to a second selection line 13 and is used to control the voltage applied to the second selection line 13. The transistors of the driving circuit 30 and the multi-layer stacked 1S1R memory cells construct a highly integrated 1TnSnR structure three-dimensional memory array. By controlling the voltages of the first selection line 11 and the second selection line 13 through the first driving transistor 31 and the second driving transistor 32, independent addressing and operation of the respective selected memory 12 in the memory layer 10 can be achieved.

[0141] Secondly, this application provides an edge chip 3, which is an on-chip homogeneous integration chip. (See reference...) Figure 4 or Figure 5a , Figure 5bThe edge chip 3 includes a substrate 4, a logic chip 2 integrated on the substrate 4, and a three-dimensional embedded non-volatile memory 1 as described in the first aspect. The three-dimensional embedded non-volatile memory 1 is disposed on the logic chip 2, or the three-dimensional embedded non-volatile memory 1 and the logic chip 2 are respectively disposed on the substrate 4. The peripheral circuits 20 and driving circuits 30 of the three-dimensional embedded non-volatile memory 1 and the logic chip 2 are fabricated in the front-end process, and the multilayer storage layer 10 of the three-dimensional embedded non-volatile memory 1 is fabricated in the back-end process.

[0142] In some embodiments, refer to Figure 5a A redistribution layer 8 is formed above the peripheral circuit 20, the driving circuit 30, and the logic chip 2, and the peripheral circuit 20, the driving circuit 30, and the logic chip 2 are electrically connected through the redistribution layer 8. The multi-layer storage layers 10 of the three-dimensional embedded non-volatile memory 1 are stacked on the redistribution layer 8, and the multi-layer storage layers 10 are electrically connected to the logic chip 2 through the redistribution layer 8, thereby enabling data interaction. In this way, the vertical space is fully utilized to improve the integration of the edge chip 3, shorten the signal transmission path between the three-dimensional embedded non-volatile memory 1 and the logic chip 2, improve signal latency, increase memory read / write speed, and improve the response speed of the edge chip 3; it also reduces the additional power consumption caused by excessively long connection lines.

[0143] In other embodiments, reference is made to Figure 5b The three-dimensional embedded non-volatile memory 1 and the logic chip 2 are respectively disposed in different areas of the substrate 4 and are electrically connected through the wiring layer inside the substrate 4 to achieve data interaction. In this way, the logic chip 2 and the three-dimensional embedded non-volatile memory 1 have independent heat dissipation, avoiding the heat concentration problem caused by the close stacking of the three-dimensional embedded non-volatile memory 1 and the logic chip 2, which is beneficial to improving the stability and reliability of the edge chip 3.

[0144] In some other embodiments, the edge chip 3 also includes a DRAM module, such as a DRAM storage array. The DRAM module is used by the edge chip 3 to temporarily store intermediate results during data processing, thereby improving the overall performance and data processing capabilities of the chip.

[0145] In this embodiment, the DRAM module may include a three-dimensional or planar DRAM memory device based on two-transistor, zero-capacitor (2T0C) technology using oxide semiconductor channels, or a conventional DRAM (1T1C DRAM memory device), or a high-bandwidth memory (HBM), integrating the DRAM module with the logic chip 2 and the three-dimensional embedded non-volatile memory 1.

[0146] The 2T0C structure DRAM memory device is made of oxide semiconductor materials and can be directly and homogeneously integrated with other memory devices (such as logic chip 2 and 3D embedded non-volatile memory 1), simplifying the manufacturing process of edge chip 3, reducing compatibility issues between different materials and processes, and improving production efficiency and yield. It also helps improve the stability and reliability of edge chip 3, reducing problems caused by performance differences due to different materials and processes.

[0147] Understandably, in tasks involving large amounts of data processing and complex algorithms, such as the training of a Transformer model, a key-value (KV) cache is used to store intermediate computation results for quick access in subsequent calculations, reducing redundant computations and improving overall computational efficiency. As the model size and the amount of data processed increase, the number of intermediate results that need to be cached also rises sharply. This necessitates a large capacity for the intermediate cache to store massive amounts of intermediate data. During computation, the KV cache is frequently read and written; therefore, the storage medium for the KV cache needs to be durable and fast, capable of withstanding a large number of read and write operations without performance degradation or data loss.

[0148] DRAM memory features high read / write speeds and good durability, capable of withstanding a large number of read / write operations. In this embodiment, the DRAM module is integrated with logic chip 2 and 3D embedded non-volatile memory 1. The DRAM module can meet the durability requirements of the intermediate buffer. The 3D embedded non-volatile memory module can store weights on-chip and provide greater bandwidth. This facilitates faster loading and updating of weights, significantly reducing the data transmission distance and latency between chips compared to traditional model training and inference, and greatly improving computational efficiency.

[0149] In one embodiment, refer to Figure 5c A redistribution layer 8 is formed above the peripheral circuits 20 and driving circuits 30 of the three-dimensional embedded non-volatile memory 1 and the logic chip 2. The peripheral circuits 20, driving circuits 30 and logic chip 2 are electrically connected through the redistribution layer 8. The multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1 is stacked on the redistribution layer 8 and electrically connected to the logic chip 2 through the redistribution layer 8. The DRAM module is directly integrated above the multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1. The DRAM module is a 2TOC structure DRAM memory.

[0150] In another embodiment, refer to Figure 5d The DRAM module is directly integrated on the redistribution layer 8, and the multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1 is stacked on the DRAM module.

[0151] In yet another embodiment, reference is made to... Figure 5e The DRAM module and the multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1 are both stacked on the redistribution layer 8.

[0152] In the fourth embodiment, refer to Figure 5f A redistribution layer 8 is formed above the peripheral circuit 20, the driving circuit 30, and the logic chip 2. The multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1 is stacked on the redistribution layer 8. An interconnect layer 51 is formed on the multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1. Interconnect plugs (not shown in the figure) are formed in the interconnect layer 51, for example, through through-silicon via (TSV) technology. DRAM modules are stacked on the side of the interconnect layer 51 away from the three-dimensional embedded non-volatile memory 1, and the DRAM modules are vertically interconnected with the three-dimensional embedded non-volatile memory 1 through the interconnect plugs of the interconnect layer 51.

[0153] In the fifth embodiment, refer to Figure 5g The three-dimensional embedded non-volatile memory 1, logic chip 2, and DRAM module are integrated on a carrier board 5. An intermediate layer 6 is provided on the carrier board 5, which has structures such as a metal wiring layer, an insulating layer, and vias. The intermediate layer 6 can redistribute and connect the signal pins of the three-dimensional embedded non-volatile memory 1, logic chip 2, and DRAM module. The three-dimensional embedded non-volatile memory 1, logic chip 2, and DRAM module are respectively mounted on the intermediate layer 6 via solder pads 7. The three-dimensional embedded non-volatile memory 1 and logic chip 2 are jointly integrated on a substrate 4, which is mounted on the intermediate layer 6 via solder pads 7, allowing the three-dimensional embedded non-volatile memory 1, logic chip 2, and DRAM module to interact with signals and data through the intermediate layer 6.

[0154] In the sixth embodiment, refer to Figure 5h The peripheral circuit 20, the driving circuit 30, the logic chip 2 and the DRAM module are respectively set on the side of the intermediate layer 6 away from the carrier board 5 by solder blocks 7. A redistribution layer 8 is formed on the peripheral circuit 20, the driving circuit 30, the logic chip 2 and the DRAM module. The multi-layer storage layer 10 of the three-dimensional embedded non-volatile memory 1 is stacked on the redistribution layer 8.

[0155] According to an exemplary embodiment, this application provides an electronic device including the three-dimensional embedded non-volatile memory 1 of the above embodiments, or including the edge chip of the above embodiments. The electronic device can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, smart wearable device, augmented reality (AR) device, virtual reality (VR) headset, global positioning system (GPS) receiver / navigator, camera, video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, printer, set-top box, etc.

[0156] According to an exemplary embodiment, this application provides a method for fabricating a three-dimensional embedded non-volatile memory 1, wherein a multilayer memory layer 10 is formed on a substrate and stacked vertically. The substrate is a logic chip 2 on which CMOS circuitry is formed. Alternatively, the substrate can be a substrate 4 on which metal wiring layers are formed. After forming the three-dimensional embedded non-volatile memory 1 on the substrate 4, the three-dimensional embedded non-volatile memory 1 and the logic chip 2 on which CMOS circuitry is formed are planar discretely integrated on the substrate. Figure 6 As shown, the fabrication method of the three-dimensional embedded non-volatile memory 1 includes the following steps:

[0157] Step S101: Form multiple first selection lines 11 on the substrate. The first selection lines 11 extend along the first direction X and are spaced apart along the second direction Y.

[0158] Step S102: A plurality of self-selection memories 12 are formed on the side of the first selection line 11 away from the substrate. The self-selection memories 12 are arrayed along the first direction X and the second direction Y. The self-selection memories 12 include a functional layer.

[0159] Step S103: A plurality of second selection lines 13 are formed on the side of the self-selection memory 12 away from the first selection line 11. The second selection lines 13 extend along the second direction Y and are spaced apart along the first direction X. The plurality of first selection lines 11, the plurality of self-selection memories 12 and the plurality of second selection lines 13 form a storage layer 10.

[0160] Step S104: Repeat the steps of forming multiple first selection lines 11, forming multiple self-selection memories 12, and forming multiple second selection lines 13 to form a vertically stacked multi-layer memory layer 10.

[0161] The fabrication method of the three-dimensional embedded non-volatile memory 1 in this embodiment forms a vertically stacked multi-layer storage layer 10, with each storage layer 10 containing multiple self-selecting memories 12. This vertically stacked architecture can integrate more self-selecting memories 12 within a unit area, increasing storage capacity to meet high-density storage requirements, such as the storage requirements of large language models, supporting in-memory computation (PIM) and near-memory computation (PNC), and possessing high bandwidth and low latency matrix-vector multiplication acceleration capabilities. The self-selecting memories 12 can achieve self-selected storage when the turn-on voltage is reached, without the need for additional gating devices (such as transistors) to be integrated with them, reducing the area occupied by a single self-selecting memory 12, simplifying the structure of the storage layer 10, and improving the integration of the memory.

[0162] In some embodiments, such as Figure 7 As shown, forming each storage layer 10 includes the following steps:

[0163] Step S201: A first selective material layer 111 and a functional stack 120 are formed on the substrate, wherein the functional stack 120 includes at least a first functional layer 121 and a second functional layer 122.

[0164] In this embodiment, refer to Figure 8 As shown, a first selective material layer 111 and a functional stack 120 can be deposited on the substrate using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering.

[0165] In this embodiment, a first functional layer 121 and a second functional layer 122 are sequentially formed on the first selected material layer 111 to form a functional stack 120. In other embodiments, the functional stack 120 may also include at least one auxiliary functional layer, such as a heat transfer layer 123, a barrier layer 124, a buffer layer 125, a first electrode layer 126 and a second electrode layer 127, or a diffusion barrier layer 128, etc.

[0166] Step S202: Etch the functional stack 120 and the first selected material layer 111 to form a first trench 151 extending along the first direction X, dividing the first selected material layer 111 into multiple first selected lines 11.

[0167] In this embodiment, refer to Figure 9 As shown, a mask layer is formed on the side of the functional stack 120 away from the first selected material layer 111. The mask layer is exposed and developed to define the pattern of the first trench 151. Based on the patterned mask layer, the functional stack 120 and the first selected material layer 111 are etched to form at least one first trench 151 penetrating the functional stack 120 and the first selected material layer 111. The first trench 151 divides the first selected material layer 111 into multiple first selection lines 11. The first selection lines 11 extend along the first direction X and are spaced apart along the second direction Y, dividing the entire functional stack 120 into strip structures extending along the first direction X. The strip-shaped functional stack 120 is disposed on the first selection lines 11.

[0168] For example, the functional stack 120 and the first selected material layer 111 can be etched using a dry or wet process.

[0169] Step S203: Form a second selective material layer 131 to cover the top surface of the functional stack 120.

[0170] In this embodiment, refer to Figure 10 As shown, the first dielectric layer 141 can be formed by chemical vapor deposition or atomic layer deposition, and the first dielectric layer 141 fills the first trench 151. Then, the first dielectric layer 141 on the top surface of the functional stack 120 is removed by chemical mechanical polishing (CMP).

[0171] Then, refer to Figure 11 As shown, a second selective material layer 131 is deposited using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering. The second selective material layer 131 covers the top surface of the functional stack 120 and the top surface of the first dielectric layer 141.

[0172] Step S204: Etch the second selective material layer 131 and the functional stack 120 to form a second trench 152 extending along the second direction Y, dividing the second selective material layer 131 into multiple second selection lines 13; the first trench 151 and the second trench 152 divide the functional stack 120 into multiple self-selection memories 12; one of the first functional layer 121 and the second functional layer 122 of the self-selection memory 12 is a resistive switching layer and the other is a gated layer.

[0173] In this embodiment, refer to Figure 12As shown, a mask layer is formed on the side of the second selectable material layer 131 away from the functional stack 120, and the patterned mask layer defines the pattern of the second trench 152. Based on the patterned mask layer, the second selectable material layer 131 and the functional stack 120 are etched to form at least one second trench 152 penetrating the second selectable material layer 131 and the functional stack 120. The second trench 152 divides the second selectable material layer 131 into multiple second selectable lines 13. The second selectable lines 13 extend along the second direction Y and are spaced apart along the first direction X, and divide the strip-shaped functional stack 120 into independently configured self-selectable memories 12. The self-selectable memories 12 are located at the intersection of the first selectable lines 11 and the second selectable lines 13, and the self-selectable memories 12 are arrayed along the first direction X and the second direction Y.

[0174] Then, refer to Figure 13 As shown, a second dielectric layer 142 is formed to fill the second trench 152 and cover the top surface of the second select line 13. After grinding the top surface of the second dielectric layer 142 into a plane, steps S201-S204 are repeated using the top surface of the second dielectric layer 142 as the process plane to form a vertically stacked multilayer memory layer 10 on the substrate. In this way, the self-selection memories 12 of each memory layer 10 in the three-dimensional embedded non-volatile memory 1 can operate in parallel.

[0175] In this embodiment, suitable materials can be selected according to the functional requirements of the gate layer and the resistive switching layer. The gate layer can be made of materials with good current control characteristics and fast response speed, while the resistive switching layer can be made of materials with stable resistive switching performance and long durability.

[0176] In other embodiments, after step S203 forms the second selective material layer 131 covering the top surface of the first functional stack 120, the second functional stack 120 is formed to cover the top surface of the second selective material layer 131. Then, the second functional stack 120, the second selective material layer 131, and the first functional stack 120 are etched to form a second trench 152. The second trench 152 divides the second selective material layer 131 into multiple second select lines 13, divides the first functional stack 120 into multiple self-selectable memories 12, and divides the second functional stack 120 into strip structures disposed on the second select lines 13. Afterwards, a second dielectric layer 142 is filled into the second trench 152. A first selective material layer 111 and a third functional layer 120 are sequentially formed on the second dielectric layer 142 and the second functional layer 120. The third functional layer 120, the first selective material layer 111, and the second functional layer 120 are etched to form a first trench 151. The first trench 151 divides the second functional layer 120 into multiple self-selectable memories 12, divides the first selective material layer 111 into multiple first select lines 11, and divides the third functional layer 120 into strip structures located on the first select lines 11. In this way, a multi-layer memory layer 10 stacked vertically can be formed, and this process is simpler, has fewer steps, and helps save production costs.

[0177] In some embodiments, the material of the gate layer includes at least one of niobium oxide and vanadium oxide. In the gate layer, these materials can respond quickly to voltage signals, enabling precise control of current flow by the gate layer.

[0178] The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide. These materials possess abundant oxygen vacancies and defect states in the resistive switching layer. Under the influence of an electric field, oxygen ions or oxygen vacancies migrate, allowing the resistance of the resistive switching layer to reversibly switch between high and low resistance states. This results in good reliability and durability, meeting the requirements for long-term data storage in the resistive switching layer.

[0179] In the above embodiments, the materials of the first dielectric layer 141 and the second dielectric layer 142 in steps S201-S204 may include one or more combinations of silicon oxide, porous silicon carbide (SiCOH), silicate glass (USG), and borosilicate glass (BPSG), and may include a multilayer structure or a mixture of multilayer materials. The fabrication process of the first dielectric layer 141 and the second dielectric layer 142 includes chemical vapor deposition, such as atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0180] In some embodiments, such as Figure 14 As shown, forming each storage layer 10 includes the following steps:

[0181] Step S301: Form a first selective material layer 111 on the substrate, and etch the first selective material layer 111 to form multiple first selective lines 11.

[0182] In this embodiment, refer to Figure 15 , Figure 16 After forming the first selected material layer 111, a mask layer is directly formed to pattern and etch the first selected material layer 111 to form the first selected line 11. Then, a first dielectric layer 141 is deposited to fill the spaces between the first selected lines 11, and the first dielectric layer 141 on the first selected lines 11 is removed by grinding, which will not be described in detail here.

[0183] Step S302: Form a functional stack 120, which covers the top surface of the first selected material layer 111. The functional stack 120 includes at least a first functional layer 121 and a second functional layer 122.

[0184] Step S303: Pattern the functional stack 120 to form a plurality of self-select memory 12 on the side of the first selection line 11 away from the substrate; one of the first functional layer 121 and the second functional layer 122 of the self-select memory 12 is a resistive switching layer and the other is a gated layer.

[0185] In this embodiment, refer to Figure 17 , Figure 18 Multiple self-selection memories 12 can be formed by etching the functional stack 120 using dual self-aligned imaging technology or self-aligned quadruple imaging technology. The multiple self-selection memories 12 are arranged at intervals along the first direction X on the first selection line 11.

[0186] Step S304: A second selection material layer 131 is formed on the side of the self-select memory 12 away from the first selection line 11, and the second selection material layer 131 is etched to form multiple second selection lines 13.

[0187] In this embodiment, refer to Figure 19 A second dielectric layer 142 is deposited to fill the spaces between adjacent selectable memories 12. Then, the second dielectric layer 142 on the top surface of the selectable memories 12 is removed by grinding. (See reference...) Figure 20 A second selectable material layer 131 is deposited to form a second selectable material layer 131, which covers the top surface of the selectable memory 12 and the top surface of the second dielectric layer 142. A second selectable line 13 is patterned and etched, which extends along the second direction Y and connects a column of selectable memories 12 arranged along the second direction Y.

[0188] In some embodiments, refer to Figure 1 , Figure 2a , Figure 2b As shown, adjacent storage layers 10 in the vertical direction Z share either the first selection line 11 or the second selection line 13.

[0189] In this embodiment, a second dielectric layer 142 is formed to fill the second trench 152 and cover the top surface of the second selection line 13. After grinding to remove the second dielectric layer 142 on the second selection line 13, a second functional stack 120 is formed on the second selection line 13 and the second dielectric layer 142. The second functional stack 120 is patterned and etched to form the self-select memory 12 of the second layer array. Then, the dielectric layer is filled, the material is ground, a first selection material layer 111 is deposited, and the first selection material layer 111 is patterned and etched to form the first selection line 11. If more memory layers 10 are to be formed, the steps of forming the self-select memory 12 and the second selection line 13 are repeated.

[0190] In some embodiments, refer to Figures 21-26 After forming the first select line 11, a first dielectric layer 141 is filled into the first trench 151 between the first select lines 11. Then, a protective layer 16 is formed covering the top surface of the first select line 11 and the first dielectric layer 141; for example, the material of the protective layer 16 may include silicon oxide. Then, the protective layer 16 on the first select line 11 is etched away to expose the top surface of the first select line 11. A diffusion barrier layer 128 is formed on the first select line 11 to prevent the material of the self-select memory 12 from diffusing into the first select line 11; for example, the material of the diffusion barrier layer 128 may include at least one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride.

[0191] In some embodiments, the functional stack 120 further includes at least one auxiliary functional layer, thus forming a self-selecting memory 12 including at least one auxiliary functional layer. The at least one auxiliary functional layer is stacked perpendicularly to the first functional layer 121 and the second functional layer 122; at least one auxiliary functional layer may be disposed between the first functional layer 121 and the second functional layer 122, or at least one auxiliary functional layer may be disposed between the first functional layer 121 and the first selection line 11; or at least one auxiliary functional layer may be disposed between the second functional layer 122 and the second selection line 13.

[0192] In some embodiments, refer to Figures 21-26 The functional stack 120 includes a first electrode layer 126, a first functional layer 121, a second functional layer 122, and a second electrode layer 127 sequentially stacked on a first selectable material layer 111. The self-selectable memory 12 formed in this embodiment includes a first electrode layer 126, a first functional layer 121, a second functional layer 122, and a second electrode layer 127 sequentially stacked along a path away from the first select line 11. The first electrode layer 126 and the second electrode layer 127 reduce the contact resistance between the functional layer and the select line.

[0193] For example, the material of the first electrode layer 126 may include at least one of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, yttrium, yttrium oxide, indium tin oxide, titanium aluminum nitride, aluminum nitride, titanium aluminum nitride, hafnium, iridium, and copper. The first electrode layer 126 may be a single-layer structure or a multi-layer structure. The selection range of the material for the second electrode layer 127 is the same as that for the first electrode layer 126, and will not be repeated here.

[0194] In some embodiments, refer to Figure 3a The functional stack 120 also includes a heat transfer layer 123, thus forming a self-select memory 12 that also includes a heat transfer layer 123. The heat transfer layer 123 is disposed between the first functional layer 121 and the second functional layer 122, and the thermal conductivity of the heat transfer layer 123 is lower than that of the resistive switching layer. For example, the material of the heat transfer layer 123 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide. The heat transfer layer 123 can be a single-layer structure or a multi-layer structure.

[0195] In some embodiments, refer to Figure 3b , Figure 3c , Figure 3dThe self-select memory 12 may further include a barrier layer 124, which is disposed between the functional layer (first functional layer 121 and / or second functional layer 122) and the first selection line 11, forming a barrier with the first selection line 11; or, the barrier layer 124 is disposed between the functional layer and the second selection line 13, forming a barrier with the second selection line 13. The barrier layer 124 and the selection line connected to it form a Schottky barrier or a tunneling barrier.

[0196] For example, the material of barrier layer 124 can be selected to have a high dielectric constant (greater than 3.9) and a wide bandgap. For example, materials for barrier layer 124 include neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, and hafnium oxide (HfO). x ( ), gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide.

[0197] In some embodiments, refer to Figure 3c , Figure 3d The self-selection memory 12 may further include a buffer layer 125, which may be disposed between the functional layer (first functional layer 121 or second functional layer 122) and the barrier layer 124. The electron affinity of the buffer layer 125 is between the functional layer and the barrier layer 124. The electron affinity of the buffer layer 125 is between the gate layer and the barrier layer 124. The buffer layer 125 is used to buffer the difference in electron affinity between the gate layer and the barrier layer 124, avoiding performance fluctuations caused by excessive difference in electron affinity between the gate layer and the barrier layer 124.

[0198] For example, the material of buffer layer 125 may include titanium oxide (TiO2). x Nickel oxide (NiO) x ), molybdenum oxide (MoO) x ), tungsten oxide (WO) x ), Vanadium oxide (VO) x ), niobium oxide (NbO) x ), manganese oxide (MnO) x ), neodymium oxide (NdO) x ), hafnium oxide (HfO) x Gallium oxide (GaO) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), silicon dioxide (SiO) x ) or magnesium oxide (MgO) x At least one of the following.

[0199] The material of the buffer layer 125 has good interface properties, which can reduce the interface states and defect states between the functional layer and the barrier layer 124, reduce the scattering and recombination probability of electrons at the interface, and improve the electron transport efficiency.

[0200] According to an exemplary embodiment, this embodiment provides a method for fabricating a three-dimensional embedded non-volatile memory 1, including forming a vertically stacked multilayer memory layer 10. The formation of each memory layer 10 includes the following steps:

[0201] Step S401: Form a first selective material layer 111 on the substrate, and etch the first selective material layer 111 to form multiple first selective lines 11.

[0202] Step S402: Form a functional stack 120, which covers the top surface of the first selected material layer 111. The functional stack 120 includes at least a first functional layer 121 and a second functional layer 122.

[0203] Step S403: Pattern the functional stack 120 to form a plurality of self-select memory 12 on the side of the first selection line 11 away from the substrate; one of the first functional layer 121 and the second functional layer 122 of the self-select memory 12 is a resistive switching layer and the other is a gated layer.

[0204] In this embodiment, steps S401-S403 are implemented in the same way as steps S301-S303 in the above embodiment, and will not be described again here.

[0205] Step S404: Form a sidewall passivation layer 17 to cover the sidewall of the self-select memory 12.

[0206] In this embodiment, refer to Figure 27 As shown, and in conjunction with reference Figure 3e , Figure 3f , Figure 24 An insulating layer 171 can be formed using atomic layer deposition (ALD) technology. The insulating layer 171 covers the sidewalls and top surface of the self-select memory 12, as well as the top surface of the first dielectric layer 141 and the first select line 11 between the self-select memory 12. Anisotropic etching is then used to remove the insulating layer 171 covering the top surface of the self-select memory 12, the first dielectric layer 141, and the first select line 11. The insulating layer 171 covering the sidewalls of the self-select memory 12 forms a sidewall passivation layer 17.

[0207] In some embodiments, refer to Figure 28 As shown, and in conjunction with reference Figure 3e , Figure 3f , Figure 24 , Figure 27 After etching the insulating layer 171, an atomic layer deposition process is used to form a third dielectric layer 172 covering the insulating layer 171 on the sidewall of the self-select memory 12 and the top surface of the self-select memory 12.

[0208] For example, the material of the insulating layer 171 may include at least one of silicon oxide, silicon nitride, or aluminum oxide; the material of the third dielectric layer 172 may include silicon oxide.

[0209] Step S405: Form a second dielectric layer 142 to fill the spaces between the self-select memory 12.

[0210] In this embodiment, refer to Figure 29 As shown, refer to Figure 28 The second dielectric layer 142 can be formed by chemical vapor deposition. The second dielectric layer 142 covers the third dielectric layer 172 and fills the gaps between the self-select memory 12. After the second dielectric layer 142 is formed, the top surface of the second dielectric layer 142 is ground into a plane, and the top surface of the second dielectric layer 142 is higher than the top surface of the third dielectric layer 172 after grinding.

[0211] Step S406: Form a conductive plug 18 on the top surface of the self-selection memory 12.

[0212] In this embodiment, a photoresist layer is formed on the top surface of the second dielectric layer 142. After patterning the photoresist layer, the second dielectric layer 142 and the third dielectric layer 172 are etched according to the photoresist layer. Figure 30 As shown, refer to Figure 29 A via is formed on the self-select memory 12, exposing the top surface of the self-select memory 12.

[0213] Then, refer to Figure 31 As shown, in conjunction with reference Figure 3e , Figure 3f , Figure 24 , Figure 30 Conductive plugs 18 can be formed in each via using atomic layer deposition or physical vapor deposition. The material of the conductive plugs 18 may include tungsten nitride, etc. Then, grinding removes the material of the conductive plugs 18 on the second dielectric layer 142 to disconnect each conductive plug 18 and achieve electrical isolation.

[0214] In other embodiments, the second dielectric layer 142 may be ground to expose the top surface of the third dielectric layer 172, and then wet etching may be used to remove the third dielectric layer 172 on the top surface of the self-select memory 12 to form a via.

[0215] Step S407: Form a second selective material layer 131 covering the top surface of each conductive plug 18 and the top surface of the second dielectric layer 142, and etch the second selective material layer 131 to form multiple second selective lines 13.

[0216] In this embodiment, refer to Figure 32 As shown, in conjunction with reference Figure 3e , Figure 3f , Figure 24 , Figure 31 The self-select memory 12 is connected to the second select line 13 above it via a conductive plug 18. The conductive plug 18 passes through the sidewall passivation layer 17 and contacts the top surface of the self-select memory 12 to connect the self-select memory 12 to the second select line 13 above it.

[0217] When the height difference between the first selection line 11 and the second selection line 13 of the self-selection memory 12 meets the process requirement height difference, a conductive plug 18 is formed on the self-selection memory 12 to increase the height of the self-selection memory 12 so that the height of the self-selection memory 12 meets the process requirement height difference between the first selection line 11 and the second selection line 13.

[0218] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0219] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A three-dimensional embedded nonvolatile memory, characterized by, The three-dimensional embedded non-volatile memory is integrated with the logic chip; The three-dimensional embedded non-volatile memory includes multiple vertically stacked storage layers; Each of the storage layers includes: A first selection line extends along a first direction and is spaced out along a second direction; The second selection line extends along the second direction and is spaced apart along the first direction, and the first direction intersects the second direction; A self-selecting memory is disposed at the intersection of the first selection line and the second selection line, along the vertical direction. The self-selecting memory is located between the first selection line and the second selection line, and each self-selecting memory includes at least one functional layer. The self-selection memory includes a first functional layer and a second functional layer stacked in a vertical direction, wherein one of the first functional layer and the second functional layer is a gating layer and the other is a resistive switching layer; The resistive switching layer can reversibly switch between a high-resistivity state and a low-resistivity state to store data; The gating layer is used to control the on / off state of current in the self-selection memory, so as to conduct the current path of the selected self-selection memory during read / write operations.

2. The 3D embedded nonvolatile memory of claim 1, wherein, The storage layers in the vertical direction share either the first selection line or the second selection line.

3. The 3D embedded nonvolatile memory of claim 2, wherein, When adjacent storage layers share the first selection line, the self-selection memory in the same column is independently addressed and operated through different second selection lines; When adjacent storage layers share the second selection line, the self-selection memories in the same row are independently addressed and operated through different first selection lines.

4. The 3D embedded nonvolatile memory of claim 1, wherein, The material of the gate layer includes at least one of niobium oxide and vanadium oxide; The resistive switching layer is made of at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

5. The three-dimensional embedded non-volatile memory according to claim 1, characterized in that, The self-selection memory further includes at least one auxiliary function layer, which is selected from at least one of the following: A heat transfer layer is disposed between the first functional layer and the second functional layer, wherein the thermal conductivity of the heat transfer layer is less than that of the resistive switching layer; A barrier layer is disposed between the functional layer and the first selection line to form a barrier with the first selection line, or it is disposed between the functional layer and the second selection line to form a barrier with the second selection line; A buffer layer is disposed between the functional layer and the barrier layer, wherein the electron affinity of the buffer layer is between the functional layer and the barrier layer; A first electrode layer and a second electrode layer, wherein the first electrode layer is disposed between the first functional layer and the first selection line, and the second electrode layer is disposed between the second functional layer and the second selection line; A diffusion barrier layer is in contact with the first selection line, or the diffusion barrier layer is in contact with the second selection line.

6. The 3D embedded nonvolatile memory of claim 1, wherein, The three-dimensional embedded non-volatile memory also includes: A sidewall passivation layer covers the sidewalls of the self-selecting memory; A conductive plug is disposed on the top surface of the self-selection memory, and the self-selection memory is connected to the first selection line or the second selection line above it through the conductive plug.

7. An edge chip, characterized by Includes a substrate and a logic chip integrated on the substrate, as well as a three-dimensional embedded non-volatile memory as described in any one of claims 1-6; The three-dimensional embedded non-volatile memory is disposed on the logic chip, or the three-dimensional embedded non-volatile memory and the logic chip are respectively disposed on the substrate.

8. An electronic device, comprising: It includes a three-dimensional embedded non-volatile memory as described in any one of claims 1-6, or it includes an edge chip as described in claim 7.

9. A method for manufacturing a three-dimensional embedded nonvolatile memory as claimed in any one of claims 1-6, characterized in that, include: Multiple first selection lines are formed on the substrate, the first selection lines extending along a first direction and spaced apart along a second direction; A plurality of self-selection memories are formed on the side of the first selection line away from the substrate, and the self-selection memories are arrayed along the first direction and the second direction; the self-selection memories include a functional layer; Multiple second selection lines are formed on the side of the self-select memory away from the first selection line. The second selection lines extend along the second direction and are spaced apart along the first direction. The multiple first selection lines, the multiple self-select memories, and the multiple second selection lines form a storage layer. The steps of forming multiple first selection lines, forming multiple self-selecting memories, and forming multiple second selection lines are repeatedly performed to form a vertically stacked multi-layer memory layer.

10. The method of claim 9, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: Forming the storage layer includes: A first selective material layer and a functional stack are formed on the substrate, wherein the functional stack includes at least a first functional layer and a second functional layer. The functional stack and the first selected material layer are etched to form a first trench extending along the first direction, dividing the first selected material layer into multiple first selection lines; A second selective material layer is formed to cover the top surface of the functional stack; The second selective material layer and the functional stack are etched to form a second trench extending along the second direction, dividing the second selective material layer into multiple second selection lines; the first trench and the second trench divide the functional stack into multiple self-selection memories; one of the first functional layer and the second functional layer of the self-selection memory is a resistive switching layer and the other is a gated layer.

11. The method of claim 9, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: Forming the storage layer includes: A first selective material layer is formed on the substrate, and the first selective material layer is etched to form a plurality of first selective lines; A functional stack is formed, the functional stack covering the top surface of the first selected material layer, the functional stack including at least a first functional layer and a second functional layer; The functional stack is patterned and etched to form a plurality of self-select memory layers on the side of the first selection line away from the substrate; one of the first functional layer and the second functional layer of the self-select memory layer is a resistive switching layer and the other is a gated layer; A second selection material layer is formed on the side of the self-selection memory away from the first selection line, and the second selection material layer is etched to form multiple second selection lines.

12. The method of claim 9, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: The storage layers in the vertical direction share either the first selection line or the second selection line.

13. The method of claim 9, wherein the three-dimensional embedded nonvolatile memory is formed by a process comprising: The substrate is a logic chip with CMOS circuitry formed on it.

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