Preparation method of semiconductor structure, semiconductor structure and semiconductor device

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor device. The preparation method of the semiconductor structure comprises the following steps: forming a laminated structure on a semiconductor substrate; etching the laminated structure to form a fin-shaped structure; based on the fin-shaped structure, a first transistor is formed on the semiconductor substrate, and a first source drain structure in the first transistor is in contact with the semiconductor substrate; a first power supply metal wire is formed on the first transistor, and the first power supply metal wire is used for providing a power supply for the first transistor; performing wafer reversing, and removing the semiconductor substrate to expose the first source-drain structure; a first signal metal wire communicated with the first source drain structure is formed, and the first signal metal wire is used for providing signals for the first transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a semiconductor structure preparation method, a semiconductor structure and a semiconductor device. BACKGROUND

[0002] A backside power distribution network (BSPDN) is a technology of forming power supply wiring of a transistor on the back surface of a wafer. By introducing the backside power distribution network, the voltage drop (IR-drop) caused by the power supply wiring resistance can be effectively reduced, and meanwhile the front surface wiring resources are released for signal wiring. However, the backside power distribution network will affect the performance of the transistor. SUMMARY

[0003] The present application provides a semiconductor structure preparation method, a semiconductor structure and a semiconductor device, which can form power supply wiring on the front surface of a wafer and form signal wiring on the back surface of the wafer, thereby improving the performance of the transistor.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure preparation method. The semiconductor structure preparation method comprises: forming a laminated structure on a semiconductor substrate; etching the laminated structure to form a fin structure; based on the fin structure, forming a first transistor above the semiconductor substrate, wherein a first source-drain structure in the first transistor is in contact with the semiconductor substrate; forming a first power supply metal line above the first transistor, wherein the first power supply metal line is used to provide a power supply for the first transistor; developing a negative film and removing the semiconductor substrate to expose the first source-drain structure; and forming a first signal metal line in communication with the first source-drain structure, wherein the first signal metal line is used to provide a signal for the first transistor.

[0005] In some embodiments, the semiconductor substrate comprises a first semiconductor substrate and a second semiconductor substrate which are arranged in layers; the first semiconductor substrate is closer to the fin structure than the second semiconductor substrate; and after etching the laminated structure to form the fin structure, the semiconductor structure preparation method further comprises: etching a first part of the first semiconductor substrate and retaining a second part of the first semiconductor substrate, wherein the first part is a part of the first semiconductor substrate which is not covered by the fin structure; and depositing an oxide material at a position where the first part is removed to form a shallow trench isolation structure, wherein the shallow trench isolation structure is used to electrically isolate the first transistor and the second semiconductor substrate.

[0006] In some embodiments, developing a negative film and removing the semiconductor substrate to expose the first source-drain structure comprises: developing a negative film and removing the second semiconductor substrate by using a mechanical planarization process; and removing the second part and the shallow trench isolation structure until the first source-drain structure is exposed.

[0007] In some embodiments, forming the first signal metal line in communication with the first source-drain structure comprises: forming a first dielectric layer and a first source-drain metal through the first dielectric layer over the first source-drain structure, wherein the first source-drain metal connects the first source-drain structure; forming a second dielectric layer and a first direct via through the second dielectric layer over the first dielectric layer; forming a first metal interconnection layer over the second dielectric layer, wherein the first metal interconnection layer comprises the first signal metal line; and the first direct via communicates the first signal metal line and the first source-drain metal.

[0008] In some embodiments, the etch selectivity of the material forming the first semiconductor substrate and the etch selectivity of the material forming the first source-drain structure are the same; wherein after the oxide material is deposited at the location where the first portion is removed to form the shallow trench isolation structure, the method further comprises: removing the second portion and depositing a semiconductor material at the location where the second portion is removed to form a sacrificial structure, wherein the etch selectivity of the material forming the sacrificial structure and the etch selectivity of the material forming the first source-drain structure are different; wherein the peeling and removing the semiconductor substrate to expose the first source-drain structure comprises: peeling and removing the second semiconductor substrate using a mechanical planarization process; and removing the sacrificial structure to form the first recess, wherein the bottom of the first recess is formed by the first source-drain structure.

[0009] In some embodiments, the etch selectivity of the material forming the first semiconductor substrate and the etch selectivity of the material forming the first source-drain structure are different; wherein the peeling and removing the semiconductor substrate to expose the first source-drain structure comprises: peeling and removing the second semiconductor substrate using a mechanical planarization process; and removing the second portion to form the first recess, wherein the bottom of the first recess is formed by the first source-drain structure.

[0010] In some embodiments, forming the first signal metal line in communication with the first source-drain structure comprises: depositing a metal material within the first recess to form a first source-drain metal, wherein the first source-drain metal connects the first source-drain structure; forming a second dielectric layer and a first direct via through the second dielectric layer over the shallow trench isolation structure; forming a first metal interconnection layer over the second dielectric layer, wherein the first metal interconnection layer comprises the first signal metal line; and the first direct via communicates the first signal metal line and the first source-drain metal.

[0011] In some embodiments, forming a first transistor based on a fin structure on a semiconductor substrate comprises: etching the fin structure in a source-drain region to form a source-drain recess; forming a first source-drain structure and a second source-drain structure in the source-drain recess based at least on the fin structure in a gate region; forming a first interlayer dielectric layer on the first source-drain structure and the second source-drain structure; wherein forming a first power supply metal line on the first transistor comprises: etching the first interlayer dielectric layer to form a source-drain metal recess; depositing a metal material in the source-drain metal recess to form a second source-drain metal, wherein the second source-drain metal is connected to the second source-drain structure; forming a front dielectric layer on the first interlayer dielectric layer and a second straight via through the front dielectric layer; forming a second metal interconnection layer on the front dielectric layer, wherein the second metal interconnection layer comprises the first power supply metal line; and the second straight via connects the first power supply metal line and the second source-drain metal.

[0012] In a second aspect, embodiments of the present application provide a semiconductor structure. The semiconductor structure comprises: a first transistor comprising: a first source-drain structure; a first power supply metal line connected to the first transistor, wherein the first power supply metal line is configured to provide power supply for the first transistor; and a first signal metal line disposed opposite to the first power supply metal line and connected to the first source-drain structure, wherein the first signal metal line is configured to provide signal for the first transistor.

[0013] In a third aspect, embodiments of the present application provide a semiconductor device, comprising: the semiconductor structure according to the second aspect.

[0014] In the present application, the first transistor is formed by using a stack structure on the semiconductor substrate, so that the first transistor is formed on the semiconductor substrate. Moreover, the first source-drain structure in the first transistor can be in contact with the semiconductor substrate, so that after the semiconductor substrate is developed and removed, the first source-drain structure can be directly exposed. Thus, the first signal metal line connected to the first source-drain structure can be formed on the exposed first source-drain structure. Compared with the solution in the related art, which needs to etch the dielectric layer in the first transistor to expose the first source-drain structure and then form the first signal metal line, the present application does not need to etch the dielectric layer inside the first transistor, so that the overlapping area of the metal connected to the first source-drain structure and the gate metal can be reduced, the parasitic capacitance of the source-drain structure and the gate structure can be effectively reduced, the working speed of the transistor can be improved, and the electrical performance of the transistor can be improved.

[0015] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0017] Figure 1 An embodiment flow chart of a method for preparing a semiconductor structure in the present application;

[0018] Figure 2 A layout diagram of a semiconductor structure in an embodiment of the present application;

[0019] Figures 3 to 18 A structure diagram of a semiconductor structure in a first preparation process in an embodiment of the present application;

[0020] Figures 19 to 23 A structure diagram of a semiconductor structure in a second preparation process in an embodiment of the present application.

[0021] The above figures:

[0022] 10, semiconductor structure; 11, first transistor; 12, second transistor; 111, first source-drain structure; 112, second source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, second source-drain metal; 116, first power supply metal line; 117, first source-drain metal; 118, first signal metal line;

[0023] 20, silicon substrate; 21, stack structure; 22, fin structure; 23, active layer; 24, sacrificial layer; 25, shallow trench isolation structure; 26, second part; 27, second semiconductor substrate; 28, dummy gate structure; 29, dummy gate sidewall; 30, front surface dielectric layer; 31, second straight-through via; 32, second metal interconnection layer; 33, carrier wafer; 34, first dielectric layer; 35, second dielectric layer; 36, first straight-through via; 37, first metal interconnection layer; 38, sacrificial structure. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to all alternative embodiments, as would be understood by one skilled in the art. The following exemplary embodiments are described herein with reference to the figures.

[0025] Currently, there are three main implementation manners of backside power supply network: buried power rails (BPR), power via, and backside contact to source / drain (BSC). After the introduction of the backside power supply network, the power supply wiring of the transistor is moved to the backside of the wafer, but the signal wiring is still led out from the front side of the wafer. There is a large overlap between the source / drain metal and the gate metal on the front side, and the introduced parasitic capacitance causes the working speed of the transistor to decrease, affecting the performance of the transistor.

[0026] In a first aspect, an embodiment of the present application provides a preparation method of a semiconductor structure, which can form power supply wiring on the front side of the wafer and form signal wiring on the backside of the wafer, thereby improving the performance of the transistor.

[0027] Figure 1 For an implementation flowchart of the preparation method of the semiconductor structure in the embodiment of the present application, as shown in Figure 1 the preparation method of the semiconductor structure in the embodiment of the present application can include:

[0028] Step S101: forming a laminated structure on a semiconductor substrate.

[0029] It can be understood that the semiconductor material can be deposited on the semiconductor substrate to form the laminated structure. Here, the laminated structure can be composed of a plurality of material layers overlapped in sequence, or can be composed of a single material layer, and the present application does not limit this.

[0030] In some embodiments, when the laminated structure is composed of a plurality of material layers overlapped in sequence, the laminated structure can be composed of a semiconductor material layer, an insulating material layer, a dielectric material layer, etc. In some embodiments, the material forming the laminated structure can be the same as the material forming the semiconductor substrate.

[0031] In some embodiments, the semiconductor substrate can be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, etc.

[0032] Step S102: etching the laminated structure to form a fin structure.

[0033] It can be understood that etching the laminated structure on the semiconductor substrate can form a fin structure on the semiconductor substrate.

[0034] In some embodiments, the fin-shaped structure can include a nanosheet stack structure. In an embodiment, the nanosheet stack structure can include a sacrificial layer and an active layer stacked in sequence in the first direction. The active layer is used to form an active device, such as a source-drain structure, in the semiconductor structure. The sacrificial layer is used to support the active layer, and the sacrificial layer can be removed in a subsequent fabrication step to prepare a gate-all-around structure.

[0035] In some embodiments, the materials forming the nanosheet stack structure can be selected according to actual needs, which are not limited in the embodiments of the present application. In some embodiments, the active layer in the nanosheet stack structure can be formed of a silicon material, and the sacrificial layer in the nanosheet stack structure can be formed of a silicon germanium material. That is, the nanosheet stack structure can be formed by alternately depositing a silicon material and a silicon germanium material on a semiconductor substrate. In some embodiments, when the fin-shaped structure includes the nanosheet stack structure, the first transistor can be a gate-all-around field effect transistor (GAAFET).

[0036] In some embodiments, the fin-shaped structure can include a pillar structure. In an embodiment, the pillar structure can be formed of silicon. In some embodiments, when the fin-shaped structure includes the pillar structure, the first transistor can be a fin field effect transistor.

[0037] In some embodiments, the step S102 can include: depositing a hard mask structure on the stack structure; and etching the stack structure to form the fin-shaped structure with the hard mask structure as a mask.

[0038] For example, the etching process can be at least one of dry etching, wet etching, and reactive ion etching.

[0039] In some embodiments, the semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate stacked in sequence; and the first semiconductor substrate is closer to the fin-shaped structure than the second semiconductor substrate.

[0040] It can be understood that the semiconductor substrate can include two parts, one part being the first semiconductor substrate and the other part being the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are stacked in sequence in the first direction. The first semiconductor substrate is closer to the fin-shaped structure than the second semiconductor substrate. In some embodiments, the first semiconductor substrate and the second semiconductor substrate are integrally formed. For example, the first semiconductor substrate and the second semiconductor substrate are both located in an original silicon wafer.

[0041] In some embodiments, the etching selectivity ratio of the material forming the first semiconductor substrate is the same as the etching selectivity ratio of the material forming the first source-drain structure. In some embodiments, the etching selectivity ratio of the material forming the first semiconductor substrate is different from the etching selectivity ratio of the material forming the first source-drain structure.

[0042] In some embodiments, when the semiconductor substrate comprises a first semiconductor substrate and a second semiconductor substrate, after step S102, the method can further comprise: etching a first portion of the first semiconductor substrate, leaving a second portion of the first semiconductor substrate, wherein the first portion is a portion of the first semiconductor substrate not covered by the fin structure; depositing an oxide material at a location where the first portion is removed, to form a shallow trench isolation structure, wherein the shallow trench isolation structure is configured to electrically isolate the first transistor and the second semiconductor substrate.

[0043] It can be understood that, after etching the stack structure to form the fin structure using the hard mask structure as a mask, the method can further comprise: etching a first portion of the first semiconductor substrate not covered by the fin structure (or the hard mask structure), leaving a second portion of the first semiconductor substrate, using the hard mask structure as a mask. In this way, an initial recess can be formed between two adjacent fin structures. After forming the initial recess, an oxide material can be deposited in the initial recess to form a shallow trench isolation (STI) structure. In an embodiment, the height of the shallow trench isolation structure can be less than or equal to the height of the second portion of the first semiconductor substrate.

[0044] It can be understood that, the oxide material can be deposited in the initial recess and thinned to a preset height, so that the height of the formed shallow trench isolation structure can be less than or equal to the height of the second portion of the first semiconductor substrate. Here, the shallow trench isolation structure is configured to electrically isolate the first transistor and the second semiconductor substrate subsequently formed.

[0045] The oxide material used to form the shallow trench isolation structure can be any one of the following: silicon dioxide (SiO2), silicon carbon oxide (SiCO), etc. For example, the thinning process can be a chemical-mechanical planarization (CMP) process.

[0046] It should be noted that, in the embodiments of the present application, the height refers to the vertical distance of the structure relative to the semiconductor substrate in the first direction. The first direction can be the stacking direction of the fin structure and the semiconductor substrate, the second direction can be the direction perpendicular to the first direction, and the second direction can be the direction perpendicular to the channel direction. The third direction can be the direction perpendicular to the first direction and the second direction, and the third direction can be the channel direction. In the third direction, the source-drain structure and the gate structure are alternately arranged. The area where the source-drain structure is located is the source-drain area, and the area where the gate structure is located is the gate area.

[0047] Step S103: forming a first transistor on the semiconductor substrate based on the fin structure.

[0048] It can be understood that the first transistor can include a first source-drain structure, a second source-drain structure, and a first gate structure. Here, a semiconductor manufacturing standard process can be used to manufacture the first transistor based on the fin structure on the semiconductor substrate.

[0049] In some embodiments, the first source-drain structure in the first transistor is in contact with the semiconductor substrate. Thus, after the semiconductor substrate is removed, the first source-drain structure is directly exposed, so that the first source-drain metal formed on the first source-drain structure no longer overlaps the first gate structure in the first transistor, reducing the parasitic capacitance inside the transistor.

[0050] In some embodiments, step S103 can include: depositing a dummy gate material in the gate region to form a dummy gate structure wrapping the fin structure, and depositing a side wall material on the sidewall of the dummy gate structure to form a dummy gate side wall. After forming the dummy gate structure, the fin structure in the source-drain region can be etched to form a source-drain recess; at least based on the fin structure in the gate region, the first source-drain structure and the second source-drain structure are formed in the source-drain recess. Then, a dielectric material is deposited on the first source-drain structure and the second source-drain structure to form a first interlayer dielectric layer. Then, the dummy gate structure is removed to sequentially deposit a gate dielectric material and a gate metal material in the gate region to form a first gate dielectric layer and a first gate metal layer, respectively, and then form a first gate structure.

[0051] Here, the dummy gate material can be polysilicon, single crystal silicon, etc. The side wall material can be an insulating material. The insulating material can be an oxide, a nitride, etc. The dielectric material can be silicon oxide, aluminum oxide, silicon nitride, etc. The embodiments of the present application do not limit this. In some embodiments, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. In some embodiments, the first gate electrode layer can be composed of multiple layers of electrode material, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0052] It can be understood that removing the fin structure in the source-drain region can form a source-drain recess. The bottom of the source-drain recess can be formed by the semiconductor substrate under the fin structure in the source-drain region. Thus, the first source-drain structure formed in the source-drain recess subsequently can be in contact with the semiconductor substrate.

[0053] It should be noted that in the case where the transistor formed by the embodiments of the present application is a full-surrounding gate field effect transistor, the source structure and the drain structure of the full-surrounding gate field effect transistor can be approximately symmetrical with respect to the nanosheet stack structure. Similarly, in the case where the transistor formed by the embodiments of the present application is a fin field effect transistor, the source structure and the drain structure of the fin field effect transistor can be approximately symmetrical with respect to the columnar structure. Therefore, for the convenience of description, the source-drain structure mentioned in the embodiments of the present application is a short name, which specifically refers to the source structure and / or the drain structure. That is, the transistor includes a first source-drain structure and a second source-drain structure. When the first source-drain structure is a drain, the second source-drain structure is a source; when the first source-drain structure is a source, the second source-drain structure is a drain. In addition, the same is true for the source-drain metal, the source-drain groove, etc.

[0054] In some embodiments, in the case where the transistor formed by the embodiments of the present application is a full-surrounding gate field effect transistor, step S103 can include: laterally etching the sacrificial structure in the nanosheet stack structure to form a side wall groove. Depositing a side wall material in the side wall groove to form an inner side wall of the transistor in the side wall groove.

[0055] In some embodiments, in the case where the bottom of the source-drain groove is composed of the second part of the first semiconductor substrate, step S103 can include: based on the second part of the first semiconductor substrate in the source-drain region and the fin structure (the active layer in the nanosheet stack structure) in the gate region, epitaxially forming a source-drain structure in the source-drain region. Here, the source-drain structure includes a first source-drain structure and a second source-drain structure.

[0056] In some embodiments, in the case where the etching selectivity of the material forming the first semiconductor substrate and the etching selectivity of the material forming the first source-drain structure are the same, step S103 can include: removing the second part of the first semiconductor substrate, and depositing a semiconductor material at the position where the second part of the first semiconductor substrate is removed to form a sacrificial structure. In this way, when the fin structure in the source-drain region is removed to form a source-drain groove, the bottom of the source-drain groove is composed of the sacrificial structure.

[0057] In some embodiments, in the case where the bottom of the source-drain groove is composed of the sacrificial structure, step S103 can include: based on the fin structure (the active layer in the nanosheet stack structure) in the gate region, epitaxially forming a source-drain structure in the source-drain region. Here, the source-drain structure includes a first source-drain structure and a second source-drain structure. The etching selectivity of the material forming the sacrificial structure and the etching selectivity of the material forming the first source-drain structure are different.

[0058] In some embodiments, when the transistor formed in the embodiments of the present application is a full-surrounding-gate field effect transistor, forming the first gate structure can include: removing the dummy gate structure to expose the nanosheet stack structure. Then, the sacrificial layers in the nanosheet stack structure are removed, leaving the active layers. Here, the sacrificial layers and the active layers are alternately stacked. Thus, after the sacrificial layers in the nanosheet stack structure are removed, the four surfaces of the active layers in the gate region can be completely exposed. On the active layers, a gate dielectric material and a gate metal material can be sequentially deposited to form a first gate dielectric layer and a first gate electrode layer, respectively. Here, the first gate dielectric layer and the first gate electrode layer share the first gate structure. The first gate structure surrounds the active layers.

[0059] It can be understood that after the first source-drain structure, the second source-drain structure, and the first gate structure are obtained, the first transistor can be obtained.

[0060] Step S104: Forming a first power supply metal line on the first transistor.

[0061] It can be understood that after the first transistor is formed, the first power supply metal line can be formed to provide power supply for the first transistor. Here, the second metal interconnection layer can be formed by using a standard back-end-of-line process of semiconductor manufacturing. The first power supply metal line can be included in the second metal interconnection layer.

[0062] In some embodiments, step S104 can include: etching the first interlayer dielectric layer to form a source-drain metal recess; depositing a metal material in the source-drain metal recess to form a second source-drain metal; forming a front surface dielectric layer on the first interlayer dielectric layer and a second straight through via hole through the front surface dielectric layer; and forming a second metal interconnection layer on the front surface dielectric layer.

[0063] It can be understood that after the first transistor is formed, the first interlayer dielectric layer can be etched until the second source-drain metal is exposed to form a source-drain metal recess. Then, a metal material can be deposited in the source-drain metal recess to form a second source-drain metal. Here, the second source-drain metal is connected to the second source-drain structure. After the second source-drain metal is formed, a dielectric material can be deposited on the first interlayer dielectric layer to form a front surface dielectric layer. Then, a second straight through via hole through the front surface dielectric layer can be formed in the front surface dielectric layer. Here, the second straight through via hole is connected to the second source-drain metal. After the second straight through via hole is formed, a second metal interconnection layer can be formed on the front surface dielectric layer by using a standard back-end-of-line process of semiconductor manufacturing. In this way, the second straight through via hole can connect the first power supply metal line and the second source-drain metal.

[0064] It can be understood that the second source-drain metal is located on the front surface of the wafer, and is used to connect the second source-drain structure and the first power metal line in the metal interconnection layer formed in the subsequent process. The front surface dielectric layer, the dielectric layer in the second metal interconnection layer, and the like can be formed by atomic layer deposition (ALD). In addition, the deposition process in the embodiments of the present application can be chemical vapor deposition (CVD) and physical vapor deposition (PVD), and the like, and the embodiments of the present application do not limit the crystal.

[0065] Here, the second metal interconnection layer is formed based on the semiconductor preparation in the subsequent process. The second metal interconnection layer is used to realize the transmission of current.

[0066] Step S105: flip and remove the semiconductor substrate to expose the first source-drain structure.

[0067] It can be understood that the first source-drain structure in the embodiments of the present application is in contact with the semiconductor substrate, and after the semiconductor substrate is flipped and removed, the first source-drain structure can be exposed. In this way, the first source-drain structure formed above the first source-drain structure does not overlap with the first gate structure in the first transistor, effectively reducing the parasitic capacitance of the first transistor.

[0068] In some embodiments, after the first transistor is prepared, an insulating material can be deposited on the first transistor to form an insulating layer. Then the insulating layer can be bonded with the carrier wafer, and then the bonded carrier wafer is flipped to realize the flipping.

[0069] In some embodiments, step S105 can include: flipping and removing the second semiconductor substrate by using a mechanical planarization process; removing the second part and the shallow trench isolation structure until the first source-drain structure is exposed.

[0070] It can be understood that after flipping, the second semiconductor substrate can be removed by using a mechanical planarization process. Then, the second part in the first semiconductor and the shallow trench isolation structure can be continuously removed by using a mechanical planarization process until the first source-drain structure is exposed.

[0071] In some embodiments, when the etching selectivity ratio of the material forming the first semiconductor substrate and the etching selectivity ratio of the material forming the first source-drain structure are the same, the second part in the first semiconductor can be removed before flipping, and a semiconductor material is deposited at the position where the second part is removed to form a sacrifice structure. In this case, step S105 can include: flipping and removing the second semiconductor substrate by using a mechanical planarization process; removing the sacrifice structure to form the first recess.

[0072] It can be understood that after the film is peeled off, the second semiconductor substrate can be removed by a mechanical planarization process. Then, the second portion can be selectively removed to form the first recess. The bottom of the first recess can be formed by the first source-drain structure. Forming the first recess can expose the first source-drain structure.

[0073] In some embodiments, when the etching selectivity of the material forming the first semiconductor substrate and the etching selectivity of the material forming the first source-drain structure are different, step S105 can include: peeling off the film, and removing the second semiconductor substrate by a mechanical planarization process; and removing the second portion to form the first recess.

[0074] It can be understood that after the film is peeled off, the second semiconductor substrate can be removed by a mechanical planarization process. Then, the second portion can be selectively removed to form the first recess. The bottom of the first recess can be formed by the first source-drain structure. Forming the first recess can expose the first source-drain structure.

[0075] Step S106: forming a first signal metal line in communication with the first source-drain structure.

[0076] It can be understood that after the first source-drain structure is exposed, the first signal metal line providing a signal for the first transistor can be formed. Here, the first metal interconnection layer can be formed by using a standard post-process of transistor manufacturing. The first signal metal line can be included in the first metal interconnection layer.

[0077] In some embodiments, when the first source-drain structure is exposed by removing the second portion of the first semiconductor structure and the shallow trench isolation structure, step S106 can include: forming a first dielectric layer on the first source-drain structure and a first source-drain metal penetrating the first dielectric layer; forming a second dielectric layer on the first dielectric layer and a first direct communication hole penetrating the second dielectric layer; and forming a first metal interconnection layer on the second dielectric layer.

[0078] It can be understood that after the first source-drain structure is exposed, a dielectric material can be deposited on the first source-drain structure to form a first dielectric layer. Then a first source-drain metal penetrating the first dielectric layer can be formed in the first dielectric layer. Here, the first source-drain metal is connected with the first source-drain structure. After the first source-drain metal is formed, a dielectric material can be deposited on the first dielectric layer to form a second dielectric layer. Then a first straight through via penetrating the second dielectric layer can be formed in the second dielectric layer. Here, the first straight through via is connected with the first source-drain metal. After the first straight through via is formed, a first metal interconnection layer can be formed on the second dielectric layer by using a standard back-end-of-line process of semiconductor manufacturing. In this way, the first straight through via can connect the first power metal line and the first source-drain metal.

[0079] It can be understood that the first source-drain metal is located on the back of the wafer and is used to connect the first source-drain structure and a first signal metal line in the metal interconnection layer formed by the back-end-of-line process. The dielectric layers such as the first dielectric layer and the second dielectric layer can be formed by processes such as ALD, CVD and PVD.

[0080] Here, the first metal interconnection layer is formed based on the back-end-of-line process of semiconductor manufacturing. The first metal interconnection layer is used to realize the transmission of signals.

[0081] In some embodiments, in the case of exposing the first source-drain structure by forming the first recess, step S106 can include: depositing a metal material in the first recess to form a first source-drain metal; forming a second dielectric layer on the shallow trench isolation structure and a first straight through via penetrating the second dielectric layer; and forming a first metal interconnection layer on the second dielectric layer.

[0082] It can be understood that after the first source-drain structure is exposed, a metal material can be deposited in the first recess to form a first source-drain metal. Here, the first source-drain metal is connected with the first source-drain structure. The height of the first source-drain metal is approximately equal to the height of the shallow trench isolation structure. After the first source-drain metal is formed, a dielectric material can be deposited on the shallow trench isolation structure to form a second dielectric layer. Then a first straight through via penetrating the second dielectric layer can be formed in the second dielectric layer. Here, the first straight through via is connected with the first source-drain metal. After the first straight through via is formed, a first metal interconnection layer can be formed on the second dielectric layer by using a standard back-end-of-line process of semiconductor manufacturing. In this way, the first straight through via can connect the first power metal line and the first source-drain metal.

[0083] In this application, a first transistor is formed on a semiconductor substrate using a stacked structure, allowing the first transistor to be formed on the semiconductor substrate. Furthermore, the first source / drain structure in the first transistor can contact the semiconductor substrate, thus directly exposing the first source / drain structure after wafer fabrication and removal of the semiconductor substrate. Subsequently, a first signal metal line communicating with the first source / drain structure can be formed on the exposed first source / drain structure. Compared to related technologies that require etching the dielectric layer of the first transistor to expose the first source / drain structure before forming the first signal metal line, this application eliminates the need to etch the dielectric layer inside the first transistor. This reduces the overlap area between the metal connecting the first source / drain structure and the gate metal, effectively reducing the parasitic capacitance between the source / drain structure and the gate structure, increasing the transistor's operating speed, and improving its electrical performance.

[0084] The following describes the fabrication method of the semiconductor structure provided in the embodiments of this application, taking the all-around gate field-effect transistor as an example. First, the first fabrication process is introduced, namely, the scheme of forming back-side interconnects on the back side of the wafer using the backside source / drain metal contact (BSMD) process. Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of this application. It should be noted that, for ease of understanding, the layout includes a back view (e.g., Figure 2 (a) in the middle and front view (e.g.) Figure 2 (b) shows the fin structure, gate structure, source / drain metal, signal metal lines, and power supply metal lines in the rear and front views. Specifically, AA' is a cross-section of the semiconductor structure along the length of the gate region (perpendicular to the channel direction); BB' is a cross-section of the semiconductor structure along the length of the source / drain region (perpendicular to the channel direction); CC' is a cross-section of the semiconductor structure along the length of the source / drain region (perpendicular to the channel direction); and DD' is a cross-section of the semiconductor structure along a third direction (channel direction).

[0085] Figures 3 to 18 This is a schematic diagram of the semiconductor structure in the first fabrication process according to an embodiment of this application. Wherein, Figures 3 to 18 (a) is a cross-sectional view of the semiconductor structure along the AA' plane. Figures 3 to 18 (b) is a cross-sectional view of the semiconductor structure along the BB' plane. Figures 3 to 18 (c) is a cross-sectional view of the semiconductor structure along the CC' plane. Figures 3 to 18 (d) is a cross-sectional view of the semiconductor structure along the DD' plane.

[0086] In one example, the fabrication process of the semiconductor structure 10 may include the following steps:

[0087] First step: Silicon and Silicon Germanium are deposited on the silicon substrate 20 in turn to form a stack structure 21, obtaining a structure as shown in Figure 3 .

[0088] Second step: The stack structure 21 is etched to form a fin structure 22, obtaining a structure as shown in Figure 4 .

[0089] Here, a hard mask structure can be deposited on the stack structure 21, and the stack structure 21 is etched to form the fin structure 22 with the hard mask structure as a mask.

[0090] It can be understood that when the transistor is a full-surrounding gate field effect transistor, the fin structure 22 can be a stack nanosheet structure. The stack nanosheet structure can include an active layer 23 and a sacrificial layer 24.

[0091] In some embodiments, the material for forming the hard mask structure can include silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon carbide (SiC), etc.

[0092] Third step: A first part of the first semiconductor substrate close to the fin structure 22 in the silicon substrate 20 is etched to reserve a second part 26 of the first semiconductor substrate. Here, the second part 26 of the first semiconductor substrate is a part of the silicon substrate 20 located below the fin structure 22. Then, an oxide material is deposited in the initial groove between the adjacent second part 26 of the first semiconductor substrate to form a shallow trench isolation structure 25, obtaining a structure as shown in Figure 5 .

[0093] In some embodiments, the height of the shallow trench isolation structure 25 is less than or equal to the height of the second part 26 of the first semiconductor substrate. The shallow trench isolation structure 25 covers the second semiconductor substrate 27.

[0094] Fourth step: Polysilicon material is deposited in the gate region to form a pseudo gate structure 28, and then sidewall material can be deposited on the sidewall of the pseudo gate structure 28 to form a pseudo gate sidewall 29, obtaining a structure as shown in Figure 6 .

[0095] Fifth step: The fin structure 22 in the source-drain region is removed, obtaining a structure as shown in Figure 7 .

[0096] Sixth step: Based on the second part 26 of the first semiconductor substrate in the source-drain region and the fin structure 22 in the gate region, a first source-drain structure 111 and a second source-drain structure 112 are formed in the source-drain region. Then, dielectric material is deposited on the first source-drain structure 111 and the second source-drain structure 112 to form a first interlayer dielectric layer 113, obtaining a structure as shown in Figure 8 .

[0097] Step 7: Remove the dummy gate structure 28, and remove the sacrificial layer 24 in the fin structure 22 in the gate region. The gate dielectric material and the gate metal material are sequentially deposited on the peripheral side of the active layer 23 in the fin structure 22 in the gate region to form the first gate structure 114, obtaining a structure as shown in FIG. 11C. Figure 9

[0098] Step 8: Etch the first interlayer dielectric layer 113 to form a second source-drain metal recess, and deposit a metal material in the second source-drain metal recess to form a second source-drain metal 115, obtaining a structure as shown in FIG. 11D. Figure 10

[0099] It can be understood that the second source-drain metal 115 is connected to the second source-drain structure 112.

[0100] Step 9: Deposit a dielectric material on the first interlayer dielectric layer 113 to form a front surface dielectric layer 30, and then form a second straight via hole 31 penetrating the front surface dielectric layer 30 in the front surface dielectric layer 30, obtaining a structure as shown in FIG. 11E. Figure 11

[0101] It can be understood that the second straight via hole 31 is connected to the second source-drain metal 115.

[0102] Step 10: Form an M0 layer in the second metal interconnection layer 32 by using a standard back-end preparation process of a semiconductor structure on the front surface dielectric layer 30. The M0 layer includes a first power supply metal line 116, obtaining a structure as shown in FIG. 11F. Figure 12

[0103] It can be understood that the M0 layer is a bottom metal layer in the second metal interconnection layer 32.

[0104] Step 11: Form an M1 layer in the second metal interconnection layer 32 by using a standard back-end preparation process of a semiconductor structure on the M0 layer, obtaining a structure as shown in FIG. 11G. Figure 13

[0105] It can be understood that the M1 layer is a high-level metal layer in the second metal interconnection layer 32.

[0106] At this point, the front-end preparation process of the first transistor 11 is completed.

[0107] Step 12: Bond the first transistor 11 with a carrier wafer 33, and perform film stripping on the first transistor 11 after bonding. Then, remove the second semiconductor substrate 27, the second part 26 of the first semiconductor substrate, and the shallow trench isolation structure 25 by using a mechanical planarization process, obtaining a structure as shown in FIG. 11H. Figure 14

[0108] ​​​​​​It can be understood that by removing the second semiconductor substrate 27, the second part 26 of the first semiconductor substrate and the shallow trench isolation structure 25, the first source-drain structure 111 in contact with the semiconductor substrate can be exposed.

[0109] Thirteenth step: depositing dielectric material on the first transistor 11 to form a first dielectric layer 34. Then a source-drain metal groove can be formed in the first dielectric layer 34. Depositing metal material in the source-drain metal groove to form a first source-drain metal 117, obtaining a structure as shown in Figure 15 .

[0110] Fourteenth step: depositing dielectric material on the first dielectric layer 34 to form a second dielectric layer 35. Then a first straight via hole 36 penetrating the second dielectric layer 35 can be formed in the second dielectric layer 35, obtaining a structure as shown in Figure 16 .

[0111] Fifteenth step: using standard back-end-of-line process of semiconductor structure, forming M0 layer in the first metal interconnection layer on the second dielectric layer 35. The M0 layer includes a first signal metal line 118, obtaining a structure as shown in Figure 17 .

[0112] It should be noted that the width of the first signal metal line 118 in the A-A' section is smaller than the width of the first power metal line 116 in the A-A' section.

[0113] Sixteenth step: using standard back-end-of-line process of semiconductor structure, forming M1 layer in the first metal interconnection layer 37 on the M0 layer, obtaining a structure as shown in Figure 18 .

[0114] It can be understood that the M1 layer is a high-level metal layer in the first metal interconnection layer 37.

[0115] So far, the first preparation process is completed.

[0116] The second preparation process is introduced below, that is, a scheme of forming backside interconnection by using self-aligned backside contact (SABC) process on the wafer backside. Figures 19 to 23 The structure of the semiconductor structure in the second preparation process of the embodiment of the present application is shown in the following figures, wherein, Figures 19 to 23 (a) is a section view of the semiconductor structure along the A-A' section, Figures 19 to 23 (b) is a section view of the semiconductor structure along the B-B' section, Figures 19 to 23 (c) is a section view of the semiconductor structure along the C-C' section, Figures 19 to 23 (d) is a section view of the semiconductor structure along the D-D' section.

[0117] In an example, the preparation process of the semiconductor structure 10 can include the following steps:

[0118] First step: same as the first step to the fifth step in the first preparation process, a structure as shown in FIG. 2A is obtained. Figure 19

[0119] Second step: the second part 26 of the first semiconductor structure in the source-drain region is removed, and silicon germanium is deposited at the position where the second part 26 of the first semiconductor structure is removed, to form a sacrificial structure 38. Then, based on the fin structure 22 in the gate region, the first source-drain structure 111 and the second source-drain structure 112 are formed in the source-drain region by epitaxy, and a dielectric material is deposited on the first source-drain structure 111 and the second source-drain structure 112, to form a first interlayer dielectric layer 113, a structure as shown in FIG. 2B is obtained. Figure 20

[0120] Third step: same as the seventh step to the eleventh step in the first preparation process, a structure as shown in FIG. 2C is obtained. Figure 21

[0121] Fourth step: the first transistor 11 is bonded with the carrier wafer 33, and the first transistor 11 is flipped after the bonding. Then, the mechanical planarization process is used to remove the second semiconductor substrate 27. Then, the sacrificial structure 38 is removed to obtain a first recess, and a metal material is deposited at the position where the first recess is removed, to form a first source-drain metal 117, a structure as shown in FIG. 2D is obtained. Figure 22

[0122] It can be understood that the metal material does not need to be deposited in the first recess of the second source-drain structure 112.

[0123] Sixth step: a dielectric material is deposited on the shallow trench isolation structure 25 to form a second dielectric layer 35. Then, a first straight through hole 36 penetrating through the second dielectric layer 35 is formed in the second dielectric layer 35. Then, the first metal interconnection layer 37 is formed on the second dielectric layer 35 by using the standard back-end preparation process of the semiconductor structure, a structure as shown in FIG. 2E is obtained. Figure 23

[0124] It should be noted that the second preparation process has an advantage over the first preparation process, that is, the self-aligned source-drain metal can be realized, and the preparation scheme is more superior.

[0125] In the embodiments of the present application, the metal layer of the power supply wiring can be formed on the front side of the wafer; then, the oxide is deposited, the wafer is bonded and flipped, the wafer is thinned, and the metal layer of the signal wiring is formed on the back side of the wafer. In addition, the embodiments of the present application support various back side interconnection processes, and the implementation of the BSMD process and the SABC process is shown in the above specific embodiments.

[0126] ​​​​​Further, the semiconductor structure provided by the embodiments of the present application can be detected by a detection analysis instrument, for example, a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscopy (STEM), and the like. Taking the TEM as an example, the embodiments of the present application can adopt a TEM sectioning manner to detect the structure of the semiconductor structure. It can be observed that, compared with the BSPDN in the related art, the semiconductor structure in the embodiments of the present application has at least two obvious differences: 1, the position of the transistor power supply interconnection is different: the BSPDN is on the wafer back surface, and the embodiments of the present application are on the wafer front surface; 2, the position of the transistor signal interconnection is different: the BSPDN is on the wafer front surface, and the embodiments of the present application are on the wafer back surface. Meanwhile, on the A-A', B-B', and C-C' sections, a wider M0 power supply metal line can be observed on the front surface (the bottom layer after being developed); and a smaller M0 signal metal line can be observed on the back surface (the top layer after being developed).

[0127] In a second aspect, the embodiments of the present application provide a semiconductor structure, which is prepared by using the preparation method in any one of the first aspect. Referring to FIGS. 1 to 3, the semiconductor structure 10 can include a first transistor 11. The first transistor 11 includes a first source-drain structure 111. A first power supply metal line 116 in communication with the first transistor 11, wherein the first power supply metal line 116 is configured to provide a power supply for the first transistor 11. A first signal metal line 118 disposed opposite to the first power supply metal line 116 and in communication with the first source-drain structure 111, wherein the first signal metal line 118 is configured to provide a signal for the first transistor 11. Figure 18 Figure 23 As shown in FIGS. 1 to 3, the semiconductor structure 10 can include a first transistor 11. The first transistor 11 includes a first source-drain structure 111. A first power supply metal line 116 in communication with the first transistor 11, wherein the first power supply metal line 116 is configured to provide a power supply for the first transistor 11. A first signal metal line 118 disposed opposite to the first power supply metal line 116 and in communication with the first source-drain structure 111, wherein the first signal metal line 118 is configured to provide a signal for the first transistor 11.

[0128] In some embodiments, the first transistor 11 further includes a second source-drain structure 112 and a first gate structure 114. The second source-drain structure 112 is connected to the first power supply metal line 116.

[0129] In some embodiments, the first signal metal line 118 is located at an M0 layer in a first metal interconnection layer 37. The first power supply metal line 116 is located at an M0 layer in a second metal interconnection layer 32. In some embodiments, the second metal interconnection layer 32 is prepared on the wafer front surface, and the first metal interconnection layer 37 is prepared on the wafer back surface. In this way, the embodiments of the present application can realize the interconnection scheme of front surface power supply wiring and back surface signal wiring.

[0130] It can be understood that the semiconductor structure in the embodiments of the present application can be prepared by using the preparation method in any one of the first aspect. Figure 18 Figure 23 ​​The preparation process of the structure shown will not be described here for the sake of brevity of the description.

[0131] In a third aspect, the embodiments of the present application provide a semiconductor device, comprising: the semiconductor structure of the above-mentioned embodiments, the semiconductor structure in the embodiments of the present application can refer to the semiconductor structure in the first aspect. Figure 18 and Figure 23 The preparation process of the structure shown will not be described here for the sake of brevity of the description.

[0132] In the description of the embodiments of the present application, the description of the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0133] The above is only the preferred embodiment of the present application and is not intended to limit the present application. Those skilled in the art can make various changes and modifications to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The preparation method comprises: forming a stack structure on a semiconductor substrate; etching the stack structure to form a fin structure; forming a first transistor on the semiconductor substrate based on the fin structure, wherein a first source-drain structure in the first transistor is in contact with the semiconductor substrate; forming a first power supply metal line on the first transistor, wherein the first power supply metal line is configured to provide power supply for the first transistor; developing and removing the semiconductor substrate to expose the first source-drain structure; forming a first signal metal line in communication with the first source-drain structure, wherein the first signal metal line is configured to provide a signal for the first transistor.

2. The production method according to claim 1, characterized by, The semiconductor substrate comprises a first semiconductor substrate and a second semiconductor substrate which are stacked; the first semiconductor substrate is closer to the fin structure than the second semiconductor substrate; wherein, after the etching the stack structure to form a fin structure, the preparation method further comprises: etching a first part of the first semiconductor substrate and retaining a second part of the first semiconductor substrate, wherein the first part is a part of the first semiconductor substrate which is not covered by the fin structure; depositing an oxide material at a position where the first part is removed to form a shallow trench isolation structure, wherein the shallow trench isolation structure is configured to electrically isolate the first transistor and the second semiconductor substrate.

3. The preparation method according to claim 2, characterized in that, The developing and removing the semiconductor substrate to expose the first source-drain structure comprises: developing and removing the second semiconductor substrate by a mechanical planarization process; removing the second part and the shallow trench isolation structure until the first source-drain structure is exposed.

4. The production method according to claim 3, characterized by, The forming a first signal metal line in communication with the first source-drain structure comprises: forming a first dielectric layer and a first source-drain metal penetrating through the first dielectric layer on the first source-drain structure, wherein the first source-drain metal is connected to the first source-drain structure; forming a second dielectric layer and a first direct communication hole penetrating through the second dielectric layer on the first dielectric layer; forming a first metal interconnection layer on the second dielectric layer, wherein the first metal interconnection layer comprises the first signal metal line; and the first direct communication hole communicates the first signal metal line and the first source-drain metal.

5. The preparation method according to claim 2, characterized in that, The etching selectivity ratio of the material forming the first semiconductor substrate is the same as the etching selectivity ratio of the material forming the first source-drain structure; wherein, after the depositing an oxide material at a position where the first part is removed to form a shallow trench isolation structure, the preparation method further comprises: removing the second part and depositing a semiconductor material at a position where the second part is removed to form a sacrificial structure, wherein the etching selectivity ratio of the material forming the sacrificial structure is different from the etching selectivity ratio of the material forming the first source-drain structure; wherein, the developing and removing the semiconductor substrate to expose the first source-drain structure comprises: developing and removing the second semiconductor substrate by a mechanical planarization process; removing the sacrificial structure to form a first recess, wherein a bottom of the first recess is formed by the first source-drain structure.

6. The preparation method according to claim 2, characterized in that, The etching selectivity of the material forming the first semiconductor substrate is different from the etching selectivity of the material forming the first source-drain structure. The film stripping and removing the semiconductor substrate to expose the first source-drain structure comprises: The film stripping and removing the second semiconductor substrate by a mechanical planarization process. The second part is removed to form a first recess, wherein a bottom of the first recess is formed by the first source-drain structure.

7. The production method according to claim 5 or 6, characterized by, The first signal metal line in communication with the first source-drain structure comprises: A metal material is deposited in the first recess to form a first source-drain metal, wherein the first source-drain metal is connected to the first source-drain structure. A second dielectric layer and a first straight through via hole penetrating through the second dielectric layer are formed on the shallow trench isolation structure. A first metal interconnection layer is formed on the second dielectric layer, wherein the first metal interconnection layer comprises the first signal metal line; and the first straight through via hole is in communication with the first signal metal line and the first source-drain metal.

8. The method of claim 1, wherein, The first transistor is formed on the semiconductor substrate based on the fin structure comprises: The fin structure in the source-drain region is etched to form a source-drain recess. The first source-drain structure and a second source-drain structure are formed in the source-drain recess based on at least the fin structure in the gate region. A first interlayer dielectric layer is formed on the first source-drain structure and the second source-drain structure. The first power supply metal line on the first transistor comprises: The first interlayer dielectric layer is etched to form a source-drain metal recess. A metal material is deposited in the source-drain metal recess to form a second source-drain metal, wherein the second source-drain metal is connected to the second source-drain structure. A front dielectric layer and a second straight through via hole penetrating through the front dielectric layer are formed on the first interlayer dielectric layer. A second metal interconnection layer is formed on the front dielectric layer, wherein the second metal interconnection layer comprises the first power supply metal line; and the second straight through via hole is in communication with the first power supply metal line and the second source-drain metal.

9. A semiconductor structure produced using the production method according to any one of claims 1 to 8, characterized in that Comprise: A first transistor comprises a first source-drain structure. A first power supply metal line in communication with the first transistor, wherein the first power supply metal line is used to provide power supply for the first transistor. A first signal metal line disposed opposite to the first power supply metal line and in communication with the first source-drain structure, wherein the first signal metal line is used to provide signal for the first transistor.

10. A semiconductor device, characterized by comprising: Comprise: The semiconductor structure of claim 9.

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