Array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate and a display panel. According to the array substrate, the first electrode is in direct contact with the source and drain electrode layer, at least the number of insulating layers located between the first electrode layer and the source and drain electrode layer can be reduced, the number of needed mask plates is reduced, the preparation efficiency is improved, and the preparation efficiency is improved by adjusting the distance between the source and drain electrode layer and the second electrode in the thickness direction of the array substrate. The distance between the first electrode and the second electrode in the thickness direction of the array substrate is larger than the distance between the first electrode and the second electrode in the thickness direction of the array substrate, the stray capacitance between the source and drain electrode layer and the second electrode is prevented from being increased due to reduction of the insulating layer, and the electrical property of the array substrate is good.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the development of display devices, the requirements of existing display devices for thin film transistors are higher and higher. Low-temperature polysilicon thin film transistors are widely used in liquid crystal display devices and OLED (Organic Light-Emitting Diode) display devices due to their fast switching speed and low power consumption. However, the preparation process of the existing low-temperature polysilicon thin film transistor is relatively complex, a large number of mask plates are required, which leads to high cost and low preparation efficiency.

[0003] Therefore, the existing display device has the technical problem of low preparation efficiency caused by the complex preparation process. SUMMARY

[0004] Embodiments of the present application provide an array substrate and a display panel to alleviate the technical problem of low preparation efficiency caused by the complex preparation process of the existing display device.

[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, an array substrate is provided, comprising:

[0006] a substrate;

[0007] a first electrode layer disposed on one side of the substrate, the first electrode layer comprising a first electrode;

[0008] a source-drain electrode layer disposed on the same side of the substrate as the first electrode layer, the first electrode directly contacting the source-drain electrode layer;

[0009] a second electrode layer disposed on the side of the source-drain electrode layer away from the substrate, the second electrode layer comprising a second electrode;

[0010] wherein the distance between the source-drain electrode layer and the second electrode in the thickness direction of the array substrate is greater than the distance between the first electrode and the second electrode in the thickness direction of the array substrate.

[0011] According to a second aspect of the present application, a display panel is provided, comprising the array substrate according to any one of the above embodiments.

[0012] The embodiment of the present application provides an array substrate and a display panel; the array substrate directly contacts a first electrode and a source-drain layer, at least can reduce an insulating layer between the first electrode layer and the source-drain layer, reduce the number of required mask plates, improve the preparation efficiency, and by making the interval between the source-drain layer and the second electrode in the thickness direction of the array substrate greater than the interval between the first electrode and the second electrode in the thickness direction of the array substrate, avoiding the parasitic capacitance between the source-drain layer and the second electrode increasing due to the reduction of the insulating layer, so that the electrical property of the array substrate is better.

[0013] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0015] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0016] Figure 1 It is a perspective view of a contrast display device.

[0017] Figure 2 It is a perspective view of a contrast display device. Figure 1 It is a perspective view of a contrast display device.

[0018] Figure 3 It is a cross-sectional schematic view of another contrast display device.

[0019] Figure 4 It is a first schematic view of an array substrate provided by the embodiment of the present application.

[0020] Figure 5 It is a second schematic view of an array substrate provided by the embodiment of the present application.

[0021] Figure 6 It is a third schematic view of an array substrate provided by the embodiment of the present application.

[0022] Figure 7 It is a structure schematic view of an array substrate corresponding to some steps in a preparation method of an array substrate provided by the embodiment of the present application.

[0023] Figure 8 It is a schematic view of a display panel provided by the embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0025] In order to explain the principle of the technical problem of the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be used as prior art in the embodiments of the present application. Figure 1 is a perspective view of a comparative display device, Figure 2 is a perspective view of a comparative display device, Figure 1 is an A-A sectional view and a B-B sectional view of the comparative display device in Figure 2 is (a) of Figure 1 is an A-A sectional view of the comparative display device in Figure 2 is (b) of Figure 1 is a B-B sectional view of the comparative display device in. As shown in Figure 1 , Figure 2 the comparative display device includes a substrate 11, a light shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film 17, a source-drain film 18, a planarization film 191, a bottom electrode film 192, a passivation film 193 and a top electrode film 194, and the active film 14 includes a channel region 143, a light doped region 142 and a heavy doped region 141.

[0026] As can be seen from Figure 2 , when the comparative display device is formed, 9 mask plates are needed, which are one mask plate for forming the light shielding film 12, one mask plate for forming the first insulating film 13 and the active film 14, one mask plate for forming the gate film 16, one mask plate for forming the via of the third insulating film 17, one mask plate for forming the source-drain film 18, one mask plate for forming the via of the planarization film 191, one mask plate for forming the bottom electrode film 192, one mask plate for forming the via of the passivation film 193 and one mask plate for forming the top electrode film 194. It can be seen that the number of mask plates needed in the forming process of the comparative display device is large, and the process steps are more, which leads to a complex process for forming the comparative display device, high cost and low preparation efficiency. Therefore, the existing display device has the technical problem of low preparation efficiency caused by a complex preparation process.

[0027] The embodiments of the present application aim at the above technical problem, and provide an array substrate and a display device to solve the above technical problem.

[0028] Figure 4A first schematic diagram of an array substrate provided by an embodiment of the present application. Figure 5 A second schematic diagram of an array substrate provided by an embodiment of the present application. Figure 6 A third schematic diagram of an array substrate provided by an embodiment of the present application. Figure 7 A structure schematic diagram of an array substrate corresponding to some steps in a preparation method of an array substrate provided by an embodiment of the present application. Figure 8 A schematic diagram of a display panel provided by an embodiment of the present application.

[0029] As shown in Figures 4 to 6 , an embodiment of the present application provides an array substrate 2, which includes a substrate 21, a first electrode layer 27, a source-drain electrode layer 28 and a second electrode layer 31. The first electrode layer 27 is arranged on one side of the substrate 21, and includes a first electrode 271. The source-drain electrode layer 28 is arranged on the same side of the substrate 21 as the first electrode layer 27, and directly contacts the first electrode 271. The second electrode layer 31 is arranged on a side of the source-drain electrode layer 28 away from the substrate 21, and includes a second electrode 311. A distance between the source-drain electrode layer 28 and the second electrode 311 in a thickness direction of the array substrate 2 (for example, a thickness L1 of a portion of an insulating layer 29 in the array substrate 2 located in a setting region of the source-drain electrode layer 28) is greater than a distance between the first electrode 271 and the second electrode 311 in the thickness direction of the array substrate (for example, a thickness L2 of a portion of the insulating layer 29 in the array substrate located between the first electrode 271 and the second electrode 311). Figures 4 to 6 Figures 4 to 6

[0030] An embodiment of the present application provides an array substrate 2, which at least reduces an insulating layer between a first electrode layer and a source-drain electrode layer by directly contacting the first electrode 271 and the source-drain electrode layer 28, reduces a number of mask plates required, improves a preparation efficiency, and by making a distance between the source-drain electrode layer 28 and the second electrode 311 in a thickness direction of the array substrate greater than a distance between the first electrode 271 and the second electrode 311 in the thickness direction of the array substrate, avoids increasing a parasitic capacitance between the source-drain electrode layer and the second electrode due to the reduction of the insulating layer, and makes an electrical property of the array substrate better.

[0031] In some embodiments, as shown in Figures 4 to 6 ​​As shown, the array substrate 2 further comprises an insulating layer 29, which is arranged between the source-drain electrode layer 28 and the second electrode layer 31; wherein the thickness L1 of the portion of the insulating layer 29 located in the arrangement region of the source-drain electrode layer 28 is greater than the thickness L2 of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311. By making the thickness L1 of the portion of the insulating layer 29 located in the arrangement region of the source-drain electrode layer 28 greater than the thickness L2 of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311, the spacing between the source-drain electrode layer 28 and the second electrode 311 in the thickness direction of the array substrate is greater than the spacing between the first electrode 271 and the second electrode 311 in the thickness direction of the array substrate, so that the parasitic capacitance between the source-drain electrode layer and the second electrode is reduced when the capacitance between the first electrode 271 and the second electrode 311 is ensured to be large, and the electrical property of the array substrate is better.

[0032] Specifically, as shown in the embodiments of the present application, Figures 4 to 6 The array substrate 2 comprises a substrate 21, a first electrode layer 27, a source-drain electrode layer 28, an insulating layer 29 and a second electrode layer 31; the first electrode layer 27 is arranged on one side of the substrate 21, and comprises a first electrode 271; the source-drain electrode layer 28 is arranged on the side of the first electrode layer 27 away from the substrate 21, and directly contacts the first electrode 271; the insulating layer 29 is arranged on the side of the source-drain electrode layer 28 away from the first electrode layer 27; the second electrode layer 31 is arranged on the side of the insulating layer 29 away from the source-drain electrode layer 28, and comprises a second electrode 311; wherein the thickness L1 of the portion of the insulating layer 29 located in the arrangement region of the source-drain electrode layer 28 is greater than the thickness L2 of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311.

[0033] The array substrate 2 of the embodiments of the present application can at least reduce the insulating layer between the first electrode layer 27 and the source-drain electrode layer 28, reduce the number of mask plates required, improve the preparation efficiency, and make the thickness of the portion of the insulating layer 29 located in the arrangement region of the source-drain electrode layer 28 greater than the thickness of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311, so as to avoid the increase of the parasitic capacitance between the source-drain electrode layer and the second electrode due to the reduction of the insulating layer 29, and make the electrical property of the array substrate better.

[0034] Specifically, the first electrode is a pixel electrode, and the second electrode is a common electrode.

[0035] Specifically, as shown in Figures 4 to 6 The array substrate 2 further comprises a second buffer layer 22, an active layer 23, a gate insulating layer 24, a gate layer 25 and an interlayer insulating layer 26, which are sequentially arranged.

[0036] Specifically, as shown in Figures 4 to 6 The second buffer layer 22 can be directly in contact with the substrate 21, so that the light shielding layer is removed, the number of required mask plates is reduced, and the preparation efficiency of the array substrate is improved.

[0037] Specifically, as shown in Figures 4 to 6 The first electrode layer 27 and the interlayer insulating layer 26 can be formed by using the same mask plate, so that the number of required mask plates is reduced, and the preparation efficiency of the array substrate is improved.

[0038] Specifically, as shown in Figure 3 In order to reduce the number of mask plates, some comparative display devices remove the light shielding film 12 and the planarization film 191, change the bottom electrode film 192 for forming the common electrode to the bottom electrode film 192 for forming the pixel electrode, change the top electrode film 194 for forming the pixel electrode to the top electrode film 194 for forming the common electrode, and make the bottom electrode film 192 and the via hole of the third insulating film 17 formed by using the same mask plate, so as to save the number of mask plates. Figure 3 As shown in the comparative display device, because the planarization film 191 is removed, the parasitic capacitance between the common electrode and the source-drain film 18 is increased, the total capacitance of the common electrode is increased, the recovery time of the common electrode after being disturbed is longer, and abnormality of the heavy load picture is easily caused during display. The embodiment of the present application aims at the above technical problems, and by making the thickness L1 of the part of the insulating layer 29 located in the setting region of the source-drain layer 28 greater than the thickness L2 of the part of the insulating layer 29 located between the first electrode 271 and the second electrode 311, the parasitic capacitance between the common electrode and the source-drain layer can be reduced, the disturbance on the common electrode can be reduced, and the electrical property of the array substrate can be improved, while ensuring that the storage capacitance between the first electrode 271 and the second electrode 311 is unchanged or even increased.

[0039] Specifically, it can be understood that in the embodiment of the present application, when the thickness of each region in a certain film layer or a certain sub-layer is not particularly mentioned, the thickness of each region of the film layer is equal (except that the edge of each pattern has a certain thickness difference due to the existence of slope), for example, in Figure 3In the embodiment, although the thickness of each part of the passivation film 193 is shown to have a certain difference, in fact, the thickness of the passivation film 193 is equal (not considering the thickness difference caused by process error) except the thickness of the region where the via is provided.

[0040] In some embodiments, as shown in FIG. 2, the insulating layer 29 is a single layer design. One side of the insulating layer 29 is in contact with the source-drain layer, and one side of the insulating layer 29 is in contact with the second electrode layer 31. Figure 4

[0041] Specifically, the material of the insulating layer is silicon nitride or silicon oxide.

[0042] In some embodiments, as shown in FIG. 3, the insulating layer 29 includes a first sub-layer 291 and a second sub-layer 292, and the second sub-layer 292 is located between the first sub-layer 291 and the second electrode layer 31; wherein the material of the first sub-layer 291 is different from the material of the second sub-layer 292, and the thickness of the part of the insulating layer 29 located between the first electrode 271 and the second electrode 311 is less than or equal to the thickness of the first sub-layer 291. By making the insulating layer include a first sub-layer and a second sub-layer, and making the material of the first sub-layer different from the material of the second sub-layer, the etching selectivity and etching precision can be improved when etching the insulating layer, and the thickness of the part of the insulating layer 29 located between the first electrode 271 and the second electrode 311 is less than or equal to the thickness of the first sub-layer 291, which can increase or maintain the size of the storage capacitor and reduce the parasitic capacitance between the common electrode and the source-drain layer. Figure 5 Specifically, as shown in FIG. 4, compared with the single layer design of the insulating layer, the etching selectivity is small, and the embodiments of the present application make the insulating layer include a first sub-layer 291 and a second sub-layer 292, and make the material of the first sub-layer 291 different from the material of the second sub-layer 292, so that the etching selectivity and etching precision can be improved.

[0043] Figure 5

[0044] Specifically, as shown in FIG. 5, compared with the single layer design of the insulating layer, the etching selectivity is small, and the embodiments of the present application make the insulating layer include a first sub-layer 291 and a second sub-layer 292, and make the material of the first sub-layer 291 different from the material of the second sub-layer 292, so that the etching selectivity and etching precision can be improved. Figure 5 ​​​As shown, the thickness of the part of the insulating layer 29 located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the insulating layer 29 located between the first electrode 271 and the second electrode 311 by etching the second sub-layer 292 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311. However, the embodiments of the present application are not limited to this. The thickness of the part of the first sub-layer located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the first sub-layer located between the first electrode 271 and the second electrode 311 by etching the part of the second sub-layer 292 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311. Or, the thickness of the part of the first sub-layer located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the first sub-layer located between the first electrode 271 and the second electrode 311 by etching the part of the second sub-layer 292 and the part of the first sub-layer 291 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311.

[0045] Specifically, as shown in FIG. 2, the thickness of each part of the first sub-layer can be equal. However, the embodiments of the present application are not limited to this. The thickness of the part of the first sub-layer located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the first sub-layer located between the first electrode 271 and the second electrode 311. Figure 5

[0046] In some embodiments, the material of the first sub-layer is silicon nitride, and the material of the second sub-layer is silicon oxide; or the material of the first sub-layer is silicon oxide, and the material of the second sub-layer is silicon nitride.

[0047] Specifically, taking the material of the first sub-layer as silicon oxide and the material of the second sub-layer as silicon nitride as an example, the insulating layer can be etched by first etching the insulating layer by carbon tetrafluoride and oxygen to form a via, and then etching the insulating layer by sulfur hexafluoride and oxygen. Since the etching rate of sulfur hexafluoride and oxygen on silicon oxide is slow, the etching selectivity and etching precision can be improved.

[0048] Specifically, when the insulating layer includes the first sub-layer and the second sub-layer, the insulating layer can be etched by using one mask plate, so as to avoid increasing the number of mask plates.

[0049] In some embodiments, as shown in FIG. 2, the thickness of the part of the insulating layer 29 located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the insulating layer 29 located between the first electrode 271 and the second electrode 311 by etching the second sub-layer 292 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311. However, the embodiments of the present application are not limited to this. The thickness of the part of the first sub-layer located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the first sub-layer located between the first electrode 271 and the second electrode 311 by etching the part of the second sub-layer 292 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311. Or, the thickness of the part of the first sub-layer located in the setting region of the source-drain layer 28 can be greater than the thickness of the part of the first sub-layer located between the first electrode 271 and the second electrode 311 by etching the part of the second sub-layer 292 and the part of the first sub-layer 291 located between the first electrode 271 and the second electrode 311 and retaining the first sub-layer 291 and the second sub-layer 292 located between the source-drain layer 28 and the second electrode 311. Figure 6 ​As shown, the insulating layer 29 includes a passivation layer 294 and a first buffer layer 293. The passivation layer 294 is disposed between the first buffer layer 293 and the second electrode layer 31. The first buffer layer 293 is disposed within the location of the source / drain layer 28, and the insulating layer between the first electrode 271 and the second electrode 311 is the passivation layer 294. By including the passivation layer 294 and the first buffer layer 293 in the insulating layer 29, with the first buffer layer 293 disposed within the location of the source / drain layer 28 and the passivation layer 294 serving as the insulating layer between the first electrode 271 and the second electrode 311, the thickness of the portion of the insulating layer 29 located within the location of the source / drain layer 28 is greater than the thickness of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311. This allows for either increasing or maintaining the storage capacitance and reducing the parasitic capacitance between the common electrode and the source / drain layer.

[0050] Specifically, such as Figure 6 As shown, by etching away the first buffer layer 293 located between the first electrode 271 and the second electrode 311, and retaining the first buffer layer 293 and passivation layer 294 located between the source / drain layer 28 and the second electrode 311, the thickness of the portion of the insulating layer 29 located in the disposed region of the source / drain layer 28 is greater than the thickness of the portion of the insulating layer 29 located between the first electrode 271 and the second electrode 311. However, the embodiments of this application are not limited to this. By etching away a portion of the first buffer layer 293 located between the first electrode 271 and the second electrode 311, and retaining the first buffer layer 293 and passivation layer 294 located between the source / drain layer 28 and the second electrode 311; or by etching away a portion of the first buffer layer 293 and passivation layer 294 located between the first electrode 271 and the second electrode 311, and retaining the first buffer layer 293 and passivation layer 294 located between the source / drain layer 28 and the second electrode 311.

[0051] Specifically, such as Figure 6 As shown, the thickness of each portion of the passivation layer 294 can be equal. However, the embodiments of this application are not limited to this; the thickness of the portion of the passivation layer 294 located in the source / drain layer setting region can be greater than the thickness of the portion of the passivation layer 294 located between the first electrode and the second electrode.

[0052] In some embodiments, such as Figure 6As shown, the first buffer layer 293 is in direct contact with the source / drain layer 28, and the projection of the first buffer layer 293 on the substrate 21 coincides with the projection of the source / drain layer 28 on the substrate 21. By making the projection of the first buffer layer 293 on the substrate 21 coincide with the projection of the source / drain layer 28 on the substrate 21, the first buffer layer 293 and the source / drain layer 28 can be formed using the same photomask, eliminating the need to increase the number of photomasks and improving the fabrication efficiency of the array substrate.

[0053] Specifically, it is understandable that, due to the different materials of the first buffer layer and the source / drain layer, and the existence of certain errors in the process, when the same mask is used to etch the first buffer layer and the source / drain layer, the slope of the first buffer layer and the source / drain layer may be different. Furthermore, due to process limitations, the first buffer layer and the source / drain layer may shrink during the etching process, resulting in the first buffer layer and the source / drain layer not completely overlapping in the actual design, but having certain differences. In this case, it is still considered that the projection of the first buffer layer 293 on the substrate 21 overlaps with the projection of the source / drain layer 28 on the substrate 21.

[0054] Specifically, such as Figure 6 As shown, the projection of the first buffer layer 293 on the substrate 21 coincides with the projection of the source / drain layer 28 on the substrate 21. Therefore, when reducing the parasitic capacitance between the common electrode and the source / drain layer, it is not necessary to increase the number of masks, thus reducing the required number of masks and improving the fabrication efficiency of the array substrate.

[0055] In some embodiments, such as Figure 6 As shown, the thickness of each portion of the passivation layer 294 is equal; or the thickness of the portion of the passivation layer 294 located in the setting region of the source-drain layer 28 is greater than the thickness of the portion of the passivation layer 294 located between the first electrode 271 and the second electrode 311.

[0056] Specifically, such as Figure 6 As shown, when the first buffer layer is disposed in the location of the source and drain layers, the thickness of each part of the passivation layer 294 can be made equal, eliminating the need to etch the passivation layer 294 and reducing the number of required photomasks.

[0057] Specifically, when the first buffer layer is disposed in the location area of ​​the source-drain layer, the thickness of the portion of the passivation layer 294 located in the location area of ​​the source-drain layer 28 can be made greater than the thickness of the portion of the passivation layer 294 located between the first electrode 271 and the second electrode 311, thereby further reducing the parasitic capacitance between the source-drain layer and the common electrode layer and improving the electrical properties of the array substrate.

[0058] In some embodiments, the dielectric constant of the first buffer layer 293 is less than the dielectric constant of the passivation layer 294. By making the dielectric constant of the first buffer layer 293 less than the dielectric constant of the passivation layer 294, the parasitic capacitance between the source-drain layer and the common electrode can be reduced, and the storage capacitance between the first electrode and the second electrode is larger, so that the effects of larger storage capacitance and smaller parasitic capacitance are achieved.

[0059] Specifically, the material of the passivation layer 294 can be silicon nitride, and the material of the buffer layer can be silicon oxide, or the material of the passivation layer 294 can be silicon nitride with high density, and the material of the buffer layer can be silicon nitride with low density, i.e., the material of the passivation layer 294 can be silicon nitride with high dielectric constant, and the material of the buffer layer can be silicon nitride with low dielectric constant.

[0060] Specifically, when the buffer layer is provided, the passivation layer can be provided in a single layer, or the passivation layer can include a first sub-layer and a second sub-layer.

[0061] In some embodiments, as shown in Figure 4 、 Figure 5 , the second electrode 311 is provided with an opening 31a in the region corresponding to the source-drain layer 28. By providing the second electrode 311 with the opening 31a in the region corresponding to the source-drain layer 28, the overlapping area of the second electrode 311 and the source-drain layer can be reduced, so that the parasitic capacitance of the common electrode and the source-drain layer can be reduced.

[0062] Specifically, as shown in Figure 4 、 Figure 5 , it can be seen that the second electrode 311 is provided with an opening 31a in the region corresponding to the source-drain layer 28, but the embodiments of the present application are not limited thereto, and the second electrode can be provided without the opening in the region corresponding to the source-drain layer 28 based on Figure 4 、 Figure 5 .

[0063] Specifically, as shown in Figure 6 , the second electrode 311 in Figure 6 is not provided with an opening 31a in the region corresponding to the source-drain layer 28, but the embodiments of the present application are not limited thereto, and the second electrode can be provided with an opening in the region corresponding to the source-drain layer 28 based on Figure 6 .

[0064] In some embodiments, as shown in Figure 4 、 Figure 5As shown, the source-drain layer 28 includes a data line (not shown), a source electrode 281 and a drain electrode 282, and the area of the opening 31a is less than or equal to the sum of the areas of the data line, the source electrode 281 and the drain electrode 282. By making the area of the opening 31a less than or equal to the sum of the areas of the data line, the source electrode 281 and the drain electrode 282, the problem of disconnection of the common electrode caused by an excessively large opening can be avoided, and the yield of the array substrate can be improved.

[0065] Specifically, it can be understood that in the array substrate, a plurality of transistors are arranged, and the drain of a part of the transistors is connected with the second electrode, and the drain does not form a parasitic capacitor with the second electrode. At this time, the thickness of the insulating layer between the drain and the second electrode can be equal to the thickness of the part of the insulating layer between the first electrode and the second electrode, or the thickness of the insulating layer between the drain and the second electrode can be equal to the thickness of the insulating layer between the data line and the second electrode.

[0066] Specifically, it can be understood that the drain of some transistors is not connected with the second electrode, and the drain of these transistors forms a parasitic capacitor with the second electrode. At the same time, the source of each transistor and the data line form a parasitic capacitor with the second electrode. Therefore, the second electrode can form an opening in the region corresponding to the source, the drain and the data line. However, in order to prevent the common electrode from being disconnected, the area of the opening can be less than or equal to the sum of the areas of the data line, the source and the drain.

[0067] Specifically, it can be understood that in some designs, the source or the drain is actually a part of the data line. At this time, the source, the drain and the data line are actually one of the data line, the source and the drain.

[0068] Specifically, as shown in Figure 4 , Figure 5 , Figure 4 , Figure 5 The source is connected with the first electrode, but the embodiments of the present application are not limited thereto. The drain can be connected with the first electrode. Alternatively, the source and the drain can be switched at positive and negative frames.

[0069] Specifically, the material of the active layer can be polysilicon, and specifically, low-temperature polysilicon. However, the embodiments of the present application are not limited thereto. For example, the material of the active layer can be metal oxide semiconductor, and specifically, indium gallium zinc oxide.

[0070] Specifically, the material of the first electrode layer can be indium tin oxide, and the material of the second electrode layer can be indium tin oxide.

[0071] Specifically, as shown in Figures 4 to 6As shown, the active layer 23 includes an active pattern 231, which includes a channel portion 231a, a lightly doped portion 231b, and a heavily doped portion 231c.

[0072] Specifically, the ion doping concentration of the channel portion 231a is less than that of the lightly doped portion 231b, and the ion doping concentration of the lightly doped portion 231b is less than that of the heavily doped portion 231c.

[0073] Figure 4 , Figure 5 The active pattern 231 is described as including a channel portion 231a, a lightly doped portion 231b, and a heavily doped portion 231c. However, the embodiments of this application are not limited to this. The active pattern 231 may include only the channel portion 231a and the heavily doped portion 231c.

[0074] Specifically, it is understood that the above embodiments have provided a detailed description of the array substrate from the aspects of film layer design, structure of each film layer, and materials. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the insulating layer includes a passivation layer and a first buffer layer, and the passivation layer is disposed between the first buffer layer and the second electrode layer; wherein, the first buffer layer is disposed in the disposed area of ​​the source and drain layer, and the insulating layer between the first electrode and the second electrode is the passivation layer; the second electrode has an opening in the area corresponding to the source and drain layer.

[0075] Meanwhile, this application provides a method for fabricating an array substrate, which fabricates an array substrate as described in any of the above embodiments.

[0076] by Figure 4 Taking the array substrate shown as an example, the structure of the array substrate corresponding to each step of the array substrate fabrication method will be explained.

[0077] Specifically, the fabrication methods of the array substrate include:

[0078] A substrate is provided, and a second buffer layer and an active layer are sequentially formed on the substrate, and the active layer is patterned; the structure of the array substrate corresponding to this step is as follows. Figure 7 As shown in (a) in the middle;

[0079] A gate insulating layer and a gate layer are sequentially formed on the active layer, and the gate layer is patterned; the structure of the array substrate corresponding to this step is as follows. Figure 7 As shown in (b);

[0080] An interlayer insulating layer and a first electrode layer are formed on the gate layer. The first electrode layer is patterned using the same photomask, and vias are formed by etching the interlayer insulating layer and the gate insulating layer. The structure of the array substrate corresponding to this step is as follows:Figure 7 (c) of FIG. 6B;

[0081] forming a source-drain layer on the first electrode layer, and patterning the source-drain layer; the structure of the array substrate corresponding to the step is as shown in (d) of FIG. 6B; Figure 7 (d) of FIG. 6B;

[0082] forming an insulating layer on the source-drain layer, and patterning the insulating layer; the structure of the array substrate corresponding to the step is as shown in (e) of FIG. 6B; Figure 7 (e) of FIG. 6B;

[0083] forming a second electrode layer on the insulating layer, and patterning the second electrode layer; the structure of the array substrate corresponding to the step is as shown in (f) of FIG. 6B. Figure 4 (f) of FIG. 6B.

[0084] The array substrate preparation method provided by the embodiments of the present application only needs six mask plates to form the array substrate, thereby reducing the number of mask plates required. By making the thickness of the part of the insulating layer located in the setting region of the source-drain layer greater than the thickness of the part of the insulating layer located between the first electrode and the second electrode, the parasitic capacitance between the source-drain layer and the second electrode caused by the reduction of the insulating layer is avoided, and the electrical property of the array substrate is better.

[0085] Meanwhile, the embodiments of the present application provide a display panel, which comprises the array substrate according to any one of the above embodiments.

[0086] Specifically, as shown in FIG. 4, the display panel 4 comprises an array substrate 2, a color filter substrate 41 and a liquid crystal layer 42; but the embodiments of the present application are not limited thereto, and the display panel can be other display panels. Figure 8 Specifically, the embodiments of the present application provide a display device, which comprises the display panel according to any one of the above embodiments.

[0087] Specifically, the display device further comprises a backlight module.

[0088] In the description of the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0089] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0090]

[0091] ​The embodiments, implementation manners and related technical features of the present application can be combined with each other without conflict.

[0092] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment without departing from the technical solution of the present application and according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a first electrode layer disposed on one side of the substrate, the first electrode layer comprising a first electrode; a source-drain electrode layer disposed on the same side of the substrate as the first electrode layer, the first electrode being in direct contact with the source-drain electrode layer; a second electrode layer disposed on a side of the source-drain electrode layer away from the substrate, the second electrode layer comprising a second electrode; wherein the distance between the source-drain electrode layer and the second electrode in the thickness direction of the array substrate is greater than the distance between the first electrode and the second electrode in the thickness direction of the array substrate.

2. The array substrate of claim 1, wherein, The array substrate further comprises an insulating layer disposed between the source-drain electrode layer and the second electrode layer; wherein the thickness of the portion of the insulating layer located in the region of the source-drain electrode layer is greater than the thickness of the portion of the insulating layer located between the first electrode and the second electrode.

3. The array substrate of claim 2, wherein, The insulating layer comprises a first sub-layer and a second sub-layer, the second sub-layer being located between the first sub-layer and the second electrode layer; wherein the material of the first sub-layer is different from the material of the second sub-layer, and the thickness of the portion of the insulating layer located between the first electrode and the second electrode is less than or equal to the thickness of the first sub-layer.

4. The array substrate of claim 3, wherein, The material of the first sub-layer is silicon nitride, and the material of the second sub-layer is silicon oxide; or the material of the first sub-layer is silicon oxide, and the material of the second sub-layer is silicon nitride.

5. The array substrate of claim 2, wherein, The insulating layer comprises a passivation layer and a first buffer layer, the passivation layer being disposed between the first buffer layer and the second electrode layer; wherein the first buffer layer is disposed in the region of the source-drain electrode layer, and the insulating layer between the first electrode and the second electrode is the passivation layer.

6. The array substrate of claim 5, wherein, The first buffer layer is in direct contact with the source-drain electrode layer, and the projection of the first buffer layer on the substrate overlaps the projection of the source-drain electrode layer on the substrate.

7. The array substrate of claim 5, wherein, The thickness of each portion of the passivation layer is equal; or the thickness of the portion of the passivation layer located in the region of the source-drain electrode layer is greater than the thickness of the portion of the passivation layer located between the first electrode and the second electrode.

8. The array substrate of claim 5, wherein, The dielectric constant of the first buffer layer is less than the dielectric constant of the passivation layer.

9. The array substrate according to any one of claims 1 to 8, wherein, The second electrode is provided with an opening in the region corresponding to the source-drain electrode layer.

10. A display panel, characterized by, The array substrate as claimed in any one of claims 1 to 9.

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