Three-junction solar cell capable of adjusting stress and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a three-junction solar cell capable of adjusting stress and a preparation method thereof, and the three-junction solar cell sequentially comprises a GaAs substrate, a corrosion cut-off layer, a contact layer, a top cell, a first tunnel junction, a middle cell, a second tunnel junction, a strain buffer layer, a bottom cell, a stress adjusting layer and an ohmic contact layer from bottom to top. By growing the stress adjusting layer on the bottom cell layer, not only can the compressive strain of the bottom cell layer on the front two cell layers and the substrate be compensated, but also the lattice constant and the thickness of the functional layer can be freely adjusted to compensate the stress generated by mismatch under the condition that the structure of the functional layer is not influenced, the warping of the epitaxial wafer is adjusted, and the reliability of the epitaxial wafer is improved. And the production yield and the device reliability of the flip cell chip can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a three-junction solar cell capable of adjusting stress and a preparation method thereof. BACKGROUND

[0002] The gallium arsenide three-junction solar cell has become the core physical main power in space application scenarios such as satellites, spacecraft and space stations due to its excellent photoelectric conversion efficiency and reliability. However, the traditional GaInP / GaInAs / Ge three-junction battery has obvious performance bottlenecks: the band gap design (such as GaInP / GaInAs / Ge) of the top, middle and bottom three-junction batteries needs to meet the lattice matching, which limits the optimized absorption of each sub-cell to the solar spectrum, causing current waste; the bottom cell adopts a germanium (Ge) sub-cell with a band gap of only 0.67eV, which significantly lowers the contribution to the voltage than the other two junctions (GaInP and GaInAs). The GaInP / GaAs / InGaAs flip-chip structure proposed by NREL breaks through the efficiency bottleneck of the traditional Ge bottom cell through band gap optimization and process innovation, and provides a higher performance and lighter solution for space photovoltaic systems.

[0003] However, when growing the GaInP / GaAs / InGaAs flip-chip three-junction solar cell, the lattice mismatch degree of the third junction and the second junction GaAs reaches 2.1%, which causes stress in the epitaxial material and induces warping deformation, and the warping increases the difficulty of subsequent chip processing and packaging processes. 0.3 Ga 0.7 As flip-chip three-junction solar cell, the lattice mismatch degree of the third junction and the second junction GaAs reaches 2.1%, which causes stress in the epitaxial material and induces warping deformation, and the warping increases the difficulty of subsequent chip processing and packaging processes. 0.3 Ga 0.7 However, the thickness of the In component maximum layer is too thick, which causes the wafer to be warped too much when growing the InGaAs cell, affects the crystal quality of the epitaxial layer, and causes performance degradation. 0.3 Ga 0.7 Therefore, it is of great significance to develop a flip-chip three-junction solar cell capable of adjusting the stress of the epitaxial layer, thereby improving the wafer warping and lattice quality.

[0004] Therefore, it is of great significance to develop a flip-chip three-junction solar cell capable of adjusting the stress of the epitaxial layer, thereby improving the wafer warping and lattice quality. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a three-junction solar cell capable of adjusting stress and a preparation method thereof, which aims to freely adjust the stress without affecting the functional layer structure, improve the crystal quality and production capacity of the flip-chip battery, and broaden the application range.

[0006] The application aims to provide a three-junction solar cell capable of adjusting stress, which is sequentially provided with a GaAs substrate, an etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, a second tunnel junction, a strain buffer layer, a bottom cell, a stress adjusting layer and an ohmic contact layer from bottom to top. The stress adjusting layer is grown in a form of component grading, and its lattice constant is gradually changed from matching the bottom cell to a set lattice constant.

[0007] In the technical solution, the stress adjusting layer is introduced into the bottom cell structure to adjust the lattice constant and compensate the stress caused by mismatching, improve the warping of the epitaxial wafer, and the stress adjusting layer is grown after the bottom cell is completed, which does not affect the crystal quality of the bottom cell material and has no effect on the performance; meanwhile, the introduced stress adjusting layer can freely adjust the stress without affecting the functional layer structure, which helps to improve the production capacity of the flip-chip and widen the application range.

[0008] Further, the stress adjusting layer is sequentially provided with In x1 GaAs, In y1 GaAs, wherein 0.29≤x1<0.32 and 0.23 In the technical solution, the lattice constant of the third junction cell layer (InGaAs) in the flip-chip three-junction gallium arsenide solar cell is increased by 5%-7% than that of the first two junctions (GaInP / GaAs) and the GaAs substrate, and the lattice expansion of the third junction cell layer will transmit compressive stress through the interface to cause elastic deformation of the first two junction cell layers during epitaxial growth. Therefore, the stress adjusting layer with a small lattice constant is grown above the third junction to increase the tensile stress on the third junction by reducing the In component y1 or increasing the thickness, so as to compensate the compressive stress of the third junction on the first two junction cell layers and the substrate, reduce the warping of the epitaxial wafer, improve the flatness of the epitaxial wafer, and reduce the processing difficulty of high-precision processes in the chip manufacturing and packaging links, which is beneficial to improve the production yield and device reliability.

[0009] Further, the material of the etching stop layer is one or a combination of GaInP, AlInP and AlGaInP; and the material of the contact layer is GaAs.

[0010] Further, the material of the top cell is (Al)GaInP, and the band gap is 1.80eV-1.95eV; the material of the middle cell is (In)GaAs, and the band gap is 1.37eV-1.42eV; and the material of the bottom cell is In x2 GaAs, and the band gap is 0.90eV-1.1eV, 0.29≤x2<0.32.

[0011] Further, the first tunnel junction is N ++GaInP / P ++ AlGaAs structure, wherein, N ++ The dopant of GaInP is one or more combinations of Te, Se, Si; P ++ The dopant of AlGaAs is one or more combinations of Mg, Zn, C.

[0012] Further, the second tunnel junction is N ++ GaAs / P ++ GaAs structure, wherein, N ++ The dopant of GaAs is one or more combinations of Te, Se, Si; P ++ The dopant of GaAs is one or more combinations of Mg, Zn, C.

[0013] Further, the material of the strain buffer layer is InAlGaAs, the doping concentration is greater than 1×10 18 / cm 3 , the dopant is at least one of Te, Se and Si; the material of the ohmic contact layer is In y1 GaAs, the doping concentration is greater than 2×10 18 / cm 3 , the dopant is at least one of Zn, Mg and C, and the In component is consistent with the stress adjustment layer.

[0014] The application also provides a preparation method of a three-junction solar cell capable of adjusting stress, specifically comprising the following steps: S1. On a GaAs substrate, a corrosion stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell and a second tunnel junction are sequentially epitaxially grown; S2. A strain buffer layer is grown on the second tunnel junction; S3. A bottom cell is grown on the strain buffer layer; S4. A stress adjustment layer is grown on the bottom cell; S5. An ohmic contact layer is grown on the stress adjustment layer.

[0015] Further, in S2, the strain buffer layer sequentially comprises 210nm of In 0.05 Al x3 GaAs, 210nm of In 0.1 Al x3 GaAs, 210nm of In 0.15 Al x3 GaAs, 210nm of In 0.2 Al x3 GaAs, 210nm of In 0.25 Al x3 GaAs, 210nm of In0.3 Al x3 GaAs, 210nm of In 0.36 Al x3 GaAs, 500nm of In 0.3 Al x3 GaAs, wherein 0.1 < x3 < 0.6. In this technical solution, by using the gradually changing component growth, the lattice can be gradually enlarged to the lattice of the bottom cell, and the material quality of the bottom cell growth is ensured.

[0016] Further, the lattice constant of the ohmic contact layer matches the lattice constant of the stress adjustment layer.

[0017] Compared with the prior art, the present application has the following beneficial effects: Since the substrate of the flip-chip has PI, Cu, Si and the like, and the electrode material has Au, Ge, Pd, Ag and the like, the stress generated when different substrates and electrode materials are combined with the epitaxial layer has a significant difference. Meanwhile, the lattice constant of the third junction cell layer in the flip-chip three-junction gallium arsenide solar cell is increased by 5%-7% compared with the first two junctions and the GaAs substrate. During the epitaxial growth process, the lattice expansion of the third junction will transmit compressive strain through the interface, resulting in elastic deformation of the first two junction cell layers. Therefore, the present application grows a stress adjustment layer with a small lattice constant on the third junction cell layer to cope with the tensile strain generated by the third junction cell layer. Not only can the stress adjustment layer compensate for the compressive strain generated by the third junction cell layer on the first two junction cell layers and the substrate, but also the introduced stress adjustment layer can freely adjust its lattice constant and thickness to compensate for the stress generated due to mismatch without affecting the functional layer structure, improve the warping of the epitaxial wafer, and help to improve the production yield and device reliability of the flip-chip, and broaden the application range. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a structural schematic diagram of a three-junction solar cell of the present application.

[0019] Label explanation in the schematic diagram: 1, GaAs substrate; 2, etching stop layer; 3, contact layer; 4, top cell; 5, first tunnel junction; 6, middle cell; 7, second tunnel junction; 8, strain buffer layer; 9, bottom cell; 10, stress adjustment layer; 11, ohmic contact layer. DETAILED DESCRIPTION

[0020] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. The description of the at least one example embodiment is merely illustrative in nature and not intended to be limiting on the application or its applications or uses. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0021] In the description of the present application, it should be understood that the terms "first", "second" and the like are used to distinguish the components, and do not have special meanings unless otherwise stated. Therefore, they cannot be understood as limiting the scope of the present application.

[0022] In the description of the present application, it should be understood that the terms such as "front", "back", "up", "down", "left", "right", "transverse", "vertical", "perpendicular", "horizontal", "top", "bottom" and the like indicate the orientation or positional relationship shown in the drawings, and are used only for the purpose of describing the present application and simplifying the description. Unless otherwise stated, these orientation terms do not indicate or imply that the device or element referred to must have a particular orientation or be constructed and operated in a particular orientation. Therefore, they cannot be understood as limiting the scope of the present application. The orientation terms "inner" and "outer" refer to the inner and outer contours of the components themselves.

[0023] Please refer to Figure 1 It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application, not the number, shape and size of the components during actual implementation. The shape, number and proportion of each component during actual implementation can be arbitrarily changed, and the layout form of the components can be more complex.

[0024] An embodiment of the present application provides a three-junction solar cell capable of adjusting stress, a structural schematic diagram of which is shown in Figure 1 The three-junction solar cell comprises, from bottom to top, a GaAs substrate 1, an etching stop layer 2, a contact layer 3, a top cell 4, a first tunnel junction 5, a middle cell 6, a second tunnel junction 7, a strain buffer layer 8, a bottom cell 9, a stress adjusting layer 10 and an ohmic contact layer 11.

[0025] In some specific embodiments, the etching stop layer material is one or a combination of GaInP, AlInP and AlGaInP.

[0026] In some embodiments, the material of the top cell is (Al)GaInP, with a band gap of 1.80eV-1.95eV; the material of the middle cell is (In)GaAs, with a band gap of 1.37eV-1.42eV; and the material of the bottom cell is In x2 GaAs, with a band gap of 0.90eV-1.1eV, 0.29≤x2<0.32; wherein the top cell and the middle cell are connected by a first tunnel junction, and the middle cell and the bottom cell are connected by a second tunnel junction.

[0027] In some embodiments, the first tunnel junction is N ++ GaInP / P ++ AlGaAs, wherein N ++ The dopant of GaInP is one or a combination of Te, Se, Si; P ++ The dopant of AlGaAs is one or a combination of Mg, Zn, C.

[0028] In some embodiments, the second tunnel junction is N ++ GaAs / P ++ GaAs, wherein N ++ The dopant of GaAs is one or a combination of Te, Se, Si; P ++ The dopant of GaAs is one or a combination of Mg, Zn, C.

[0029] In some embodiments, the stress adjustment layer is grown in a form of composition grading, with a lattice constant gradually changing from matching the bottom cell to a set lattice constant, from bottom to top: In x1 GaAs, In y1 GaAs, wherein 0.29≤x1<0.32, 0.23

[0030] In some embodiments, the material of the ohmic contact layer is In y1 GaAs, with a thickness of 200nm, wherein 0.23

[0031] Some embodiments of the present application provide a method for preparing a three-junction solar cell capable of adjusting stress, comprising the following steps: S1. On a GaAs substrate, a etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell and a second tunnel junction are grown in sequence; specifically, the growth is performed by using a MOCVD (metal organic chemical vapor deposition) process, wherein the material of the contact layer is GaAs, the material of the etching stop layer is one or a combination of GaInP, AlInP and AlGaInP, the material of the top cell is (Al)GaInP, and the band gap is 1.80eV-1.95eV; the first tunnel junction is N ++ GaInP / P ++ AlGaAs, wherein N ++ The dopant of the GaInP is one or a combination of Te, Se and Si; P ++ The dopant of the AlGaAs is one or a combination of Mg, Zn and C; the material of the middle cell is (In)GaAs, and the band gap is 1.37eV-1.42eV; the second tunnel junction is N ++ GaAs / P ++ GaAs, wherein N ++ The dopant of the GaAs is one or a combination of Te, Se and Si; P ++ The dopant of the GaAs is one or a combination of Mg, Zn and C.

[0032] S2. A strain buffer layer is grown on the second tunnel junction; specifically, 210nm of In 0.05 Al x3 GaAs, 210nm of In 0.1 Al x3 GaAs, 210nm of In 0.15 Al x3 GaAs, 210nm of In 0.2 Al x3 GaAs, 210nm of In 0.25 Al x3 GaAs, 210nm of In 0.3 Al x3 GaAs, 210nm of In 0.36 Al x3 GaAs, 500nm of In 0.3 Al x3 GaAs, wherein the doping concentration is greater than 1×10 18 / cm 3 , and the dopant is at least one of Te, Se and Si, and 0.1

[0033] S3. A bottom cell is grown on the strain buffer layer; specifically, the material of the bottom cell is In x2GaAs has a bandgap of 0.90 eV-1.1 eV and 0.29 ≤ x2 < 0.32.

[0034] S4. A stress-regulating layer is grown on the bottom cell; specifically, the stress-regulating layer adopts a compositional step transition, with the lattice constant transitioning from matching the bottom cell to a predetermined lattice constant, in the following order from bottom to top: In x1 GaAs, In y1 Composed of GaAs, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is at least one of Zn, Mg, and C, where 0.29 ≤ x1 < 0.32 and 0.23 < y1 ≤ 0.27. The warpage of the epitaxial wafer can be adjusted by changing the In composition and thickness of the stress-adjusting layer. This layer grows after the bottom cell has been fully grown, without affecting the crystal quality of the bottom cell material or its performance.

[0035] S5. An ohmic contact layer is grown on the stress-adjusting layer, specifically, the material of the ohmic contact layer is In. y1 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopant is at least one of Zn, Mg and C, and the In composition and stress-regulating layer are consistent to ensure lattice matching.

[0036] To further illustrate the present invention, a method for preparing a stress-adjustable triple-junction solar cell provided by the present invention will be described in detail below with reference to specific embodiments.

[0037] Example 1 A method for fabricating a stress-adjustable triple-junction solar cell specifically includes the following steps: Specifically, the following steps are included: S1. Using MOCVD technology, the etching stop layer GaInP, the contact layer GaAs, the top cell (Al)GaInP, and the first tunnel junction N are epitaxially grown sequentially on a GaAs substrate. ++ GaInP / P ++ AlGaAs, mid-cell (In)GaAs, second tunnel junction N ++ GaAs / P ++ GaAs; where N ++ The dopant for GaInP is Te; P ++ The dopants in AlGaAs are Mg and N. ++ The dopants in GaAs are Te and P. ++ The dopant in GaAs is Mg.

[0038] S2. 210 nm In atoms are sequentially grown on the second tunnel junction. 0.05 Al0.2 GaAs, 210 nm of In 0.1 Al 0.2 GaAs, 210 nm of In 0.15 Al 0.2 GaAs, 210 nm of In 0.2 Al 0.2 GaAs, 210 nm of In 0.25 Al 0.2 GaAs, 210 nm of In 0.3 Al 0.2 GaAs, 210 nm of In 0.36 Al 0.2 GaAs, 500 nm of In 0.3 Al 0.2 GaAs composition strain buffer layer, doping concentration is greater than 1 x 10 18 / cm 3 , and the dopant is Te.

[0039] S3. Growing a bottom cell In 0.3 GaAs on the strain buffer layer, and the band gap is 0.90 eV-1.1 eV.

[0040] S4. Growing a stress adjustment layer on the bottom cell, from bottom to top, sequentially: 300 nm of In 0.3 GaAs, 400 nm of In 0.25 GaAs composition, doping concentration is greater than 1 x 10 18 / cm 3 , and the dopant is Zn.

[0041] S5. Growing a 200 nm ohmic contact layer In 0.25 GaAs on the stress adjustment layer, doping concentration is greater than 2 x 10 18 / cm 3 , and the dopant is Zn.

[0042] Embodiment 2 A method for preparing a stress-adjustable three-junction solar cell, specifically comprising the following steps: Specifically comprising the following steps: S1. Using MOCVD process, epitaxially growing, on a GaAs substrate, in sequence, an etching stop layer AlInP, a contact layer GaAs, a top cell (Al)GaInP, a first tunnel junction N ++ GaInP / P ++ AlGaAs, a middle cell (In)GaAs, a second tunnel junction N ++ GaAs / P ++ GaAs; wherein, N ++The dopant for GaInP is a combination of Se, Si; P ++ The dopant for AlGaAs is a combination of Zn, C; N ++ The dopant for GaAs is a combination of Se, Si; P ++ The dopant for GaAs is a combination of Zn, C.

[0043] S2. On the second tunnel junction, 210 nm of In 0.05 Al 0.6 GaAs, 210 nm of In 0.1 Al 0.6 GaAs, 210 nm of In 0.15 Al 0.6 GaAs, 210 nm of In 0.2 Al 0.6 GaAs, 210 nm of In 0.25 Al 0.6 GaAs, 210 nm of In 0.3 Al 0.6 GaAs, 210 nm of In 0.36 Al 0.6 GaAs, 500 nm of In 0.3 Al 0.6 GaAs, 500 nm of In 18 / cm 3 , with a dopant of Se and Si.

[0044] S3. On the strain buffer layer, grow a bottom cell In 0.31 GaAs with a band gap of 0.90 eV - 1.1 eV.

[0045] S4. On the bottom cell, grow a stress adjustment layer, from bottom to top: 300 nm of In 0.31 GaAs, 400 nm of In 0.26 GaAs, with a doping concentration greater than 1 x 10 18 / cm 3 , with a dopant of Mg and C.

[0046] S5. On the stress adjustment layer, grow an ohmic contact layer of 200 nm of In 0.26 GaAs, with a doping concentration greater than 2 x 10 18 / cm 3 , with a dopant of Mg and C.

[0047] In summary, the application grows a stress adjustment layer with small lattice constant on the bottom cell layer, which not only compensates the compressive strain generated by the bottom cell layer to the front two-junction cell layer and the substrate, but also freely adjusts the lattice constant and thickness of the functional layer structure to compensate the stress generated by mismatch, adjusts the warping of the epitaxial wafer, and helps to improve the production yield and device reliability of the flip-chip battery.

[0048] Finally, it should be emphasized that the above description is only the preferred embodiment of the application and is not intended to limit the application. For those skilled in the art, the application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A stress-adjustable triple-junction solar cell, characterized by The three-junction solar cell is sequentially GaAs substrate, etching stop layer, contact layer, top cell, first tunnel junction, middle cell, second tunnel junction, strain buffer layer, bottom cell, stress adjustment layer and ohmic contact layer from bottom to top. The stress adjustment layer is grown in a form of component step change, and its lattice constant is changed from matching the bottom cell to a set lattice constant.

2. The stress-adjustable triple-junction solar cell according to claim 1, wherein The stress adjustment layer is sequentially from bottom to top: In x1 GaAs, In y1 GaAs, wherein 0.29≤x1<0.32, 0.23 y1≤0.

27.

3. The stress-adjustable triple-junction solar cell according to claim 1, wherein The material of the etching stop layer is one or a combination of GaInP, AlInP and AlGaInP, and the material of the contact layer is GaAs.

4. The stress-adjustable triple-junction solar cell according to claim 1, wherein The material of the top cell is (Al)GaInP, and the band gap is 1.80eV-1.95eV; the material of the middle cell is (In)GaAs, and the band gap is 1.37eV-1.42eV; the material of the bottom cell is In x2 GaAs, and the band gap is 0.90eV-1.1eV, 0.29≤x2<0.

32.

5. The stress-adjustable triple-junction solar cell according to claim 1, wherein The first tunnel junction is N ++ GaInP / P ++ AlGaAs structure, wherein, N ++ The dopant of GaInP is one or a combination of more than one of Te, Se, Si; P ++ The dopant of AlGaAs is one or a combination of more than one of Mg, Zn, C.

6. The stress-adjustable triple-junction solar cell according to claim 1, wherein The second tunnel junction is N ++ GaAs / P ++ GaAs structure, wherein, N ++ The dopant of GaAs is one or a combination of more than one of Te, Se, Si; P ++ The dopant of GaAs is one or a combination of more than one of Mg, Zn, C.

7. The stress-adjustable triple-junction solar cell according to claim 1, wherein The material of the strain buffer layer is InAlGaAs, the doping concentration is greater than 1 x 1018 / cm3, and the dopant is at least one of Te, Se and Si; the material of the ohmic contact layer is InGaAs, the doping concentration is greater than 2 x 1018 / cm3, the dopant is at least one of Zn, Mg and C, and the In component is consistent with the stress adjustment layer. 18 3 y1 18 3 The material of the strain buffer layer is InAlGaAs, the doping concentration is greater than 1 x 1018 / cm3, and the dopant is at least one of Te, Se and Si; the material of the ohmic contact layer is InGaAs, the doping concentration is greater than 2 x 1018 / cm3, the dopant is at least one of Zn, Mg and C, and the In component is consistent with the stress adjustment layer.​​​​ 8. The method of claim 1-7, wherein the method is capable of adjusting stress of a triple-junction solar cell, characterized in that, Specifically, the method comprises the following steps: S1. On a GaAs substrate, an etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell and a second tunnel junction are sequentially grown by epitaxy; S2. A strain buffer layer is grown on the second tunnel junction; S3. A bottom cell is grown on the strain buffer layer; S4. A stress adjustment layer is grown on the bottom cell; S5. An ohmic contact layer is grown on the stress adjustment layer.

9. The method of claim 8, wherein the method further comprises: S2, the strain buffer layer comprises in sequence 210 nm of In 0.05 Al x3 GaAs, 210 nm of In 0.1 Al x3 GaAs, 210 nm of In 0.15 Al x3 GaAs, 210 nm of In 0.2 Al x3 GaAs, 210 nm of In 0.25 Al x3 GaAs, 210 nm of In 0.3 Al x3 GaAs, 210 nm of In 0.36 Al x3 GaAs, 500 nm of In 0.3 Al x3 GaAs, where 0.1 < x3≤ 0.

6.

10. The method of claim 8, wherein the method further comprises: The lattice constant of the ohmic contact layer matches the lattice constant of the stress adjustment layer.

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