Three-dimensional memory device including dummy via cavity and method of manufacturing same

Abstract

A semiconductor structure includes: a first layer alternating stack of first insulating layers and first conductive layers; a second layer alternating stack of a second insulating layer and a second conductive layer, the second layer alternating stack overlying the first layer alternating stack; a memory opening extending vertically through the first layer alternating stack and the second layer alternating stack; a memory opening filling structure in the memory opening and including a memory film and a vertical semiconductor channel; a first contact via structure in contact with one of the first conductive layers; a first layer of tubular dielectric spacer, the first layer of tubular dielectric spacer including a first inner sidewall contacting the first contact via structure and contacting each of the first conductive layers overlying the one of the first conductive layers; and a first layer pillar structure extending vertically through each of the first layer conductive layers, and having a top surface coplanar with a topmost surface of the alternately stacked first layers.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of the entire contents of U.S. Nonprovisional Application No. 18 / 495,534, filed October 26, 2023, with the U.S. Patent and Trademark Office, entitled “THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUMMY VIA CAVITIES AND METHOD FORMAKINGSAME,” which is incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more particularly to three-dimensional memory devices including virtual via cavities and methods for manufacturing the same. Background Technology

[0004] A three-dimensional vertical NAND string with one bit per cell is disclosed in the article entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell” by T. Endoh et al. (2001), pages 33-36. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising: a first-tier alternating stack of first-tier insulating layers and first-tier conductive layers; a second-tier alternating stack of second-tier insulating layers and second-tier conductive layers overlying the first-tier alternating stack; a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack; a memory opening fill structure located in the memory opening and comprising a memory film and a vertical semiconductor channel; a first contact via structure contacting one of the first-tier conductive layers; a first-tier tubular dielectric spacer comprising a first inner sidewall contacting a first cylindrical surface segment of the first contact via structure, and comprising a first outer sidewall contacting each of the first-tier conductive layers overlying the one of the first-tier conductive layers; a second-tier tubular dielectric spacer comprising a second inner sidewall contacting a second cylindrical surface segment of the first contact via structure, and comprising a second outer sidewall contacting each of the second-tier conductive layers; a first-tier pillar structure vertically extending through each of the first-tier conductive layers in the first-tier alternating stack, and having a top surface coplanar with a topmost surface of the first-tier alternating stack; and an additional first-tier tubular dielectric spacer laterally surrounding the first-tier pillar structure, and having a same material composition and a same lateral thickness as the first-tier tubular dielectric spacer.

[0006] According to another aspect of the disclosure, a method of forming a semiconductor structure is provided. The method includes forming a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers over a substrate; forming first-tier sacrificial memory opening fill structures extending through the first-tier alternating stack; forming first-tier pillar structures in the first-tier alternating stack, wherein the first-tier pillar structures include first-type first-tier pillar structures that do not extend through a bottommost first-tier sacrificial material layer within the first-tier alternating stack and second-type first-tier pillar structures that extend through each first-tier sacrificial material layer within the first-tier alternating stack; forming a second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers over the first-tier alternating stack; forming second-tier sacrificial memory opening fill structures extending through the second-tier alternating stack; forming second-tier pillar structures in the second-tier alternating stack, wherein the second-tier pillar structures include first-type second-tier pillar structures formed on top surfaces of the first-type first-tier pillar structures and second-type second-tier pillar structures that do not extend through a bottommost second-tier sacrificial material layer within the second-tier alternating stack; replacing the second-tier sacrificial memory opening fill structures and the second-tier sacrificial memory opening fill structures with memory opening fill structures including vertical semiconductor channels and memory films; replacing the first-tier sacrificial material layers and the second-tier sacrificial material layers with first-tier conductive layers and second-tier conductive layers, respectively; replacing the first-type second-tier pillar structures and the first-type first-tier pillar structures with first-contact via structures contacting top surfaces of one of the first-tier conductive layers; and replacing the second-type second-tier pillar structures with second-contact via structures. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure for forming a memory die after forming a block layer insulating layer, an in-process source-level material layer, and a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers over a carrier substrate according to an embodiment of the disclosure.

[0008] Figure 2A is a schematic vertical cross-sectional view of an exemplary structure after forming first-tier memory openings and first-tier support openings according to an embodiment of the disclosure.

[0009] Figure 2B is Figure 2A a top-down view of the exemplary structure of Figure 2A the cutting plane of the vertical cross-sectional view of

[0010] Figure 3A is a schematic vertical cross-sectional view of an exemplary structure after forming first-tier sacrificial opening fill structures according to an embodiment of the disclosure.

[0011] Figure 3B isFigure 3A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 3A The cutting plane of the vertical cross-section.

[0012] Figure 4A This is a schematic vertical cross-sectional view of an exemplary structure following the formation of a patterned hard mask layer and after the initial anisotropic etching process, according to an embodiment of the present disclosure.

[0013] Figure 4B yes Figure 4A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 4A The cutting plane of the vertical cross-section.

[0014] Figure 5 This is a schematic vertical cross-sectional view of an exemplary structure after applying and patterning a first photoresist layer and performing a first anisotropic etching process, according to an embodiment of the present disclosure.

[0015] Figure 6 This is a schematic vertical cross-sectional view of an exemplary structure after applying and patterning a second photoresist layer and performing a second anisotropic etching process, according to an embodiment of the present disclosure.

[0016] Figure 7 This is a schematic vertical cross-sectional view of an exemplary structure after applying and patterning a Nth photoresist layer and performing a Nth anisotropic etching process, according to an embodiment of this disclosure.

[0017] Figure 8 This is a schematic vertical cross-sectional view of an exemplary structure after applying and patterning a terminal photoresist layer and performing a terminal anisotropic etching process according to an embodiment of the present disclosure.

[0018] Figure 9 This is a schematic vertical cross-sectional view of an exemplary structure after the removal of the final photoresist layer, according to an embodiment of this disclosure.

[0019] Figure 10 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first layer of tubular dielectric spacers, according to an embodiment of the present disclosure.

[0020] Figure 11A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first-layer column structure, according to an embodiment of the present disclosure.

[0021] Figure 11B yes Figure 11A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 11A The cutting plane of the vertical cross-section.

[0022] Figure 12 is a schematic vertical cross-sectional view of an exemplary structure after forming a second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers in accordance with an embodiment of the present disclosure.

[0023] Figure 13 is a schematic vertical cross-sectional view of an exemplary structure after forming second-tier sacrificial opening fill structures in accordance with an embodiment of the present disclosure.

[0024] Figure 14A is a schematic vertical cross-sectional view of an exemplary structure after forming second-tier tubular dielectric spacers and second-tier pillar structures in accordance with an embodiment of the present disclosure.

[0025] Figure 14B is a top-down view of the exemplary structure of Figure 14A is a top-down view of the exemplary structure of Figure 14A is a cutting plane of the vertical cross-sectional view of

[0026] Figure 15 is a schematic vertical cross-sectional view of an exemplary structure after forming a third-tier alternating stack of third-tier insulating layers and third-tier sacrificial material layers in accordance with an embodiment of the present disclosure.

[0027] Figure 16 is a schematic vertical cross-sectional view of an exemplary structure after forming third-tier sacrificial opening fill structures in accordance with an embodiment of the present disclosure.

[0028] Figure 17A is a schematic vertical cross-sectional view of an exemplary structure after forming third-tier tubular dielectric spacers and third-tier pillar structures in accordance with an embodiment of the present disclosure.

[0029] Figure 17B is a top-down view of the exemplary structure of Figure 17A is a top-down view of the exemplary structure of Figure 17A is a cutting plane of the vertical cross-sectional view of

[0030] Figure 18A to 18D is a sequential vertical cross-sectional view of a region around a multi-tier memory opening during formation of a memory opening fill structure in accordance with an embodiment of the present disclosure.

[0031] Figure 19A is a vertical cross-sectional view of an exemplary structure after forming a memory opening fill structure and support pillar structures in accordance with an embodiment of the present disclosure.

[0032] Figure 19B is a top-down view of the exemplary structure of Figure 19A is a top-down view of the exemplary structure of Figure 19A is a cutting plane of the vertical cross-sectional view of

[0033] Figure 20A is a vertical cross-sectional view of an exemplary structure after formation of a contact level dielectric layer and lateral isolation trench in accordance with an embodiment of the present disclosure.

[0034] Figure 20B is a top-down view of the exemplary structure of Figure 20A . The hinged vertical plane A-A' is the cutting plane of the vertical cross-sectional view of Figure 20A .

[0035] Figure 21A is a vertical cross-sectional view of an exemplary structure after formation of a source cavity in accordance with an embodiment of the present disclosure.

[0036] Figure 21B is a top-down view of the exemplary structure of Figure 22A . The hinged vertical plane A-A' is the cutting plane of the vertical cross-sectional view of .

[0037] Figure 22B is a vertical cross-sectional view of an exemplary structure after formation of a source contact layer in accordance with an embodiment of the present disclosure.

[0038] Figure 23 is a top-down view of the exemplary structure of Figure 24 . The hinged vertical plane A-A' is the cutting plane of the vertical cross-sectional view of .

[0039] Figure 25A is a vertical cross-sectional view of an exemplary structure after formation of a laterally extending cavity in accordance with an embodiment of the present disclosure.

[0040] Figure 25B is a vertical cross-sectional view of an exemplary structure after formation of a layer conductive layer in accordance with an embodiment of the present disclosure.

[0041] Figure 26A is a vertical cross-sectional view of an exemplary structure after formation of an isolation trench fill structure in accordance with an embodiment of the present disclosure.

[0042] Figure 27A is a top-down view of the exemplary structure of Figure 27B . The hinged vertical plane A-A' is the cutting plane of the vertical cross-sectional view of Figure 28A .

[0043] Figure 29A is a vertical cross-sectional view of an exemplary structure after formation of a connection via cavity in accordance with an embodiment of the present disclosure.

[0044] Figure 29B is a top-down view of the exemplary structure of Figure 30 . The hinged vertical plane A-A' is the cutting plane of the vertical cross-sectional view of Figure 31 .

[0045] Figure 32 is a vertical cross-sectional view of the exemplary structure after forming a layer contact via cavity according to an embodiment of the disclosure.

[0046] Figure 1 is a top-down view of the exemplary structure of Figure 31 is a cutting plane of the vertical cross-sectional view of Figure 32

[0047] Figure 2A is a vertical cross-sectional view of the exemplary structure after forming a drain contact via cavity according to an embodiment of the disclosure.

[0048] Figure 2B is a top-down view of the exemplary structure of Figure 3A is a cutting plane of the vertical cross-sectional view of Figure 3B

[0049] Figure 4A is a vertical cross-sectional view of the exemplary structure after forming a layer contact via structure and a drain contact via structure according to an embodiment of the disclosure.

[0050] Figure 4B is a top-down view of the exemplary structure of Figure 5 is a cutting plane of the vertical cross-sectional view of Figure 6

[0051] Figure 7 is a vertical cross-sectional view of the exemplary structure after forming a memory-side dielectric material layer and a memory-side metal interconnect structure according to an embodiment of the disclosure.

[0052] Figure 5 is a vertical cross-sectional view of the exemplary structure after attaching a logic die to a memory die according to an embodiment of the disclosure.

[0053] Figure 5 is a vertical cross-sectional view of the exemplary structure after removing a carrier substrate according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0054] Embodiments of the disclosure relate to a three-dimensional memory device including dummy via cavities for providing a uniform etch pattern factor during fabrication and methods of fabricating the same, aspects of which are now described in detail. Embodiments of the disclosure can be used to form semiconductor devices, such as three-dimensional memory devices including multiple memory strings.

[0055] ​​​The drawings are not drawn to scale. Multiple instances of an element can be duplicated in the drawings where multiple instances are illustrative of a single instance of that element. Numerical designations, such as“first,”“second,” and“third,” are used to identify similar elements, and different numerical designations are used to identify different elements. The term“at least one” element means all possible combinations, including individual elements and mixtures thereof.

[0056] Like reference numbers refer to like elements throughout. Unless explicitly stated otherwise, elements having“contact” between them are in direct contact providing an edge or surface shared by the elements. Two or more elements are“separated” or“between” each other if they are not in direct contact with each other or with each other. As used herein, a first element that is“on” a second element can be on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is“directly on” a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is“electrically connected to” a second element if there is an electrically conductive path between the first element and the second element composed of at least one electrically conductive material. As used herein,“prototype” structure or“in-process” structure refers to a transient structure that is subsequently modified in shape or composition of at least one of its components.

[0057] As used herein,“layer” refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or it can be smaller than the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than a thickness of a first continuous structure. For example, a layer can be between any pair of horizontal planes that are between or at a top surface and a bottom surface of a first continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, thereabove, and / or therebelow.

[0058] As used herein, first and second surfaces are“vertically coincident” with each other if a second surface overlies or underlies a first surface and there is a vertical plane or a substantially vertical plane that includes the first and second surfaces. A substantially vertical plane is a plane that extends linearly along a direction that is offset from a vertical direction by an angle that is less than 5 degrees. A vertical or substantially vertical plane is straight along a vertical or substantially vertical direction, and can or can not include a curvature along a direction that is perpendicular to the vertical or substantially vertical direction.

[0059] As used herein, a“memory level” or“memory array level” refers to a level corresponding to a general region between a first horizontal plane of a topmost surface of an array comprising memory elements (i.e., a plane parallel to a top surface of a substrate) and a second horizontal plane of a bottommost surface of the array comprising memory elements. As used herein, a“through-stack” element refers to an element that extends vertically through a memory level.

[0060] As used herein, a“semiconductor material” refers to a material having electrical conductivity in a range of 1.0 x 10 -5 S / m to 1.0 x 10 7 S / m. As used herein, an“electrical dopant” refers to a p-type dopant that adds holes to a valence band within a band structure, or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, a“conductive material” refers to a material having electrical conductivity greater than 1.0 x 10 5 S / m. As used herein, an“insulator material” or“dielectric material” refers to a material having electrical conductivity less than 1.0 x 10 -5 S / m. As used herein, a“heavily doped semiconductor material” refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material formed as a crystalline material or converted to a crystalline material by an anneal process (e.g., from an initial amorphous state), i.e., to provide electrical conductivity greater than 1.0 x 10 5 S / m. A“doped semiconductor material” can be a heavily doped semiconductor material, or can be a semiconductor material including electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration providing electrical conductivity in a range of 1.0 x 10 -5 S / m to 1.0 x 10 7 S / m. An“intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a“metallic material” refers to a conductive material including at least one metallic element therein. All measurements of electrical conductivity are made under standard conditions.

[0061] In general, a semiconductor package (or“package”) refers to a monolithic semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include a semiconductor chip (or“chip”) or multiple semiconductor chips that are fully bonded, such as through flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or“die”) or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands concurrently as the total number of dies within it. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there can be some limitations. In the case where a die is a memory die (i.e., a die that includes memory elements), a concurrent read operation, a concurrent write operation, or a concurrent erase operation can be performed in each plane within the same memory die. In a memory die, each plane contains a plurality of memory blocks (or“blocks”), which are the smallest unit that can be erased in a single erase operation. Each memory block contains a plurality of pages, which are the smallest unit that can be selected for programming. Pages are also the smallest unit that can be selected for a read operation.

[0062] Reference is made to Figure 6 FIG. 1 illustrates an exemplary structure in accordance with embodiments of the present disclosure. The exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can be selectively removed with respect to the material of the overlying materials subsequently formed. Alternatively, the substrate 9 can include a silicon wafer that remains in the final memory device. In this case, the peripheral circuitry (e.g., driver circuitry) can be formed on the surface of the substrate 9, and the bonding of a separate logic die including the peripheral circuitry described below with respect to FIG. 2 can be omitted. Figure 5

[0063] An optional insulating material layer can be formed on the top surface of the carrier substrate 9 or over the peripheral circuitry, if present. The insulating material layer can subsequently serve as a barrier material layer for optional processes to remove the carrier substrate 9, and is referred to herein as a barrier layer insulating layer 106. In one embodiment, the barrier layer insulating layer 106 includes a dielectric material, such as an undoped silicate glass (i.e., silicon oxide), a doped silicate glass, or silicon nitride. The thickness of the barrier layer insulating layer 106 can be in a range from 50 nm to 600 nm, such as from 100 nm to 300 nm, although lesser and greater thicknesses can also be employed.

[0064] ​An optional in-process source-level material layer 110' can be formed over the blocking layer insulating layer 106. The in-process source-level material layer 110' can include various layers that are later modified to form a source-level material layer. When formed, the source-level material layer includes a source contact layer that serves as a common source region for vertical field effect transistors of a three-dimensional memory device. In one embodiment, the in-process source-level material layer 110' can include, from bottom to top, a lower source-level semiconductor layer 112, an optional lower sacrificial liner 103, a source-level sacrificial layer 104, an optional upper sacrificial liner 105, and an upper source-level semiconductor layer 116. Alternatively, the source-level material layer 110' can be omitted, and a source region can be formed in the substrate 9 after the illustrated carrier substrate 9 is removed. Figure 6 The top source contact layer is formed after the illustrated carrier substrate 9 is removed. Alternatively, if the substrate 9 includes a silicon wafer, a source region can be formed in the substrate 9 if the source-level material layer 110' is omitted.

[0065] The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 can include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 can be opposite to the conductivity of the vertical semiconductor channel to be subsequently formed. For example, if the vertical semiconductor channel to be subsequently formed has a first conductivity type of doping, the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 have a second conductivity type of doping that is opposite to the first conductivity type. The thickness of each of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 can be in a range from 10 nm to 300 nm, such as from 20 nm to 150 nm, although lesser and greater thicknesses can also be used.

[0066] The source-level sacrificial layer 104 includes a sacrificial material that can be selectively removed relative to the lower sacrificial liner 103 (or relative to the lower source-level semiconductor layer 112) and the upper sacrificial liner 105 (or relative to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 can include a semiconductor material, such as undoped amorphous silicon or silicon germanium with a germanium atomic concentration greater than 20%. The thickness of the source-level sacrificial layer 104 can be in a range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses can also be used.

[0067] The lower sacrificial liner 103 (if present) and the upper sacrificial liner 105 (if present) include a material that can be used as an etch stop material during removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in a range from 2 nm to 30 nm, although lesser and greater thicknesses can also be used.

[0068] A first-tier alternating stack of first-tier insulative layers 132 and first-tier spacer material layers can be formed over the in-process source-level material layer 110’. In one embodiment, the first-tier spacer material layers can include first-tier sacrificial material layers 142. In this case, a first-tier alternating stack of first-tier insulative layers 132 and first-tier sacrificial material layers 142 (132, 142) can be formed over the in-process source-level material layer 110’. The first-tier insulative layers 132 are a first subset of the insulative layers 32, and the first-tier sacrificial material layers 142 are a first subset of the sacrificial material layers 42. The first-tier insulative layers 132 include an insulative material such as an undoped silicate glass (i.e., silicon oxide) or a doped silicate glass, and the first-tier sacrificial material layers 142 include a sacrificial material such as silicon nitride or silicon germanium. In one embodiment, the first-tier insulative layers 132 can include silicon oxide layers, and the first-tier sacrificial material layers 142 can include silicon nitride layers. The first-tier alternating stack (132, 142) can include a number of repetitions of a unit layer stack including a first-tier insulative layer 132 and a first-tier sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first-tier alternating stack (132, 142) can be, for example, in a range from 8 to 1,024, such as from 32 to 256, although fewer and greater numbers of repetitions can also be employed.

[0069] A thickness of each of the first-tier insulative layers 132 can be in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses can also be employed. A thickness of each of the first-tier sacrificial material layers 142 can be in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0070] Exemplary structures include at least one memory array region 100 and at least one contact region area 300. While two memory array regions 100 are shown, it is to be understood that there can be only one memory array region 100 per memory plane located between two contact region areas 300. Alternatively, there can be more than two memory array regions 100 per memory plane. The memory array region 100 is a region in which a three-dimensional array of memory elements is to be subsequently formed. The contact region area 300 is a region in which layer contact via structures of contact word lines and select gate electrodes are to be subsequently formed. According to one aspect of the disclosure, a multi-layer structure including a plurality of layer structures stacked vertically is employed to form a three-dimensional memory array. The plurality of layer structures can include at least a first layer structure and a second layer structure, and can optionally include a third layer structure and additional upper layer structures. The contact region area 300 can include two or more contact regions, such as a first contact region 301 in which first contact via structures provide electrical connections to first layer conductive layers in the first layer structure, a second contact region 302 in which second contact via structures provide electrical connections to second layer conductive layers in the second layer structure, and a third contact region 303 in which third contact via structures provide electrical connections to third layer conductive layers in the third layer structure, etc. While three contact regions (301, 302, 303) are illustrated in the contact region area 300, there can be two or four or more contact regions in each contact region area 300.

[0071] While embodiments are described in which the first spacer material layer is formed as a first layer of sacrificial material 142, in alternative embodiments, the first spacer material layer can be formed as a first layer of conductive material. In general, the spacer material layers formed in any alternating stack of insulating and spacer material layers of the disclosure can be formed as conductive layers or can be subsequently at least partially replaced with conductive layers.

[0072] Referring to Figure 5 and Figure 6A first etch mask layer (not shown) can be formed over the first-tier alternating stack (132, 142) and can be lithographically patterned to form various openings therein. A first anisotropic etch process can be performed to transfer a pattern of the openings in the first etch mask layer through the first-tier alternating stack (132, 142). Various openings can be formed through the first-tier alternating stack (132, 142). The various openings can include first-tier memory openings 149 formed in the memory array region 100 and first-tier support openings 119 formed in the contact region area 300. Each of the first-tier memory openings 149 and the first-tier support openings 119 can vertically extend through the first-tier alternating stack (132, 142) and into the in-process source-level material layer 110’. In one embodiment, a bottom surface of the first-tier memory openings 149 and the first-tier support openings 119 can be formed within the lower source-level semiconductor layer 112 or at an interface between the lower source-level semiconductor layer and the blocking layer insulative layer 106.

[0073] The first-tier memory openings 149 can have a maximum diameter in a range from 50 nm to 400 nm, such as from 70 nm to 300 nm, although smaller and larger maximum diameters can be employed. The first-tier support openings 119 can have a maximum diameter in a range from 50 nm to 400 nm, such as from 70 nm to 300 nm, although smaller and larger maximum diameters can be employed. Each of the first-tier memory openings 149 and the first-tier support openings 119 can have tapered sidewalls having a taper angle in a range from 0.01 degrees to 3 degrees, such as from 0.1 degrees to 1.5 degrees, although smaller and larger taper angles can also be employed. Thus, each of the first-tier memory openings 149 and the first-tier support openings 119 can have a greater lateral extent (such as diameter) at a top portion than at a bottom portion. Each of the first-tier memory openings 149 and the first-tier support openings 119 can have a vertical cross-sectional profile that includes a first tapered surface extending through the first-tier alternating stack (132, 142).

[0074] In one embodiment, the at least one memory array region 100 can be laterally spaced apart from the contact region area 300 along a first horizontal direction hd1. The first-tier memory openings 149 can include a plurality of rows of first-tier memory openings 149 arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd2. A plurality of clusters of the first-tier memory openings 149 can be formed in the memory array region 100, each cluster including a respective two-dimensional periodic array of the first-tier memory openings 149. The clusters of the first-tier memory openings 149 can be laterally spaced apart along the second horizontal direction hd2.

[0075] Referring to Figure 5 andFigure 6 A first sacrificial fill material can be deposited in the first-tier memory openings 149 and the first-tier support openings 119. The first sacrificial fill material can include a semiconductor material (such as amorphous silicon, polysilicon, silicon germanium, etc.), a carbon-based material including greater than 80 atomic percent carbon atoms (such as amorphous carbon or diamond-like carbon), or a polymer material.

[0076] A planarization process can be performed to remove portions of the first sacrificial fill material from above a horizontal plane including a top surface of the first-tier alternating stack (132, 142). The planarization process can be stopped so that each remaining portion of the first sacrificial fill material has a top surface at or near the horizontal plane including a top surface of the first-tier alternating stack (132, 142). The planarization process can include a recess etch process and / or a chemical mechanical polishing process. The remaining portions of the first sacrificial fill material filling the first-tier memory openings 149 and the first-tier support openings 119 constitute first-tier sacrificial opening fill structures (148, 118). The first-tier sacrificial opening fill structures (148, 118) include first-tier sacrificial memory opening fill structures 148 formed in the first-tier memory openings 149 and first-tier sacrificial support opening fill structures 118 formed in the first-tier support openings 119.

[0077] Referring to Figure 5 and Figure 6 A patterned hardmask layer 121 can be formed over the first-tier alternating stack (132, 142). The patterned hardmask layer 121 can include any etch mask material that can be subjected to a subsequent ashing process for removing the patterned photoresist material layer. The patterned hardmask layer 121 can include a dielectric metal oxide material, a metallic material (such as a metal nitride material), or a semiconductor material (such as amorphous silicon in the case where the first-tier sacrificial opening fill structures (148, 118) include a carbon-based material or a polymer material). The patterned hardmask layer 121 can be formed by depositing a blanket (unpatterned) hardmask material layer, forming a photoresist material layer (not illustrated) over the blanket hardmask material layer, lithographically patterning the photoresist material layer to form openings in areas where via cavities are to be subsequently formed, and transferring the pattern in the patterned photoresist layer through the blanket hardmask material layer by performing an anisotropic etch process. An array of openings (122, 122D) are formed through the patterned hardmask layer 121. The photoresist material can be subsequently removed.

[0078] The openings (122, 122D) in the patterned hardmask layer 121 can be formed across each of the contact regions (301, 302, 303) with the same or similar pattern factor. As used herein, “pattern factor” refers to the ratio of the locally calculated area to be etched (such as the area of the openings through the patterned hardmask layer 121) to the total area (which includes the area of the openings and the area of the patterned hardmask layer 121). As used herein, “locally calculated” refers to an area with a radius of about 10 times the lateral dimension of the relevant geometric feature, such as the diameter of each opening in the patterned hardmask layer 121. In one embodiment, first contact via structures to contact the first conductive layers can be subsequently formed only in the first contact region 301. Accordingly, the openings 122 are formed in the patterned hardmask layer 121 in locations where the first contact via structures are to be subsequently formed. However, additional dummy openings 122D are formed in the patterned hardmask layer 121 in the second contact region 302 and the third contact region 303. In one embodiment, the dummy openings 122D have a pattern for second contact via structures to contact the second conductive layers in the second layer structure and a pattern for third contact via structures to contact the third conductive layers in the third layer structure. In general, the number of conductive layers to be formed for each layer structure can be approximately the same, and each area of the contact regions (301, 302, 303) can be approximately the same. In this case, the pattern factor for the openings (122, 122D) in the patterned hardmask layer 121 can be approximately the same across all of the contact regions (301, 302, 303).

[0079] An anisotropic etch process (which is also referred to as an initial anisotropic etch process) can be performed to etch through the topmost first layer insulating layer 132 beneath the openings (122, 122D) in the patterned hardmask layer 121. First layer via cavities 891 and first layer dummy cavities 891D can be formed through the topmost first layer insulating layer 132.

[0080] Referring to Figure 6 , Figure 6 and Figure 5 , a series of bulk-level photoresist layers (171, 172, 177) in combination with a series of anisotropic etch processes can be subsequently employed to sequentially uncover respective subsets of the openings in the patterned hardmask layer 121 in the first contact region 301 without uncovering the second contact region 302 or the third contact region 303, and extend the pattern of the openings (122, 122D) in the patterned hardmask layer 121 through a respective number of pairs of first layer insulating layers 132 and first layer sacrificial material layers 142.

[0081] For example, about half of the openings 122 through the patterned hardmask layer 121 in the first contact region 301 can be uncovered by the first bulk-level photoresist layer 171, and the first layer sacrificial material layers 142 beneath the uncovered openings 122 can be removed by performing an anisotropic etch process as described above with reference to FIGS. 3A-3C. The second bulk-level photoresist layer 172 can then be applied to cover the remaining openings 122 in the first contact region 301, and the second layer sacrificial material layers 142 beneath the covered openings 122 can be removed by performing an anisotropic etch process as described above with reference to FIGS. 3A-3C. Figure 6The illustrated first anisotropic etch process etches a first layer of insulating material 132 and a first layer of sacrificial material 142 under the unmasked openings (122, 122D) in the patterned hardmask layer 121.

[0082] The entire set of openings (122, 122D) in the patterned hardmask layer 121 that are not covered by the first block-level photoresist layer 171 includes about 50% of the openings 122 in the patterned hardmask layer 121 in the first contact region 301, 100% of the openings 122D in the patterned hardmask layer 121 in the second contact region 302, and 100% of the openings 122D in the patterned hardmask layer 121 in the third contact region 303. Thus, the total etch area includes about 5 / 6 of the area of all of the openings (122, 122D) in the patterned hardmask layer 121, and the first anisotropic etch process is performed with a high pattern factor corresponding to such etch area. A first subset of the first layer via cavities 891 extends a depth equal to the sum of the thickness of the first layer of insulating material 132 and the thickness of the first layer of sacrificial material 142, while a second subset of the first layer via cavities 891 does not extend in depth. Each dummy first layer via cavity 891D located in the second contact region 302 and the third contact region 303 can extend vertically during the first anisotropic etch process. A subset of the dummy first layer via cavities 891D formed in the second contact region 302 and the third contact region 303 are used as dummy via cavities to increase the pattern factor during the first anisotropic etch process. By increasing the pattern factor, the end-point detection of the first anisotropic etch process is increased because the area of the sacrificial material layer 142 exposed in the combination of the first layer via cavities 891 and the dummy first layer via cavities 891D is larger than the area of the sacrificial material layer 142 exposed in the first layer via cavities 891 alone. Subsequently, the first block-level photoresist layer 171 can be removed after the illustrated processing steps. Figure 7 The first block-level photoresist layer 171 is removed after the illustrated processing steps.

[0083] Subsequently, about half of all of the openings 122 in the patterned hardmask layer 121 in the first contact region 301 can be covered by the second block-level photoresist layer 172, and the second anisotropic etch process can be performed as described above with respect to the first anisotropic etch process. Figure 8 The illustrated second anisotropic etch process etches two first layers of insulating material 132 and two first layers of sacrificial material 142 under the unmasked openings in the patterned hardmask layer 121. The first subset of the openings 122 covered by the first block-level photoresist layer 171 at the processing step of Figure 9 The first subset of the openings 122 covered by the first block-level photoresist layer 171 at the processing step of Figure 10 The second subset of the openings 122 covered by the first block-level photoresist layer 171 at the processing step of Figure 11A The second subset of the openings 122 covered by the first block-level photoresist layer 171 at the processing step of Figure 11B The second subset of the openings 122 covered by the first block-level photoresist layer 171 at the processing step ofFigure 12 the first subset of openings 122 not covered by the first bulk photoresist layer 171 at the processing step of Figure 13 the second subset of openings 122 not covered by the first bulk photoresist layer 171 at the processing step of Figure 3A the second subset of openings 122 not covered by the first bulk photoresist layer 171 at the processing step of Figure 3B the second subset of openings 122 not covered by the first bulk photoresist layer 171 at the processing step of

[0084] The entire set of openings (122, 122D) in the patterned hardmask layer 121 not covered by the second bulk photoresist layer 172 includes about 50% of the openings 122 in the patterned hardmask layer 121 in the first contact region 301, 100% of the openings 122D in the patterned hardmask layer 121 in the second contact region 302, and 100% of the openings 122D in the patterned hardmask layer 121 in the third contact region 303. Thus, the total etch area includes about 5 / 6 of the area of all of the openings in the patterned hardmask layer 121, and the second anisotropic etch process is performed with a higher pattern factor corresponding to such etch area. According to one aspect of the disclosure, the pattern factor used for the second anisotropic etch process can be the same as the pattern factor used for the first anisotropic etch process. This feature improves the end point detection of the second anisotropic etch process.

[0085] A subset of the first layer via cavities (891, 891D) extend a depth equal to twice the sum of the thickness of the first layer insulating layer 132 and the thickness of the first layer sacrificial material layer 142, while another subset of the first layer via cavities 891 do not extend in depth. Thus, after the processing step of Figure 14A the various combinations of coverage and non-coverage of the various bulk photoresist layers (171, 172) provide four different depths for the first layer via cavities (891, 891D). Each dummy first layer via cavity 891D located in the second contact region 302 and the third contact region 303 can extend vertically during the second anisotropic etch process. A subset of the dummy first layer via cavities 891D formed in the second contact region 302 and the third contact region 303 are used as dummy via cavities that increase the pattern factor during the first anisotropic etch process to improve the end point detection of the etch process. The second bulk photoresist layer 172 can be subsequently removed after Figure 14B the processing steps illustrated.

[0086] Reference is made to Figure 4A to 11B and Figure 15The above-described scheme can be repeated up to the Nth block-level photoresist layer and Nth anisotropic etch process. N can be an integer in the range of 2 to 10, but larger integers for N can also be employed. For each arbitrary integer i selected between and including 2 and N (in other words, for the ith iteration of the combination of the block-level photoresist layer patterning step and the subsequent anisotropic etch process step), about half of all openings 122 through the patterned hardmask layer 121 in the first contact region 301 can be covered by the ith block-level photoresist layer, and unmasked openings (122, 122D) in the patterned hardmask layer 121 can be etched below by performing the ith anisotropic etch process 2 (i-1) first layer insulating layers 132 and 2 (i-1) first layer sacrificial material layers 142. During the ith anisotropic etch process, a subset of the first layer via cavities (891, 891D) extends a depth equal to 2 i times the sum of the thickness of the first layer insulating layers 132 and the thickness of the first layer sacrificial material layers 142, while another subset of the first layer via cavities 891 does not extend in depth. After the ith anisotropic etch process, the mask pattern of the block-level photoresist layer can be combined to provide up to 2 i different depths for the first layer via cavities 891. Thus, after the Nth anisotropic etch process, the first layer via cavities 891 in the first contact region 301 can have up to 2 N different depths for the first layer via cavities 891.

[0087] For each ith anisotropic etch process, the entire set of openings in the patterned hardmask layer 121 that are not covered by each block-level photoresist layer includes about 50% of the openings 122 in the patterned hardmask layer 121 in the first contact region 301, 100% of the openings 122D in the patterned hardmask layer 121 in the second contact region 302, and 100% of the openings 122D in the patterned hardmask layer 121 in the third contact region 303. Thus, the total etched area includes about 5 / 6 of the area of all of the openings (122, 122D) in the patterned hardmask layer 121, and each ith anisotropic etch process is performed with a higher pattern factor corresponding to such etched area. According to one aspect of the disclosure, the pattern factor of each ith anisotropic etch process can be the same regardless of the integer i in the range from 1 to N. This feature improves end-point detection of each anisotropic etch process for deepening the first-tier via cavities 891. Each dummy first-tier via cavity 891D located in the second contact region 302 and the third contact region 303 can be vertically extended during each ith anisotropic etch process. A subset of the dummy first-tier via cavities 891D formed in the second contact region 302 and the third contact region 303 are used as dummy via cavities that increase the pattern factor during each ith anisotropic etch process to improve end-point detection of the etch process. Each block-level photoresist layer can be subsequently removed after the corresponding anisotropic etch process is performed.

[0088] While an embodiment is described in which the etch depth of the ith anisotropic etch process is equal to 2 i times the sum of the thickness of the first-tier insulating layer 132 and the thickness of the first-tier sacrificial material layer 142, the etch depth of any anisotropic etch process can be arbitrarily selected from a set of N depths in any order. The N depths are integer multiples of a unit size that is the sum of the thickness of the first-tier insulating layer 132 and the thickness of the first-tier sacrificial material layer 142. The integer multiples can or can not consist of non-negative integer powers of 2, but using non-negative integer powers of 2 is preferred when generating different depths for the first-tier via cavities 891.

[0089] Reference is made to Figure 16, the exemplary structure after performing an Nth anisotropic etch process with an Nth block-level photoresist layer 177 is illustrated. The integer N can be selected such that each of the first-tier sacrificial material layers 142 can be physically exposed to a respective one of the first-tier via cavities 891 in the first contact region 301. In addition, the dummy openings 122D in the patterned hardmask layer 121 in the second and third contact regions 302, 303 are not masked by any of the block-level photoresist layers (171, 172, …, 177). A top surface of the bottommost first-tier sacrificial material layer 142 can be physically exposed to each of the dummy first-tier via cavities 891D formed underneath the second and third contact regions 302, 303. The Nth block-level photoresist layer 177 can be subsequently removed, e.g., by ashing.

[0090] Referring to Figure 3A , a terminal block-level dielectric layer 178 can be applied over the exemplary structure and can be lithographically patterned to cover an entire area of the first contact region 301 without covering the second or third contact regions 302, 303. A terminal anisotropic etch process can be performed to vertically extend each of the dummy first-tier via cavities 891D in the second and third contact regions 302, 303 through the bottommost first-tier sacrificial material layer 142. The bottommost first-tier insulating layer 132 can be physically exposed to each of the dummy first-tier via cavities 891D formed underneath the second and third contact regions 302, 303.

[0091] Referring to Figure 3B , the terminal block-level dielectric layer 178 can be subsequently removed, e.g., by ashing.

[0092] Referring to Figure 17A , a first dielectric spacer material layer can be conformally deposited in the peripheral regions of the first-tier via cavities (891, 891D). The first dielectric spacer material layer comprises a dielectric material that is different from the material of the first-tier sacrificial material layers 142. For example, the first dielectric spacer material layer comprises a dielectric material such as silicon oxide. A thickness of the first dielectric spacer material layer is less than half of a lateral dimension of each of the first-tier via cavities (891, 891D). For example, the thickness of the first dielectric spacer material layer can be in a range from 2% to 25% of the lateral dimension of each of the first-tier via cavities. In one embodiment, the thickness of the first dielectric spacer material layer can be in a range from 10 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0093] An anisotropic etch process can be performed to remove the horizontally extending portions of the first dielectric spacer material layer. The anisotropic etch process can continue to change the etch chemistry to selectively remove the patterned hardmask layer 121 relative to the material of the first layer insulating layer 132. Each remaining portion of the first dielectric spacer material layer in the respective first layer via cavities (891, 891D) constitutes a first layer tubular dielectric spacer 821. The first layer tubular dielectric spacer 821 includes first type first layer tubular dielectric spacers 821A formed in the first contact region 301 and having different heights; second type first layer tubular dielectric spacers 821B formed in the second contact region 302 and having the same height; and third type first layer tubular dielectric spacers 821C formed in the third contact region 303 and having the same height. The second type first layer tubular dielectric spacers 821B and the third type first layer tubular dielectric spacers 821C include dummy spacers that can have a larger vertical dimension (i.e., height) than each of the first type first layer tubular dielectric spacers 821A.

[0094] Referring to Figure 17B and Figure 4A to 11B A first sacrificial via fill material can be deposited in the remaining volume of the first layer via cavities (891, 891D). The first sacrificial via fill material can include a semiconductor material (such as amorphous silicon, polysilicon, silicon germanium, etc.), a carbon-based material (such as amorphous carbon or diamond-like carbon) including greater than 80 atomic percent carbon atoms, or a polymeric material. The first sacrificial via fill material can be the same as or different from the first sacrificial fill material of the first layer sacrificial opening fill structures (148, 118).

[0095] An executable planarization process can be performed to remove portions of the first sacrificial via fill material from above a horizontal plane including a top surface of the first-tier alternating stack (132, 142). The planarization process can be stopped so that each remaining portion of the first sacrificial fill material has a top surface at or near a horizontal plane including a top surface of the first-tier alternating stack (132, 142). The planarization process can include a recess etch process and / or a chemical mechanical polishing process. The remaining portions of the first sacrificial via fill material filling the first-tier via openings (891, 891D) constitute first-tier pillar structures 831. The first-tier pillar structures 831 include first-tier pillar structures of a first type 831 A formed in the first contact regions 301, first-tier pillar structures of a second type 831B formed in the second contact regions 301, and first-tier pillar structures of a third type 831C formed in the third contact regions 303. The first-tier pillar structures of the first type 831A do not extend through the bottommost first-tier sacrificial material layer 142 within the first-tier alternating stack (132, 142). The first-tier pillar structures of the second type 831B and the first-tier pillar structures of the third type 831C extend through each first-tier sacrificial material layer 142 within the first-tier alternating stack (132, 142). The first-tier pillar structures of the second type 831B and the first-tier pillar structures of the third type 831C include dummy first-tier pillar structures that will not be replaced with contact via structures in subsequent process steps and will remain in the final device.

[0096] In one embodiment, each of the first-tier pillar structures 831 includes a respective top surface formed within a horizontal plane including a topmost surface of the first-tier alternating stack (132, 142). In one embodiment, each of the first-tier pillar structures 831 can be formed directly on and within a respective one of the first-tier tubular dielectric spacers 821. In one embodiment, an annular top surface of each of the first-tier tubular dielectric spacers 821 can be formed within a horizontal plane including a topmost surface of the first-tier alternating stack (132, 142). In one embodiment, a top surface of each of the first-tier pillar structures 831 can be formed within a horizontal plane including a topmost surface of the first-tier alternating stack (132, 142).

[0097] Reference is made to Figure 18A to 18DA second layer of alternating stacks of a second layer of insulating layers 232 and a second layer of spacer material layers can be formed over the first layer of alternating stacks (132, 142). In one embodiment, the second layer of spacer material layers can include a second layer of sacrificial material layers 242. In this case, a second layer of alternating stacks (232, 242) of a second layer of insulating layers 232 and a second layer of sacrificial material layers 242 can be formed over the first layer of alternating stacks (132, 142). The second layer of insulating layers 232 is a second subset of the insulating layers 32, and the second layer of sacrificial material layers 242 is a second subset of the sacrificial material layers 42. In one embodiment, the second layer of insulating layers 232 can include silicon oxide layers, and the second layer of sacrificial material layers 242 can include silicon nitride layers. The second layer of alternating stacks (232, 242) can include a number of repetitions of a unit layer stack including a second layer of insulating layers 232 and a second layer of sacrificial material layers 242. The total number of repetitions of the unit layer stack within the second layer of alternating stacks (232, 242) can be, for example, in a range from 8 to 1,024, such as from 32 to 256, although fewer and greater numbers of repetitions can also be employed.

[0098] Referring Figure 18A Referring Figure 18B and Figure 18C The processing steps described with reference to FIGS. 1-6 can be performed with any desired modifications to form the second layer of memory openings and the second layer of support openings, and to form the second layer of sacrificial memory opening fill structures 248 and the second layer of sacrificial support opening fill structures 218. In general, the pattern of the second layer of memory openings and the pattern of the second layer of sacrificial memory opening fill structures 248 can be the same as the pattern of the first layer of memory openings 149 and the pattern of the first layer of sacrificial memory opening fill structures 148. Further, the pattern of the second layer of support openings and the pattern of the second layer of sacrificial support opening fill structures 218 can be the same as the pattern of the first layer of support openings 119 and the pattern of the first layer of sacrificial support opening fill structures 118.

[0099] In one embodiment, each successive combination of the first layer sacrificial memory opening-fill structure 148 and the second layer sacrificial memory opening-fill structure 248 may have a stepped vertical profile, the stepped vertical profile including a first tapered surface extending through the first alternating stack (132, 142) (i.e., the tapered surface of the first layer sacrificial memory opening-fill structure 148), a second tapered surface extending through the second alternating stack (232, 242) (i.e., the tapered surface of the second layer sacrificial memory opening-fill structure 248), and a first horizontal connecting surface connecting the first and second tapered surfaces and located in a horizontal plane including the interface between the first alternating stack (132, 142) and the second alternating stack (232, 242), the horizontal plane including the top surface of the first layer column structure 831. The first horizontal connecting surface may be an annular horizontal top surface segment of the first layer sacrificial memory opening-fill structure 148.

[0100] refer to Figure 18D and Figure 19A You can repeat the reference if you need to make any changes. Figure 19B The described processing steps form a second layer of via cavities through the alternating stacks of the second layers (232, 242). Each second layer via cavity located in the first contact region 301 and the third contact region 303 may extend vertically during each anisotropic etching process that patterns the second layer via cavity. A subset of the second layer via cavities formed in the third contact region 303 is used as dummy via cavities that add a patterning factor during each anisotropic etching process to improve end-point detection of the etching process. Generally, the pattern of the second layer via cavities in a planar view may be the same as that of the first layer via cavities in a planar view, but the depth distribution of the second layer via cavities may differ from that of the first layer via cavities. According to one aspect of this disclosure, the depth of the second layer via cavities may be selected such that each second layer sacrificial material layer 242 includes a corresponding physically exposed horizontal top surface below the corresponding second layer via cavity formed in the second contact region 302. Furthermore, each second-layer via cavity formed in the first contact area 301 and the third contact area 303 can be formed through each layer in the second layer alternating stack (232, 242), such that the top surface of the corresponding first-layer pillar structure 831 and the annular top surface of the corresponding first-layer tubular dielectric spacer 821 are physically exposed below each second-layer via cavity in the first contact area 301 and the third contact area 303.

[0101] Each second-tier via cavity can be filled with a combination of a respective second-tier tubular dielectric spacer 822 and a respective second-tier pillar structure 832. The second-tier tubular dielectric spacers 822 include first-type second-tier tubular dielectric spacers 822A formed in the first contact region 301 and having a same height equal to a total thickness of the second-tier alternating stack (232, 242); second-type second-tier tubular dielectric spacers 822B formed in the second contact region 302 and having different heights and not contacting any underlying first-tier tubular dielectric spacer 821; and third-type second-tier tubular dielectric spacers 822C formed in the third contact region 303 and having a same height. The first-type second-tier tubular dielectric spacers 822A and the third-type second-tier tubular dielectric spacers 822C can have a greater vertical dimension (i.e., height) than each of the second-type second-tier tubular dielectric spacers 822B.

[0102] The second-tier pillar structures 832 include first-type second-tier pillar structures 832A formed in the first contact region 301, second-type second-tier pillar structures 832B formed in the second contact region 301, and third-type second-tier pillar structures 832C formed in the third contact region 303. The second-type second-tier pillar structures 832B do not extend through the bottommost second-tier sacrificial material layer 242 within the second-tier alternating stack (232, 242). The first-type second-tier pillar structures 832A and the third-type second-tier pillar structures 832C extend through each second-tier sacrificial material layer 242 within the second-tier alternating stack (232, 242). The third-type second-tier pillar structures 832C include dummy pillar structures.

[0103] In one embodiment, each of the first-type second-tier pillar structures 832A includes a respective bottom surface that contacts a top surface of a respective first-type first-tier pillar structure 831 A, and each of the third-type second-tier pillar structures 832C includes a respective bottom surface that contacts a top surface of a respective third-type first-tier pillar structure 831C. In one embodiment, each of the second-tier pillar structures 832 includes a respective top surface that is formed within a horizontal plane that includes a topmost surface of the second-tier alternating stack (232, 242). In one embodiment, each of the second-tier pillar structures 832 can be formed directly on and within a respective one of the second-tier tubular dielectric spacers 822. In one embodiment, an annular top surface of each of the second-tier tubular dielectric spacers 822 can be formed within a horizontal plane that includes a topmost surface of the second-tier alternating stack (232, 242). In one embodiment, a top surface of each of the second-tier pillar structures 832 can be formed within a horizontal plane that includes a topmost surface of the second-tier alternating stack (232, 242).

[0104] Referring to Figure 18A to 18D , a third-tier alternating stack of third-tier insulating layers 332 and second- spacer-material layers can be formed over the second-tier alternating stack (232, 242). In one embodiment, the third-tier spacer-material layers can include third-tier sacrificial-material layers 342. In this case, a third-tier alternating stack (332, 342) of third-tier insulating layers 332 and third-tier sacrificial-material layers 342 can be formed over the second-tier alternating stack (232, 242). The third-tier insulating layers 332 are a third subset of the insulating layers 32, and the third-tier sacrificial-material layers 342 are a third subset of the sacrificial-material layers 42. In one embodiment, the third-tier insulating layers 332 can include silicon oxide layers, and the third-tier sacrificial-material layers 342 can include silicon nitride layers. The third-tier alternating stack (332, 342) can include a plurality of repetitions of a unit layer stack that includes a third-tier insulating layer 332 and a third-tier sacrificial-material layer 342. The total number of repetitions of the unit layer stack within the third-tier alternating stack (332, 342) can be, for example, in a range from 8 to 1,024, such as from 32 to 256, although fewer and greater numbers of repetitions can also be employed.

[0105] Referring to Figure 20A , referring to Figure 20B and Figure 21AThe described processing steps can be performed in any desired variation to form third-tier memory openings and third-tier support openings, and to form third-tier sacrificial memory opening fill structures 348 and third-tier sacrificial support opening fill structures 318. Generally, the pattern of third-tier memory openings and the pattern of third-tier sacrificial memory opening fill structures 348 can be the same as the pattern of second-tier memory openings and the pattern of second-tier sacrificial memory opening fill structures 248. Also, the pattern of third-tier support openings and the pattern of third-tier sacrificial support opening fill structures 318 can be the same as the pattern of second-tier support openings and the pattern of second-tier sacrificial support opening fill structures 218.

[0106] In one embodiment, each successive combination of first-tier sacrificial memory opening fill structures 148, second-tier sacrificial memory opening fill structures 248, and third-tier sacrificial memory opening fill structures 348 can have a stepped vertical cross-sectional profile that includes a first tapered surface (i.e., the tapered surface of first-tier sacrificial memory opening fill structures 148) extending through the first-tier alternating stack (132, 142), a second tapered surface (i.e., the tapered surface of second-tier sacrificial memory opening fill structures 248) extending through the second-tier alternating stack (232, 242), a third tapered surface (i.e., the tapered surface of third-tier sacrificial memory opening fill structures 348) extending through the third-tier alternating stack (332, 342), a first horizontal connecting surface connecting the first tapered surface and the second tapered surface and lying in a horizontal plane that includes the interface between the second-tier alternating stack (232, 242) and the third-tier alternating stack (332, 342), and a second horizontal connecting surface connecting the second tapered surface and the third tapered surface and lying in a horizontal plane that includes the interface between the second-tier alternating stack (232, 242) and the third-tier alternating stack (332, 342). The first horizontal connecting surface can be a ring-shaped horizontal top surface segment of first-tier sacrificial memory opening fill structures 148. The second horizontal connecting surface can be a ring-shaped horizontal top surface segment of second-tier sacrificial memory opening fill structures 248.

[0107] Referring to Figure 21B and Figure 22A Referring to Figure 22BThe processing steps described to form third-tier via cavities through the third-tier alternating stack (332, 342). Generally, the pattern of the third-tier via cavities in plan view can be the same as the pattern of the first-tier via cavities in plan view, but the depth profile of the third-tier via cavities is different relative to the depth profile of the first-tier via cavities. According to one aspect of the present disclosure, the depths of the third-tier via cavities can be selected such that each of the third-tier sacrificial material layers 342 includes a respective physically exposed horizontal top surface below a respective third-tier via cavity formed within the third contact region 303. Further, each of the third-tier via cavities formed in the first contact region 301 and the second contact region 302 can be formed through each of the layers within the third-tier alternating stack (332, 342) such that the top surface of the respective second-tier pillar structure 832 and the annular top surface of the respective second-tier tubular dielectric spacer 822 are physically exposed below each of the third-tier via cavities in the first contact region 301 and the second contact region 302.

[0108] Each of the third-tier via cavities can be filled with a combination of a respective third-tier tubular dielectric spacer 823 and a respective third-tier pillar structure 833. The third-tier tubular dielectric spacers 823 include first-type third-tier tubular dielectric spacers 823A formed in the first contact region 301 and having a same height equal to the total thickness of the third-tier alternating stack (332, 342); second-type third-tier tubular dielectric spacers 823B formed in the second contact region 302 and having the same height; and third-type third-tier tubular dielectric spacers 823C formed in the third contact region 303 and having different heights and not contacting any underlying second-tier tubular dielectric spacer 822. The first-type third-tier tubular dielectric spacers 823A and the second-type third-tier tubular dielectric spacers 823B can have a greater vertical dimension (i.e., height) than each of the third-type third-tier tubular dielectric spacers 823C.

[0109] The third-tier pillar structures 833 include first-type third-tier pillar structures 833A formed in the first contact region 301, second-type third-tier pillar structures 833B formed in the second contact region 301, and third-type third-tier pillar structures 833C formed in the third contact region 303. The third-type third-tier pillar structures 833C do not extend through the bottommost third-tier sacrificial material layer 342 within the third-tier alternating stack (332, 342). The first-type third-tier pillar structures 833A and the second-type third-tier pillar structures 833B extend through each of the third-tier sacrificial material layers 342 within the third-tier alternating stack (332, 342).

[0110] In one embodiment, each of the first-type third-tier pillar structures 833A includes a respective bottom surface that contacts a top surface of a respective first-type second-tier pillar structure 832A, and each of the second-type third-tier pillar structures 833B includes a respective bottom surface that contacts a top surface of a respective second-type second-tier pillar structure 832B. In one embodiment, each of the third-tier pillar structures 833 includes a respective top surface that is formed within a horizontal plane that includes a topmost surface of the third-tier alternating stack (332, 342). In one embodiment, each of the third-tier pillar structures 833 can be formed directly on and within a respective one of the third-tier tubular dielectric spacers 823. In one embodiment, an annular top surface of each of the third-tier tubular dielectric spacers 823 can be formed within a horizontal plane that includes a topmost surface of the third-tier alternating stack (332, 342). In one embodiment, a top surface of each of the third-tier pillar structures 833 can be formed within a horizontal plane that includes a topmost surface of the third-tier alternating stack (332, 342).

[0111] Subsequently, a mask layer (not illustrated) can be applied over the example structure and can be lithographically patterned to form openings over each of the third layer sacrificial opening fill structure 348 and the third layer sacrificial support opening fill structure 318. The mask layer can comprise a hard mask layer comprising a hard mask material such as silicon oxide, silicon nitride, or a metallic material, or can comprise a photoresist material, depending on the nature of subsequent processes performed to remove the sacrificial fill material of the third layer sacrificial opening fill structures (348, 318), the second layer sacrificial opening fill structures (248, 218), and the first layer sacrificial opening fill structures (148, 118). The third layer sacrificial opening fill structures (348, 318), the second layer sacrificial opening fill structures (248, 218), and the first layer sacrificial opening fill structures (148, 118) can subsequently be selectively removed with respect to the materials of the insulating layers (132, 232, 332), the sacrificial material layers (142, 242, 342), and the in-process source-level material layer 110’ by performing a selective removal process. The selective removal process can comprise an ashing process or a selective etching process such as a wet etching process or a reactive ion etching process. A memory opening is formed in each volume from which the combination of the third layer sacrificial memory opening fill structure 348, the second layer sacrificial memory opening fill structure 248, and the first layer sacrificial memory opening fill structure 148 is removed. The memory opening extends through multiple layers of the structure, and is therefore referred to herein as a multilayer memory opening. A support opening is formed in each volume from which the combination of the third layer sacrificial support opening fill structure 318, the second layer sacrificial support opening fill structure 218, and the first layer sacrificial support opening fill structure 118 is removed. The mask layer can subsequently be removed, for example by ashing.

[0112] Figure 23 is a sequential vertical cross-sectional view around a region of a multilayer memory opening 49 during formation of a memory opening fill structure 58 according to embodiments of the present disclosure.

[0113] Referring to Figure 24 , an example structure is illustrated with a memory opening 49.

[0114] Referring to Figure 25AA layer stack including a memory material layer 54 can be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing changes in resistivity, ferroelectric polarization, or any other measurable physical property. Where the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0115] The semiconductor channel material layer 60L can be deposited on top of the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have a first conductivity type of doping, which can be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a first conductivity type of doping. In an exemplary example, the atomic concentration of the first conductivity type of dopant in the semiconductor channel material layer 60L can be 1.0 × 10⁻⁶. 13 / cm 3 Up to 3.0×10 17 / cm 3 Within the range, such as 1.0 × 10 14 / cm 3 Up to 3.0×10 16 / cm 3 However, smaller and larger atomic concentrations can also be used. A dielectric core layer 62L, including a dielectric filling material (e.g., silicon oxide), can be deposited in the remaining volume of the memory opening 49 and deposited on top of a third layer of alternating stacks (332, 342).

[0116] refer to Figure 25B The dielectric core layer 62L may be vertically recessed, such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane including the bottom surface of the topmost third insulating layer 332. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62.

[0117] refer to Figure 26A , Figure 27A and Figure 27B A doped semiconductor material having a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5.0 × 10⁻⁶. 18 / cm3 to 2.0 x 10 21 / cm 3 but lesser or greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0118] The deposited excess portions of the doped semiconductor material having the second conductivity type and horizontal portions of the semiconductor channel material layer 60L can be removed from above the horizontal plane comprising the top surface of the top third insulating layer 332, e.g., by a chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L, which has a doping of the first conductivity type, constitutes a vertical semiconductor channel 60.

[0119] Each portion of the layer stack comprising the memory material layer 54 remaining in the respective memory opening 49 constitutes a memory film 50. In one embodiment, the memory film 50 can comprise the optional blocking dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56. Each contiguous combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 comprises a respective vertical stack of memory elements, which stack can include portions of the memory material layer 54 located at the level of the sacrificial material layer 42. In general, a memory opening fill structure 58 comprising the memory film 50 and the vertical semiconductor channel 60 can be formed in each memory opening 49.

[0120] In one embodiment, each support opening can be filled with a support pillar structure 20 having the same set of materials as the memory opening fill structure 58. In an alternative embodiment, the sacrificial fill material in the support openings can be removed before or after the processing steps described with reference to Figure 28A Each support pillar structure 20 can be substantially composed of at least one dielectric fill material, and thus can comprise a different material than the materials of each memory opening fill structure 58, in this case.

[0121] While an embodiment in which three alternating stacks are formed is described, other embodiments are expressly contemplated herein, which can include only two alternating stacks, or can include K alternating stacks, where K is an integer greater than 3.

[0122] Reference is made to Figure 29A and Figure 29BA dielectric material such as an undoped silicate glass or a doped silicate glass can be deposited over the third-tier alternating stack (332, 342) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in a range from 100 nm to 600 nm, such as from 200 nm to 400 nm, although lesser and greater thicknesses can also be employed.

[0123] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form elongated openings extending laterally between adjacent clusters of the memory opening fill structures 58 along the first horizontal direction hd1. An anisotropic etch process can be performed to transfer the pattern of openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (132, 142), (232, 242), (332, 342), and the in-process source-level material layer 110’. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 (which can be a word line direction) can be formed through the contact-level dielectric layer 80, the alternating stacks (132, 142), (232, 242), (332, 342), and the in-process source-level material layer 110’. Each of the lateral isolation trenches 79 can include a respective pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and that extend vertically from a top surface of the blocking layer insulating layer 106 to a top surface of the contact-level dielectric layer 80. The top surface of the blocking layer insulating layer 106 can be physically exposed beneath each of the lateral isolation trenches 79. The photoresist layer can be subsequently removed, e.g., by ashing.

[0124] Reference is made to Figure 30 and Figure 31An etchant can be introduced into the lateral isolation trench 79 by performing an isotropic etch process that selectively etches the material of the source-level sacrificial layer 104 relative to the materials of the alternating stacks {(132, 142), (232, 242), (332, 342)}, the contact-level dielectric layer 80, the lower source-level semiconductor layer 112, the upper source-level semiconductor layer 116, the upper sacrificial liner 105 (if present), and the lower sacrificial liner 103 (if present). For example, if the source-level sacrificial layer 104 includes undoped amorphous silicon or a silicon-germanium alloy, a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be used to selectively remove the source-level sacrificial layer 104 relative to the alternating stacks {(132, 142), (232, 242), (332, 342)}, the contact-level dielectric layer 80, the lower source-level semiconductor layer 112, and the upper source-level semiconductor layer 116. A source cavity 109 is formed in the volume from which the source-level sacrificial layer 104 is removed. Each of the memory opening fill structures in the memory opening fill structure 58 is physically exposed to the source cavity 109. In particular, each of the memory opening fill structures in the memory opening fill structure 58 includes a sidewall that is physically exposed to the source cavity 109.

[0125] A series of isotropic etchants, such as wet etchants, can be applied to the physically exposed portions of the memory film 50 to sequentially etch various constituent layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper sacrificial liner 105 (if present) and the lower sacrificial liner 103 (if present) can be incidentally etched during the removal of the portions of the memory film 50 that are at the level of the source cavity 109. The volume of the source cavity 109 can be enlarged by removing portions of the memory film 50 at the level of the source cavity 109, as well as the upper and lower sacrificial liners. The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each of the memory films 50 relative to at least one source-level semiconductor layer, such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116, and the vertical semiconductor channel 60.

[0126] Reference is made to Figure 32 and ​A doped semiconductor material having a second conductivity type can be deposited on a physically exposed semiconductor surface surrounding the source cavity 109. The physically exposed semiconductor surface includes the bottom portion of the outer wall of the vertical semiconductor channel 60 and a horizontal surface of at least one source semiconductor layer (such as the bottom surface of the upper source semiconductor layer 116 and / or the top surface of the lower source semiconductor layer 112). For example, the physically exposed semiconductor surface may include the bottom portion of the outer wall of the vertical semiconductor channel 60, the top horizontal surface of the lower source semiconductor layer 112, and the bottom surface of the upper source semiconductor layer 116.

[0127] In one embodiment, a doped semiconductor material of a second conductivity type can be deposited on a physically exposed semiconductor surface surrounding the source cavity 109 using a selective semiconductor deposition process. The deposited doped semiconductor material forms a source contact layer 114 that contacts the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be 1.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 Within the range, such as 1.0 × 10 20 / cm 3 Up to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may consist substantially of semiconductor atoms and dopant atoms of a second conductivity type. Alternatively, at least one non-selective doping semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0128] A source layer 110 is formed by a stack of layers including a lower source semiconductor layer 112, a source contact layer 114, and an upper source semiconductor layer 116, which replaces the source material layer 110' in the process. The source layer 110 lies beneath a first alternating stack of layers (132, 146), and each vertical semiconductor channel 60 contacts a corresponding surface of the source layer 110.

[0129] refer to ​An isotropic etch process can be performed to selectively remove the sacrificial material layers (142, 242, 342) relative to the insulating layers (132, 232, 332), the stopper layer insulating layer 106, the memory opening fill structures 58, and the source layer 110. In an illustrative example, the insulating layers (132, 232, 332) can comprise silicon oxide, and the sacrificial material layers (142, 242, 342) can comprise silicon nitride. In this case, the isotropic etch process that removes the sacrificial material layers (142, 242, 342) can comprise a wet etch process employing hot phosphoric acid. Lateral extension cavities 43 can be formed in the volumes from which the sacrificial material layers (142, 242, 342) are removed. The lateral extension cavities 43 can comprise first layer lateral extension cavities 143 formed in the volumes from which the first layer sacrificial material layers 142 are removed; second layer lateral extension cavities 243 formed in the volumes from which the second layer sacrificial material layers 242 are removed; and third layer lateral extension cavities 343 formed in the volumes from which the third layer sacrificial material layers 342 are removed. The sidewall surface segments of the memory opening fill structures 58 can be physically exposed to the lateral extension cavities 43.

[0130] Referring to ​ An outer barrier dielectric layer (not shown), such as an aluminum oxide layer, can optionally be formed in the lateral extension cavities 43 by a conformal deposition process. At least one electrically conductive material, such as at least one metallic material, can be conformally deposited in the lateral extension cavities 43. The at least one electrically conductive material can comprise, for example, a combination of a metallic barrier material and a metallic fill material. The metallic barrier material can comprise, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or combinations thereof. The metallic fill material can comprise, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or alloys or layer stacks thereof. Excess portions of the at least one electrically conductive material deposited in the lateral isolation trenches 79 or over the contact level dielectric layer 80 can be removed by performing an etch-back process, which can comprise an isotropic etch process and / or an anisotropic etch process. Each remaining portion of the at least one electrically conductive material that fills a respective one of the lateral extension cavities 43 constitutes an electrically conductive layer 46. Specifically, the electrically conductive layers 46 can comprise first layer electrically conductive layers 146 formed in the first layer lateral extension cavities 143, second layer electrically conductive layers 246 formed in the second layer lateral extension cavities 243, and third layer electrically conductive layers 346 formed in the third layer lateral extension cavities 343. Alternating stacks of the insulating layers 32 and the electrically conductive layers 46 can be formed between each pair of adjacent lateral isolation trenches 79 over the carrier substrate 9. Multiple alternating stacks of the insulating layers 32 and the electrically conductive layers 46 can be laterally spaced apart from one another by the lateral isolation trenches 79.

[0131] Referring to ​ and ​An insulating spacer material layer can be conformally deposited in the lateral isolation trenches 79 and over the contact-level dielectric layer 80. An optional anisotropic etch process can be performed to remove horizontal extensions of the insulating spacer material layer. Each remaining laterally elongated tubular portion of the insulating spacer material layer in the peripheral regions of the lateral isolation trenches 79 constitutes an insulating spacer 74. At least one electrically conductive fill material, such as at least one metallic fill material, can be optionally conformally deposited in the remaining volumes of the lateral isolation trenches 79. Excess portions of the at least one electrically conductive fill material can be removed from over the contact-level dielectric layer 80, e.g., by a planarization process, which can employ a recess etch process and / or a chemical mechanical polishing process. Each remaining portion of the at least one electrically conductive fill material filling a respective lateral isolation trench 79 constitutes an electrically conductive wall structure 76. Each continuous combination of an insulating spacer 74 and an electrically conductive wall structure 76 constitutes an isolation trench fill structure (74, 76) filling a respective lateral isolation trench 79. Alternatively, each lateral isolation trench 79 can be filled only with the at least one dielectric fill material to form an isolation trench fill structure consisting essentially of the at least one dielectric fill material.

[0132] Referring to ​ and with reference to 26B, a photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form openings in regions overlying the third pillar structure 833. In one embodiment, the pattern of openings in the photoresist layer can be identical in plan view (i.e., a view along the vertical direction) to the pattern of the third pillar structure 833. An anisotropic etch process can be performed to form via cavities through the contact-level dielectric layer 80. The via cavities formed through the contact-level dielectric layer 80 are referred to herein as connection via cavities 89’. The top surfaces of the third pillar structure 833 can be physically exposed at the bottoms of each of the connection via cavities 89’. The photoresist layer can be subsequently removed, e.g., by ashing.

[0133] Referring to ​ and ​ The sacrificial via fill material of the pillar structures (833, 832, 831) exposed in the connection via cavities 89’ can be removed by a selective removal process. The selective removal process can include a wet etch process, a reactive ion etch process, or an ashing process. The connection via cavities 89’ serve as conduits for transporting etchant or oxidizing agent during the selective removal process.

[0134] According to one aspect of the disclosure, the entirety of the third-tier pillar structures 833, the first-type second-tier pillar structures 832A, the second-type second-tier pillar structures 832B, and the first-type first-tier pillar structures 831A can be removed by a selective removal process. However, the third-type second-tier pillar structures 832C and the third-type first-tier pillar structures 831C are vertically spaced apart from the overlying third-type third-tier pillar structures 833C by at least the bottommost third-tier insulating layers 332, and thus are not removed during the selective removal process. Further, the second-type first-tier pillar structures 831B are vertically spaced apart from the overlying second-type second-tier pillar structures 832B by at least the bottommost second-tier insulating layers 232, and thus are not removed during the selective removal process.

[0135] The layer contact via cavities 89 are formed in a combination of the volume of the connection via cavities 89’ and the volume from which the third-tier pillar structures 833, the first-type second-tier pillar structures 832A, the second-type second-tier pillar structures 832B, and the first-type first-tier pillar structures 831A are removed. The layer contact via cavities 89 include first via cavities 991 formed in the first contact regions 301, second via cavities 992 formed in the second contact regions 302, and third via cavities 993 formed in the third contact regions 303. Each first via cavity 991 includes the volume of the connection via structures 89’, the volume from which the voids of the first-type third-tier pillar structures 833A are removed, the volume from which the voids of the first-type second-tier pillar structures 832A are removed, and the volume from which the voids of the first-type first-tier pillar structures 831A are removed. Each second via cavity 992 includes the volume of the connection via structures 89’, the volume from which the voids of the second-type third-tier pillar structures 833B are removed, and the volume from which the voids of the second-type second-tier pillar structures 832B are removed. Each third via cavity 993 includes the volume of the connection via structures 89’ and the volume from which the voids of the third-type third-tier pillar structures 833C are removed.

[0136] Referring to ​ And with reference to 28B, a photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form openings in regions overlying the memory opening fill structures 58. An anisotropic etch process can be performed to etch portions of the contact-level dielectric layer 80 that are not masked by the photoresist layer. The drain contact via cavities 87 can be formed through the contact-level dielectric layer 80. The top surfaces of the memory opening fill structures 58, such as the top surfaces of the drain regions 63, can be physically exposed at the bottoms of each of the drain contact via cavities 87. The photoresist layer can then be removed, e.g., by ashing. Alternatively, the drain contact via cavities 87 can be formed during the same lithography and etch steps as the connection via cavities 89’.

[0137] Referring to ​ And ​A conformal deposition of at least one conductive material can be made in each of the layer contact via cavities 89 and the drain contact via cavities 87. For example, a combination of a conductive barrier material and a conductive fill material can be deposited in the drain contact via cavities 87 and the layer contact via cavities 89. Excess portions of the at least one conductive material can be removed from above the horizontal plane comprising the top surface of the contact level dielectric layer 80 by a planarization process, which can employ a recess etch process and / or a chemical mechanical polishing process. The remaining portions of the at least one conductive material filling the drain contact via cavities 87 constitute drain contact via structures 88 that contact the top surface of a respective one of the drain level regions in the drain regions 63. The remaining portions of the at least one conductive material filling the layer contact via cavities 89 constitute layer contact via structures 86 that contact the top surface of a respective one of the conductive layers in the conductive layers 46.

[0138] The layer contact via structures 86 include first contact via structures 861 that contact the top surface of a respective one of the first layer conductive layers 146, second contact via structures 862 that contact the top surface of a respective one of the second layer conductive layers 246, and third contact via structures 863 that contact the top surface of a respective one of the third layer conductive layers 346. Generally, each successive combination of the first type third layer pillar structures 833A, the first type second layer pillar structures 832A, and the first type first layer pillar structures 831A can be replaced with a first contact via structure 861 that contacts the top surface of a respective one of the first layer conductive layers 146. Each successive combination of the second type third layer pillar structures 833B and the second type second layer pillar structures 832B can be replaced with a second contact via structure 862 that contacts the top surface of a respective one of the second layer conductive layers 246. Each third type third layer pillar structure 833C can be replaced with a third contact via structure 863 that contacts the top surface of a respective one of the third layer conductive layers 346. During formation of the layer contact via structures 86, the second type first layer pillar structures 831B, the third type first layer pillar structures 831C, and the third type second layer pillar structures 832C do not change in structure or material composition.

[0139] In general, each first-type first-tier tubular dielectric spacer 821A contacts a top surface segment of a respective one of the first-tier electrically conductive layers 146, and includes a respective first inner sidewall that contacts a first cylindrical surface segment of a respective first contact via structure 861, and further includes a respective first outer sidewall that contacts each first-tier electrically conductive layer 146 overlying a respective one of the first-tier electrically conductive layers 146. Each first-type second-tier tubular dielectric spacer 822A includes a respective second inner sidewall that contacts a second cylindrical surface segment of a respective one of the first contact via structures 861, and includes a respective second outer sidewall that contacts each second-tier electrically conductive layer 246.

[0140] Each of the second-type first-tier pillar structures 831B and the third-type first-tier pillar structures 831C vertically extends through each first-tier electrically conductive layer 146 in the first-tier alternating stack (132, 146). Each of the second-type first-tier pillar structures 831B and the third-type first-tier pillar structures 831C can have a respective top surface that is coplanar with a topmost surface of the first-tier alternating stack (132, 146). Each of the second-type first-tier tubular dielectric spacers 821B laterally surrounds a respective one of the second-type first-tier pillar structures 831B. Each of the third-type first-tier tubular dielectric spacers 821C laterally surrounds a respective one of the third-type first-tier pillar structures 831C. Each of the first-tier tubular dielectric spacers 821 can have a same material composition and a same lateral thickness (as measured between an inner cylindrical sidewall and an outer cylindrical sidewall).

[0141] In one embodiment, each top surface of the tier contact via structures 86 can be formed within a horizontal plane that includes a top surface of the contact-level dielectric layer 80. Each portion of the tier contact via structures 86 embedded in the contact-level dielectric layer 80 can be in direct contact with the contact-level dielectric layer 80.

[0142] Each second contact via structure 862 contacts a respective one of the second-tier conductive layers 246. Each second-type second-tier tubular dielectric spacer 822B laterally surrounds and contacts a respective one of the second contact via structures 862, and contacts a top surface of a respective one of the second-tier conductive layers 246. Each second-type second-tier tubular dielectric spacer 822B contacts each second-tier conductive layer 246 overlying a respective one of the second-tier conductive layers 246. Each second-type first-tier pillar structure 831B underlies, is vertically spaced apart from, and has an area overlap with, a respective overlying second contact via structure 862 in a plan view.

[0143] Each first-type third-tier tubular dielectric spacer 823A includes a respective third inner sidewall that contacts a third cylindrical surface segment of a respective one of the first contact via structures 861, and includes a third outer sidewall that contacts each of the third-tier conductive layers 346.

[0144] Each third-type second-tier pillar structure 832C vertically extends through the second-tier alternating stack (232, 246), has a top surface that is coplanar with a topmost surface of the second-tier alternating stack (232, 246), and has a bottom surface that contacts a top surface of a respective third-type first-tier pillar structure 831C. Each third-type second-tier tubular dielectric spacer 822C laterally surrounds a respective third-type second-tier pillar structure 832C.

[0145] All of the first-tier tubular dielectric spacers 821 can have a same material composition and a same lateral thickness. All of the second-tier tubular dielectric spacers 822 can have a same material composition and a same lateral thickness. All of the third-tier tubular dielectric spacers 823 can have a same material composition and a same lateral thickness.

[0146] Each first-type third-tier tubular dielectric spacer 823A can have an annular bottom surface that contacts an annular top surface of a respective underlying first-type second-tier tubular dielectric spacer 822A. Each first-type second-tier tubular dielectric spacer 822A can have an annular bottom surface that contacts an annular top surface of a respective underlying first-type first-tier tubular dielectric spacer 821A. Each second-type third-tier tubular dielectric spacer 823B can have an annular bottom surface that contacts an annular top surface of a respective underlying second-type second-tier tubular dielectric spacer 822B. Each third-type second-tier tubular dielectric spacer 822C can have an annular bottom surface that contacts an annular top surface of a respective underlying third-type first-tier tubular dielectric spacer 821C.

[0147] Each of the second-type first-tier pillar structures 831B and the third-type first-tier pillar structures 831C includes a material selected from a semiconductor material, a carbon-based material including greater than 80 atomic percent of carbon atoms, or a polymeric material. Each of the third-type second-tier pillar structures 832C includes a material selected from a semiconductor material, a carbon-based material including greater than 80 atomic percent of carbon atoms, or a polymeric material.

[0148] In one embodiment, each of the second-type first-tier pillar structures 831B and the third-type first-tier pillar structures 831C can include a respective bottom surface that contacts a top surface of a bottommost first-tier insulating layer 132 within the first-tier alternating stack (132, 146). In one embodiment, each of the second-type first-tier pillar structures 831B can include a respective top surface that contacts a bottom surface of a bottommost second-tier insulating layer 232 within the second-tier alternating stack (232, 246). In one embodiment, each of the third-type first-tier pillar structures 831C can include a respective top surface that contacts a bottom surface of a respective one of the third-type second-tier pillar structures 832C. In one embodiment, each of the third-type second-tier pillar structures 832C can include a respective top surface that contacts a bottom surface of a bottommost third-tier insulating layer 332 within the third-tier alternating stack (332, 346).

[0149] In one embodiment, each of the second-type first-tier tubular dielectric spacers 821B and the third-type first-tier tubular dielectric spacers 821C can include a respective annular bottom surface that contacts a top surface of a bottommost first-tier insulating layer 132 within the first-tier alternating stack (132, 146). In one embodiment, each of the second-type first-tier tubular dielectric spacers 821B can include a respective annular top surface that contacts a bottom surface of a bottommost second-tier insulating layer 232 within the second-tier alternating stack (232, 246). In one embodiment, each of the third-type first-tier tubular dielectric spacers 821C can include a respective annular top surface that contacts an annular bottom surface of a respective one of the third-type second-tier tubular dielectric spacers 822C. In one embodiment, each of the third-type second-tier tubular dielectric spacers 822C can include a respective annular top surface that contacts a bottom surface of a bottommost third-tier insulating layer 332 within the third-tier alternating stack (332, 346).

[0150] Referring to ​ An additional dielectric material layer and an additional metal interconnect structure can be formed over the contact level dielectric layer 80. The additional dielectric material layer can include at least one via level dielectric layer, at least one additional line level dielectric layer, and / or at least one additional line and via level dielectric layer. The additional metal interconnect structure can include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed over the contact level dielectric layer 80 is referred to herein as a memory side dielectric material layer 960. The additional metal interconnect structure is collectively referred to as a memory side metal interconnect structure 980. The memory side dielectric material layer 960 includes a bit line level dielectric material layer that embeds bit lines that are a subset of the memory side metal interconnect structure 980.

[0151] Metal bonding pads, which are referred to herein as memory side bonding pads 988, can be formed at the top most level of the memory side dielectric material layer 960. The memory side bonding pads 988 can be electrically connected to the memory side metal interconnect structure 980 as well as various nodes of the three-dimensional memory array including the alternating stack of insulating layers 32 and electrically conductive layers 46 and the memory opening fill structures 58. Through the above described steps, the memory die 900 is formed.

[0152] In one embodiment, the memory die 900 can include a three-dimensional memory array underlying the first dielectric material layer 110 and including an alternating stack of insulating layers 32 and electrically conductive layers 46, a two-dimensional array of memory openings 49 extending vertically through the alternating stack, and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and including respective vertical stacks of memory elements and respective vertical semiconductor channels 60, a two-dimensional array of drain contact via structures 88 electrically connected to respective ones of the vertical semiconductor channels 60 via respective drain regions 63; and a two-dimensional array of layer contact via structures 86 electrically connected to respective ones of the electrically conductive layers 46, a subset of the electrically conductive layers serving as word lines of the three-dimensional memory array.

[0153] Referring to ​ A logic die 700 can be provided. In this case, the peripheral circuitry 720 can be formed on a logic side substrate 709, which can be a semiconductor substrate. The peripheral circuitry 720 can be configured to control operation of the memory array within the memory die 900. The logic side metal interconnect structure 780 embedded within the logic side dielectric material layer 760 can be formed over the logic side substrate 709, which can include a semiconductor substrate, to form the logic die 700. The logic die 700 also includes logic side bonding pads 788 embedded within the logic side dielectric material layer 760.

[0154] A bonded assembly can be formed by bonding the logic die 700 with the memory die 900. The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bond pads 788 to the memory-side bond pads 988. The bonding between the memory die 900 and the logic die 700 can be performed with a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), through a die-to-bond process, or through a die-to-die bonding process. The logic-side bond pads 788 within each logic die 700 can be bonded to the memory-side bond pads 988 within a respective memory die 900. In alternative embodiments, the logic die 700 can be omitted if the peripheral circuitry 720 is formed on the substrate 9 of the memory die 900.

[0155] Referring to ​ The carrier substrate 9 can optionally be removed, for example, by grinding, polishing, cleaving, an isotropic etching process, and / or an anisotropic etching process. If a polishing process such as a chemical mechanical polishing process is employed to remove the carrier substrate 9, the stop insulating layer 106 can be subsequently employed as a polishing stop material layer. If an etching process such as a wet etching process is employed to remove the carrier substrate 9, the stop insulating layer 106 can be subsequently employed as an etching stop material layer. If the source layer 110 formation described above is omitted, the stop insulating layer 106 and the underlying bottom portion of the memory film 50 can also be removed, and a top source contact layer can be formed in contact with the exposed bottom portion of the vertical semiconductor channel 60.

[0156] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a semiconductor structure is provided that includes: a first-tier alternating stack (132, 146) of first-tier insulating layers 132 and first-tier conductive layers 146; a second-tier alternating stack (232, 246) of second-tier insulating layers 232 and second-tier conductive layers 246 overlying the first-tier alternating stack (132, 146); a memory opening 49 vertically extending through the first-tier alternating stack (132, 146) and the second-tier alternating stack (232, 246); a memory opening fill structure 58 located in the memory opening 49 and including a memory film 50 and a vertical semiconductor channel 60; a first contact via structure 861 contacting one of the first-tier conductive layers 146; a first-tier tubular dielectric spacer 821 including a first inner sidewall contacting a first cylindrical surface segment of the first contact via structure 861, and including a first outer sidewall contacting each of the first-tier conductive layers 146 overlying the one of the first-tier conductive layers 146; a second-tier tubular dielectric spacer 822 including a second inner sidewall contacting a second cylindrical surface segment of the first contact via structure 861, and including a second outer sidewall contacting each of the second-tier conductive layers 246; a first-tier pillar structure (such as a second-type first-tier pillar structure 831B or a third-type first-tier pillar structure 831C) vertically extending through each of the first-tier conductive layers 146 in the first-tier alternating stack (132, 146) and having a top surface coplanar with a topmost surface of the first-tier alternating stack (132, 146); and an additional first-tier tubular dielectric spacer 821 laterally surrounding the first-tier pillar structure (such as the second-type first-tier pillar structure 831B or the third-type first-tier pillar structure 831C) and having a same material composition and a same lateral thickness as the first-tier tubular dielectric spacer 821.

[0157] In one embodiment, the semiconductor structure further includes a peripheral circuit 720, wherein the first contact via structure 861 is electrically connected to the peripheral circuit 720, and the first-tier pillar structure (831B or 831C) includes a dummy pillar not electrically connected to the peripheral circuit 720.

[0158] In one embodiment, the memory opening fill structure 58 has a stepped vertical cross-sectional profile including a first tapered surface extending through the first-tier alternating stack (132, 146), a second tapered surface extending through the second-tier alternating stack (232, 246), and a first horizontal connecting surface connecting the first tapered surface and the second tapered surface and lying in a horizontal plane including a top surface of a first-tier pillar structure such as a second-type first-tier pillar structure 831B or a third-type first-tier pillar structure 831C.

[0159] In one embodiment, the semiconductor structure includes a contact-level dielectric layer 80 overlying the second-tier alternating stack (232, 246). A top surface of the first contact via structure 861 lies in a horizontal plane including a top surface of the contact-level dielectric layer 80; and a portion of the first contact via structure 861 embedded in the contact-level dielectric layer 80 is in direct contact with the contact-level dielectric layer 80.

[0160] In one embodiment, an annular top surface of the first-tier tubular dielectric spacer 821 lies in a horizontal plane including a topmost surface of the first-tier alternating stack (132, 146); and an annular top surface of the second-tier tubular dielectric spacer 822 lies in a horizontal plane including a topmost surface of the second-tier alternating stack (232, 246). In one embodiment, an annular bottom surface of the second-tier tubular dielectric spacer 822 is in contact with the annular top surface of the first-tier tubular dielectric spacer 821.

[0161] In one embodiment, the semiconductor structure includes: a second contact via structure 862 contacting one of the second-tier conductive layers 246; and an additional second-tier tubular dielectric spacer such as a second-type second-tier tubular dielectric spacer 822B laterally surrounding and contacting the second contact via structure 862 and contacting each of the second-tier conductive layers 246 overlying the one of the second-tier conductive layers 246. In one embodiment, a first-tier pillar structure such as a second-type first-tier pillar structure 831B underlies the second contact via structure 862, is vertically spaced apart from the second contact via structure and has an area overlap with the second contact via structure in a plan view.

[0162] In one embodiment, the semiconductor structure includes: a third-tier alternating stack (332, 236) of third-tier insulating layers 332 and third-tier conductive layers 346 overlying the second-tier alternating stack (232, 246), wherein the memory opening fill structures 58 and the first contact via structures 861 vertically extend through the third-tier alternating stack (332, 236); and third-tier tubular dielectric spacers (such as first-type third-tier tubular dielectric spacers 823A) including third inner sidewalls contacting third cylindrical surface segments of the first contact via structures 861 and including third outer sidewalls contacting each of the third-tier conductive layers 346.

[0163] In one embodiment, the semiconductor structure includes: a second-tier pillar structure (such as third-type second-tier pillar structure 832C) vertically extending through the second-tier alternating stack (232, 246) and having a top surface coplanar with a topmost surface of the second-tier alternating stack (232, 246) and having a bottom surface contacting a top surface of a first-tier pillar structure (such as third-type first-tier pillar structure 831C); and an additional second-tier tubular dielectric spacer (such as third-type second-tier tubular dielectric spacer 822C) laterally surrounding the second-tier pillar structure (such as third-type second-tier pillar structure 832C) and having a same material composition and a same lateral thickness as the second-tier tubular dielectric spacer (such as first-type second-tier tubular dielectric spacer 822A). In one embodiment, an annular bottom surface of the additional second-tier tubular dielectric spacer (such as third-type second-tier tubular dielectric spacer 822C) contacts an annular top surface of the additional first-tier tubular dielectric spacer (such as third-type first-tier tubular dielectric spacer 821C).

[0164] In one embodiment, the semiconductor structure includes a source layer 110 underlying the first-tier alternating stack (132, 146), wherein the vertical semiconductor channel 60 contacts a surface of the source layer 110. In one embodiment, the first-tier pillar structure (e.g., second-type first-tier pillar structure 831B or third-type first-tier pillar structure 831C) comprises a material selected from a semiconductor material, a carbon-based material including atomic percentage of carbon atoms greater than 80%, or a polymeric material.

[0165] In one embodiment, the first-tier pillar structures, such as the second-type first-tier pillar structures 831B, include a bottom surface that contacts a top surface of a bottommost first-tier insulating layer 132 within the first-tier alternating stack (132, 146), and include a top surface that contacts a bottom surface of a bottommost second-tier insulating layer 232 within the second-tier alternating stack (232, 246). In one embodiment, the first-tier tubular dielectric spacer 821 includes an annular bottom surface that contacts a top surface of a bottommost first-tier insulating layer 132 within the first-tier alternating stack (132, 146), and includes an annular top surface that contacts a bottom surface of a bottommost second-tier insulating layer 232 within the second-tier alternating stack (232, 246).

[0166] In one embodiment, the semiconductor structure further includes support pillar structures 20 extending through the first alternating stack and the second alternating stack, where the support pillar structures 20 have a different material composition than the first-tier pillar structures (831B or 831C).

[0167] While the foregoing is directed to particular preferred embodiments, it is understood that the disclosure is not limited thereto. Various modifications can be made by those skilled in the art, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not mutually exclusive. Unless explicitly stated otherwise, the word “comprising” or “containing” contemplates all embodiments in which the word “consisting essentially of’ or the word “consisting of’ is substituted for the word “comprising” or “containing.” Whenever two or more elements are listed in the same paragraph or different paragraphs in connection with alternative embodiments, a Markush group is also implicitly disclosed consisting of the list of elements. Whenever a dependent verb “comprise” is used in the present disclosure to describe the formation of an element or the performance of a process step, embodiments in which the element is not formed or the process step is not performed are also clearly contemplated, provided that the resulting device or apparatus is capable of providing an equivalent result. Thus, whenever the formation of such an element or the performance of such a process step is omitted, the auxiliary verb “comprise” should also be interpreted as “may” or “may, or can not,” as applied to the formation of an element or the performance of a process step, these equivalent results including slightly superior results and slightly inferior results. Where embodiments employing a particular structure and / or configuration are exemplified in the present disclosure, it is understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not explicitly prohibited or otherwise known to be impossible to one of ordinary skill in the art. If publications, patent applications, and / or patents are cited in this text, each of the documents in the series of documents can be expressly incorporated by reference in its entirety.

Claims

1. A semiconductor structure comprising: a first-tier alternating stack of first-tier insulative layers and first-tier conductive layers; a second-tier alternating stack of second-tier insulative layers and second-tier conductive layers overlying the first-tier alternating stack; a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack; a memory opening fill structure located in the memory opening and comprising a memory film and a vertical semiconductor channel; a first contact via structure contacting one of the first-tier conductive layers; a first-tier tubular dielectric spacer comprising a first inner sidewall contacting a first cylindrical surface segment of the first contact via structure, and comprising a first outer sidewall contacting each of the first-tier conductive layers overlying the one of the first-tier conductive layers; a second-tier tubular dielectric spacer comprising a second inner sidewall contacting a second cylindrical surface segment of the first contact via structure, and comprising a second outer sidewall contacting each of the second-tier conductive layers; a first-tier pillar structure vertically extending through each of the first-tier conductive layers in the first-tier alternating stack, and having a top surface coplanar with a topmost surface of the first-tier alternating stack; and an additional first-tier tubular dielectric spacer laterally surrounding the first-tier pillar structure, and having a same material composition and a same lateral thickness as the first-tier tubular dielectric spacer.

2. The semiconductor structure of claim 1, further comprising a peripheral circuit, wherein the first contact via structure is electrically connected to the peripheral circuit, and the first-tier pillar structure comprises a dummy pillar not electrically connected to the peripheral circuit.

3. The semiconductor structure of claim 1, further comprising a contact-level dielectric layer overlying the second-tier alternating stack, wherein: a top surface of the first contact via structure is located within a horizontal plane comprising a top surface of the contact-level dielectric layer; and a portion of the first contact via structure embedded in the contact-level dielectric layer is in direct contact with the contact-level dielectric layer.

4. The semiconductor structure of claim 1, wherein: a ring-shaped top surface of the first-tier tubular dielectric spacer is located within a horizontal plane comprising the topmost surface of the first-tier alternating stack; and a ring-shaped top surface of the second-tier tubular dielectric spacer is located within a horizontal plane comprising a topmost surface of the second-tier alternating stack.

5. The semiconductor structure of claim 4, wherein a ring-shaped bottom surface of the second-tier tubular dielectric spacer is in contact with the ring-shaped top surface of the first-tier tubular dielectric spacer.

6. The semiconductor structure of claim 1, further comprising: ​ ​ a second contact via structure contacting one of the second tier conductive layers; and an additional second tier tubular dielectric spacer laterally surrounding and contacting the second contact via structure and contacting each of the second tier conductive layers overlying the one of the second tier conductive layers.

7. The semiconductor structure of claim 6, wherein the first tier pillar structure underlies, is vertically spaced apart from, and has an area overlap with the second contact via structure in a plan view.

8. The semiconductor structure of claim 1, further comprising: a third tier alternating stack of third tier insulating layers and third tier conductive layers overlying the second tier alternating stack, wherein the memory opening fill structure and the first contact via structure vertically extend through the third tier alternating stack; and a third tier tubular dielectric spacer comprising a third inner sidewall contacting a third cylindrical surface section of the first contact via structure and comprising a third outer sidewall contacting each of the third tier conductive layers.

9. The semiconductor structure of claim 8, further comprising: a second tier pillar structure vertically extending through the second tier alternating stack and having a top surface coplanar with a topmost surface of the second tier alternating stack and having a bottom surface contacting the top surface of the first tier pillar structure; and an additional second tier tubular dielectric spacer laterally surrounding the second tier pillar structure and having a same material composition and a same lateral thickness as the second tier tubular dielectric spacer.

10. The semiconductor structure of claim 9, wherein an annular bottom surface of the additional second tier tubular dielectric spacer is in contact with an annular top surface of the additional first tier tubular dielectric spacer.

11. The semiconductor structure of claim 1, wherein the memory opening fill structure has a stepped vertical cross-sectional profile comprising a first tapered surface extending through the first tier alternating stack, a second tapered surface extending through the second tier alternating stack, and a first horizontal connecting surface connecting the first tapered surface and the second tapered surface and lying in a horizontal plane comprising the top surface of the first tier pillar structure.

12. The semiconductor structure of claim 1, wherein the first tier pillar structure comprises a material selected from a semiconductor material, a carbon-based material comprising atomic percent of carbon atoms greater than 80%, or a polymeric material.

13. The semiconductor structure of claim 1, wherein: the first tier pillar structure comprises a bottom surface contacting a top surface of a bottommost first tier insulating layer within the first tier alternating stack and comprises a top surface contacting a bottom surface of a bottommost second tier insulating layer within the second tier alternating stack; and the first tier pillar structure comprises a bottom surface contacting a top surface of a bottommost first tier insulating layer within the first tier alternating stack and comprises a top surface contacting a bottom surface of a bottommost second tier insulating layer within the second tier alternating stack; and The first-tier tubular dielectric spacer includes an annular bottom surface contacting a top surface of a bottommost first-tier insulating layer within the first-tier alternating stack, and includes an annular top surface contacting a bottom surface of a bottommost second-tier insulating layer within the second-tier alternating stack.

14. The semiconductor structure of Claim 1, further comprising a support pillar structure extending through the first-tier alternating stack and the second-tier alternating stack, wherein the support pillar structure has a different material composition than the first-tier pillar structures.

15. A method of forming a semiconductor structure, the method comprising: forming a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers over a substrate; forming first-tier sacrificial memory opening fill structures extending through the first-tier alternating stack; forming first-tier pillar structures in the first-tier alternating stack, wherein the first-tier pillar structures include first-type first-tier pillar structures that do not extend through a bottommost first-tier sacrificial material layer within the first-tier alternating stack, and second-type first-tier pillar structures that extend through each first-tier sacrificial material layer within the first-tier alternating stack; forming a second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers over the first-tier alternating stack; forming second-tier sacrificial memory opening fill structures extending through the second-tier alternating stack; forming second-tier pillar structures in the second-tier alternating stack, wherein the second-tier pillar structures include first-type second-tier pillar structures formed on top surfaces of the first-type first-tier pillar structures, and second-type second-tier pillar structures that do not extend through a bottommost second-tier sacrificial material layer within the second-tier alternating stack; replacing the second-tier sacrificial memory opening fill structures and the second-tier sacrificial memory opening fill structures with memory opening fill structures including vertical semiconductor channels and memory films; replacing the first-tier sacrificial material layers and the second-tier sacrificial material layers with first-tier conductive layers and second-tier conductive layers, respectively; replacing the first-type second-tier pillar structures and the first-type first-tier pillar structures with first-contact via structures contacting top surfaces of one of the first-tier conductive layers; and replacing the second-type second-tier pillar structures with second-contact via structures.

16. The method of Claim 15, wherein the second-type first-tier pillar structures do not change in structure or material composition during formation of the first-contact via structures and the second-contact via structures.

17. The method of Claim 15, wherein the second-type second-tier pillar structures have an area overlap with the second-type first-tier pillar structures in plan view, and are vertically spaced apart from the second-type first-tier pillar structures.

18. The method of Claim 15, further comprising: forming first-tier via cavities in the first-tier alternating stack; and forming first-tier tubular dielectric spacers in peripheral regions of the first-tier via cavities, wherein: the first-tier tubular dielectric spacers include annular bottom surfaces contacting top surfaces of bottommost first-tier insulating layers within the first-tier alternating stack, and include annular top surfaces contacting bottom surfaces of bottommost second-tier insulating layers within the second-tier alternating stack. Each of the first-tier pillar structures is formed directly on and within a respective one of the first-tier tubular dielectric spacers.

19. The method of claim 15, further comprising: forming a third-tier alternating stack of third-tier insulating layers and third-tier sacrificial material layers over the second-tier alternating stack; forming third-tier sacrificial memory opening fill structures through the third-tier alternating stack; and forming third-tier pillar structures in the third-tier alternating stack, wherein the third-tier pillar structures include first-type third-tier pillar structures formed on top surfaces of the first-type second-tier pillar structures, second-type third-tier pillar structures formed on top surfaces of the second-type second-tier pillar structures, and third-type third-tier pillar structures that do not extend through a bottommost third-tier sacrificial material layer within the third-tier alternating stack, wherein: the third-tier sacrificial material layers are replaced with third-tier electrically conductive layers; a portion of the first contact via structures replaces the first-type third-tier pillar structures; and a portion of the second contact via structures replaces the second-type third-tier pillar structures.

20. The method of claim 19, wherein: the first-tier pillar structures further include third-type first-tier pillar structures that extend through each of the first-tier sacrificial material layers in the first-tier alternating stack; the second-tier pillar structures further include third-type second-tier pillar structures that extend through each layer in the second-tier alternating stack and contact the first-tier pillar structures; a portion of third contact via structures that contact one of the third-tier electrically conductive layers replaces the third-type third-tier pillar structures; and the third-type first-tier pillar structures and the second-tier pillar structures do not change in material composition or shape during formation of the first contact via structures, the second contact via structures, and the third contact via structures.

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