Backside power supply for hybrid height standard cell circuits

Abstract

A semiconductor structure includes a first plurality of backside power rail interconnects within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. The first isolation region is located between a first cell height region of the substrate and a second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. A second isolation region electrically separates adjacent power rail interconnects.

Description

BACKGROUND

[0001] The present invention relates generally to the field of semiconductor devices, and more specifically to powering active devices.

[0002] Modern integrated circuits (ICs) are composed of transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from one another, but are later interconnected to form functional circuits. Typical interconnect structures include lateral interconnects (e.g., metal lines (wirings)) and vertical interconnects (e.g., vias and contacts). Integrated circuits are powered through power rails, which are located in metal layers of the integrated circuit. For example, a bottom metal layer (M0 or M1) can include multiple metal lines, such as a VDD power rail and a VSS power rail.

[0003] As IC dimensions continue to shrink, backside power rails (BPRs), i.e., power rails formed in the backside of a wafer (typically underneath transistor “fins”), and backside power supply (“backside” underneath transistor substrate) have been proposed to mitigate design challenges and enable technology scaling beyond 5nm technology nodes. BPR technology can free up resources for dense logic connections that limit modern processor performance, enable further scaling of standard logic cells by removing overhead in the area occupied by power rails, and allow for thicker, low-resistance power rails, thereby enabling lower voltage (IR) drop. However, existing BPR technology still faces various challenges, including wiring resistance, alignment margin, layout flexibility, and package density. SUMMARY

[0004] By providing a semiconductor structure and a method of manufacturing the same, the disadvantages of the prior art are overcome and additional advantages are provided, the semiconductor structure comprising a self-aligned backside interconnect structure for flexible cell height integration.

[0005] According to one embodiment of the present disclosure, a semiconductor structure comprises: a first plurality of backside power rail interconnects located within a first cell height region of a substrate; a second plurality of backside power rail interconnects located in a second cell height region of the substrate; a first isolation region located between the first cell height region of the substrate and the second cell height region of the substrate, the first isolation region electrically separating the first cell height region and the second cell height region; and a second isolation region located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent power rail interconnects.

[0006] According to another embodiment of the disclosure, a method of forming a semiconductor structure includes forming a first plurality of backside power rail interconnects within a first unit height region of a substrate; forming a second plurality of backside power rail interconnects within a second unit height region of the substrate; forming a first isolation region between the first unit height region of the substrate and the second unit height region of the substrate, the first isolation region electrically separating the first unit height region and the second unit height region; and forming a second isolation region between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent power rail interconnects. BRIEF DESCRIPTION OF DRAWINGS

[0007] The detailed description set forth below is intended as a non-limiting example of the present application, and is better understood in connection with the accompanying drawings, in which:

[0008] FIG. 1 is a top view of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, showing different cross-sectional views for describing embodiments of the disclosure;

[0009] FIG. 2A is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line Y1-Y1’ shown in FIG. 1A, showing formation of a nanosheet stack; FIG. 1

[0010] FIG. 2B is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line Y2-Y2’ shown in FIG. 1A; FIG. 1

[0011] FIG. 2C is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line X-X’ shown in FIG. 1A; FIG. 1

[0012] FIG. 3A is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line Y1-Y1’ shown in FIG. 1A, showing patterning of the nanosheet stack to form a plurality of nanosheet fins; FIG. 1

[0013] FIG. 3B is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line Y2-Y2’ shown in FIG. 1A; FIG. 1

[0014] FIG. 3C is a cross-sectional view of the semiconductor structure according to an embodiment of the disclosure, taken along the line X-X’ shown in FIG. 1A; FIG. 1

[0015] FIG. 2A-2C ​​​​​​is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 2A illustrating deposition of a sacrificial liner between nanosheet fins;

[0016] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown in FIG. 2B ;

[0017] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 2C ;

[0018] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 2A-2C after performing an etch process to extend the first openings and form backside trenches;

[0019] FIG. 2A-2C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown in FIG. 3A-3C ;

[0020] FIG. 3A is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 1 ;

[0021] FIG. 3B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1 after performing an etch process to extend the first openings and form backside trenches;

[0022] FIG. 3C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown in FIG. 1 ;

[0023] FIG. 2A-2C is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 2A-2C ;

[0024] FIG. 3A is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1 after performing steps of removing the planarization layer, removing the sacrificial liner, forming an STI liner within the first openings, forming STI regions, and removing the hardmask layer;

[0025] FIG. 3B is a cross-sectional view of the semiconductor structure taken alongFIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0026] FIG. 4A-4C is a cross-sectional view of the semiconductor structure taken along the line FIG. 4A a cross-sectional view of the semiconductor structure taken along the line X-X’ shown;

[0027] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 4B a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown;

[0028] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 4C a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0029] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 4A-4B a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown;

[0030] FIG. 5A-5C is a cross-sectional view of the semiconductor structure taken along the line FIG. 5A a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown;

[0031] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 5B a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0032] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 5C a cross-sectional view of the semiconductor structure taken along the line X-X’ shown;

[0033] FIG. 1 is a top view of the semiconductor structure according to embodiments of the disclosure;

[0034] FIG. 5A-5C is a cross-sectional view of the semiconductor structure taken along the line FIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown;

[0035] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line FIG. 5A-5Ca cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0036] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0037] FIG. 6A-6C is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6A a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0038] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6B a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0039] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6C a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0040] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6A-6B a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0041] FIG. 7A-7C is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6A-6C a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0042] FIG. 7A is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0043] FIG. 7B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0044] FIG. 7C is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 1 a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0045] FIG. 6A-6B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown; FIG. 6A-6B a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown;

[0046] FIG. 6A-6B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1A, after forming a first backside ILD according to embodiments of the disclosure; FIG. 6A-6B

[0047] FIG. 6A-6B is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown in FIG. 1A, after forming a first backside ILD according to embodiments of the disclosure; FIG. 6A-6B

[0048] FIG. 6A-6B is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 1A, after forming a first backside ILD according to embodiments of the disclosure; FIG. 6A-6C

[0049] FIG. 8A-8C is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1A, after recessing the first BILD to expose the placeholder layer according to embodiments of the disclosure; FIG. 8A

[0050] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2’ shown in FIG. 1A, after recessing the first BILD to expose the placeholder layer according to embodiments of the disclosure; FIG. 8B

[0051] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 1A, after recessing the first BILD to expose the placeholder layer according to embodiments of the disclosure; FIG. 8C

[0052] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1A, after selectively removing the placeholder layer according to embodiments of the disclosure; FIG. 7A-7C

[0053] FIG. 7A-7C is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in FIG. 1A, after selectively removing the placeholder layer according to embodiments of the disclosure; FIG. 7A-7C

[0054] FIG. 8A-8C is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 1A, after selectively removing the placeholder layer according to embodiments of the disclosure; FIG. 8C

[0055] FIG. 9A to FIG. 9D is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1’ shown in FIG. 1A, after backside metallization according to embodiments of the disclosure; FIG. 9A

[0056] FIG. 1 is a cross-sectional view of the semiconductor structure taken along the line X-X’ shown in FIG. 1A, after backside metallization according to embodiments of the disclosure; FIG. 9B ​​​​​​​​​​The cross-sectional view of the semiconductor structure taken by line Y2-Y2' is shown.

[0057] FIG. 1 According to embodiments of this disclosure FIG. 9C The cross-sectional view of the semiconductor structure taken by line X-X' is shown.

[0058] FIG. 1 This is a top view of a semiconductor structure according to an embodiment of the present disclosure;

[0059] FIG. 9D According to embodiments of this disclosure, after forming the back-side power supply network (BSPDN), along... FIG. 8A-8C The cross-sectional view of the semiconductor structure cut by line Y1-Y1' is shown.

[0060] FIG. 1 According to embodiments of this disclosure FIG. 9A The cross-sectional view of the semiconductor structure taken by line Y2-Y2' is shown; and

[0061] FIG. 9D According to embodiments of this disclosure FIG. 10A-10C The cross-sectional view of the semiconductor structure 100 taken by line X-X' is shown.

[0062] The accompanying drawings are not necessarily drawn to scale. They are merely schematic representations and not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, similar numbers denote similar elements. Detailed Implementation

[0063] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative examples of the claimed structures and methods that can be implemented in various forms. The invention can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0064] For purposes of the description hereinafter, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as shown in the drawings, and their derivatives, as appropriate. Terms such as "over", "under", "top", "bottom", "positioned on" or "positioned on top" shall mean that the first element (e.g., first structure) is present on the second element (e.g., second structure) wherein intervening elements (e.g., contact face structure) can be present between the first element and the second element. The term "direct contact" means that the first element (e.g., first structure) and the second element (e.g., second structure) are connected without an intermediate conductive, insulating, or semiconductive layer at the contact site of the two elements.

[0065] To avoid obscuring the presentation of embodiments of the application, in the following detailed description some processing steps or operations that are known in the art can be combined together for presentation and explanation purposes and can not be described in detail in some cases. In other cases, some processing steps or operations that are known in the art can not be described at all. It should be understood that the following description focuses on the distinctive features and elements of various embodiments of the application.

[0066] It should be understood that, although the disclosed embodiments include a detailed description of exemplary nanosheet FET architectures with silicon nanosheets and silicon germanium nanosheets, implementations of the teachings herein are not limited to the particular FET architectures described herein. Rather, embodiments of the application are capable of being implemented in conjunction with any other type of FET device now known or later developed.

[0067] Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same, including backside metal contacts and backside power rails (BPRs) that are self-aligned with respect to shallow trench isolation (STI) and diffusion break isolation regions. The BPRs are electrically separated from each other by the STI at N2P spaces and by the diffusion break isolation regions at the interfaces between regions of different cell heights. The self-aligned BPRs are arranged in a grid shape, which allows for forming a semiconductor structure with a heterogeneous or mixed cell height.

[0068] Embodiments of a semiconductor structure that can form a backside interconnect structure are described in detail below by reference to the accompanying drawings in FIG. 10A

[0069] Reference is now made to FIG. 1 , which shows a top view of a semiconductor structure 100 at an intermediate step during a semiconductor manufacturing process, in accordance with embodiments of the present disclosure. In particular, FIG. 10B ​Different cross-sectional views of the semiconductor structure 100 to be used to describe embodiments of the present disclosure are depicted. The cross-sectional views are taken along line X-X’, line Y1-Y1’, and line Y2-Y2’. As shown in the figures, line X-X’ represents a cut along a nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1’ represents a cut across source / drain regions in the NFET region 12 and PFET region 16 of a first cell height region 30A of the semiconductor structure 100, and line Y2-Y2’ represents a cut across source / drain regions in the NFET region 12 and PFET region 16 of a second cell height region 30B of the semiconductor structure 100. According to embodiments, the cell height of the first cell height region 30A is less than the cell height of the second cell height region 30B.

[0070] In one or more embodiments, the cross-sectional views taken along line Y1-Y1’ and line Y2-Y2’ can also include a view of the NFET region 12 and / or PFET region 16 and a view of the N2P space (i.e., N-P boundary) 14 between the NFET and PFET regions 12, 16.

[0071] FIG. 1 A cross-sectional view of the semiconductor structure 100 after formation of the nanosheet stack 10 according to embodiments of the present disclosure is shown. In this embodiment, FIG. 10C is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1’ as FIG. 1 shown; FIG. 12A-12C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2’ as FIG. 9C shown; and FIG. 9C is a cross-sectional view of the semiconductor structure 100 taken along line X-X’ as FIG. 9C shown.

[0072] In the depicted example, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 positioned above the substrate 102, and a first semiconductor layer 106 disposed above the first sacrificial layer 104. According to embodiments, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked with respect to each other in a direction perpendicular to the substrate 102, as shown in the figures.

[0073] The substrate 102 can be, for example, a bulk substrate, which can be made of any known semiconductor material, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium gallium arsenide phosphide. Typically, the substrate 102 can be approximately a few hundred microns thick, but is not so limited. In other embodiments, the substrate 102 can be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, in which a buried insulator layer separates a base substrate from a top semiconductor layer.

[0074] With continued reference to FIG. 9C , according to embodiments, the first sacrificial layer 104 can be formed on the substrate 102 using an epitaxial growth process. For example, in the described embodiments, the first sacrificial layer 104 is formed by epitaxially growing a layer of SiGe having a germanium concentration that varies between about 15 atomic percent to about 35 atomic percent. In preferred embodiments, the first sacrificial layer 104 is made of epitaxially grown SiGe having a germanium concentration of about 30 atomic percent. Although in some embodiments, the first sacrificial layer 104 can be made of silicon dioxide (SiO2). In such embodiments, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 can be an SOI wafer, in which the first sacrificial layer 104 is a buried oxide (BOX) having a thickness that ranges from about 20 nm to about 100 nm, and all ranges therebetween. In one or more embodiments, the first sacrificial layer 104 can act as an etch stop layer during subsequent substrate removal.

[0075] Similarly, the first semiconductor layer 106 is formed by epitaxially growing a layer of Si having a thickness that varies between about 30 nm to about 150 nm, although other thicknesses are within the contemplated scope of the present disclosure.

[0076] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as“epitaxial growth and / or deposition” and“epitaxially formed and / or grown” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the growing semiconductor material has the same or substantially similar crystallographic properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move across and orient themselves to the crystal lattice arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material formed on the deposition surface has the same or substantially similar crystallographic properties as the deposition surface. For example, epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} crystal orientation. In some embodiments, the epitaxial growth and / or deposition process selectively forms on a semiconductor surface and does not deposit material on a dielectric surface such as a silicon dioxide or silicon nitride surface.

[0077] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). The temperature range of the epitaxial deposition process can range from 500 °C to 900 °C. While higher temperatures generally result in faster deposition, faster deposition can result in crystal defects and film cracking.

[0078] Several different precursors can be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas sources for the epitaxial semiconductor material deposition include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source including, but not limited to, germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. While an epitaxial silicon-germanium alloy layer can be formed utilizing a combination of these gas sources. A carrier gas such as hydrogen, helium, and argon can be used.

[0079] In the depicted embodiment, as shown in the figure, the alternating sequence of sacrificial semiconductor material layers and semiconductor channel material layers are vertically stacked on top of one another in a direction perpendicular to the substrate 102 to form a nanosheet stack 10. Specifically, the alternating sequence includes a nanosheet stack sacrificial layer 108 positioned above the first semiconductor layer 106, a second sacrificial semiconductor layer 110 positioned above the nanosheet stack sacrificial layer 108, and a semiconductor channel layer 112 positioned above the second sacrificial semiconductor layer 110. In the example shown in the figure, the alternating second sacrificial semiconductor layer 110 and semiconductor channel layer 112 are formed in the (nanosheet) stack 10 above the nanosheet stack sacrificial layer 108. The term "sacrificial" as used herein means a layer or other structure (or a portion thereof) that is removed prior to completion of the final device.

[0080] For example, in the described example, a portion of the second sacrificial semiconductor layer 110 is to be removed from the stack in the channel region of the device to allow the semiconductor channel layer 112 to be released from the nanosheet stack 10. Notably, although the second sacrificial semiconductor layer 110 and the semiconductor channel layer 112 are made of silicon germanium (SiGe) and silicon (Si), respectively, in the present example, any combination of sacrificial and channel materials can be used in accordance with the present technology. For example, a selective etching technique can alternatively be employed that allows Si to be used as a sacrificial material between SiGe channel layers.

[0081] With continued reference to FIG. 10C The first (sacrificial) layer in the stack, i.e., the nanosheet stack sacrificial layer 108, is formed on the first semiconductor layer 106 using an epitaxial growth process. For example, in the described embodiment, the nanosheet stack sacrificial layer 108 is formed by epitaxially growing a layer of SiGe having a higher concentration of germanium, with the concentration of germanium varying between about 45 atomic percent to about 70 atomic percent. In a preferred embodiment, the nanosheet stack sacrificial layer 108 includes a layer of SiGe having a germanium concentration of about 55 atomic percent. The higher concentration of germanium atoms allows the nanosheet stack sacrificial layer 108 to be selectively removed relative to the remaining alternating layers of the nanosheet stack 10, as will be described in detail below. By way of example only, the nanosheet stack sacrificial layer 108 can be formed having different thicknesses from about 5 nm to about 20 nm, with thicknesses greater than 20 nm and less than 5 nm also being used.

[0082] Generally, the layers in the nanosheet stack 10 (e.g., SiGe layers and Si layers) can be formed by epitaxial growth using the first semiconductor layer 106 as a seed layer. For example, the second sacrificial semiconductor layers 110 are formed by epitaxial growth of SiGe layers. In this embodiment, the germanium concentration of the second sacrificial semiconductor layers 110 can vary from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, each of the second sacrificial semiconductor layers 110 includes a SiGe layer having a germanium concentration of about 30 atomic percent.

[0083] To continue building the nanosheet stack 10, the semiconductor channel layers 112 are formed by epitaxial growth of Si layers. As shown in the figure, the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 have substantially similar or identical thicknesses. The nanosheet stack 10 is grown by forming the (SiGe) sacrificial semiconductor layers 110 and the (Si) semiconductor channel layers 112 in an alternating fashion on the nanosheet stack sacrificial layers 108. Thus, each of the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 in the nanosheet stack 10 can be formed in the same manner as described above (e.g., using an epitaxial growth process) with thicknesses varying from about 6 nm to about 12 nm, although other thicknesses are within the contemplated scope of the present disclosure.

[0084] Thus, each layer in the nanosheet stack 10 has nanoscale dimensions and can therefore also be referred to as a nanosheet. Moreover, as described above, the (Si) semiconductor channel layers 112 in the nanosheet stack 10 will be used to form the channel layers of the device. Thus, the dimensions of the semiconductor channel layers 112 determine the dimensions of the channel region of the semiconductor structure 100.

[0085] As described above, the goal is to produce a stack of alternating (sacrificial and channel) SiGe and Si layers on a wafer. The number of layers in the stack can be customized according to the particular application. Thus, the configurations depicted and described herein are merely examples intended to illustrate the present technology. For example, the current nanosheet stack 10 can contain more or fewer layers than shown in the figures.

[0086] The nanosheet stack 10 can be used to produce a gate-all-around device that includes a vertically stacked nanosheet of semiconductor channel material for either a positive channel field effect transistor (hereinafter “PFET”) or a negative channel field effect transistor (hereinafter “NFET”).

[0087] FIG. 10C According to embodiments of the present disclosure, a cross-sectional view of the semiconductor structure 100 is shown after the nanosheet stack 10 is patterned to form a plurality of nanosheet fins (hereinafter “nanosheet fins”). In this embodiment, FIG. 11A-11C is along FIG. 11Aa cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' shown in FIG. 1 is along FIG. 11B a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2' shown in FIG. 1 is along FIG. 11C a cross-sectional view of the semiconductor structure 100 taken along the line X-X' shown in

[0088] In the depicted embodiment, a hard mask material (e.g., silicon nitride) is deposited over the nanosheet stack 10 in FIG. 1 by using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 202 can be formed with different thicknesses from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm can also be used.

[0089] After deposition of the hard mask layer 202, lithographic patterning is performed on the deposited hard mask layer 202 to form a hard mask of a plurality of individual fins. According to an exemplary embodiment, reactive ion etching (RIE) can be used to etch through the nanosheet stack 10 FIG. 11A-11C to form nanosheet fins 302. The etching process can continue until an upper portion of the first semiconductor layer 106 located between adjacent nanosheet fins 302 is removed, thereby forming a plurality of trenches (not shown). The plurality of trenches (not shown) formed during the lithographic patterning process can then be filled with one or more insulating materials to form shallow trench isolation (STI) regions, which will be described in detail below. It is noted that FIG. 12A-12C the nanosheet fins 302 depicted in FIG. 11A-11C correspond to the first unit height region 30A of the semiconductor structure 100 shown in FIG. 12A the nanosheet fins 302 depicted in FIG. 1 correspond to the second unit height region 30B of the semiconductor structure 100 shown in

[0090] Referring now to FIG. 12B , a cross-sectional view of the semiconductor structure 100 is shown after deposition of a sacrificial liner 420 between the nanosheet fins 302 according to an embodiment of the disclosure. In this embodiment, FIG. 1 is along FIG. 12C a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1' shown in FIG. 1 is along FIG. 11A-11C a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2' shown in FIG. 13A-13C is along FIG. 12A-12C a cross-sectional view of the semiconductor structure 100 taken along the line X-X' shown in

[0091] In the depicted embodiment, a sacrificial liner 420 is formed along the opposing sidewalls of each nanosheet fin 302. The sacrificial liner 420 reduces the space between adjacent nanosheet fins 302 (i.e., fin-to-fin spacing). The sacrificial liner 420 can include a layer of SiO2, AlOx, TiOx, TiN, or similar material placed on the semiconductor structure 100 using any suitable deposition method. For example, the sacrificial liner 420 can be formed by using a conformal deposition process followed by anisotropic RIE. In example embodiments, the sacrificial liner 420 can have a different thickness from about 3 nm to about 15 nm, including ranges therebetween. In the depicted embodiment, after the sacrificial liner 420 is deposited, the portions of the uppermost surface of the first semiconductor layer 106 that are not covered by the sacrificial liner 420 remain exposed, as shown in FIG. 13A .

[0092] Referring now to FIG. 1 , a cross-sectional view of the semiconductor structure 100 is shown after lithographic opening of the N2P space, in accordance with embodiments of the present disclosure. In this embodiment, FIG. 13B is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in FIG. 1 ; FIG. 13C is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in FIG. 1 ; and FIG. 12A-12C is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in FIG. 12A-12C .

[0093] In accordance with embodiments, an organic planarization layer (OPL) or simply planarization layer 504 can be deposited on the semiconductor structure 100. The planarization layer 504 can be made of any organic planarization material that is capable of effectively preventing damage to the underlying layers during subsequent etch processes. The planarization layer 504 can include, but is not limited to, an organic polymer including C, H, and N. In one embodiment, the organic planarization material can be free of silicon (Si). In another embodiment, the organic planarization material can be free of Si and fluorine (F). As defined herein, a material is free of an atomic element when the level of that atomic element in the material is at or below trace levels that can be detected using analytical methods available in the art. Examples of non-limiting organic planarization materials for forming the planarization layer 504 can include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. The planarization layer 504 can be deposited by, for example, spin coating.

[0094] With continued reference to FIG. 12A-12CAfter the photolithography process followed by the etching process on the semiconductor structure 100, portions of the planarization layer 504 are removed from the semiconductor structure 100 corresponding to the region of the N2P space 14 shown in FIG. 12A-12C FIG. 6B. As described above with reference to FIG. 12A-12C FIG. 6A, the N2P space 14 is located between the NFET and PFET regions 12, 16 of the semiconductor structure 100. Thus, the planarization layer 504 is removed only from the region between the nanosheet fins 302 corresponding to the N2P space 14. As shown in FIG. 14A-14C FIG. 6B, portions of the planarization layer 504 remain between adjacent nanosheet fins 302 located within the same polarity region, i.e., either the NFET or PFET region 12, 16 as shown in FIG. 14A FIG. 6A. After the planarization layer 504 is removed from the N2P space 14, a first opening 508 remains in the semiconductor structure 100. The first opening 508 exposes an uppermost surface of the first semiconductor layer 106 located within the N2P space 14 FIG. 1 ) and not covered by the sacrificial liner 420. In some embodiments, the etching of the planarization layer 504 can be performed by, for example, OPL RIE including trace dot detection.

[0095] Referring now to FIG. 14B FIG. 7, a cross-sectional view of the semiconductor structure 100 is shown after an etching process to extend the first opening 508 and form a backside recess, in accordance with embodiments of the disclosure. In this embodiment, FIG. 1 is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in FIG. 14C FIG. 7A; FIG. 1 is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in FIG. 10A-10C FIG. 7B; and FIG. 14A-14C is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in FIG. 15A-15C FIG. 7C.

[0096] In this embodiment, an etching process, such as reactive ion etching (RIE), can be performed on the semiconductor structure 100 to increase the size of the first opening 508. As shown in FIG. 15A FIG. 7A, after the etching process, the first opening 508 extends through the top portion of the first semiconductor layer 106, the first sacrificial layer 104, and the substrate 102, providing a backside trench region for the semiconductor structure 100. In one or more embodiments, the first opening 508 can have a (positive) tapered etch profile that narrows in a direction toward the substrate 102.

[0097] Referring now to FIG. 1According to embodiments of this disclosure, the process involves removing the planarization layer 504, removing the sacrificial liner 420, forming the STI liner 708 within the first opening 508, forming the STI region 710, and removing the hard mask layer 202. FIG. 15B Following the steps of ), a cross-sectional view of the semiconductor structure 100 is shown. In this embodiment, FIG. 1 It is along FIG. 15C The cross-sectional view of the semiconductor structure 100 taken by line Y1-Y1' is shown. FIG. 1 It is along FIG. 16A-16C The cross-sectional view of the semiconductor structure 100 taken by line Y2-Y2' is shown; and FIG. 15A-15C It is along FIG. 16A The cross-sectional view of the semiconductor structure 100 taken by line X-X' is shown.

[0098] The planarization layer 504 can be removed from the semiconductor structure 100 using suitable techniques (including but not limited to oxygen plasma, nitrogen plasma, hydrogen plasma, or other carbon stripping or ashing processes) with minimal or no damage to the underlying layers. Similarly, the sacrificial liner 420 can be selectively removed from the semiconductor structure 100 using, for example, an SC1 wet cleaning process.

[0099] The planarization layer 504 and sacrificial liner 420 are removed to expose or reveal the nanosheet fins 302. In one or more embodiments, the STI liner 708 can be conformally deposited at the first opening 508 ( FIG. 1 Within. For example, the STI liner 708 can be formed by conformal deposition (e.g., CVD) of a first dielectric material (such as silicon nitride (SiN)), which clamps the first opening 508. FIG. 16B The narrower bottom portion extends toward the substrate 102. It should be noted that after the sacrificial liner 420 is removed, the first opening 508 ( FIG. 1 The STI liner 708 may include a top portion having a first critical size (CD1) and a bottom portion having a second critical size (CD2). After the STI liner 708 is deposited, since CD2 is smaller than CD1, the STI liner 708 substantially fills the first opening 508. FIG. 16C The bottom part of ). First opening 508 ( FIG. 1 The remaining space within the top (wider) portion of the semiconductor structure 100 can be filled with a second dielectric material to form an STI region 710 in the semiconductor structure 100 for electrically isolating the nanosheet fin 302.

[0100] The second dielectric material can be formed, for example, by CVD of a dielectric material including, but not limited to, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. In some embodiments, the critical dimension (CD2) of the bottom portion of the first opening 508( FIG. 15A-15C ) can have a larger dimension, allowing the second dielectric material forming the STI region 710 to be deposited within the bottom portion of the first opening 508( FIG. 16A-16C ). After the STI region 710 is formed, the hard mask layer 202( FIG. 15A-15C ) can be removed from the semiconductor structure 100 using any suitable etching technique.

[0101] Reference is now made to FIG. 17A-17C , according to embodiments of the disclosure, after forming the dummy gate 810, forming a sacrificial hard mask 820 over the dummy gate 810, removing the nanosheet stack sacrificial layer 108, forming the sidewall spacers 804 and the bottom dielectric isolation layer 806, recessing the nanosheet fin 302, and forming the inner spacer 808, a cross-sectional view of the semiconductor structure 100 is shown. In this embodiment, FIG. 17A is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in FIG. 1 ; FIG. 17B is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in FIG. 1 ; and FIG. 17C is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in FIG. 1 .

[0102] In the depicted embodiment, the dummy gate 810 and the sacrificial hard mask 820 form a sacrificial gate structure of the semiconductor structure 100. The process of forming the dummy gate 810 and the sacrificial hard mask 820 is typical and well known in the art. In one or more embodiments, the dummy gate 810 is formed of amorphous silicon (a-Si) and the sacrificial hard mask 820 is formed of silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations.

[0103] After the dummy gate 810 and the sacrificial hard mask 820 are deposited on the semiconductor structure 100, the dummy gate 810 and the sacrificial hard mask 820 are patterned as shown in the figure. As known to those skilled in the art, the process of patterning the dummy gate 810 typically involves exposing a pattern on a photoresist layer (not shown) and transferring the pattern to the sacrificial hard mask 820 and the dummy gate 810 using known photolithography and RIE processes. The dummy gate 810 is formed and patterned over the uppermost semiconductor channel layer 112. Although not shown in the figure, the dummy gate 810 is also formed along the sidewalls of the nanosheet fin 302.

[0104] The process continues by removing the nanosheet stack sacrificial layer 108 FIG. 17D ) from the semiconductor structure 100. According to embodiments, the nanosheet stack sacrificial layer 108 is selectively removed relative to the first semiconductor layer 106, the second sacrificial semiconductor layer 110, the semiconductor channel layer 112, the dummy gate 810, and the sacrificial hard mask 820. For example, a dry etch process with high selectivity can be used to selectively remove the nanosheet stack sacrificial layer 108 ​ ) from the semiconductor structure 100. Removing the nanosheet stack sacrificial layer 108 creates a second opening (not shown) in the semiconductor structure 100.

[0105] Subsequently, a spacer material can be deposited on the semiconductor structure 100. The spacer material is deposited along the sidewalls of the dummy gate 810 and the sacrificial hard mask 820 to form sidewall spacers 804. The spacer material forming the sidewall spacers 804 substantially fills the second opening (not shown) created after removing the nanosheet stack sacrificial layer 108 ​ ) from the semiconductor structure 100. The sidewall spacers 804 can be formed using a spacer pull-down formation process. The sidewall spacers 804 can also be formed using a sidewall image transfer (SIT) spacer formation process, which includes spacer material deposition followed by a directional RIE on the deposited spacer material. In one or more embodiments, the spacer material deposited between the bottom surface of the nanosheet fin 302 and the substrate 102 can be referred to as a bottom dielectric isolation layer 806. In some embodiments, the bottom dielectric isolation layer 806 and the sidewall spacers 804 can be composed of different materials.

[0106] Non-limiting examples of various spacer materials used to form the sidewall spacers 804 and the bottom dielectric isolation layer 806 can include conventional low-k materials such as Si02, SiOC, SiOCN, or SiBCN. In general, the thickness of the sidewall spacers 804 can vary between about 5 nm to about 20 nm, including ranges therebetween.

[0107] As known to those skilled in the art, the sidewall spacers 804 can be used as a mask to recess portions of the nanosheet fin 302 that are not covered by the sidewall spacers 804 and the dummy gate 810. For example, a RIE process can be used to recess portions of the nanosheet fin 302 that are not under the sidewall spacers 804 and the dummy gate 810. According to embodiments, the nanosheet fin 302 can be recessed until the top portion of the bottom dielectric isolation layer 806 is reached. In one or more embodiments, the recessing of the nanosheet fin 302 forms a third opening (or source / drain recess) 840 in the semiconductor structure 100.

[0108] With continued reference to ​ , an outer portion of each second sacrificial semiconductor layer 110 is selectively recessed using, for example, a selective etching process such as a hydrogen chloride (HC1) gas etch. Preferably, the selective etching process used to recess the second sacrificial semiconductor layer 110 is capable of etching silicon germanium without etching silicon. The interior spacers 808 can be formed within the recessed cavities (not shown) formed after etching the second sacrificial semiconductor layer 110. For example, the interior spacers 808 can be formed by conformal deposition of an interior spacer dielectric material that bridges the recessed cavities (not shown) formed after etching the second sacrificial semiconductor layer 110. The interior spacers 808 can be formed using any suitable dielectric material such as silicon dioxide, silicon nitride, SiOC, SiOCN, SiBCN, and can include a single layer or multiple layers of dielectric material. An isotropic etch can then be performed to remove excess interior spacer material from other areas of the semiconductor structure 100.

[0109] As shown in ​ , the outer sidewalls of the interior spacers 808 are vertically aligned with the semiconductor channel layer 112 and, thus, with the upper portions of the sidewall spacers 804 located on the opposite sidewalls of the dummy gate 810.

[0110] Referring now to ​ , according to embodiments of the disclosure, a cross-sectional view of the semiconductor structure 100 is shown after forming a sacrificial placeholder layer 920 for forming a backside contact and forming a source / drain region 930. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in ​ ; and ​ is a top view of the semiconductor structure 100.

[0111] Although not shown in the figures, it is noted that prior to forming the placeholder layer 920, a lithography process can be performed on the semiconductor structure 100, followed by an etching process (e.g., RIE) to selectively remove portions of the first semiconductor layer 106, which further increases the size of the third opening 840 ​ ) of the third opening 840 (not shown). The selective etching of the first semiconductor layer 106 can be performed according to the desired location of the subsequently formed backside metal contacts.

[0112] According to embodiments, a layer of any material suitable for forming the placeholder layer 920 can be deposited within the enlarged third opening 840 (not shown). In one or more embodiments, the material forming the placeholder layer 920 can include, for example, SiGe, AlOx, TiOx, etc. In particular, the material forming the placeholder layer 920 substantially fills the recess formed within the first semiconductor layer 106 after further increasing the size of the third opening 840 (not shown). As the name implies, the placeholder layer 920 acts as a placeholder for the subsequently formed backside metal contacts.

[0113] The process is continued by forming source / drain regions 930. The source / drain regions are formed within the NFET and PFET regions 12, 16 (shown in ​ ) of the semiconductor structure 100 using methods well known in the art, as known to those skilled in the art. For example, the source / drain regions 930 can be formed using an epitaxial layer growth process on the exposed end portions of the semiconductor channel layer 112.

[0114] The source / drain regions 930 can be formed on opposite sides of the nanosheet fin 302 in direct contact with the end portions of the semiconductor channel layer 112 and the end portions of the inner spacers 808. The top portions of the source / drain regions 930 can include a diamond shape, which is a result of different growth rates in epitaxial deposition processes inherent to each crystallographic orientation plane of the material forming the source / drain regions 930. In other embodiments, the source / drain regions 930 can have a shape other than the diamond shape shown in ​ .

[0115] Reference is now made to ​ , a top view of the semiconductor structure 100 showing exemplary locations 940 of the subsequently formed backside metal contacts obtained within the first and second cell height regions 30A, 30B by implementing the previously described process steps.

[0116] Reference is now made to ​ , a cross-sectional view of the semiconductor structure 100 is shown after completion of the front-end-of-line (FEOL) process steps, according to embodiments of the present disclosure. In this embodiment, ​ is along ​a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown.

[0117] The semiconductor structure 100 as shown in FIG. 1 has been formed using known semiconductor fabrication operations. Accordingly, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can be described in detail herein or not described in detail. Moreover, the various tasks and process steps described herein can be incorporated in a more comprehensive process or process sequence, in accordance with some embodiments. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps are only mentioned briefly herein or are omitted entirely without providing the well-known process details. ​

[0118] After forming the source / drain regions 930, an interlayer dielectric layer 1020 can be formed to fill the voids in the semiconductor structure 100. The interlayer dielectric layer 1020 can be formed by, for example, CVD of a dielectric material. Non-limiting examples of dielectric materials that form the interlayer dielectric layer 1020 can include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

[0119] As known to those skilled in the art, after depositing the interlayer dielectric layer 1020, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100. This process exposes the top surface of the dummy gate 810( ​ ) in preparation for a replacement metal gate process that will be described in detail below.

[0120] Accordingly, the dummy gate 810( ​ ) is removed from the semiconductor structure 100. As known in the art, in a gate-last fabrication process, the removed dummy gate is later replaced with a high-k metal gate structure (i.e., replacement gate 1010). According to embodiments, the second sacrificial semiconductor layer 110( ​ ) can also be removed from the semiconductor structure 100 using known etching processes (including, for example, RIE, wet etching, or dry gas (HCI) etching). Removal of the sacrificial semiconductor layer 110( ​ ) creates a cavity (not shown) between the inner spacers 808, which is subsequently filled with a corresponding gate dielectric and work function metal to form the high-k metal gate structure or replacement gate 1010, as shown in FIG. 1.​​ as shown.

[0121] Replacement gate 1010 includes a gate dielectric, such as hafnium oxide (Hf02), zirconium dioxide (Zr02), hafnium-aluminum oxide (HfAlOx), hafnium-lanthanum oxide (HfLaOx), and the like, as well as one or more work function metals, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and conductive metals including, for example, aluminum (Al), tungsten (W), or cobalt (Co). Replacement gate 1010 surrounds (stacks) semiconductor channel layer 112. In one or more embodiments, a gate cap (not shown) can be formed over replacement gate 1010. After formation of replacement gate 1010, chemical mechanical polishing (CMP) can be performed to remove excess material and polish the upper surface of semiconductor structure 100.

[0122] In one or more embodiments, a gate cut process can be performed on semiconductor structure 100 to isolate gate structures from different CMOS cells. In this process, a gate cut region (not shown in the figures) can be formed before or after the replacement metal gate (RMG), and then filled with a dielectric material such as Si02, SiN, SiBCN, SiOCN, SiOC, SiC, and the like. A similar process can be performed to form a diffusion break isolation region 1040 between two adjacent “active” nanosheet fins 302, as shown in ​ to prevent unwanted current flow between two active nanosheet fins 302 of semiconductor structure 100. It is noted that diffusion break region 1040 extends deeper than etch stop layer 104, which helps to form a self-aligned backside metal line.

[0123] Reference is now made to ​ , showing a cross-sectional view of semiconductor structure 100 after intermediate- of-line (MOL) contact patterning and metallization and formation of back-end-of-line (BEOL) interconnect layer 1110 and carrier wafer 1112, in accordance with an embodiment of the present disclosure. In this embodiment, ​ is a cross-sectional view of semiconductor structure 100 taken along line Y1-Y1’ as shown in ​ is a cross-sectional view of semiconductor structure 100 taken along line Y2-Y2’ as shown in ​ is a cross-sectional view of semiconductor structure 100 taken along line Y2-Y2’ as shown in ​ is a cross-sectional view of semiconductor structure 100 taken along line X-X’ as shown in ​ is a cross-sectional view of semiconductor structure 100 taken along line X-X’ as shown in ​ is a cross-sectional view of semiconductor structure 100 taken along line X-X’ as shown in

[0124] In the depicted embodiment, a plurality of conductive structures including metal contacts 1102 are formed in the semiconductor structure 100 for electrically connecting the FEOL devices to subsequently formed metal layers. The process of forming the metal contacts 1102 is standard and well known in the art. Typically, the process includes forming a trench (not shown) within the interlayer dielectric layer 1020 and then filling the trench with a conductive material or combination of conductive materials to form the metal contacts 1102. In one or more embodiments, the conductive material filling the metal contacts 1102 can include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0125] The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal evaporation or e-beam evaporation, or sputtering. A planarization process (e.g., CMP) is performed to remove any conductive material from the upper surface of the semiconductor structure 100. In particular, in the depicted example, the metal contacts 1102 can include an uppermost source / drain contact (CA) extending to the source / drain regions 930 and a gate contact (CB) to the replacement gate 1010 (not shown).

[0126] According to embodiments, a BEOL interconnect layer 1110 can then be formed over and electrically connected to the FEOL device layer 30 of the semiconductor structure 100. Although not shown in the figures, the BEOL interconnect layer 1110 typically includes contacts, insulating layers (dielectric), metal layers, and bonding sites for chip-to-package connections, as is well known to those skilled in the art. As noted above, the various steps of manufacturing semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many of the conventional steps will only be briefly mentioned or omitted entirely herein without providing well-known processing details.

[0127] According to embodiments, after the BEOL interconnect layer 1110 is formed, the semiconductor structure 100 (i.e., semiconductor wafer) is bonded to a carrier wafer (or auxiliary substrate) 1112. The carrier wafer 1112 can be used as a reinforcement substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 1112 can be achieved through conventional wafer bonding processes, such as dielectric-to-dielectric bonding or Cu-to-Cu bonding.

[0128] Accordingly, the carrier wafer 1112 can include a silicon oxide layer or a SiCN layer, or any other layer suitable for use in direct bonding techniques applied in state-of-the-art packaging technologies. The device wafer is bonded to the carrier wafer 1112 through such known direct bonding techniques, thereby obtaining a semiconductor-on-insulator structure. ​The components are shown. Although not shown in the figure, the wafer is flipped after the device wafer is bonded to the carrier wafer 1112.

[0129] Now for reference ​ According to embodiments of this disclosure, in the removal of substrate 102 ( ​ Following this, a cross-sectional view of the semiconductor structure 100 is shown. In this embodiment, ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line Y1-Y1' is shown. ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line Y2-Y2' is shown; and ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line X-X' is shown.

[0130] In the depicted embodiment, after the wafer is flipped (not shown), the substrate 102 can be removed using conventional grinding, CMP, and selective etching processes (including wet or dry etching techniques). ​ In one or more embodiments, a polishing process is performed until the substrate 102 is substantially removed from the semiconductor structure 100 with only a few micrometers of Si remaining. Subsequently, an optional CMP process may be used to reduce thickness errors, and finally, a highly selective Si etching process is used to selectively remove the remaining substrate 102 from the semiconductor structure 100 relative to the first sacrificial layer 104 and the STI liner 708. In the depicted embodiment, the first sacrificial layer 104 acts as an etch stop layer during the highly selective Si removal process, preventing excessive Si etching that could damage the replacement gate 1010 and the source / drain region 930.

[0131] Now for reference ​ According to embodiments of this disclosure, after removing the first sacrificial layer 104 and removing... ​ Following the remaining Si-containing region (i.e., the first semiconductor layer 106) shown, a cross-sectional view of the semiconductor structure 100 is illustrated. In this embodiment, ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line Y1-Y1' is shown.

[0132] ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line Y2-Y2' is shown; and ​ It is along ​ The cross-sectional view of the semiconductor structure 100 taken by line X-X' is shown.

[0133] Any suitable etching technique can be used to selectively remove the first sacrificial layer 104 ​ ) relative to the STI liner 708. In embodiments where the first sacrificial layer 104 ​ ) is made of SiGe, a hot SCI or dry HCl etch can be used to remove the first sacrificial layer 104. In embodiments where the first sacrificial layer 104 ​ ) is made of SiO2, a DHF wet clean can be used to remove the first sacrificial layer 104.

[0134] In one or more embodiments, processing similar to that described in ​ for removing the substrate 102 can be performed to remove the first semiconductor layer 106 from the semiconductor structure 100. Selective removal of the first sacrificial layer 104 and the first semiconductor layer 106 ​ exposes the placeholder layer 920, the STI liner 708, and the bottom dielectric isolation layer 806.

[0135] Referring now to ​ , a cross-sectional view of the semiconductor structure 100 is shown after forming a first backside interlayer dielectric (BILD) 1402, in accordance with embodiments of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in ​ ; and ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in ​ .

[0136] The first BILD 1402 is formed using standard methods and materials, such as those described above for forming the interlayer dielectric layer 1020 shown in ​ . As shown in ​ , the first BILD 1402 is disposed over and in direct contact with the exposed surfaces of the placeholder layer 920, the STI liner 708, and the bottom dielectric isolation layer 806. In exemplary embodiments, the thickness of the first BILD 1402 can vary between about 40 nm to about 300 nm, including ranges therebetween. In one or more embodiments, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100 after forming the first BILD 1402. After the planarization process, the exposed surface of the STI liner 708 is substantially coplanar with the first BILD 1402.

[0137] Referring now to ​, a cross-sectional view of the semiconductor structure 100 is shown after recessing the first BILD 1402 to expose the placeholder layer 920, according to embodiments of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in ​ ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in ​ ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in ​

[0138] The first BILD 1402 can be recessed using any selective etching technique known in the art, such that the process of recessing the first BILD 1402 does not affect the STI liner 708 or the diffusion break isolation region 1040, as shown in the figures. In an exemplary embodiment, a wet DHF etch process can be performed to selectively etch the first BILD 1402.

[0139] Reference is now made to ​ , a cross-sectional view of the semiconductor structure 100 is shown after selectively removing the placeholder layer 920 shown in ​ ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y1-Y1’ shown in ​ ​ is a cross-sectional view of the semiconductor structure 100 taken along the line Y2-Y2’ shown in ​ ​ is a cross-sectional view of the semiconductor structure 100 taken along the line X-X’ shown in ​

[0140] In the depicted embodiment, a fourth opening 1602 is formed in the semiconductor structure 100 after removing the placeholder layer 920 ​ . As shown in ​ , the fourth opening 1602 (i.e., a backside contact via) exposes one or more of the source / drain regions 930. More specifically, the area of the source / drain regions 930 exposed by the fourth opening 1602 corresponds to a first surface or bottom surface of one or more of the source / drain regions 930, the first surface or bottom surface being opposite a second surface or top surface that is in contact with the interlayer dielectric layer 1020. As can be observed in the figures, the fourth opening 1602 exposes the first surface or bottom surface of at least one source / drain region 930 that is adjacent to another source / drain region 930 that is in electrical contact with the metal contact 1102. Suitable techniques for removing the placeholder layer 920 from the semiconductor structure 100 are described above.​​​​​​​​ Exemplary techniques of the present disclosure can include, but are not limited to, dry HCl etching, which can cause minimal or no damage to the underlying layers.

[0141] Referring now to ​ , a cross-sectional view of the semiconductor structure 100 is shown after backside metallization, in accordance with embodiments of the present disclosure. In this embodiment, ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1’ as shown in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2’ as shown in ​ ; ​ is a cross-sectional view of the semiconductor structure 100 taken along line X-X’ as shown in ​ ; and ​ is a top view of the semiconductor structure 100 (after wafer flip).

[0142] In accordance with embodiments, backside metal is deposited in the semiconductor structure 100, substantially filling the fourth openings 1602( Figures 16A-16C ) to form backside metal contacts 1710 to one or more source / drain regions 930. In one or more embodiments, the backside metal contacts 1710 can be formed between adjacent source / drain regions 930 located within the NFET (i.e., N2N space) region 12( Figure 1 ) or the PFET (i.e., P2P space) region 16( Figure 1 ) of the semiconductor structure 100. In the depicted embodiment, the backside metal contacts 1710 are formed in direct contact with the first surface or bottom surface of one or more source / drain regions 930.

[0143] As shown in the figures, a layer of the same backside metal is further deposited over the filled fourth openings 1602 (i.e., backside metal contacts 1710) and over the first BILD 1402. The layer of backside metal formed over the backside metal contacts 1710 and the first BILD 1402 substantially surrounds the protruding portions of the STI liner 708 and the diffusion break isolation regions 1040. Thus, the protruding portions of the STI liner 708 and the diffusion break isolation regions 1040 electrically separate the deposited backside metal, thereby forming a backside power rail (BPR) region in the semiconductor structure 100. In the depicted embodiment, the backside power rail (BPR) 1720 can be formed in the semiconductor structure 100 simultaneously with the backside metal contacts 1710.

[0144] In one or more embodiments, the semiconductor structure 100 can include an NFET device. In such embodiments, the BPR 1720 includes a VSS rail embedded in the NFET region of the semiconductor structure 100 for electrical connection to the N-type source / drain regions 930 through the backside metal contacts 1710 (located between adjacent N-type source / drain regions 930). In other embodiments, the semiconductor structure 100 can include a PFET device, where the BPR 1720 includes a VDD rail embedded in the PFET region of the semiconductor structure 100 for electrical connection to the (P-type) source / drain regions 930 through the backside metal contacts 1710 (located between adjacent P-type source / drain regions 930).

[0145] It should be noted that the source / drain regions 930 connected to the backside power rail (i.e., the BPR 1720) are not connected to the BEOL interconnect layer 1110. More specifically, as shown in the figures, at least one BPR 1720 is electrically connected to the source / drain regions 930 of the transistor through the backside metal contacts 1710, with the bottom dielectric isolation layer 806, the first BILD 1402, and / or the STI region 702 electrically isolating the at least one BPR 11720 from the source / drain regions 930 that are not electrically connected to the backside metal contacts 1710.

[0146] The backside metal used to form the backside metal contacts 1710 and the BPR 1720 can include similar conductive materials and can be formed using similar deposition processes as those used to form the metal contacts 1102. In some embodiments, forming the backside metal contacts 1710 and the BPR 1720 can include depositing layers of, for example, silicide liners (such as Ti, Ni, NiPt), adhesion metal liners (such as TiN), and low-resistance metals (such as Ru, Co, W, or Cu). The thickness of the layers of backside material extending over the backside metal contacts 1710 and the first BILD 1402 can vary between about 30 nm to about 200 nm, including ranges therebetween.

[0147] Referring now to Figure 17D , a top-down view of the semiconductor structure 100 after wafer flip shows the self-aligned backside BPRs 1720 formed within respective first and second cell height regions 30A and 30B. Each BPR 1720 is separated by the STI liner 708 at the N2P space 14 Figure 1 ) and by the diffusion break isolation region 1040 at the interface between the first and second cell height regions 30A and 30B, thereby providing Figure 17DThe mesh-like configuration shown is illustrated. Therefore, the proposed embodiments provide a semiconductor structure with a hybrid and flexible cell height. Additionally, embodiments of this disclosure can provide other benefits, such as allowing the patterning of complex back-side metal interconnects (BM1) without using back-side EUV or other high-cost lithography processes, forming very small BM1s in side-by-side spaces, and increasing VDD / VSS coupling capacitance.

[0148] Now for reference Figures 18A-18C According to an embodiment of this disclosure, a cross-sectional view of the semiconductor structure 100 is shown after the back-side power supply network (BSPDN) 1830 has been formed. In this embodiment, Figure 18A Is along as Figure 1 The cross-sectional view of the semiconductor structure 100 taken by line Y1-Y1' is shown. Figure 18B Is along as Figure 1 The cross-sectional view of the semiconductor structure 100 taken by line Y2-Y2' is shown; and Figure 18C Is along as Figure 1 The cross-sectional view of the semiconductor structure 100 taken by line X-X' is shown.

[0149] In one or more embodiments, voids within the semiconductor structure 100 can be filled by depositing a second BILD 1802 that is substantially similar to the first BILD 1702. Furthermore, the second BILD 1802 can electrically isolate the BPR 1720. Planarization can be performed in the semiconductor structure 100 after the deposition of the second BILD 1802. In the depicted embodiment, a back-side via (or BV1) 1815 is formed within the second BILD 1802 for electrically connecting one or more BPRs 1720 and BSPDN 1830. It should be noted that the process for forming the back-side via 1815 is standard and well known in the art.

[0150] In one or more embodiments, the structure of the BSPDN 1830 can be manufactured according to known techniques and can be selected based on the exact function of the transistor arrangement.

[0151] It should be noted that the BEOL interconnect layer 1320 in the semiconductor structure 100 manufactured according to the disclosed technology is separated from the BSPDN 2130, thereby increasing the path resources for signal routing in the BEOL layer in the semiconductor structure 100.

[0152] Accordingly, embodiments of the present disclosure provide a semiconductor structure including a first plurality of backside power rail interconnects located within a first unit height region of a substrate, electrically separated from a second plurality of backside power rail interconnects located in a second unit height region of the substrate by a first isolation region, wherein each of the first plurality of backside power rail interconnects and each of the second plurality of backside power rail interconnects are separated from each other by a second isolation region. In other words, the first isolation region located between the first unit height region of the substrate and the second unit height region of the substrate electrically separates the first unit height region and the second unit height region, while the second isolation region located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects electrically separates the adjacent power rail interconnects.

[0153] According to embodiments, the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are configured in a mesh shape arrangement. In one or more embodiments, the first isolation region includes a diffusion break isolation region and the second isolation region includes a dielectric liner extending from a shallow trench isolation region, the dielectric liner having a critical dimension smaller than a critical dimension of the shallow trench isolation region.

[0154] According to embodiments, each of the first plurality of backside power rail interconnects and each of the second plurality of backside power rail interconnects are electrically separated at N2P space by a dielectric liner extending from a shallow trench isolation region.

[0155] According to embodiments, the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are located between a device region and a backside power supply network.

[0156] According to embodiments, the backside power supply network is electrically connected to at least one of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects by a backside via.

[0157] According to embodiments, one or more of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are electrically connected to the device region by a backside metal contact.

[0158] According to embodiments, the device region further includes a front-of-line layer including one or more field effect transistors, the front-of-line layer electrically connected to a back-end-of-line interconnect layer located on a first side of the front-of-line layer by a plurality of metal contacts, the one or more field effect transistors electrically separated by a shallow trench isolation region.

[0159] According to embodiments, the semiconductor structure further includes a carrier wafer in contact with a surface of the back-end-of-line interconnect layer, the surface opposite the one or more field effect transistors and the plurality of metal contacts.

[0160] The method as described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having many unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers, with leads that are affixed to the main board or other higher level carrier) or in multi-chip packages (e.g., ceramic carriers that have either or both surface interconnections or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a main board, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer

[0161] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "optional" or "optionally" means that the subsequently described event or circumstance can or can not occur, and that the description includes instances where the event occurs and instances where it does not.

[0162] Spatially relative terms, such as "inner", "outer", "beneath", "below", "lower", "above", "upper", "top", "bottom" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0163] Approximating language, such as "approximately," "about," and "substantially" as used herein, can be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as "about," "approximately," and "substantially," are not to be limited to the specific value recited. In at least some instances, an approximate language can correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein, unless context or language indicates otherwise. "About" applied to a value of a specified range means that the value can be the exact value or ±10% from the stated value, unless otherwise indicated, depending upon the instrument's precision.

[0164] The description of various embodiments of the present application is presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the embodiments to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art, without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: a first plurality of backside power rail interconnects located within a first cell height region of a substrate; a second plurality of backside power rail interconnects located within a second cell height region of the substrate; a first isolation region located between the first cell height region of the substrate and the second cell height region of the substrate, the first isolation region electrically separating the first cell height region and the second cell height region; and a second isolation region located between adjacent ones of the first plurality of backside power rail interconnects and between adjacent ones of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent ones.

2. The semiconductor structure of claim 1, wherein, the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are configured in a grid-like arrangement.

3. The semiconductor structure according to any of the preceding claims 1 to 2, wherein, the first isolation region comprises a diffusion break isolation region.

4. The semiconductor structure according to any of the preceding claims 1 to 3, wherein, the second isolation region comprises a dielectric liner extending from a shallow trench isolation region.

5. The semiconductor structure of claim 4, wherein, a critical dimension of the dielectric liner is less than a critical dimension of the shallow trench isolation region.

6. The semiconductor structure of claim 4, wherein, each of the first plurality of backside power rail interconnects and each of the second plurality of backside power rail interconnects are electrically separated at an N2P space by the dielectric liner extending from the shallow trench isolation region.

7. The semiconductor structure according to any of the preceding claims 1 to 6, wherein, the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are located between a device region and a backside power supply network.

8. The semiconductor structure of claim 7, wherein, the backside power supply network is electrically connected to at least one of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects by a backside via.

9. The semiconductor structure of claim 7, wherein, one or more of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are electrically connected to the device region by a backside metal contact.

10. The semiconductor structure of claim 8, wherein, the device region further comprises: a front-of-line layer comprising one or more field effect transistors, the front-of-line layer being electrically connected to a back-of-line interconnect layer on a first side of the front-of-line layer by a plurality of metal contacts, the one or more field effect transistors being electrically separated by the shallow trench isolation region.

11. The semiconductor structure of claim 10, further comprising: a carrier wafer in contact with a surface of the back-of-line interconnect layer opposite the one or more field effect transistors and the plurality of metal contacts.

12. A method of forming a semiconductor structure, comprising: forming a first plurality of backside power rail interconnects within a first cell height region of a substrate; forming a second plurality of backside power rail interconnects within a second cell height region of the substrate; forming a first isolation region between the first cell height region of the substrate and the second cell height region of the substrate, the first isolation region electrically separating the first cell height region and the second cell height region; and forming a second isolation region between adjacent ones of the first plurality of backside power rail interconnects and between adjacent ones of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent ones.

13. The method of claim 12, wherein, The first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are configured in a grid-like arrangement.

14. The method according to any of the preceding claims 12 to 13, wherein, The first isolation region comprises a diffusion break isolation region.

15. The method according to any of the preceding claims 12 to 14, wherein, The second isolation region comprises a dielectric liner extending from a shallow trench isolation region.

16. The method of claim 15, wherein, A critical dimension of the dielectric liner is less than a critical dimension of the shallow trench isolation region.

17. The method of claim 16, wherein, Each of the first plurality of backside power rail interconnects and each of the second plurality of backside power rail interconnects are electrically separated at an N2P space by the dielectric liner extending from the shallow trench isolation region.

18. The method according to any of the preceding claims 12 to 17, wherein, The first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are located between a device region and a backside power supply network.

19. The method of claim 18, wherein, The backside power supply network is electrically connected to at least one of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects through a backside via.

20. The method of claim 18, wherein, One or more of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are electrically connected to the device region through a backside metal contact.

21. The method of claim 18, wherein, The device region further comprises: forming a front-of-line layer, the front-of-line layer comprising one or more field effect transistors, the front-of-line layer being electrically connected to a back-end-of-line interconnect layer located on a first side of the front-of-line layer through a plurality of metal contacts, the one or more field effect transistors being electrically separated by the shallow trench isolation region.

22. The method of claim 21, further comprising: a carrier wafer in contact with a surface of the back-end-of-line interconnect layer opposite the one or more field effect transistors and the plurality of metal contacts.

23. The method of claim 21, further comprising: forming the one or more field effect transistors, wherein at least one of the one or more field effect transistors is located within the first cell height region and at least another of the one or more field effect transistors is located within the second cell height region; forming the first isolation region between the first cell height region and the second cell height region; forming the second isolation region within a space between field effect transistors of different polarity; removing the substrate to expose the first isolation region and the second isolation region; and forming the first plurality of backside power rail interconnects within the first cell height region and the second plurality of backside power rail interconnects within the second height region.

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