High-frequency CMOS ultrasonic transducer

Abstract

The invention relates to a high frequency CMOS ultrasonic transducer. In described examples of a CMOS IC, an ultrasonic transducer (1200) having a terminal is formed on a substrate (1230) of the IC. CMOS circuitry (1236) having an ultrasonic signal terminal is formed on the substrate. At least one metal interconnect layer (1238) overlies the ultrasound transducer and the CMOS circuitry. At least one metal interconnect layer connects the CMOS circuitry ultrasound signal terminal to the terminal of the ultrasound transducer.

Description

[0001] This application is a divisional application of Chinese patent application 202080081611.7 entitled "High-Frequency CMOS Ultrasonic Transducer", filed on October 1, 2020. Technical Field

[0002] This application relates to a high-frequency ultrasonic transducer formed within a complementary metal-oxide-semiconductor (CMOS) integrated circuit. Background Technology

[0003] Ultrasonic transducers and sensors are acoustic devices, which fall into three main categories: transmitters, receivers, and transceivers. Transmitters convert electrical signals into ultrasound, receivers convert ultrasound back into electrical signals, and transceivers can both transmit and receive ultrasound.

[0004] Ultrasonic transducers are used in systems to assess targets by interpreting reflected signals (similar to radar). The transmitted signal consists of short bursts of ultrasonic energy. After each burst, the electronics search for the return signal within a small time window corresponding to the time required for the energy to travel through the medium. Only signals received during this period are used for additional signal processing.

[0005] Medical ultrasound transducers (probes) come in various shapes and sizes to create cross-sectional images of different parts of the body. The transducer can pass over surfaces and make contact with the body. Arrays of ultrasound transducers can be used to sense fingerprints for access control, such as on laptops or mobile phones.

[0006] Ultrasonic sensors are widely used in automobiles as parking sensors to help drivers reverse into parking spaces. They are also being tested for many other automotive applications, including ultrasonic people detection and assisting autonomous UAV navigation. Summary of the Invention

[0007] In the described example of the CMOS IC, an ultrasonic transducer with terminals is formed on the IC substrate. A CMOS circuit system with ultrasonic signal terminals is formed on the substrate. At least one metal interconnect layer covers the ultrasonic transducer and the CMOS circuit system. The at least one metal interconnect layer connects the ultrasonic signal terminals of the CMOS circuit system to the terminals of the ultrasonic transducer.

[0008] Attached illustrations

[0009] Figure 1 is a cross-sectional view of an integrated circuit (IC) that includes a memory cell using a ferroelectric capacitor (FeCap) as a storage element.

[0010] Figure 2A , Figure 2B These are the corresponding top and side cross-sectional views of a row of FeCap used to form an ultrasonic transducer.

[0011] Figure 3 This is a cross-sectional view of a single simulated FeCap illustrating the simulated electric field around the FeCap.

[0012] Figure 4 yes Figure 3 Dispersion plotting of various patterns within the FeCap structure.

[0013] Figure 5 This is a cross-sectional view of the simulated oscillation within a row of FeCap shown in the figure.

[0014] Figure 6 This is a scatter plot of the guided mode operation of the diagram showing the frequency versus the FeCap pitch.

[0015] Figure 7 This is a cross-sectional view illustrating the simulated operation of an ultrasonic resonator formed by a row of FeCaps.

[0016] Figure 8 This is a cross-sectional view illustrating the simulated operation of an ultrasonic transmitter formed by a row of FeCaps.

[0017] Figure 9 This is a cross-sectional view of the FeCap ultrasonic transducer coupled to a water droplet.

[0018] Figure 10A , Figure 10B , Figure 10C These are schematic diagrams of various example FeCap connections.

[0019] Figure 11 This is a top view of an example FeCap ultrasonic transducer.

[0020] Figure 12 This is a cross-sectional view of an example packaged FeCap ultrasonic transducer.

[0021] Figure 13 This is a flowchart illustrating the operation of the ultrasonic transmitter on a CMOS IC. Detailed Implementation

[0022] In the accompanying drawings, the same elements are represented by the same reference numerals to maintain consistency.

[0023] Piezoelectric micromechanical ultrasonic transducer (PMUT) array technology is currently used for ultrasound imaging in medical applications to capture images of soft tissues such as muscles, internal organs, blood flow, and fetal observation. Improvements in microelectromechanical systems (MEMS) have led to ultrasonic transducers based on plate bending modes, offering significant improvements in bandwidth, cost, and yield compared to conventional large-scale thickness-mode PZT sensors. However, currently available PMUT-based transducers have limited operating frequencies, typically in the 2–14 MHz range, due to the constraints of their bending modes. Low-frequency operation results in low-resolution images. Furthermore, these arrays are typically fabricated on a substrate and then bonded to a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC), which includes electronics for controlling the array. This leads to complex packaging and integration issues.

[0024] Ferroelectric random access memory (FRAM) is a non-volatile memory technology that behaves similarly to DRAM (Dynamic Random Access Memory). Each individual bit can be accessed, but unlike EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash memory, FRAM does not require a dedicated sequence for writing data, nor does it require a high programming voltage. Each ferroelectric memory cell contains one or more ferroelectric capacitors (FeCap). Due to the influence of semi-permanent electric dipoles formed in the crystal structure of ferroelectric materials, the dielectric constant of ferroelectric capacitors is typically much higher than that of linear dielectrics. When an external electric field is applied across a ferroelectric dielectric, the dipoles tend to align themselves with the field direction. This is caused by tiny shifts in the positions of atoms, resulting in a shift in the charge distribution within the crystal structure. These tiny shifts in atomic positions produce a piezoelectric effect.

[0025] Ferroelectricity is a property of certain materials that exhibit spontaneous polarization, which can be reversed by applying an external electric field. Ferroelectric materials are typically in single-crystal or polycrystalline form and possess reversible spontaneous polarization within a certain temperature range. One known ferroelectric material is lead zirconate titanate (PZT), which is part of a solid solution formed between ferroelectric lead titanate and antiferroelectric lead zirconate. Different compositions are used for different applications; for memory applications, PZT is preferred as it is compositionally closer to lead titanate, while piezoelectric applications utilize the divergent piezoelectric coefficient associated with a quasi-isomorphic phase boundary found to be close to 50 / 50 composition.

[0026] As will be described in more detail below, FeCap can be used as a component to generate stress and strain within the CMOS IC itself to form an ultrasonic transducer device, thereby eliminating the need for a separate array substrate. A periodic array of FeCaps is arranged to create an acoustic waveguide that can guide the generated wave along the front-end process (FEOL) layer of the CMOS die. FEOL is the first part of IC fabrication, where individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. FEOL typically covers everything except the deposition of metal interconnect layers. The deposition of metal layers, intermediate dielectric layers, and vias is performed during back-end process (BEOL) processing.

[0027] By adjusting the dimensions of the FeCap array, waveguide properties can be manipulated to create reflectors and radiators that help guide acoustic waves generated by the piezoelectric activity of the FeCap array. The transducer can operate in transmit and / or receive modes. FeCap arrays can produce very high-frequency ultrasonic transducers truly integrated into CMOS technology for high-resolution, short-range applications. The examples described below operate at frequencies up to 700+ MHz.

[0028] Figure 1 is a cross-sectional view of a portion of a prior art integrated circuit 100, which includes memory cells using ferroelectric capacitors (FeCap) 110 as storage elements. Ferroelectric random access memory has been implemented in several configurations. The one-transistor-one-capacitor (1T-1C) memory cell design of the FeRAM array is structurally similar to the memory cells in widely used DRAMs because both cell types include a capacitor and an access transistor. In DRAM cell capacitors, linear dielectrics are used, while in FeRAM cell capacitors, the dielectric structure includes ferroelectric materials, typically lead zirconate titanate (PZT).

[0029] FeCap 110 represents a number of FeCaps included in IC 100. FeCap 110 has a base plate 104 and a top plate 106 patterned by conductive layers. Dielectric PZT material 108 is sandwiched between the base plate 104 and the top plate 106 to form a capacitor configuration. Through-hole 102 connects conductive signal lines 103 to the base plate 104. Through-hole 112 connects conductive signal lines in a first metal layer 114 to the top plate 106. A second metal layer 116 provides an additional signal routing layer that interconnects the signal lines in the first metal layer 114 via through-holes (not shown).

[0030] Figure 2A This is a top cross-sectional view of a portion of the CMOS IC 200, which includes FeCap rows used as ultrasonic transducers manufactured within the CMOS IC 200. Figure 2BThis is a side cross-sectional view of a portion of the CMOS IC 200. FeCap 210 represents a linear array of FeCaps included in IC 200. FeCap 210 has a base plate 204 and a top plate 206 patterned by conductive layers. Ferroelectric PZT material 208 is sandwiched between the lower plate 204 and the upper plate 206 to form a capacitor configuration. Through-hole 202 connects conductive signal lines 203 to the lower plate 204. Through-hole 212 connects contacts 214 and thus conductive signal lines 215 in the first metal layer to the upper plate 106. Contacts 216 in a second metal layer provide an additional signal routing layer that interconnects to the signal lines in the first metal layer via through-holes (not shown).

[0031] A linear array of FeCaps 210 is formed along axis 220. Each FeCap 210 has a width (w) 224 and a length (L) 222. The linear array of FeCaps is arranged with a pitch (p) 225. The array of FeCaps is arranged such that the length 222 of each FeCap 210 is perpendicular to axis 220. As will be described in more detail below, the appropriate width and pitch of the FeCaps in the linear array are selected to generate ultrasonic waves in the central portion of the linear array, preventing the ultrasonic waves from scattering from one end of the linear array and causing the ultrasonic waves to “leak” or scatter from the other end of the linear array, thus forming an ultrasonic transmitter. In this example, the length L is 10 μm. In another example, L can be larger or smaller for the corresponding signal strength.

[0032] In this example, substrate 230 is bulk silicon. N+ wells and p+ wells are formed on top of substrate 230 to provide regions for CMOS transistor implantation. During the FEOL process of CMOS IC 200, FeCap 210 is also formed on the N-well layer 231 using known or later-developed fabrication techniques. Contacts 214, 216 and vias 212 are formed during the BEOL process of CMOS IC 200 using known or later-developed fabrication techniques. In this example, silicon dioxide layers 232, 233, 234 provide electrical insulation around and between the first and second metal layers and the contacts such as contacts 214, 216. In other examples, various types of known or later-developed interconnect dielectric layers can be used between multiple metal layers.

[0033] FeCap 210 is fabricated during the FEOL process of CMOS IC 200 using known or later-developed manufacturing techniques. A first conductive layer forming substrate 204 can be deposited on substrate 200. Then, a ferroelectric layer forming FeCap is deposited on the first conductive layer. Then, a second conductive layer is deposited on the ferroelectric layer. An etching process is then performed to form individual plates of the linear array of FeCap. In another example, each layer can be patterned and etched individually. In this example, the first and second conductive layers of the plates forming the linear array of FeCap are metal alloys.

[0034] Figure 3 This is a cross-sectional view of a single simulated FeCap 310, illustrating the simulated electric field around the FeCap. To better understand the operation of FeCap-based ultrasonic transducers, numerical finite element method (FEM) simulation tools were used to simulate similar... Figure 2A , Figure 2B The structure of the FeCap 210 was simulated. Two-dimensional (2D) and three-dimensional (3D) FEM simulation tools are available from several vendors.

[0035] In this example, the simulated unit cell 300 includes a region 337 that simulates the mechanical and material properties of a selected FEOL CMOS process to simulate the structure of FeCap 310, which includes a lower plate 304, an upper plate 306, a PZT layer 308, and a via 302. Region 337 also simulates the mechanical and material properties of a selected BEOL CMOS process to simulate the structure of vias 312, 318, and contacts 314, 316. Region 337 also simulates the dielectric layer surrounding the vias and contacts, such as... Figure 2B Layers 232, 233, and 234. Finally, it is assumed that a conventional IC passivation process (silicon dioxide, silicon nitride, etc.) of a chosen CMOS process is used. FeCap 310 has a width of 324 and a pitch of 325 for adjacent FeCaps. For this simulation, the length of FeCap 310 is perpendicular to the view and is considered to be a plane that extends infinitely in and out of the view.

[0036] Regions 338 and 339 represent “Perfect Matching Layers” (PMLs), which are added to allow for the simulation of the ultrasonic radiation generated by FeCap 310 in a hypothetically infinitely extending plane. PMLs 338 and 339 have corresponding simulation properties that match those of their adjacent region 337. In this example, PML 338 is dielectrically matched to region 337 above FeCap 310, while PML 339 is matched to the silicon substrate below FeCap 310.

[0037] Since the goal is to simulate a resonator, the wave on the left must be associated with the wave on the right with a constant phase shift. Therefore, the wave vector time interval (pitch 325) must be a constant value. Given a constant phase shift, simulations at multiple characteristic frequencies are performed to identify all possible propagation modes in the structure. Depending on the phase shift, frequency, and material properties, various traveling and evanescent waves are formed. An evanescent field, or evanescent wave, is an oscillating field that does not propagate but whose energy is spatially concentrated near the source. Shaded areas 335 and 336 illustrate evanescent fields. The simulation results can be visualized using a scatter plot.

[0038] Figure 4 yes Figure 3 A scatter plot of various patterns within the FeCap structure. In this plot, k x "a" is the wave vector in the x-direction, and "a" is the period of the structure. When k x When multiplied by "a" equals π, there is a 180-degree offset between the left and right boundaries of the unit cell. When k x When multiplying by "a" equals 0, there is a 0-degree phase shift.

[0039] There are two types of waves that can propagate in solids: longitudinal waves and shear waves. Longitudinal waves have a faster speed of sound than shear waves. Each type of wave will have its own acoustic cone. Thus, an acoustic cone 401 has a steep slope for longitudinal waves in bulk silicon, an acoustic cone has a slightly shallower slope for shear waves in bulk silicon, and two similar cones have a lower slope for interlayer dielectrics.

[0040] In this drawing, acoustic cone region 401 represents the area that can propagate to the substrate (such as...). Figure 2B All longitudinal waves in the bulk silicon of substrate 230. Acoustic cone region 402 represents shear waves that can propagate in bulk silicon. Acoustic cone region 403 represents shear waves that can propagate in oxides (such as...) Figure 2B All longitudinal waves propagating in the dielectric layers 232, 233, 234. Acoustic cone region 404 represents shear waves that can propagate in the dielectric layers. Region 404 has a shallower slope because the speed of sound in the oxide is lower than the speed of sound in silicon. In region 405 below region 404, plane waves cannot propagate into the bulk silicon, but they can propagate into the dielectric. The sound velocity (c) setting defines the slope of the line for each region (acoustic cone) 401, 404. Each line is described by expression (1).

[0041] ω=ck x (1)

[0042] The plotting line 406 below region 404 represents a wave that cannot propagate into bulk silicon or a bulk dielectric. Therefore, this mode creates a “trap” mode, referred to herein as a “guided mode.” FeCap creates a “slow-wave” structure for very specific frequencies. This mode line cannot propagate into bulk silicon or a bulk dielectric because it has a much slower wave rate. In this simulation example, the specific guided mode frequency is approximately 700 MHz, as shown in 408, where k... x a = π.

[0043] The result shown by guide mode plot line 406 is similar to Snell's law in optics, which defines the angle of refraction when light passes through the boundary separating two media with different speeds of light. In this case, due to the different speeds of sound of oxide and silicon, total internal reflection will occur from the bulk silicon at the bottom of the FeCap cell and the bulk oxide at the top of the cell at the guide mode frequency.

[0044] The guide mode plotting line 407 is the second guide mode, which begins to appear as the FeCap pitch decreases and the operating frequency increases.

[0045] Refer again Figure 3 This simulation illustrates operation at a pilot frequency of approximately 700 MHz. The shaded areas on the upper plate 306 and lower plate 304 indicate that stress occurs only around the FeCap and does not propagate downwards into the bulk silicon or upwards into the bulk oxide. The lightly shaded areas 335 and 336 indicate that the pilot mode wave attempts to penetrate but cannot; therefore, it cannot propagate vertically. Thus, a waveguide is created that can confine acoustic vibrations to a high frequency of approximately 700 MHz.

[0046] Figure 5 The illustration shows a pilot mode frequency of approximately 700 MHz within the same row of FeCap unit cells as FeCap unit cell 300 (see [reference]). Figure 4 The diagram shows a cross-sectional view of the simulated oscillation. Regions 540, 543, and 544 represent negative energy generated by the evanescent wave, while regions 541, 542, and 545 represent positive energy generated by the evanescent wave. Therefore, moving from one element to another results in a 180-degree phase shift and resonant operation.

[0047] Figure 6 This is an example dispersed plot illustrating the guided mode operation of the FeCap pitch with varying frequencies. In this example plot, the pitch of the FeCap in the simulated linear array is varied from 1.0 micrometer to 2.5 micrometers to create a similar effect. Figure 4 A series of scatter plots. Then plot the scatter plots for each of the series at k. x Equal to 1 indicated operation point to form Figure 6The scatter plot. As the size of FeCap increases, the guidance mode enters a lower frequency, as indicated by guidance mode plot line 606, see... Figure 4 Plot line 406 in the diagram. Guidance pattern plot line 607 illustrates another guidance pattern, which begins to appear more clearly at lower FeCap pitches; see [link to diagram]. Figure 4 The plotting line 407. The two guiding modes indicated by plotting lines 606 and 607 cannot propagate into the silicon or the dielectric, therefore they are guided.

[0048] Therefore, as the pitch of the FeCap increases, the linear array of FeCap resonates at a lower frequency. Similarly, the acoustic cones enter at lower frequencies. Acoustic cone 604 is a shear mode that can propagate into the dielectric. Acoustic cone 609 is a shear mode that can propagate into both bulk silicon and the dielectric. Acoustic cone 603 is a longitudinal mode that can propagate into the dielectric. The longitudinal modes that can propagate into bulk silicon appear at higher frequencies and are therefore not present at lower frequencies. Figure 6 As shown in the image.

[0049] In this example, a horizontal line 610 is drawn on the plot at approximately 715 MHz. This line intercepts the guide mode line 606 at 1.95 μm. In the region 612 to the right, such as at 2.2 μm, the horizontal line 610 is above the guide mode line 606 and below the acoustic cone 604, thus blocking propagation. In this way, a reflector is created in a linear array of FeCap.

[0050] The pitch of the FeCap in the reflector section only needs to be slightly larger than the pitch of the FeCap in the main waveguide section of the linear array of FeCaps. In this example, the FeCap pitch in the range of 2.0 μm–2.3 μm, as indicated at 612, is suitable for reflector mode operation. However, if the pitch is made too large, operation will occur above the drawing cone 604 and propagation into the bulk silicon and / or bulk oxide will occur.

[0051] The capacitor width and pitch are selected based on numerical FEM simulations to achieve optimal energy constraints. The lithographic constraints of the process set the minimum possible capacitor size and pitch. While such minimum process dimensions may produce functional devices, they do not necessarily yield good performance. Preferred dimensions (width and pitch) vary depending on the exact layer structure of the capacitor, the surrounding dielectric, and different layer thicknesses. Both the capacitor pitch and width determine the resonant frequency of the device. However, as the capacitor pitch and width increase, the resonant frequency decreases with increasing wavelength. This results in a longer evanescent wave “tail” in the bulk and BEOL layers. There is a soft upper limit to the capacitor size and pitch depending on the exact composition of the process layers. Beyond this upper limit, the wavelength at the resonant frequency is too large, making the waveguide structure in the FEOL appear “too thin” to achieve any practical guidance, resulting in significant losses in the bulk and BEOL layers due to the very large evanescent tail.

[0052] Figure 7 This is a cross-sectional view illustrating the simulated operation of an ultrasonic resonator 700 formed by a linear array of FeCap units. In this example, each FeCap unit is similar to... Figure 3 The FeCap 300. In the main waveguide region 701, the FeCap has a pitch p1, which is selected to produce a guided operation mode at a selected frequency. The corresponding pitches p2 of the FeCap in region 702 and p3 in region 703 are selected to be greater than p1, such that regions 702 and 703 act as reflectors at the selected frequency of the main waveguide region 701.

[0053] In this example, the pitch p1 of FeCap in the main waveguide region 701 is selected to produce pilot mode operation at approximately 715 MHz. (Reference) Figure 6 The corresponding pitch of FeCap in region 701 is selected to be approximately 1.95 μm. The corresponding pitches of FeCap in regions 702 and 703 are selected to reflect the selected 715 MHz signal. (Reference) Figure 6 The corresponding pitches of the FeCap in reflector regions 702 and 703 are chosen to be greater than approximately 2.0 μm and less than approximately 2.3 μm. Therefore, a 715 MHz signal cannot propagate left or right in reflector regions 702 and 703, and cannot propagate upwards or downwards in the main waveguide region 701. Thus, the example linear array of FeCap 700 operates as a resonator and produces a resonant signal at a frequency of 715 MHz.

[0054] Theoretically, there is no maximum or minimum limit to the length of the FeCap array. This theory assumes the existence of "many" periods such that the structure maintains translational symmetry (~periodicity) at every point in space. In practice, the main waveguide section 701 and the reflector section 702 require a minimum of four or five periods for the device to function properly. There is no upper limit to the number of periods, but as the device approaches the theoretically translationally symmetric state at each point, more periods are better. In this example, the length of the main waveguide section 701 is approximately 20 μm.

[0055] As the width of the reflector FeCap in reflector section 702 increases, a greater impedance mismatch and greater reflection (and scattering) will occur. Therefore, a smaller number of reflector segments will be required. For the example design, the corresponding pitch / width of the reflector FeCap can range from 10% to 50% wider than the main waveguide FeCap. Smaller reflectors are also possible, but require a larger number. Larger reflectors are also possible; however, at some point, the cutoff of another mode will begin to be low enough, and the reflector will fail. The reflector can have a gradual pitch / width change or a sudden pitch / width change.

[0056] Figure 8 This is a cross-sectional view illustrating the simulated operation of an ultrasonic transmitter 800 formed by a linear array of FeCap cells. In this example, the FeCap cells in the main waveguide region 801 and the reflector region are similar to... Figure 3 The FeCap 300, with the appropriate pitch selected, operates in waveguide mode at approximately 715 MHz.

[0057] In order for transmitter 800 to radiate the ultrasonic signal generated by main waveguide region 801, in this example simulation, the signal must be coupled into a radiating medium adjacent to the transmitter device represented by region 804. In this example simulation, radiating medium 804 is provided with an oxide layer (such as FeCap) above the FeCap. Figure 2B The oxide layers 232, 233, 234 and PML region 338 in the middle have roughly the same ultrasonic properties.

[0058] If the corresponding pitch of FeCap in the transition region 803 is chosen to be the same as the pitch within the main waveguide region 801, then there will be no "radiator structure." Waves from the main waveguide region 801 will also continue to travel in that segment. However, due to the abrupt truncation of the period of the capacitor at the boundary 814 between the transition region 803 and the radiating medium 804, it will cause large reflections and scattering. In other words, there will be a mismatch with the radiating medium, and therefore very poor radiation efficiency. This configuration can work as a low-Q resonator, but it is not a good radiator.

[0059] The gradual transition in the size of FeCap in transition region 803 facilitates the matching of ultrasonic impedance between transition region 803 and radiating medium 804. In this example, radiating medium 804 is simulated as an oxide, which can be formed in region 337 with various oxide layers (such as 232, 233, 234, etc.). Figure 2B The same oxide as )). Reference Figure 6 For the selected frequency of 715MHz indicated by horizontal line 610, reducing the FeCap pitch moves the operating mode to the left to region 605, in which plane waves cannot propagate into bulk silicon, but they can propagate into oxide.

[0060] In this example, the pitch and width of the FeCap in transition region 803 gradually decrease. For example, starting from FeCap 810, the pitch and width of the FeCap in transition region 803 gradually decrease to the smallest feasible size for the CMOS manufacturing process being simulated. In addition to reducing the pitch and width, the second-layer via 318 and contact 316 are removed in the portion of the FeCap indicated at 811. Figure 3 Furthermore, in the FeCap section indicated by 812, the first layer through-hole 312 and contact 314 have also been removed. Figure 3 A small number of the top contacts and bottom through-holes of the FeCap within section 812 are removed to gradually reduce the physical size of the linear array of FeCaps in transition section 803. The aim is to gradually reduce the physical size of the FeCap structure so that the ultrasonic impedance of transition section 803 gradually transitions to match the ultrasonic impedance of the radiating medium 804.

[0061] The gradual decrease in the size and pitch of the FeCap in the transition region 803 causes the ultrasonic signal generated in the main waveguide region 801 to propagate through the transition region 803 and then smoothly launch into the radiating medium 804. Within the transition region 803, the ultrasonic signal begins to propagate upward into the BEOL oxide layer, thereby forming a radiating structure by the FeCap in the transition region 803. Signal waves 816, 817, and 818 represent the ultrasonic signals that are launched into the radiating medium 804 and simultaneously remain above the bulk silicon substrate region 339.

[0062] Figure 9 This is a cross-sectional view of a CMOS IC 930, illustrating simulated operation of an example FeCap ultrasonic transducer 900 coupled to a water droplet 920. The transducer 900 comprises a linear array of FeCap 910s and a radiating medium 904, the linear array of which is similar to... Figure 2A , Figure 2B The diagram shows a linear array of FeCap, and the radiating medium 904 is similar to... Figure 8 The radiation medium in it is 804. (For example, regarding...) Figure 8 Described, in the main waveguide section 901 of the linear array of FeCaps, each FeCap has a corresponding pitch and width, which are selected to produce pilot-mode operation for a selected frequency. In this example, a pitch of approximately 1.95 μm is selected and a width is chosen to produce pilot-mode operation at approximately 715 MHz. The corresponding pitch of the reflector section 902 of the FeCaps is selected to be larger than the corresponding pitch in section 901 to provide a reflector operation mode at the selected frequency of 715 MHz. In this example, the corresponding pitch of the FeCaps in section 902 is selected in the range of 2.0–2.3 μm.

[0063] The portion 903 of FeCap in the linear array 910 is formed similar to Figure 8 The transition region 803 is the transition region in the middle. The corresponding pitch and width of FeCap in part 903 gradually decrease to facilitate the matching of ultrasonic impedance between the transition region 903 and the radiation medium 904.

[0064] The radiating medium 904 forms a traveling wave radiator. This structure needs to be long enough to allow multiple wavelengths along the surface and function like a true traveling wave radiator. Simulations indicate that in the upper BEOL material, the length of the radiating medium 904 should be at least five to ten wavelengths to produce a good radiation pattern. The longer the radiating medium 904, the more beams will be emitted, and the higher the radiation efficiency. In this example, four beams 911, 912, 913, and 914 are emitted from the radiating medium 904 into the water droplet 920. In this example, the length of the radiating medium 904 is approximately 150 μm.

[0065] However, in another application, multiple beams may not be desired. Therefore, the length of the radiator medium can be selected based on the desired radiation pattern of the target application.

[0066] In this example, the radiating medium 904 is formed from a dielectric layer formed during the BEOL process of the CMOS device 930. A portion 905 of the CMOS IC 930 includes an oxide layer formed during the BEOL process of the CMOS device 930. In one example, portion 905 also includes a CMOS circuitry coupled to the transducer 900 to provide control and processing of ultrasonic signals from the transducer 900. The substrate 906 is bulk silicon. In this example, at least two interconnect layers are fabricated over the CMOS circuitry in the transducer 900 and region 905 to provide interconnection. Contacts within the transducer 900 (such as contacts 214, 216) Figure 2B It can be connected to the interconnect layer.

[0067] The CMOS circuitry within region 905 includes circuitry for generating an ultrasonic signal that is coupled to transducer 900 via an interconnect layer.

[0068] In applications, transducer 900 can be interfaced with various targets to evaluate them using ultrasound imaging techniques. For medical imaging, ultrasound transducer 900 can be interfaced with a human or animal body to "see" the body. For simulation purposes, water is used as a similar component to the human and animal body. As illustrated by waves 911, 912, 913, 914, etc., the ultrasound waves generated by the main waveguide portion 901 and reflector portion 902 travel downwards along transition portion 903 and then to radiation region 904. The 715MHz ultrasound waves propagate through the dielectric constituting radiation region 904 and are then emitted into the surrounding medium. A simulated water droplet 920 illustrates how the emitted ultrasound waves propagate as waves 911, 912, 913, 914, etc., through the water droplet 920.

[0069] The ultrasonic wave length of a 715 MHz signal in water is approximately 2 μm, which is ideal for high-resolution short-range ultrasonic imaging applications. For example, compare this to existing techniques using ultrasonic signals with a frequency of 10 MHz; the wavelength in water is much larger, and therefore the resulting image resolution is lower than that derived from a 715 MHz ultrasonic signal.

[0070] Figure 10A , Figure 10B , Figure 10C It is used for Figure 9 Schematic diagrams of various example FeCap connection schemes for transducer 900. Figure 10A In section 903, all FeCaps in the radiator structure, section 901 in the main waveguide, and section 902 in the reflector have their base plates connected together and connected to a ground reference. The top plates of the FeCaps in sections 902 and 903 remain floating. An ultrasonic excitation signal is applied to the alternating top plates in section 901. In this example, the excitation signal is generated by a CMOS IC 930 (…). Figure 9 The circuit system on the circuit provides a 715MHz signal. The positive excitation signal Vdrive+ is applied to every other FeCap (such as FeCap 1011, 1013) in section 901, while the negative excitation signal Vdrive- is applied to the middle FeCap (such as FeCap 1010, 1012).

[0071] exist Figure 10BIn section 903, all FeCaps in the radiator structure, section 901 in the main waveguide, and section 902 in the reflector have their base plates connected together and connected to a ground reference. The top plates of the FeCaps in sections 902 and 903 are also tied to the ground reference. An ultrasonic excitation signal is applied to the top plate in section 901. In this example, the excitation signal is generated by a CMOS IC 930 (…). Figure 9 The circuit system on the circuit provides a 715MHz signal. The positive excitation signal Vdrive+ is applied to every other FeCap (such as FeCap 1011, 1013) in section 901, while the negative excitation signal Vdrive- is applied to the middle FeCap (such as FeCap 1010, 1012).

[0072] exist Figure 10C In section 903, all FeCaps in the radiator structure, section 901 in the main waveguide, and section 902 in the reflector have their base plates connected together and connected to a ground reference. The top plates of the FeCaps in sections 902 and 903 are connected to a bias voltage reference. An ultrasonic excitation signal is applied to the upper plate in section 901. In this example, the excitation signal is generated by a CMOS IC 930 (…). Figure 9 The circuit system on the circuit provides a 715MHz signal. The positive excitation signal Vdrive+ is applied to every other FeCap (such as FeCap 1011, 1013) in section 901, while the negative excitation signal Vdrive- is applied to the middle FeCap (such as FeCap 1010, 1012).

[0073] It remains floating with the top plate of FeCap in the reflector section 902. Figure 10A In comparison, connection Figure 10B and Figure 10C The top plate of the FeCap in the reflector section 902 slightly increases the attenuation.

[0074] Figure 11 It is used for Figure 9 The image shows a top view of a linear array of FeCap 910, an example of an ultrasonic transducer 900. FeCap 1110 represents all the FeCaps in the linear array 910. FeCap 1110 is similar to the image about... Figure 2A , Figure 2B FeCap 210 is described in more detail. In this example, the upper plate of each FeCap is visible, such as upper plate 1106. In this example, a continuous polysilicon layer 1108 spans all FeCaps in the linear array 910 to form a baseboard routing interconnect.

[0075] In this example, FeCap are interconnected, as shown below. Figure 10B The diagram is schematic. Vdrive+ is coupled via signal line 1115 to the top plate of every other FeCap in the main waveguide section 901, with signal line 1115 connected to the corresponding first-level contact, such as first-level contact 1114. Similarly, Vdrive- is coupled via signal line 1116 to the top plate of the intermediate FeCap in section 901, with signal line 1116 connected to the corresponding first-level contact.

[0076] Figure 12 This is a cross-sectional view of IC 1240, which includes an example package of FeCap ultrasonic transducer 1200. FeCap ultrasonic transducer 1200 is similar to FeCap transducer 900 (…). Figure 9 It includes a linear array of FeCap 1210s arranged as a main waveguide section, a reflector section, and a transition section. The ultrasonic transducer 1200 also includes a radiating medium 1204. The ultrasonic transducer 1200 is fabricated on a CMOS die 1230 using known CMOS fabrication techniques. The substrate 1231 is bulk silicon. During the FEOL process, various circuit systems 1236, including a linear array of FeCap 1210s, are formed on the substrate 1231. A metal interconnect layer 1238 and an oxide insulating layer are formed during the BEOL process.

[0077] Die bonding pads (such as pad 1232) are also formed on substrate 1231 and interconnected to circuit system 1236 via signal lines formed in one or more metal interconnect layers 1238 of CMOS die 1230.

[0078] A CMOS die 1230 is mounted on a die attachment pad 1244, which is part of a metal leadframe including leadframe bonding pads (such as pad 1245) to provide connectivity to external circuitry. Bond wires (such as bond wire 1233) connect the die bonding pads on the CMOS die 1230 to corresponding leadframe bonding pads.

[0079] The CMOS die 1230 is encapsulated by a molding compound 1242 using known or later-developed packaging techniques. In this example, an opening 1246 is provided in the finished package to allow the radiation medium 1204 to interface with an externally supplied fluid 1220. For example, the packaged IC 1240 may be immersed in a can or other container containing the fluid 1220. In another example, the packaged IC 1240 may be part of a medical ultrasound imaging device. In that case, for example, the fluid 1220 may be a liquid or gel that provides an interface between the radiation medium 1204 and a human or animal body.

[0080] In this example, the packaged IC is a quad flat no-lead package (QFN). QFN packages (such as quad flat no-leads (QFN) and dual in-line flat no-leads (DFN)) physically and electrically connect integrated circuits to a printed circuit board. QFN (also known as micro leadframe (MLF) and SON (small outline no-leads)) is a surface mount technology and one of several packaging technologies that allows ICs to be attached to the surface of a printed circuit board (PCB) without through-holes. QFNs are near-chip-level packaged plastic encapsulations made with a planar copper leadframe substrate. Peripheral solder joints on the bottom of the package provide electrical connections to the PCB. Other examples may use other known or later-developed packaging technologies, such as quad flat packages, ball grid arrays, etc.

[0081] Figure 13 This is a flowchart illustrating the operation of an ultrasonic transmitter on a CMOS IC. (See above for reference.) Figure 8 , Figure 9 As described in more detail elsewhere, a linear array of FeCaps fabricated on a CMOS IC can operate as an ultrasonic transmitter. The waveguide portions of the FeCap array located in the middle of the row each have a corresponding width and pitch, which are selected to produce a guided operating mode for the selected ultrasonic frequency. The reflector portions of the FeCap array are located at one end of the row. Each FeCap in the reflector portion has a corresponding width larger than the corresponding width of the FeCap in the waveguide portion. The radiator portions of the FeCap array are located at the other end of the row. Each FeCap in the radiator portion has a corresponding width smaller than the corresponding width of the FeCap in the waveguide portion. The radiator dielectric is coupled to the radiator portions of the FeCap array.

[0082] At position 1301, an ultrasonic signal is applied to the waveguide portion of the FeCap. This ultrasonic signal can be generated by the circuitry within the IC housing the FeCap.

[0083] At position 1302, ultrasonic waves are generated by the waveguide portion of the FeCap. The frequency of the ultrasonic signal is selected to match the guiding operation mode generated within the waveguide portion of the FeCap.

[0084] At position 1303, a portion of the ultrasonic wave is partially reflected by the reflector. The reflected wave amplifies the ultrasonic signal formed within the waveguide section.

[0085] At 1304, a portion of the ultrasonic signal is radiated from the radiating structure formed by the radiator portion of the FeCap. To match the acoustic impedance of the radiating structure with the acoustic impedance of the radiating medium, the corresponding width and size of the FeCap in the radiator portion gradually decrease.

[0086] At 1305, the radiated portion propagates through a radiating medium that can be used to guide the radiated wave in a specific direction. For example, the radiating medium can guide the waveguide to an opening in the IC's encapsulation, such as... Figure 12 As shown in the diagram.

[0087] As described above, one or more ultrasonic transducers and acoustic processing circuitry are integrated within a standard CMOS IC, forming a structure that does not contain air gaps or is entirely solid.

[0088] High-frequency operation in the 700MHz range can be used for very high resolution over short distances to provide high-resolution ultrasound imaging.

[0089] Applications include: surface inspection, medical imaging, surgical guidance, intravenous / arterial imaging, microfluidic flow measurement and metering, insulin / drug microflow metering, blood flow measurement, on-chip acoustic communication, isolation between voltage domains, pain detection, etc.

[0090] Other embodiments

[0091] The described example illustrates a single ultrasonic transducer. However, in another example, two or more ultrasonic transducers can be fabricated on a single CMOS IC. Figure 9 As illustrated, the ultrasonic transducer 900 is less than 250 μm in length, including the radiating medium 904. The plate on the linear array of FeCap 910 is only 10 μm long. Because the overall size of the ultrasonic transducer 900 is only about 250 μm by 10 μm, many ultrasonic transducers can be fabricated on a single CMOS IC.

[0092] In the described example, the ultrasonic transducer operates at a frequency of 715 MHz. In other examples, the width of the FeCap in the waveguide, reflector, and radiating sections of a linear array of FeCaps can be selected to generate guided ultrasonic operation across a frequency range of 600-900 MHz or higher. The lowest frequency depends on the available material thickness, while the highest frequency depends on the lithography capabilities of the technology. Using existing technologies, the range can be pushed down to 350 MHz and up to over 1 GHz.

[0093] In the described example, a single-layer FeCap is illustrated. In another embodiment, multi-layer FeCap and / or multi-layer thick tungsten can be implemented using three-dimensional integration techniques. In one example, multiple layers can be fabricated directly on top of each other. In another example, the delay structure can be fabricated in the higher metal layer of a BEOL stack. RF metal-insulator-metal (RF-MIM) capacitors can be fabricated in the upper BEOL layer to move away from parasitics and losses in the substrate. Using multi-layer FeCap, RF-MIM capacitors, and / or multi-layer thick tungsten, the frequency range can be extended down to tens of MHz. For example, systems can operate at frequencies of 20 MHz or lower using these techniques.

[0094] In the described example, an ultrasonic signal is emitted from an ultrasonic transmitter. In another example, the same structure can be used to receive an ultrasonic signal. By controlling the transmission and reception operations, the same structure can function as a transducer.

[0095] In some examples, only a single transmitting device or a single receiving device may be implemented. In another example, only a single transducer device may be implemented.

[0096] In the described example, contacts in the two metal layers are gradually removed to form a transition structure. In another example, three or more interconnected layers may exist above a linear array of FeCaps. In this case, contacts and / or vias from all layers can be removed in a gradual manner to facilitate a gradual reduction in the physical size of the FeCap cells to create a transition structure.

[0097] In the example described where the metal layer is copper, copper has an acoustic impedance similar to that of oxides. Therefore, copper contacts and vias have only a small effect on the acoustic impedance. However, in another example, the metal layer could be aluminum, which has a significantly different acoustic impedance than oxides. In this case, gradually removing the aluminum contacts / vias to form a tapered transition structure has a greater effect. Similarly, gradually changing the size of other types of conductive structures used for interconnection can have different effects on the acoustic impedance.

[0098] In the described example, the corresponding widths of the FeCap in the main waveguide section are approximately equal. However, due to normal manufacturing tolerances, the corresponding widths may vary. In this example, a variation of up to 5% is possible.

[0099] In this specification, the term "coupled" and its derivatives refer to indirect, direct, optical, and / or wireless electrical connections. Therefore, if a first device is coupled to a second device, the connection can be via a direct electrical connection, via an indirect electrical connection via other devices and connections, via an optoelectronic connection, and / or via a radio connection.

[0100] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. An ultrasonic transducer, comprising: Substrate; A linear array of ferroelectric capacitors, i.e. FeCaps, arranged in a single row on the substrate, each FeCap having a corresponding length and a corresponding width, such that the length of each of the FeCaps in the array is perpendicular to the axis of the row; The waveguide portion of the FeCap array, located in the middle of the row, has each FeCap having a corresponding first width; The reflector portion of the FeCap array, located at the first end of the row, wherein each FeCap in the reflector portion has a corresponding width larger than the first width; and The radiator portion of the FeCap array is located at the second end of the row opposite the first end, wherein each FeCap in the radiator portion has a corresponding width smaller than the first width.

2. The ultrasonic transducer of claim 1, wherein the corresponding width of the FeCap in the radiator portion gradually decreases from the first width to the second width.

3. The ultrasonic transducer according to claim 1, wherein each of the FeCap array has a corresponding first conductive plate and a corresponding second conductive plate, and a ferroelectric material is present between the first plate and the second plate.

4. The ultrasonic transducer of claim 3, wherein the first conductive plate of at least one FeCap in the radiator portion is connected to at least two contact pads, the first conductive plate of at least one FeCap in the radiator portion is connected to only one contact pad, and the first conductive plate of at least one FeCap in the radiator portion is not connected to a contact pad.

5. The ultrasonic transducer of claim 4, wherein at least one of the FeCap portions of the radiator does not have a first conductive plate.

6. The ultrasonic transducer of claim 1, wherein the corresponding width of the FeCap in the reflector portion is in the range of 10% to 50% larger than the first width.

7. The ultrasonic transducer of claim 6, wherein the FeCap in the reflector portion has a gradually increasing width.

8. A complementary metal-oxide-semiconductor integrated circuit, i.e., a CMOS IC, comprising: Substrate; An ultrasonic transducer formed on the substrate, the ultrasonic transducer having signal terminals; A CMOS circuit system formed on the substrate, the circuit system having an ultrasonic signal terminal; and At least one metal interconnect layer covers the ultrasonic transducer and the CMOS circuit system, wherein the at least one metal interconnect layer connects the ultrasonic signal terminal to the terminal of the ultrasonic transducer.

9. The CMOS IC according to claim 8, wherein the ultrasonic transducer comprises: A linear array of ferroelectric capacitors, i.e. FeCaps, arranged in a single row on the substrate, each FeCap having a corresponding length and a corresponding width, such that the length of each of the FeCaps in the array is perpendicular to the axis of the row; The waveguide portion of the FeCap array, located in the middle of the row, has each FeCap having a corresponding first width; The reflector portion of the FeCap array, located at the first end of the row, wherein each FeCap in the reflector portion has a corresponding width larger than the first width; and The radiator portion of the FeCap array is located at the second end of the row opposite the first end, wherein each FeCap in the radiator portion has a corresponding width smaller than the first width.

10. The CMOS IC of claim 9, further comprising a molding compound encapsulating the substrate, wherein openings are provided in the molding compound to expose portions of the linear array of the FeCap.

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