Capacitive MEMS acoustic emission sensor chip structure and preparation process thereof

Abstract

The invention provides a capacitive MEMS acoustic emission sensor chip structure and a preparation process thereof, the capacitive MEMS acoustic emission sensor chip structure is composed of a bottom electrode, a dielectric layer, a sacrificial layer, a top film layer and an anchor point, and through a phase reversal design, the anti-noise capability is greatly enhanced while high sensitivity and a flat passband are maintained. The method comprises the following steps of: cleaning a substrate, forming a bottom electrode, depositing a dielectric layer, depositing a sacrificial layer and an anchor region, forming a top film layer and releasing the sacrificial layer, and combining a multi-layer photoresist process and XeF2 dry etching to realize the stripping of a thick metal film and the release of the sacrificial layer. According to the invention, integration and flat passband of the controllable cavity structure and the high-performance vibrating diaphragm are realized, so that the device has great application prospects in the aspects of structural health monitoring and nondestructive testing of industrial equipment.

Description

Technical Field

[0001] This invention relates to the field of structural design and fabrication of MEMS sensors, and particularly to the structure and fabrication process of capacitive MEMS acoustic emission sensor chips. Background Technology

[0002] Structural Health Monitoring (SHM) involves the continuous monitoring of large civil infrastructure such as bridges, tunnels, pipelines, and railways to detect early signs of structural damage and prevent catastrophic safety incidents that could lead to irreversible economic losses and casualties.

[0003] Therefore, damage detection of critical components in major engineering facilities is of great scientific significance. Over time, infrastructure is subjected to environmental stresses and other factors that can lead to structural damage. Early detection of such damage is crucial to ensuring the long-term integrity and safety of these structures.

[0004] One of the key methods used in SHM (Sound Analysis) is monitoring acoustic emission (AE) signals. In accidents such as crack initiation or mechanical failure, any impact can lead to the rapid release of local strain energy within the structure, and this released energy generates AE signals. The generated AE signals have a wide frequency range, and designing highly sensitive broadband sensors is a pressing problem to solve in order to accurately detect and analyze them.

[0005] Current research has shown that CMUTs with multi-element heterogeneous designs achieve wide bandwidth coverage (e.g., 100kHz–1MHz) by integrating micro-elements with different resonant frequencies, adapting to multi-mode guided wave detection needs. Leveraging the advantages of miniaturized and customizable MEMS processes, they offer flexibility for deployment in confined spaces or complex structural surfaces, and the use of environmentally friendly lead-free materials aligns with industrial sustainable development trends. Currently, this technology has been preliminarily validated in out-of-plane / in-plane vibration detection of structures such as aluminum plates. However, due to the presence of low-passband troughs, it is difficult to design for wideband guided wave sensing in rough vacuum environments. Furthermore, the superposition of outputs from various micro-elements within the bandgap frequency range and the difficulty in eliminating low-frequency and high-frequency noise interference result in significantly lower sensitivity and signal-to-noise ratio (typically only 20–40dB) compared to traditional piezoelectric sensors, limiting their practicality in weak signal scenarios.

[0006] Furthermore, in the manufacturing of traditional MEMS acoustic emission sensors, the sacrificial layer is mostly a uniform structure, resulting in a single cavity size and uneven stress distribution in the vibrating membrane, which limits device performance (such as bandwidth and sensitivity) and array integration density. In addition, there are challenges in the manufacturing process, such as controlling the uniformity of air gaps and stress matching of multilayer thin films. Existing sacrificial layer release processes using wet etching are prone to structural collapse or residue, affecting yield, and a single photoresist process is difficult to achieve complete peeling of thick films. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a capacitive MEMS acoustic emission sensor chip structure and its fabrication process. Under a rough vacuum environment, not only are sharp low-frequency troughs effectively passivated, but the sensitivity at low and high frequencies is also effectively reduced, significantly improving the performance of the passband and bandgap.

[0008] The present invention achieves the above-mentioned technical objectives through the following technical means.

[0009] A chip structure for a MEMS acoustic emission sensor includes, from bottom to top along the z-axis, a bottom electrode, a dielectric layer, a sacrificial layer, a top film layer, and anchor points. The bottom electrode is composed of a chromium and gold bilayer metal, serving as a fixed electrode to provide electrostatic drive. The dielectric layer is composed of a double layer of hafnium dioxide and silicon dioxide for electrical insulation. The sacrificial layer is made of polysilicon (Poly-Si) to form an air gap between the top film layer and the bottom electrode. The top film layer is made of copper to form a suspended vibration structure, serving as both an electrode and a mechanical vibration membrane. The anchor points are formed by ICP etching a localized area of ​​the sacrificial layer to expose the dielectric layer, achieving both mechanical fixation and electrical connection of the top film layer.

[0010] In the above scheme, the anchor point and sacrificial layer are made of polysilicon (Poly-Si) with a thickness of 600-800 nm; the bottom electrode uses chromium with a thickness of 20-30 nm and gold with a thickness of 500-700 nm, with a total thickness of 520-730 nm for the two metal layers; the thicknesses of hafnium dioxide and silicon dioxide in the dielectric layer are 180-220 nm and 35-45 nm, respectively; the top film layer is achieved by stripping a 5-7 μm copper structure using multilayer photoresist.

[0011] A fabrication process for a MEMS acoustic emission sensor chip includes the following steps: First, the substrate is pretreated by cleaning and activation. Then, a bottom electrode pattern is defined using a photoresist pattern reversal process. Subsequently, electron beam evaporation deposition is performed, and excess metal is stripped to form the bottom electrode. Next, a dielectric region is defined using a pattern reversal process. Hafnium dioxide and silicon dioxide are deposited by electron beam evaporation to form a double-layer dielectric structure. Then, a polysilicon sacrificial layer and anchor region are defined using a pattern reversal process. Silicon dioxide is then deposited by electron beam evaporation. The top film region is defined using a multilayer photoresist pattern reversal process. Chromium and copper are then deposited by electron beam evaporation to form the top film. Finally, the sacrificial layer is released by dicing, BOE, and XeF2 etching. After final cleaning and nitrogen drying, the device fabrication is completed.

[0012] The above solution includes the following steps:

[0013] 1) Substrate pretreatment, cleaning, and activation;

[0014] 2) Define the bottom electrode pattern using a pattern reversal process;

[0015] 3) Degumming is performed using the ICP process;

[0016] 4) Electron beam evaporation deposition of a chromium-copper metal layer;

[0017] 5) The bottom electrode is formed through a stripping operation;

[0018] 6) Define dielectric regions using pattern reversal technology;

[0019] 7) Perform ICP desmearing process;

[0020] 8) Electron beam evaporation deposits hafnium dioxide and silicon dioxide to form a double-layer dielectric structure;

[0021] 9) Perform the stripping operation;

[0022] 10) Use a pattern inversion process to define the polysilicon sacrificial layer and anchor region for the device in step 9);

[0023] 11) Perform ICP desmearing process;

[0024] 12) Electron beam evaporation deposition of silicon dioxide is performed to form a sacrificial layer and anchor points;

[0025] 13) Perform the stripping operation;

[0026] 14) Define the top film layer by performing a pattern reversal process using multilayer spin-coating photoresist;

[0027] 15) Perform ICP desmearing process;

[0028] 16) Electron beam evaporation deposition of chromium and copper;

[0029] 17) Perform the stripping operation;

[0030] 17) Perform a slicing, then wash with Piranha solution and quickly perform BOE (Buffered Oxide Etch) operation, rinse with deionized water and dry.

[0031] 18) Sacrificial layer release is achieved through XeF2 etching;

[0032] 19) After final cleaning and nitrogen drying, the device fabrication is complete.

[0033] In the above scheme, in step 12), the anchor point and the sacrificial layer use the same mask for pattern inversion, so that the anchor point is formed smoothly; in step 14), multilayer photoresist is spin-coated to form a top film layer to achieve the removal of the thick metal film; the thick metal film is completely removed by repeated stacking of single-layer photoresist to avoid residual short circuits; in step 19), XeF2 is used to perform dry etching on the wafer obtained in step 18); the release efficiency of the sacrificial layer and the cavity integrity are improved.

[0034] In the above scheme, in step 1), the Pyrex substrate is cleaned with acetone, isopropanol (IPA), and deionized water in sequence, dried with nitrogen, and then baked on a hot plate at 120°C for 5 to 10 minutes.

[0035] In the above scheme, in step 2), the bottom electrode pattern on the mask is sequentially transferred onto the photoresist by spin-coating HMDS coating and AZ5214E ​​photoresist through mask cover exposure and overexposure.

[0036] In the above scheme, in step 5), the wafer is placed in a container filled with acetone to remove residual photoresist and unwanted metal.

[0037] In the above scheme, in step 14), the first layer of photoresist is spin-coated onto the clean wafer obtained in step 13), followed by soft baking. The second layer of photoresist is spin-coated again with the same parameters, followed by soft baking again. The above operation is repeated until the photoresist thickness reaches the expected thickness. Then, photolithography exposure is performed using a mask, followed by reverse baking. Finally, general exposure and development are performed to display a clear top film pattern. The photoresist pattern forms a negative sidewall angle (70-75°) to ensure metal deposition.

[0038] In the above scheme, in step 19), XeF2 is etched using a dry etching process with parameters of pressure 5.5 to 6.5 Torr, single etching time 600 to 700 seconds, and 5 to 8 cycles.

[0039] Beneficial effects:

[0040] 1. The chip structure of the MEMS acoustic emission sensor provided by this invention can have broadband sensitivity in the frequency range of 40kHz to 1MHz, which makes it more advantageous in resisting noise interference. While maintaining a flat passband, it greatly enhances the noise resistance capability, making it very promising for application in structural health monitoring (SHM) of infrastructure such as bridges, railways, and pipelines, and non-destructive testing (NDT) of industrial equipment.

[0041] 2. This invention solves the problems of low device yield caused by the traditional process of wet etching of the sacrificial layer during sacrificial layer release, which easily leads to film structure collapse, and the difficulty in achieving complete peeling of thick metal films by a single photoresist process. The device fabricated achieves the integration of a controllable cavity structure and a high-performance diaphragm.

[0042] 3. The micro-element structure design provided by this invention can be fabricated using MEMS technology. As a collection of methods and technologies for manufacturing microscale systems, MEMS can realize the miniaturization, integration, and low cost of capacitive MEMS acoustic emission sensors.

[0043] 4. The MEMS acoustic emission sensor fabrication process provided by this invention solves the problem of peeling off the thick metal film on the top layer of the sensor micro-element, avoiding the risk of residue and short circuit.

[0044] 5. The MEMS acoustic emission sensor fabrication process provided by this invention uses XeF2 dry etching instead of wet etching during sacrificial layer release, combined with progressive pressure and time control (6 Torr, 600 seconds / cycle), which improves cavity integrity by more than 90%, ensuring membrane structure integrity and high yield.

[0045] 6. The optimized structure of the HfO2 / SiO2 double dielectric layer of this invention balances high dielectric constant and interface stability. After accelerated lifetime testing (85℃ / 85% RH, 1000 hours), the performance degradation is less than 5%, which effectively improves the reliability of the device.

[0046] 7. This invention significantly enhances noise immunity while maintaining high sensitivity and a flat passband. Compared to traditional MEMS acoustic emission sensor elements, the micro-element structure design provided by this invention effectively passivates sharp low-frequency troughs in a rough vacuum environment, and also effectively reduces sensitivity at low and high frequencies, significantly improving passband and bandgap performance. The micro-element structure design provided by this invention exhibits a flatter sensitivity-frequency response curve under air damping conditions. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a capacitive MEMS acoustic emission sensor chip structure according to the present invention.

[0048] Figure 2 This is a flowchart illustrating the fabrication process of a capacitive MEMS acoustic emission sensor chip structure according to the present invention.

[0049] Figure 3 for Figure 2 The theoretical schematic diagram of the multilayer photoresist thick metal film lift-off process involved in the process. Detailed Implementation

[0050] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0051] In the description of this invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "axial", "radial", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0052] This invention provides a chip structure and fabrication process for a MEMS acoustic emission sensor. The chip structure consists of a bottom electrode, a dielectric layer, a sacrificial layer, a top film layer, and anchor points. This allows the chip structure to exhibit broadband sensitivity in the frequency range of 40kHz to 1MHz, giving it a significant advantage in resisting noise interference. While maintaining a flat passband, it enhances noise immunity, thereby improving the accuracy and clarity of the detected signal. Furthermore, this invention efficiently fabricates the acoustic emission device through a series of steps: substrate cleaning, bottom electrode formation, dielectric layer deposition, sacrificial layer and anchor area deposition, and top film layer formation and sacrificial layer release. By employing multilayer spin-coating of photoresist and XeF2 dry etching combined with pressure and time control, the problem of removing a thick metal layer from the top film is solved, avoiding residue and short circuits, while simultaneously improving the integrity of the film structure and the yield.

[0053] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Combined with appendix Figures 1 to 3 As shown, the structure, from bottom to top along the Z-axis, consists of a bottom electrode, a dielectric layer, a sacrificial layer, a top film layer, and anchor points, wherein:

[0055] (1) The bottom electrode adopts a chromium-gold double-layer metal structure to provide electrostatic driving as a fixed electrode; in one embodiment of the present invention, the chromium thickness is 25nm, the gold thickness is 600nm, and the total thickness of the double-layer metal is 625nm.

[0056] (2) The dielectric layer surface is covered with hafnium dioxide (HfO2) and silicon dioxide (SiO2) for electrical insulation;

[0057] In one embodiment of the present invention, HfO2 / SiO2 is used to optimize the double dielectric layer structure, which balances high dielectric constant and interface stability to improve device reliability. The thicknesses of hafnium dioxide (HfO2) and silicon dioxide (SiO2) are 200 nm and 40 nm, respectively.

[0058] (3) The sacrificial layer is made of polysilicon (Poly-Si). After being released by XeF2 dry etching, it forms an air gap between the top film and the bottom electrode. The gap height is precisely controlled by the thickness of the sacrificial layer. In one embodiment of the present invention, the polysilicon (Poly-Si) thickness is 700nm.

[0059] (4) The top film is made of chromium (Cr) and copper (Cu) materials to form a suspended vibration structure, which has the functions of both electrode and mechanical vibration film; In one embodiment of the present invention, the thicknesses of chromium (Cr) and copper (Cu) are 50nm and 6μm, respectively.

[0060] (5) The anchor point is made of polysilicon (Poly-Si). The dielectric layer is exposed in a local area by ICP etching of the sacrificial layer to achieve mechanical fixation and electrical connection of the top film layer.

[0061] A fabrication process for a capacitive MEMS acoustic emission sensor chip structure includes the following steps:

[0062] Step 1: Substrate cleaning and pretreatment;

[0063] Clean the surface by sequentially washing with acetone, isopropanol (IPA), and deionized water (DI water) for 3 minutes; dry with nitrogen for 3 minutes to avoid water residue; bake at 150°C for 15 minutes to remove surface moisture and enhance the adhesion of subsequent photoresist.

[0064] Step 2: Define the bottom electrode area using the pattern inversion process, including:

[0065] a. Spin coating of HMDS coating and photoresist;

[0066] HMDS coating is spin-coated onto the substrate in step one, followed by hot baking at 150°C for 5 minutes to enhance the chemical bonding between HMDS and the substrate; then photoresist is spin-coated to form a photoresist layer of about 3μm thickness to prepare a bottom electrode with high conductivity and high adhesion; finally, a soft baking at 150°C hot plate for 5 minutes is performed to remove the solvent.

[0067] In one embodiment of the present invention, the HMDS coating spin-coating parameters are 2000 RPM, acceleration is 1000 RPM / s, and time is 1 minute. The photoresist is AZ5214E ​​image reversal photoresist with spin-coating parameters of 1000 RPM, acceleration of 500 RPM / s, and time of 1 minute.

[0068] b. Define the electrode pattern;

[0069] UV exposure and development using a photomask define the bottom electrode pattern. Then, reverse baking is performed to solidify the exposed areas. Following this, general exposure without a photomask is performed to dissolve the unexposed areas. Finally, development completes the process, resulting in a clear electrode pattern.

[0070] In one embodiment of the present invention, the baking temperature is 200°C and the baking time is 2 minutes. During development, AZ400K developer is mixed with deionized water at a ratio of 1:4 and the development time is 1 minute.

[0071] Step 3: Perform adhesive removal using the ICP process;

[0072] First, the substrate is placed on another thick glass plate to prevent deformation due to excessive thinness. It is then heated before the ICP process is performed. In one embodiment of this invention, heating for 10 minutes is followed by ICP, with the duration being 20 seconds.

[0073] Step 4: Electron beam evaporation deposition to form the bottom electrode;

[0074] A chromium (Cr) adhesion layer and a gold (Au) conductive layer are deposited by electron beam evaporation. In one embodiment of this invention, the Cr adhesion layer is deposited at a depth of 25 nm with an initial deposition rate of... Au conductive layer deposition 600nm, rate The total thickness error is controlled within ±5%.

[0075] Step 5: Perform the peeling operation;

[0076] After thoroughly removing photoresist and excess metal by soaking in 60°C acetone, rinse with deionized water and dry with nitrogen.

[0077] Step 6: Define the dielectric layer region using the pattern inversion process;

[0078] Define the dielectric layer region using the same pattern inversion process as in step two, being careful to preserve the bottom electrode pads.

[0079] Step 7: Electron beam evaporation to deposit a dielectric layer;

[0080] In one embodiment of the present invention, the dielectric layer consists of an HfO2 layer and a SiO2 layer, wherein the SiO2 layer directly covers the HfO2 layer to enhance interface stability. The HfO2 layer is deposited at 200 nm, and the SiO2 layer is deposited at 40 nm. Gradually grow to Ensure there are no pinhole defects.

[0081] Step 8: Perform the same ICP desmearing process as in Step 3;

[0082] Silicon dioxide (SiO2) is deposited immediately after hafnium dioxide (HfO2) deposition to obtain a double dielectric layer of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which aims to solve the problem that photoresist cannot be coated on the surface of hafnium dioxide (HfO2);

[0083] Step 9: Perform the same peeling operation as in Step 5;

[0084] Step 10: Define the polysilicon sacrificial layer and anchor region in the pattern inversion process;

[0085] The polysilicon sacrificial layer and anchor region are defined using the same pattern inversion process as in step two. In one optional embodiment of this invention, to ensure a smooth, crack-free anchor region structure and to form a releasable gap structure, the anchor region and the sacrificial layer are combined using a mask. Furthermore, the polysilicon region should be as small as possible to control the XeF2 etching area.

[0086] Step 11: Perform the same ICP desmearing process as in Step 3;

[0087] Step 12: Electron beam evaporation deposition of polysilicon (Poly-Si) to form a sacrificial layer and anchor region;

[0088] In one embodiment of the present invention, the polycrystalline silicon (Poly-Si) thickness is 700 nm, and the formation rate is... To ensure low stress and high uniformity, the anchor points and sacrificial layer use the same mask for pattern inversion, aiming to ensure smooth formation of the anchor points;

[0089] Step 13: Perform the same stripping operation as in Step 5;

[0090] During the formation of the top electrode and the film structure, a multilayer photoresist process was employed because a thick metal film needed to be peeled off. This was done to fabricate a high-mechanical-strength vibrating film and to integrate vias to reduce air damping.

[0091] Appendix Figure 3A theoretical picture of the lift-off process for thick metal films with multilayer photoresist is given, including steps fourteen to seventeen:

[0092] Step 14: Define the top film layer by performing a pattern reversal process using multilayer spin-coating photoresist;

[0093] Spin coat the first layer of photoresist onto the clean wafer obtained in step thirteen, then perform soft baking, spin coat the second layer of photoresist again with the same parameters, and perform soft baking again. Repeat the above operation until the photoresist thickness reaches the expected thickness. Then use a mask for photolithography exposure, reverse baking, and finally perform general exposure and development to display a clear top film pattern.

[0094] In one embodiment of the present invention, a three-layer spin-coating photoresist method is used, with the following parameters:

[0095] The first layer was spin-coated with AZ 5214E ​​photoresist at a spin speed of 1000 rpm, with an expected thickness of 3 μm and a soft bake temperature of 110°C for 15 seconds.

[0096] The second layer was spin-coated with the same parameters, with an expected thickness of 3 μm, and then soft-baked again (110℃, 15 seconds).

[0097] The third layer is spin-coated with the same parameters, requiring a total thickness of 8-9 μm, followed by final soft baking (110℃, 30 seconds).

[0098] In one optional embodiment of the present invention, during photolithography exposure and development, the initial exposure dose is 60 mJ / cm². 2 (Mask alignment accuracy ±0.5μm); Reverse baking at 120℃ hot plate for 1 minute; Wide exposure without mask, full film exposure dose 250mJ / cm². 2 Develop with AZ 726MIF developer (2.38% TMAH) for 90 seconds. To avoid metal sidewall residue, a negative sidewall angle (70-75°) is formed; this negative angle has negligible impact on the device. Multilayer photoresist spin-coating is performed during top film formation to achieve thick metal film lift-off. The aim is to achieve complete lift-off of the thick metal film through repeated stacking of single-layer photoresist, avoiding residual short circuits.

[0099] Step 15: Perform the same ICP desmearing process as in Step 3;

[0100] Step 16: Electron beam evaporation deposition of chromium and copper films;

[0101] In one optional embodiment of the present invention, the thicknesses of chromium and copper are 50 nm and 6 μm, respectively, and the deposition rate is...

[0102] Step 17: Perform the same stripping operation as in Step 5;

[0103] Step 18: Cut the wafer, then place the chip in a diluted Piranha solution (H2SO4:H2O2 = 1:20) for 5 seconds to remove residual photoresist and enhance surface hydrophilicity. Immediately afterwards, immerse it in buffered oxide etch (BOE) solution for 10 seconds to remove the oxide layer.

[0104] Step 19: Release the sacrificial layer using XeF2 dry etching;

[0105] The etching process requires multiple cycles until the polysilicon layer is completely etched, the sacrificial layer is fully released, and a vibrating CMUT cell is formed. In one embodiment of the invention, the XeF2 dry etching pressure is 6 Torr, and the time is controlled at 600 seconds per cycle, with 5 cycles, to improve the release efficiency of the sacrificial layer and the integrity of the cavity.

[0106] Step 20: Perform final cleaning, dry with nitrogen, and then encapsulate. The device fabrication is now complete.

[0107] The embodiments in this specification are described in a progressive manner. Specific examples are used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention. The above embodiments are only preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention are within the scope of protection claimed by the present invention.

[0108] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0109] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A chip structure for a MEMS acoustic emission sensor, characterized in that, From bottom to top along the z-axis, the structure includes a bottom electrode, a dielectric layer, a sacrificial layer, a top film layer, and anchor points. The bottom electrode is composed of a chromium and gold bilayer metal, serving as a fixed electrode to provide electrostatic drive. The dielectric layer is composed of a double layer of hafnium dioxide and silicon dioxide for electrical insulation. The sacrificial layer is composed of polysilicon (Poly-Si) to form an air gap between the top film layer and the bottom electrode. The top film layer is made of copper to form a suspended vibration structure, serving as both an electrode and a mechanical vibration film. The anchor points are formed by ICP etching of local areas of the sacrificial layer to expose the dielectric layer, achieving mechanical fixation and electrical connection of the top film layer.

2. The chip structure of the MEMS acoustic emission sensor according to claim 1, characterized in that, The anchor point and sacrificial layer are made of polysilicon (Poly-Si) with a thickness of 600–800 nm; the bottom electrode is made of chromium with a thickness of 20–30 nm and gold with a thickness of 500–700 nm, with a total thickness of 520–730 nm for the two metal layers; the thickness of hafnium dioxide and silicon dioxide in the dielectric layer is 180–220 nm and 35–45 nm, respectively; the top film layer is achieved by stripping a 5–7 μm copper structure with multiple layers of photoresist.

3. A fabrication process for a MEMS acoustic emission sensor chip, characterized in that, The process includes the following steps: First, the substrate is pretreated, cleaned, and activated. Then, a bottom electrode pattern is defined using a photoresist pattern reversal process. Electron beam evaporation deposition is then performed, followed by the removal of excess metal to form the bottom electrode. Next, a dielectric region is defined using a pattern reversal process. Hafnium dioxide and silicon dioxide are deposited by electron beam evaporation to form a double-layer dielectric structure. Then, a polysilicon sacrificial layer and anchor region are defined using a pattern reversal process. Silicon dioxide is then deposited by electron beam evaporation. The top film region is defined using a multilayer photoresist pattern reversal process. Chromium and copper are then deposited by electron beam evaporation to form the top film. Finally, the sacrificial layer is released through dicing, BOE, and XeF2 etching. After final cleaning and nitrogen drying, the device fabrication is complete.

4. The fabrication process of the MEMS acoustic emission sensor chip according to claim 3, characterized in that, It includes the following steps: 1) Substrate pretreatment, cleaning, and activation; 2) Define the bottom electrode pattern using a pattern reversal process; 3) Degumming is performed using the ICP process; 4) Electron beam evaporation deposition of a chromium-copper metal layer; 5) The bottom electrode is formed through a stripping operation; 6) Define dielectric regions using pattern reversal technology; 7) Perform ICP desmearing process; 8) Electron beam evaporation deposits hafnium dioxide and silicon dioxide to form a double-layer dielectric structure; 9) Perform the stripping operation; 10) Use a pattern inversion process to define the polysilicon sacrificial layer and anchor region for the device in step 9); 11) Perform ICP desmearing process; 12) Electron beam evaporation deposition of silicon dioxide is performed to form a sacrificial layer and anchor points; 13) Perform the stripping operation; 14) Define the top film layer by performing a pattern reversal process using multilayer spin-coating photoresist; 15) Perform ICP desmearing process; 16) Electron beam evaporation deposition of chromium and copper; 17) Perform the stripping operation; 17) Perform a streaking operation, then wash with Piranha solution and quickly perform BOE (Buffered Oxide Etch) operation, rinse with deionized water and dry. 18) Sacrificial layer release is achieved through XeF2 etching; 19) After final cleaning and nitrogen drying, the device fabrication is complete.

5. The fabrication process of the MEMS acoustic emission sensor chip according to claim 4, characterized in that, In step 12), the anchor point and the sacrificial layer use the same mask for pattern inversion, so that the anchor point is formed smoothly; In step 14), a top film layer is formed by spin-coating multiple layers of photoresist to achieve the removal of the thick metal film; the thick metal film is completely removed by repeatedly stacking single layers of photoresist to avoid residual short circuits. In step 19), XeF2 is used to perform dry etching on the wafer obtained in step 18; this improves the release efficiency of the sacrificial layer and the integrity of the cavity.

6. The fabrication process of the MEMS acoustic emission sensor chip according to claim 4, characterized in that, In step 1), the Pyrex substrate is cleaned sequentially with acetone, isopropanol (IPA), and deionized water, dried with nitrogen, and then baked on a hot plate at 120°C for 5 to 10 minutes.

7. The fabrication process of the MEMS acoustic emission sensor chip according to claim 4, characterized in that, In step 2), the bottom electrode pattern on the mask is sequentially transferred onto the photoresist by spin-coating HMDS and AZ5214E ​​photoresist, through mask exposure and overexposure.

8. The fabrication process of the MEMS acoustic emission sensor chip according to claim 4, characterized in that, In step 5), the wafer is placed in a container filled with acetone to remove residual photoresist and unwanted metal.

9. The fabrication process of the MEMS acoustic emission sensor chip according to claim 5, characterized in that, In step 14), the first layer of photoresist is spin-coated onto the clean wafer obtained in step 13), followed by soft baking. The second layer of photoresist is spin-coated again with the same parameters, followed by soft baking again. The above operation is repeated until the photoresist thickness reaches the expected thickness. Then, photolithography exposure is performed using a mask, followed by reverse baking. Finally, general exposure and development are performed to display a clear top film pattern. The photoresist pattern forms a negative sidewall angle (70-75°) to ensure metal deposition.

10. The fabrication process of the MEMS acoustic emission sensor chip according to claim 5, characterized in that, In step 19), XeF2 is etched using a dry etching process with parameters of 5.5–6.5 Torr pressure, 600–700 seconds per etching cycle, and 5–8 cycles.

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