Carry chain calibration method and device, time measurement unit and equipment

Abstract

The invention relates to a carry chain calibration method and device, a time measurement unit and equipment. The method comprises the following steps: acquiring a bit output sequence of a carry chain; segmenting the bit output sequence to obtain a plurality of segments to be processed; screening a target segment from the segments to be processed, and counting the number of times that each bit carry output is 1 in the target segment; and generating a remapping table of the physical bit position and the logic bit index of the carry chain based on the number of times that each bit carry output in each target segment is 1, and remapping the bit output sequence of the carry chain. By adopting the method, the precision of the multi-stage carry chain can be improved, so that systematic jitter is inhibited.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a carry chain calibration method, apparatus, time measurement unit, and device. Background Technology

[0002] In semiconductor testing equipment, high-precision time measurement units (TMUs) are implemented using time-to-digital converter (TDC) circuits. These TDC circuits are built upon carry chains within field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). The accuracy of the TMU is directly determined by the linear relationship between the number of cascaded stages and the propagation delay of the carry chain, which serves as the signal propagation path. However, the following factors can lead to uneven propagation delay distribution in multi-stage carry chains: 1. Process variations cause differences in propagation delay between adjacent carry stages; 2. Environmental interference, voltage noise, and other factors are particularly significant in high-frequency scenarios; 3. In multi-stage carry chains (such as the -CARRY8 cascade in Xilinx UltraScale), the error of a single stage increases with the number of cascaded stages, leading to a deterioration in global jitter.

[0003] To suppress uneven carry chain propagation delay distribution, existing technologies mainly rely on three methods: static layout constraints, dynamic phase compensation, and hardware-assisted calibration. The first method, static layout constraint optimization, such as using EDA tools to force placement and routing tools to optimize the delay consistency of the carry chain path, cannot dynamically compensate for delay fluctuations caused by process variations or environmental changes (temperature, voltage), and its calibration accuracy is insufficient in high-frequency scenarios (>500MHz). The second method, dynamic phase compensation, utilizes the programmable delay units of the FPGA to adjust the carry chain phase through closed-loop feedback. However, this method requires additional logic resources, has a long calibration cycle (requiring multiple iterations), and cannot solve the problem of global timing offset accumulation in multi-level carry chains. The third method, hardware-assisted calibration (such as on-chip calibration using TDC), requires increased chip area and power consumption, resulting in high costs, and TDC itself may introduce measurement errors.

[0004] In summary, there is an urgent need for a solution that does not rely on additional hardware, has a short calibration cycle (no iteration required), and can solve the problem of global timing offset accumulation in multi-level carry chains, so as to meet the timing accuracy requirements of semiconductor test equipment. Summary of the Invention

[0005] Therefore, it is necessary to provide a carry chain calibration method, apparatus, time measurement unit, and device that can be used for semiconductor testing equipment to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a carry chain calibration method, the method comprising:

[0007] Obtain the output sequence of each bit in the carry chain;

[0008] Each bit output sequence is segmented to obtain several segments to be processed;

[0009] Each target segment is selected from each segment to be processed, and the number of times each bit in each target segment has a carry output of 1 is counted.

[0010] Based on the number of times each bit is 1 in each target segment, a remapping table is generated for the physical bit position and logical bit index of the carry chain, and the bit output sequence of the carry chain is remapped.

[0011] In one embodiment, the probability of the bit carry output being 1 increases monotonically with the logic bit index from the least significant bit to the most significant bit, or the probability of the bit carry output being 1 decreases monotonically with the logic bit index from the most significant bit to the least significant bit.

[0012] In one embodiment, segmenting each of the bit output sequences to obtain several segments to be processed includes:

[0013] Based on segmentation rules and guard interval rules, each bit output sequence is segmented to obtain several segments to be processed. The segmentation rules include that the length of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed. The guard interval rule is to set a guard interval of target length before and after the segment to be processed, and the bits outside the guard interval are the valid bits of the segment to be processed. The valid bits are used to count the number of times the carry output is 1.

[0014] In one embodiment, the step of filtering the target segment from each of the segments to be processed includes:

[0015] The segment to be processed, consisting only of rising edges, is identified as the target segment; or

[0016] The segment to be processed, which includes only the rising edge, is identified as the target segment.

[0017] In one embodiment, segmenting each of the bit output sequences to obtain several segments to be processed includes:

[0018] The bit output sequences are segmented based on the overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed.

[0019] After counting the number of times each bit carries out as 1 in each of the target segments, the method further includes:

[0020] Obtain the difference in the number of times the overlapping bit in adjacent target segments has a carry output of 1;

[0021] If the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering the target segment from each segment to be processed continues until the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are equal.

[0022] In one embodiment, the step of re-segmenting each of the bit output sequences to obtain several segments to be processed includes:

[0023] After reducing the segment length of the segment to be processed and / or increasing the guard interval, the bit output sequence is segmented based on the new segment length and / or the new guard interval to obtain several segments to be processed.

[0024] In one embodiment, generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times each bit in each target segment has a carry output of 1, and remapping the bit output sequence of the carry chain, includes:

[0025] Based on the difference in the number of times the carry output is 1 corresponding to the overlapping bits of adjacent target segments, the number of times the carry output is 1 for the effective bits after the overlapping bits in the next target segment in the adjacent target segments is corrected.

[0026] Based on the number of times the corrected carry output of each bit in each target segment is 1, a remapping table of the physical bit position and logical bit index of the carry chain is generated, and the bit output sequence of the carry chain is remapped.

[0027] In one embodiment, the correction of the number of carry-outs of valid bits following overlapping bits in the next target segment being 1 based on the difference in the number of times the carry-out output is 1 for overlapping bits in adjacent target segments includes:

[0028] Starting from the first target segment, calculate the difference in the number of times the overlapping bit carry output is 1 in adjacent target segments;

[0029] The difference is added to the number of times the carry output of the effective bits after the overlapping bits in the next target segment is 1, to obtain the corrected number of times the carry output of the effective bits after the overlapping bits is 1, until all target segments have been processed.

[0030] In one embodiment, generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the corrected carry output of each bit in each of the target segments is 1, and remapping the bit output sequence of the carry chain includes:

[0031] Based on the number of times the corrected carry output of each bit in each target segment is 1, the bits are sorted in ascending order or descending order.

[0032] The bit output sequence of the carry chain is remapped based on the remapping table.

[0033] Secondly, this application also provides a carry chain calibration device, the device comprising:

[0034] The acquisition module is used to acquire the output sequence of each bit in the carry chain;

[0035] The segmentation module is used to segment each bit output sequence to obtain several segments to be processed.

[0036] The frequency statistics module is used to filter each target segment from each segment to be processed, and to count the number of times the carry output of each bit in each target segment is 1.

[0037] The remapping calibration module is used to generate a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the carry output of each bit in each target segment is 1, and to remap the bit output sequence of the carry chain.

[0038] Thirdly, this application also provides a time measurement unit, including a carry chain, that performs the steps of the method as described in any of the above embodiments.

[0039] Fourthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0040] The aforementioned carry chain calibration method, apparatus, time measurement unit, and device acquire the bit output sequence of the carry chain; segment the bit output sequence to obtain several segments to be processed; select target segments from the segments to be processed and count the number of times each bit in the target segment has a carry output of 1; generate a remapping table between the physical bit positions and logical bit indices of the carry chain based on the number of times each bit in the target segment has a carry output of 1, and remap the bit output sequence of the carry chain. In this way, by statistically analyzing the frequency distribution of carry outputs of logic 1 at each physical bit position, a remapping relationship between physical bit positions and logical bit indices is established, converting physical bit positions into logical bit indices, thereby improving the accuracy of time measurement. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a diagram illustrating the application environment of the carry chain calibration method in one embodiment;

[0043] Figure 2 This is a flowchart illustrating a carry chain calibration method in one embodiment;

[0044] Figure 3 This is a schematic diagram of the time-domain waveform corresponding to the three-bit output sequence in one embodiment;

[0045] Figure 4 This is a segmentation diagram in one embodiment;

[0046] Figure 5 This is a flowchart of the additive splicing step in one embodiment;

[0047] Figure 6 This is a schematic diagram of remapping in one embodiment;

[0048] Figure 7 for Figure 6 A schematic diagram showing the position of each bit in the illustrated embodiment;

[0049] Figure 8 A flowchart of the carry chain calibration method in another embodiment;

[0050] Figure 9 A schematic diagram showing the length and number of bubbles in each bit of the segmented calibration carry chain;

[0051] Figure 10A schematic diagram showing the length and number of bubbles in each bit of the carry chain after segmented calibration;

[0052] Figure 11 This is a structural block diagram of the carry chain calibration device in one embodiment;

[0053] Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0056] In this application, "output carry-1" means that the output value of the carry-in is 1.

[0057] The carry chain calibration method provided in this application embodiment can be applied to, for example... Figure 1 The time measurement unit shown is a carry chain. This time measurement unit includes a carry chain, wherein the time measurement unit can calibrate the bit output sequence of the carry chain to optimize the jitter performance of the test measurement unit (TMU) by dynamically statistically analyzing the carry chain propagation delay distribution.

[0058] It should be noted that the jitter involved in this application refers to the deviation of the signal edge from the ideal timing, including: timing delay caused by carry chain, environmental noise / interference, which cause signal jitter.

[0059] The time measurement unit in this application can be a time measurement unit in an FPGA or ASIC, and in other embodiments, it can also be a time measurement unit in other chips.

[0060] Timing delays and jitter can lead to the accumulation of timing errors. A timing measurement unit can be used to precisely measure the accumulation of timing errors, quantify delay and jitter parameters, and thus optimize the system timing design.

[0061] In a multi-level carry chain structure, all carry outputs have a fixed physical layout. Once the hardware implementation is determined, the physical position (i.e., bit index) of each carry bit is also fixed. Taking a carry chain with 8 taps (called carry8) as an example, its 8 carry outputs correspond to bit positions 0 to 7 in sequence; the second carry8 follows immediately after the highest bit output (i.e., bit 7) of the previous carry chain, and subsequent levels follow the same pattern, forming a continuous sequence of bit indices. Ideally, this structure corresponds to a monotonically increasing curve, where the horizontal axis represents the bit position, increasing from the LSB to the most significant bit MSB, and the vertical axis represents the probability that the carry output of that bit is logic 1. In actual hardware operation, the propagation timing characteristics of carry signals can dynamically shift due to factors such as timing jitter, process deviations, or environmental noise. These timing deviations distort the probability distribution of carry output as logic 1. For example, process deviations may cause an abnormally large carry propagation delay for physical bit 3, resulting in a carry output probability lower than the ideal value, while the physical position of this bit (bit index = 3) remains fixed. Therefore, the observed "probability-bit position" curve will deviate from the ideal monotonically increasing characteristic (such as the appearance of local plateaus or non-monotonic points), but the overall trend still maintains a monotonically increasing trend from LSB to MSB. Based on this statistical regularity, this application proposes a calibration method: by statistically analyzing the carry output 1 frequency of each physical position in a massive sample, a measured probability distribution curve is constructed; this curve is compared with the ideal monotonically increasing model to establish a remapping table of physical bit position → logic bit index, which is used to remap the carry chain output data—when physical bit k is remapped to logic bit n, the system writes the k-th bit of the original output data into the n-th bit of the result.

[0062] One point to note is that this application relies on the randomness of operands and requires statistical analysis based on a large number of random carry-chain bit output sequences. As the sample size approaches infinity, the observed probability will converge to the theoretical probability. In this application, counting the number of carry-out outputs of 1 approximates the probability of a carry-out output of 1 through frequency analysis. For ease of understanding, this application can set the number of carry-chain bit output sequences to be greater than a threshold. This threshold can be determined manually, but it is necessary to ensure that the sample size is sufficiently large.

[0063] In one exemplary embodiment, such as Figure 2 As shown, a carry chain calibration method is provided, which is applied to... Figure 1 Taking the time measurement unit in the middle as an example, the explanation includes the following steps 202 to 208. Wherein:

[0064] S202: Obtain the output sequence of each bit in the carry chain.

[0065] Specifically, the carry chain generates a bit output sequence when an input is present. For example, a periodic square wave signal can be input into the carry chain (R = N × K bits), where N represents the number of carry chains (N levels), K represents the number of taps in each carry chain level (which is also equal to the number of bits in each carry chain level), and R represents the total number of bits in each time-domain waveform. The frequency f of the periodic square wave is determined by the operating scenario of the Time Measurement Unit (TMU). R is greater than the number of bits in one period of the periodic square wave. R, N, and K are all positive integers greater than or equal to 1.

[0066] Combination Figure 3 As shown, the time measurement unit acquires M consecutive output sequences of R bits. Figure 3 In the illustrated embodiment, N=4, K=8, M=3, and R=32. In this embodiment, by acquiring a multi-level carry chain, the synchronization of all levels can be optimized, avoiding the accumulation of errors caused by cascading during single-level calibration.

[0067] In some optional embodiments, R bits are flipped from bit R-1, bit R-2, ..., bit 1, bit 0 to bit 0, bit 1, ..., bit R-2, bit R-1. This way, when the bit output sequence is subsequently judged, the rising edge is actually a falling edge. In other optional embodiments, this flipping step is omitted.

[0068] S204: Segment the output sequence of each bit to obtain several segments to be processed.

[0069] Specifically, the segment to be processed is obtained by segmenting each bit output sequence. The purpose of segmentation is to ensure that the statistical window does not span two level transitions and only includes rising or falling edges. The segment to be processed includes multiple bits, and the bits include 0 and 1, so that each segment to be processed includes either rising or falling edges.

[0070] Each segment to be processed is continuous, and there is overlap between adjacent segments. This allows for difference correction based on the number of times the carry-out output of the overlapping bits is 1. In some optional embodiments, the segments to be processed include segmentation rules or a combination of segmentation rules and guard interval rules. The segmentation rules ensure that the statistical window does not span two level transitions, only including rising or falling edges. Especially in high-frequency scenarios, there are not only multiple carry chains but also multiple cycles with high and low level changes. Only within a certain segment to be processed is the probability of the carry-out output of a bit strictly monotonically increasing with the logic bit index from LSB to MSB. If the segment is not divided into multiple segments, the statistical range will be affected by level transitions, which will not satisfy the monotonically increasing "bit-probability" relationship, and the statistical results will be invalid. Therefore, this application requires segmentation of each bit. The guard interval rule is to avoid the influence of adjacent segments on the current segment to be processed, so that only the valid bits in the middle are counted. In other embodiments, the segments to be processed also include an overlap rule when segmenting. The overlap rule is that there are overlapping bits between the valid bits of adjacent segments to be processed. This allows for verification based on the overlapping bits to ensure the accuracy of the segments to be processed, thereby improving the verification efficiency.

[0071] S206: Select the target segment from the segments to be processed, and count the number of times each bit in the target segment has a carry output of 1.

[0072] Specifically, the target segment is selected from the segments to be processed, including only segments with rising or falling edges, where the target segments are also continuous and overlapping.

[0073] Count the number of times each bit in each target segment has a carry-out output of 1, that is, count the number of times a high level occurs in each target segment. In other embodiments, the number of times a 0 occurs in each bit can also be counted. Alternatively, both the number of 1s and the number of 0s can be counted.

[0074] S208: Generate a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times each bit in each target segment has a carry output of 1, and remap the bit output sequence of the carry chain.

[0075] In some optional embodiments, the probability of a carry-out output being 1 monotonically increases with the logical bit index from the least significant bit to the most significant bit, or the probability of a carry-out output being 1 monotonically decreases with the logical bit index from the most significant bit to the least significant bit. The number of times a bit appears as 0 is negatively correlated with the bit's position in the carry chain; that is, in a certain target segment, the number of carry-out outputs being 0 is monotonically decreasing with the bit's position.

[0076] In the ideal carry chain propagation model, the probability of a carry output being 1 increases strictly monotonically with the logical bit index from least significant bit to most significant bit (LSB→MSB), or the probability of a carry output being 1 decreases monotonically with the logical bit index from most significant bit to least significant bit. When factors such as process variations cause non-monotonic points in the mapping between physical bit positions and logical bit indices, this theoretical characteristic will be reconstructed after remapping the carry chain bit output sequence using the remapping table. The physical bit position with the lowest statistical frequency will be mapped to the logical LSB, and the physical bit position with the highest statistical frequency will be mapped to the logical MSB.

[0077] In other words, the higher the position of the carry-in bit, the greater the delay and the greater the probability of the carry-out output being 1. Therefore, the order of the bits in the carry-in chain can be determined according to the probability of each bit outputting 1 with a carry.

[0078] For any position k of the full adder

[0079] ,when and This will inevitably lead to a carry-over.

[0080] carry propagation ,when When a carry-over from a lower position propagates to a higher position.

[0081] Carry Output .

[0082] Therefore, carry output can be generated in two ways: one is by directly generating the carry. and 1+1=10; another way is through propagation: When the carry-over from the lower bit is propagated to the higher bit, that is, 1+0+1=10.

[0083] Probability calculation (input uniformly random)

[0084]

[0085]

[0086]

[0087] ( Depends on , and They are mutually exclusive, so there is no overlap.

[0088] LSB (k=0), ,

[0089] ,

[0090]

[0091] …

[0092] By mathematical induction, we can obtain:

[0093]

[0094] The larger k is (i.e., the higher the bit in the carry chain), the more likely it is to be. The larger.

[0095] Therefore, estimating the delay of each bit in the carry chain by counting the number of carry-out 1s implies a key statistical mathematical foundation: the number of carry-out 1s is monotonically increasing with the time it takes for the signal to propagate to that bit. If both rising and falling edges exist within a statistical window, this statistical method's mathematical foundation fails. Especially in high-frequency scenarios, multi-level chains only increase the number of cycles for the output bits, and multi-segmentation is a prerequisite for calibration. Furthermore, according to the law of large numbers, as the sample size approaches infinity, the observation frequency will converge to the theoretical probability. Therefore, in practical applications, a sufficiently large sample size (i.e., a sufficiently large value for M, meaning a sufficient number of bit output sequences) is required to approximate this limit.

[0096] Therefore, in this application, a remapping table of physical bit positions and logical bit indices of the carry chain is generated by counting the number of times each bit in each target segment has a carry output of 1. The bit output sequence of the carry chain is then remapped to determine the accurate position of each bit and achieve calibration.

[0097] This method involves inputting a periodic signal and capturing multiple sets of bit sequences. By segmenting and counting the number of 1s in each bit, the propagation delay difference of each bit can be quantified, thus eliminating statistical errors introduced by level transitions. Furthermore, the calibration process is implemented entirely through digital logic, eliminating the need for a time-delay converter (TDC) or programmable delay units, making it suitable for resource-sensitive FPGA / ASIC designs.

[0098] The number of times each bit in each target segment has a carry-out output of 1 can be counted using a counter. This count is performed on the i-th segment. The counter is obtained by summing the data bit by bit. The dimension is 1×R.

[0099] For ease of understanding, each target segment can determine its corresponding start and end positions after segmentation, as well as the position of the valid bit (i.e., its position in the multi-level carry chain; for example, if the multi-level carry chain is 32 bits, it can be any bit in the 32 bits). By summing the number of times the carry output of the bits with the same position in all target segments is 1, we can obtain the number of times the carry output of this bit is 1.

[0100] The above-described carry chain calibration method obtains the bit output sequence of the carry chain; segments the bit output sequence to obtain several segments to be processed; selects target segments from the segments to be processed and counts the number of times each bit in the target segment has a carry output of 1; generates a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times each bit in the target segment has a carry output of 1, and remaps the bit output sequence of the carry chain to have a carry output of 1. In this way, the bit output sequence of the multi-level carry chain is dynamically segmented and frequency counted, which can improve the accuracy of the multi-level carry chain and thus suppress systematic jitter.

[0101] In some optional embodiments, the bit output sequence is segmented to obtain several segments to be processed, including: segmenting the bit output sequence based on segmentation rules and guard interval rules to obtain several segments to be processed. The segmentation rules include that the length of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed. The guard interval rule is to set a guard interval of target length before and after the segment to be processed, and the bits outside the guard interval are the valid bits of the segment to be processed. The valid bits are used to count the number of times the carry output is 1.

[0102] To ensure that each segment to be processed does not span two level transitions and includes only one rising edge or one falling edge, this application sets a segmentation rule: the length of each segment to be processed is less than or equal to the shorter of the durations of 1 and 0 within the current cycle of the segment to be processed. Figure 3 If one cycle has a high level lasting 7 bits and a low level lasting 5 bits, then L≤5. In this way, at least one segment to be processed has a bit carry output of 0 and 1.

[0103] The protection interval rule is designed to avoid the influence of adjacent segments to be processed. This is because a small segment of bits at the beginning and end of a segment is affected by the bits before and after it. Therefore, a protection interval of target length G is set before and after each segment to be processed, where G is greater than or equal to 1. Figure 4 As shown, Figure 4 This is a segmentation diagram in one embodiment. The length of each segment is L, and the target length, i.e., the protection interval length, is G. Subsequent calculations only include the valid bits in the middle, i.e., the bits in each segment excluding the protection interval length. The length of the valid bits is... .

[0104] In some alternative embodiments, filtering target segments from the segments to be processed includes: determining the segments to be processed that include only rising edges as target segments; or determining the segments to be processed that include only falling rising edges as target segments.

[0105] In high-frequency scenarios, there will be many cycles, and the high and low levels will change multiple times. Directly counting the entire segment would violate the aforementioned implicit statistical mathematical foundation. Therefore, it is necessary to segment the data so that each segment contains only one edge (rising edge or falling edge).

[0106] Each segment to be processed is filtered to obtain a target segment that includes only rising edges or only falling edges. It should be noted that during a single calibration process, either the target segment including rising edges is selected from all the segments to be processed, or the target segment including falling edges is selected from all the segments to be processed.

[0107] Each bit output sequence is divided into several segments to be processed. Each segment to be processed in the M bit output sequences is filtered to obtain a target segment that includes only rising edges or only falling edges. The filtering process can be carried out in parallel. For example, the M bit output sequences can be filtered in parallel by M threads.

[0108] The selection method for the target segment is that the first few bits of the segment are all 0 and the last few bits are all 1. For example, when judging the i-th segment bits P to LP-1, the first 4 bits and the last 4 bits are selected for judgment, i.e., bits P to LP-1. All zeros, and bits The segments to be processed that are all 1s are selected, among which The target segments obtained by filtering from each segment to be processed in the M-group bit output sequence total a certain number. Group, .

[0109] One point to note is that here we select the first 4 bits and the last 4 bits for judgment. In other embodiments, we can also select the first 2 bits and the last 2 bits for judgment. We just need to ensure that the selected first 4 bits and last 4 bits are not repeated and that the number of selected bits is less than the length L of the segment to be processed. For example, if we select the first 4 bits and last 4 bits, then L should be greater than 4 + 4, that is, L is greater than 8.

[0110] In the above embodiments, since the length L of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed, there is at least one segment to be processed that includes only a rising edge or only a falling edge. In this embodiment, based on the position of the bit carry output 0 and 1, the segments to be processed that only include a rising edge are selected as target segments, or the segments to be processed that only include a falling edge are selected as target segments.

[0111] In some optional embodiments, the bit output sequence is segmented to obtain several segments to be processed, including: segmenting the bit output sequence based on an overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed; after counting the number of times each bit in each target segment has a carry output of 1, the method further includes: obtaining the difference between the number of times the overlapping bits in adjacent target segments have a carry output of 1; if the difference between the number of times the overlapping bits have a carry output of 1 is not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering target segments from each segment to be processed is continued until the difference between the number of times the overlapping bits have a carry output of 1 is equal.

[0112] The overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed, and n bits are reserved between adjacent segments. >n≥2) bit overlap region, used to verify the correctness of segmentation. In order to improve the calibration efficiency, n takes the minimum value of 2. The last 2 bits in the effective length of the i-th segment overlap with the first 2 bits in the effective length of the (i+1)-th segment.

[0113] Combination Figure 4 As shown, it is divided into S segments. , This indicates rounding down, where 2 is the number of overlapping bits in the bit overlap region. In other embodiments, other values ​​can be used; here, only n=2 is used for illustration.

[0114] After all target segments have been statistically analyzed, the entire set of logical bits cannot be directly sorted. This is because although there are M sets of sample carry chains output sequences, the total number of test samples after each segmentation may be different. Therefore, the absolute count values ​​of the same bit in two adjacent target segments will not be equal, and the target segments will be discontinuous. However, in reality, the probability increments of two adjacent bits are equal (slopes are consistent) in different target segments.

[0115] Assume the number of samples that meet the first target segment is M1 (M1≤M), the curve of two overlapping bits and its carry output is "1" is y=k1*x +b1, and the statistical results of overlapping bits x1 and x2 are y11=k1*x1 +b1 and y12=k1*x2+b1, respectively.

[0116] The number of samples in the second target segment is M2 (M2≤M). The curve of the two overlapping bits and their carry output of 1 is y=k2*x +b2. The statistical results of the overlapping bits x1 and x2 are y21= k2*x1+b2 and y22= k2*x2 +b2, respectively.

[0117] Specifically, the probability increments of the carry-out output of 1 for two overlapping bits in the first and second target segments are k1 = (y12-y11) / (x2-x1) and k2 = (y22-y21) / (x2-x1), respectively. Since the probability increment k1 = k2, y12-y11 = y22-y21, meaning the difference in the number of carry-out outputs of 1 for the two overlapping bits is equal in the first and second target segments. Similarly, if there are three overlapping bits, then the third bit x3 and its adjacent second bit also satisfy y13-y12 = y23-y22 in the first and second target segments, respectively, where y13 and y23 represent the number of carry-out outputs of 1 for x3 in the first and second target segments. Likewise, if there are more overlapping bits, the difference in carry-out outputs of 1 between any two adjacent bits is equal in all target segments. Rearranging the equations y12-y11=y22-y21, we get y12-y22 = y11-y21, and y13-y12= y23-y22, we get y13-y23=y12-y22. Clearly, y13-y23 = y12-y22 = y11-y21. This physically means that the frequency difference between corresponding bits in adjacent overlapping segments is equal. That is, for adjacent target segments, the difference in the number of times the carry outputs of the two segments of the first overlapping bit are 1 should be equal to the difference in the number of times the carry outputs of the two segments of the second overlapping bit are 1. If the number of overlapping bits is greater than or equal to 3, then the difference in the number of times the carry outputs of the two segments of the first overlapping bit are 1 should be equal to the difference in the number of times the carry outputs of the two segments of the second overlapping bit are 1, and also equal to the difference in the number of times the carry outputs of the two segments of the third overlapping bit are 1. In other words, the difference in the number of times the carry outputs of the two ends of each overlapping bit should be equal.

[0118] If the difference in the number of times the carry output is 1 for overlapping bits in at least one target segment is not equal, a segmentation error is determined, and therefore the bit output sequence needs to be segmented to obtain several segments to be processed. In some optional embodiments, the bit output sequence is re-segmented to obtain several segments to be processed, including: reducing the segment length of the segments to be processed and / or increasing the guard interval, and then segmenting the bit output sequence based on the new segment length and / or the new guard interval to obtain several segments to be processed.

[0119] A segmentation error means that the first and last bits of the current segment are still affected by the adjacent segments before and after it. Therefore, it is necessary to increase the guard interval G and / or reduce the segment length L of the segment to be processed in order to reduce the influence of the adjacent segments before and after it.

[0120] Among them, still with Figure 3 For example, assuming L=5, G=1, and n=2, using waveform 1 as the bit output sequence, the first segment to be processed is 00001, the second segment is 00011, the third segment is 00111, the fourth segment is 01111, the fifth segment is 11111, the sixth segment is 11111, and so on, resulting in 32 segments to be processed. These segments are then filtered to obtain the target segment. Similarly, using waveform 2 as the bit output sequence, the first segment to be processed is 00011, the second segment is 00111, the third segment is 01111, the fourth segment is 11111, the fifth segment is 11111, the sixth segment is 11111, and so on, resulting in 32 segments to be processed.

[0121] Based on the selected target segment, the number of times each bit in the valid bits has a carry-out of 1 is counted. Assuming there are only 12 segments to be processed from waveforms 1 to 3 (in other embodiments, more may be included; this embodiment is for illustrative purposes only), the positions corresponding to the two first segments are the same. Therefore, the number of times each valid bit has a carry-out of 1 can be counted: the second bit has a carry-out of 1 0 times, the third bit has a carry-out of 1 0 times, and the fourth bit has a carry-out of 1 1 time. The positions corresponding to the two second segments are the same, so the number of times each bit has a carry-out of 1 can be counted. The number of times the valid bits appear is: the third bit has a carry-out of 1 0 times, the fourth bit has a carry-out of 1 0 times, and the fifth bit has a carry-out of 1 2 times.

[0122] Due to the aforementioned overlap rules, adjacent target segments contain overlapping bits in their effective bits. For target segments with different positions, the number of times the carry-out output of this overlapping bit is 1 is counted. The difference in the number of carry-out outputs of the two segments of the first overlapping bit should be equal to the difference in the number of carry-out outputs of the two segments of the second overlapping bit. For example, if the effective overlapping bits in the first and second segments to be processed are the third and fourth bits, then the difference in the number of carry-out outputs of the two segments of the third bit should be equal to the difference in the number of carry-out outputs of the two segments of the fourth bit. However, this is not the case, therefore G and / or L need to be adjusted.

[0123] In the above embodiments, the accuracy of the segmentation is verified by overlapping bits at adjacent ends, eliminating statistical errors introduced by level transitions.

[0124] In some optional embodiments, the bit output sequence of the carry chain is remapped based on the number of times each bit in each target segment has a carry output of 1, including: correcting the number of times the carry output of the effective bits after the overlapping bits in the next target segment in the adjacent target segment has a carry output of 1 based on the difference in the number of times the overlapping bits in adjacent target segments have a carry output of 1; and remapping the bit output sequence of the carry chain based on the corrected number of times the carry output of each bit in each target segment has a carry output of 1.

[0125] In this application, since the screening conditions of adjacent segments are inconsistent, the difference of overlapping bits is used for compensation and splicing. Multiple segments are successively checked and additively spliced ​​to complete the global calibration.

[0126] In some alternative embodiments, combined with Figure 5 As shown, Figure 5 This is a flowchart of an additive splicing step in one embodiment. The additive splicing step is mainly to compensate for the difference in the absolute value of statistical frequencies caused by the different total number of test samples after screening different target segments (M1≠M2). Taking the above example, the intercepts need to be equal. Therefore, the compensation difference for the second segment is Δ=b1-b2, i.e., y21+Δ= y21+b1-b2=y11, and similarly y22+Δ=y12. Specifically, in this embodiment, this additive splicing step, based on the difference in the number of times the carry output is 1 corresponding to the overlapping bits of adjacent target segments, corrects the number of times the carry output is 1 for the effective bits after the overlapping bits in the next target segment of the adjacent target segment. This includes:

[0127] S502: Starting from the first target segment, calculate the difference in the number of times the overlapping bit carry outputs as 1 in adjacent target segments.

[0128] During the segmentation process, the changing selection conditions for each segment cause the objective probability "absolute value" to become a "relative value," resulting in a difference in the frequency of identical bits appearing in two segments. Therefore, the probability of the first target segment is used as a benchmark to compensate for the "relative values" of all other target segments. Here, the relative value is the difference in the number of times overlapping bits in adjacent target segments output 1. The core of multi-segment additive concatenation is to normalize all "probability" calculations to a single standard; in this application, the probability of the first target segment is chosen as the benchmark.

[0129] Here, we assume that the frequencies of the overlapping bits at the end of the i-th target segment counter are respectively and The frequencies of the overlapping bits at the beginning of the (i+1)th target segment are respectively and And satisfy , here This is the difference in the number of times the overlapping bit carry outputs 1 in adjacent target segments.

[0130] S504: Add the difference to the number of times the carry output of the effective bits after the overlapping bits in the next target segment is 1, to obtain the corrected number of times the carry output of the effective bits after the overlapping bits is 1, until all target segments have been processed.

[0131] The number of times the carry output of the effective bit region after the first overlapping bit of the (i+1)th target segment is 1 is uniformly added. And update the global counter with the result. The count corresponding to the bit position is denoted as the i-th update.

[0132]

[0133] This represents the effective bits following the overlapping bits at the beginning of the (i+1)th target segment. express Compared with the i-th update The difference in the number of times the overlapping bit carry outputs 1 is used to update the final global counter segment by segment.

[0134] In the above embodiments, the difference in the number of times the carry output is 1 in the overlapping area of ​​adjacent segments is used for correction, and the segmented statistical results are concatenated into a global frequency table to ensure the consistency of the delay distribution of multi-level carry chains. The layout parameters are dynamically adjusted according to the frequency sorting to suppress systematic jitter.

[0135] In some optional embodiments, a remapping table of physical bit positions and logical bit indices of the carry chain is generated based on the number of times the corrected carry output of each bit in each target segment is 1, and the bit output sequence of the carry chain is remapped, including: sorting the bits in ascending order or descending order based on the number of times the corrected carry output of each bit in each target segment is 1; and remapping the bit output sequence of the carry chain based on the sorted bits.

[0136] The system globally corrects the number of times each bit in the counter outputs a carry of 1. It can sort the carry outputs of 1 from high to low or from low to high. After sorting the counts from low to high, the corresponding mapping order is from LSB to MSB; after sorting the counts from high to low, the corresponding mapping order is from MSB to LSB.

[0137] For ease of understanding, combined with Figure 6 As shown, Figure 6 The waveform is an output bit sequence with bits ordered from 0 to 64. Figure 7 for Figure 6 The diagram illustrates the position of each bit in the illustrated embodiment. Assuming that after remapping, the number of times the 5th bit carries and outputs 1 is less than the number of times the 7th bit carries and outputs 1, the number of times the 7th bit carries and outputs 1 is less than the number of times the 3rd bit carries and outputs 1, the number of times the 3rd bit carries and outputs 1 is less than the number of times the 4th bit carries and outputs 1, and the number of times the 4th bit carries and outputs 1 is less than the number of times the 6th bit carries and outputs 1, the order of the bits from the least significant bit to the most significant bit after remapping is the 5th bit, the 7th bit, the 3rd bit, the 4th bit, and the 6th bit. The processing of bits 19 to 21 is similar and will not be described in detail here.

[0138] For ease of understanding, combined with Figure 8 As shown, Figure 8 The flowchart of the carry chain calibration method in another embodiment is as follows: First, a periodic square wave signal is input to a multi-stage carry chain, and M sets of R bit output sequences are acquired.

[0139] Then, based on the segmentation rules and guard interval rules, each bit output sequence is segmented to obtain several segments to be processed.

[0140] Several target segments are obtained by filtering several segments to be processed.

[0141] The number of times each bit in the target segments with the same position outputs 1 is counted. Based on the premise that the difference in the number of times each overlapping bit in the effective bits of adjacent target segments outputs 1 in the two target segments should be the same, the segmentation result is verified. If the verification fails, the values ​​of G and / or L are adjusted to re-segment.

[0142] If the check is successful, additive concatenation is performed to update the number of times each bit in the counter has a carry output of 1. Finally, the bits are sorted based on the number of times each bit has a carry output of 1, and remapping is performed based on the sorted bits.

[0143] For ease of understanding, combined with Figure 9 As shown, Figure 9 This diagram illustrates the time length and number of bubbles at each bit position in the 65536 random carry outputs of the 98-level CARRY8 carry chain before segmented calibration. Figure 10 This diagram illustrates the duration and number of bubbles at each bit position in the 65536 random carry outputs of the carry chain after segmented calibration. The bubbles represent jitter occurring on the rising edge of the cycle; darker colors indicate more bubbles, representing more unstable transitions at the rising edge. Longer durations indicate longer periods of rising edge instability, leading to inaccurate TMU calculations. Calibration significantly reduces bubble length and number, substantially improving the instability of the carry chain output.

[0144] In the above embodiments, by inputting a periodic signal and capturing multiple sets of bit sequences, the propagation delay difference of each bit is quantified using a segmented statistical frequency method. This is combined with overlapping bit verification (to verify the validity of the segmentation) to eliminate statistical errors introduced by level transitions. The frequency difference between adjacent overlapping segments is used for correction, and the segmented statistical results are concatenated into a global frequency table to ensure the consistency of the delay distribution of multi-level carry chains. Layout parameters are dynamically adjusted according to the frequency sorting to suppress systematic jitter. The calibration process is implemented entirely through digital logic, requiring no TDC or programmable delay unit, making it suitable for resource-sensitive FPGA / ASIC designs.

[0145] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0146] Based on the same inventive concept, this application also provides a carry chain calibration device for implementing the carry chain calibration method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more carry chain calibration device embodiments provided below can be found in the limitations of the carry chain calibration method described above, and will not be repeated here.

[0147] In one exemplary embodiment, such as Figure 11 As shown, a carry chain calibration device is provided, comprising: a data acquisition module 1001, a segmentation module 1002, a frequency statistics module 1003, and a remapping calibration module 1004, wherein:

[0148] Acquisition module 1001 is used to acquire the output sequence of each bit of the carry chain;

[0149] Segmentation module 1002 is used to segment each bit output sequence to obtain several segments to be processed;

[0150] The frequency statistics module 1003 is used to filter each target segment from each segment to be processed, and to count the number of times the carry output of each bit in each target segment is 1.

[0151] The remapping calibration module 1004 is used to generate a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the carry output of each bit in each target segment is 1, and to remap the bit output sequence of the carry chain.

[0152] In some alternative embodiments, the probability of the bit carry output being 1 increases monotonically with the logic bit index from the least significant bit to the most significant bit, or the probability of the bit carry output being 1 decreases monotonically with the logic bit index from the most significant bit to the least significant bit.

[0153] In some optional embodiments, the segmentation module 1002 is segmented based on any of the following methods: or the bit output sequence is segmented based on segmentation rules and guard interval rules to obtain several segments to be processed. The segmentation rules include that the length of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed. The guard interval rule is to set a guard interval of target length before and after the segment to be processed, and the bits outside the guard interval are the valid bits of the segment to be processed. The valid bits are used to count the number of times the carry output is 1.

[0154] In some optional embodiments, the frequency statistics module 1003 is specifically used to determine the segment to be processed that includes only the rising edge as the target segment; or to determine the segment to be processed that includes only the falling rising edge as the target segment.

[0155] In some optional embodiments, the segmentation module 1002 is specifically used to segment each bit output sequence based on an overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed.

[0156] The aforementioned device further includes: a verification module, used to obtain the difference in the number of times the carry output is 1 corresponding to the overlapping bits in adjacent target segments; when the difference in the number of times the carry output is 1 corresponding to each overlapping bit is not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering the target segment from each segment to be processed is continued until the difference in the number of times the carry output is 1 corresponding to each overlapping bit is equal.

[0157] In some optional embodiments, the segmentation module 1002 is specifically used to reduce the segment length of the segment to be processed and / or increase the guard interval, and then segment the bit output sequence based on the new segment length and / or the new guard interval to obtain several segments to be processed.

[0158] In some optional embodiments, the remapping calibration module 1004 is specifically used to correct the number of carry-outs of valid bits after overlapping bits in the next target segment in adjacent target segments based on the difference in the number of carry-outs of overlapping bits in adjacent target segments; generate a remapping table of physical bit positions and logical bit indices of carry chain based on the corrected number of carry-outs of each bit in each target segment, and remap the bit output sequence of carry chain.

[0159] In some optional embodiments, the remapping calibration module 1004 is specifically used to calculate the difference in the number of times the carry output of the overlapping bits in adjacent target segments is 1, starting from the first target segment; add the difference to the number of times the carry output of the effective bits after the overlapping bits in the next target segment is 1, to obtain the corrected number of times the carry output of the effective bits after the overlapping bits is 1, until all target segments have been processed.

[0160] In some optional embodiments, the remapping calibration module 1004 is specifically used to sort the bits in ascending or descending order based on the number of times the corrected carry output of each bit in each target segment is 1; and to remap the bit output sequence of the carry chain based on the sorted bits.

[0161] Each module in the aforementioned carry chain calibration device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0162] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 12 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a carry chain calibration method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0163] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0164] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0165] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0166] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0167] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0168] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0169] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A carry chain calibration method, characterized in that, The method includes: Obtain the output sequence of each bit in the carry chain; Each bit output sequence is segmented to obtain several segments to be processed; Each target segment is selected from each segment to be processed, and the number of times each bit in each target segment has a carry output of 1 is counted. Based on the number of times each bit in each target segment has a carry output of 1, a remapping table is generated between the physical bit position and the logical bit index of the carry chain, and the bit output sequence of the carry chain is remapped.

2. The method according to claim 1, characterized in that, The probability of the bit carry output being 1 increases monotonically with the logic bit index from the least significant bit to the most significant bit, or the probability of the bit carry output being 1 decreases monotonically with the logic bit index from the most significant bit to the least significant bit.

3. The method according to claim 1, characterized in that, The segmentation of each bit output sequence to obtain several segments to be processed includes: Based on segmentation rules and guard interval rules, each bit output sequence is segmented to obtain several segments to be processed. The segmentation rules include that the length of each segment to be processed is less than or equal to the shorter duration of 1 and 0 in the current period of the segment to be processed. The guard interval rule is to set a guard interval of target length before and after the segment to be processed, and the bits outside the guard interval are the valid bits of the segment to be processed. The valid bits are used to count the number of times the carry output is 1.

4. The method according to claim 1, characterized in that, The step of filtering the target segment from each of the segments to be processed includes: The segment to be processed, consisting only of rising edges, is identified as the target segment; or The segment to be processed, which includes only the rising edge, is identified as the target segment.

5. The method according to any one of claims 1 to 4, characterized in that, The segmentation of each bit output sequence to obtain several segments to be processed includes: The bit output sequences are segmented based on the overlap rule to obtain several segments to be processed, wherein the overlap rule is that there are overlapping bits between the effective bits of adjacent segments to be processed. After counting the number of times each bit carries out as 1 in each of the target segments, the method further includes: Obtain the difference in the number of times the overlapping bit in adjacent target segments has a carry output of 1; If the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are not equal, the bit output sequence is re-segmented to obtain several segments to be processed, and the step of filtering the target segment from each segment to be processed continues until the differences in the number of times the carry output is 1 corresponding to each of the overlapping bits are equal.

6. The method according to claim 5, characterized in that, The process of re-segmenting each bit output sequence to obtain several segments to be processed includes: After reducing the segment length of the segment to be processed and / or increasing the guard interval, the bit output sequence is segmented based on the new segment length and / or the new guard interval to obtain several segments to be processed.

7. The method according to any one of claims 1 to 4, characterized in that, The step of generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times each bit in each target segment has a carry output of 1, and remapping the bit output sequence of the carry chain, includes: Based on the difference in the number of times the carry output is 1 for the overlapping bits of the adjacent target segments, the number of times the carry output is 1 for the effective bits after the overlapping bits in the next target segment is corrected. Based on the number of times the corrected carry output of each bit in each target segment is 1, a remapping table of the physical bit position and logical bit index of the carry chain is generated, and the bit output sequence of the carry chain is remapped.

8. The method according to claim 7, characterized in that, The correction of the number of carry-outs of valid bits following the overlapping bits in the next target segment being 1, based on the difference in the number of carry-outs of overlapping bits in adjacent target segments, includes: Starting from the first target segment, calculate the difference in the number of times the carry output of the overlapping bits in adjacent target segments is 1; The number of times the carry-out of the effective bits after the overlapping bits in the next target segment is 1 is added to the difference to obtain the corrected number of times the effective bits after the overlapping bits are 1, until all target segments have been processed.

9. The method according to claim 7, characterized in that, The step of generating a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the corrected carry output of each bit in each target segment is 1, and remapping the bit output sequence of the carry chain, includes: Based on the number of times the corrected carry output of each bit in each target segment is 1, the bits are sorted in order from low to high or from high to low to generate a remapping table of physical bit positions and logical bit indices of the carry chain. The bit output sequence of the carry chain is remapped based on the remapping table.

10. A carry chain calibration device, characterized in that, The device includes: The acquisition module is used to acquire the output sequence of each bit in the carry chain; The segmentation module is used to segment each bit output sequence to obtain several segments to be processed. The frequency statistics module is used to filter each target segment from each segment to be processed, and to count the number of times the carry output of each bit in each target segment is 1. The remapping calibration module is used to generate a remapping table of physical bit positions and logical bit indices of the carry chain based on the number of times the carry output of each bit in each target segment is 1, and to remap the bit output sequence of the carry chain.

11. A time measurement unit, characterized in that, Includes a carry chain, performing the steps of the method as described in any one of claims 1 to 9.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.

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