Current sampling self-checking circuit and battery management system

Abstract

The application discloses a current sampling self-checking circuit and a battery management system. The current sampling self-checking circuit comprises a first selection module and a second selection module, the first selection module is connected with a first differential input end of an analog-to-digital converter and a first detection end of a current detection module, the second selection module is connected with a second differential input end of the analog-to-digital converter and a second detection end of the current detection module, when the difference between a first differential voltage and a second differential voltage is not equal to a preset value, it is indicated that at least one of the first selection module, the second selection module, the analog-to-digital converter and the current detection module is faulty, self-checking can be realized by twice testing based on one circuit, and therefore high cost and larger occupied area required by double circuits can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a current sampling self-checking circuit and a battery management system. BACKGROUND

[0002] For the current sampling circuit connected with the differential input type analog to digital converter (ADC), it can be used to detect the charge and discharge current of the battery. If it is a single current sampling circuit, when the reference fails, the ADC fails, the resistance and capacitance in the current sampling circuit fails, the wire breaks, the system cannot be detected, and the fault cannot be diagnosed.

[0003] However, if it is two current sampling circuits, two same current sampling circuits are compared with each other for self-checking diagnosis, two ADCs and two reference chips are needed, and the cost of high-precision ADC is higher. This not only leads to high cost, but also needs to occupy larger area. SUMMARY

[0004] The present application provides a current sampling self-checking circuit and a battery management system to alleviate the technical problems of high cost and large occupied area required for self-checking of the current sampling circuit.

[0005] In a first aspect, the present application provides a current sampling self-checking circuit, which comprises a first selection module and a second selection module, the first selection module is connected with a first differential input end of an analog to digital converter and a first detection end of a current detection module, and the first selection module is configured to generate a first output voltage to the first differential input end according to one of a first test voltage and a second test voltage; the second selection module is connected with a second differential input end of the analog to digital converter and a second detection end of the current detection module, and the second selection module is configured to generate a second output voltage to the second differential input end according to the other of the first test voltage and the second test voltage; wherein when the first selection module generates the first output voltage according to the first test voltage and the second selection module generates the second output voltage according to the second test voltage, the voltage difference between the first differential input end and the second differential input end is a first differential voltage; when the first selection module generates the first output voltage according to the second test voltage and the second selection module generates the second output voltage according to the first test voltage, the voltage difference between the first differential input end and the second differential input end is a second differential voltage; when the difference between the first differential voltage and the second differential voltage is not equal to a preset value, it indicates that at least one of the first selection module, the second selection module, the analog to digital converter and the current detection module has a fault.

[0006] Optionally, the first selection module comprises a first power supply unit, a second power supply unit and a first selection unit, the first power supply unit is configured to generate a first intermediate voltage according to the first test voltage; the second power supply unit is configured to generate a second intermediate voltage according to the second test voltage; the first selection unit is connected with the first power supply unit and the second power supply unit, and the first selection unit is configured to generate the first output voltage according to one of the first intermediate voltage and the second intermediate voltage.

[0007] Optionally, the first power supply unit comprises a first operational amplifier and a first resistor, a first input end of the first operational amplifier is connected with the first test voltage, a second input end of the first operational amplifier is connected with an output end of the first operational amplifier; a first end of the first resistor is connected with the output end of the first operational amplifier, and a second end of the first resistor is connected with the first selection unit.

[0008] Optionally, the second power supply unit comprises a second operational amplifier and a second resistor, a first input end of the second operational amplifier is connected with the second test voltage, a second input end of the second operational amplifier is connected with an output end of the second operational amplifier; a first end of the second resistor is connected with the output end of the second operational amplifier, and a second end of the second resistor is connected with the first selection unit; wherein, a resistance value of the second resistor is equal to a resistance value of the first resistor.

[0009] Optionally, the first selection unit comprises a first multiplexer and a third resistor, a first input end of the first multiplexer is connected with the second end of the first resistor, a second input end of the first multiplexer is connected with the second end of the second resistor; a first end of the third resistor is connected with an output end of the first multiplexer, and a second end of the third resistor is connected with the first differential input end and the first detection end.

[0010] Optionally, the second selection module comprises a third power supply unit, a fourth power supply unit and a second selection unit, the third power supply unit is configured to generate a third intermediate voltage according to the first test voltage; the fourth power supply unit is configured to generate a fourth intermediate voltage according to the second test voltage; the second selection unit is connected with the third power supply unit and the fourth power supply unit, and the second selection unit is configured to generate the second output voltage according to one of the third intermediate voltage and the fourth intermediate voltage.

[0011] Optionally, the third power supply unit comprises a third operational amplifier and a fourth resistor, a first input end of the third operational amplifier is connected with the first test voltage, a second input end of the third operational amplifier is connected with an output end of the third operational amplifier; a first end of the fourth resistor is connected with the output end of the third operational amplifier, and a second end of the fourth resistor is connected with the second selection unit.

[0012] Optionally, the fourth power supply unit comprises a fourth operational amplifier and a fifth resistor, a first input terminal of the fourth operational amplifier is connected to the second test voltage, a second input terminal of the fourth operational amplifier is connected to an output terminal of the fourth operational amplifier; a first terminal of the fifth resistor is connected to the output terminal of the fourth operational amplifier, and a second terminal of the fifth resistor is connected to the second selection unit; wherein a resistance value of the fifth resistor is equal to a resistance value of the fourth resistor.

[0013] Optionally, the second selection unit comprises a second multiplexer and a sixth resistor, a first input terminal of the second multiplexer is connected to the second terminal of the fourth resistor, and a second input terminal of the second multiplexer is connected to the second terminal of the fifth resistor; a first terminal of the sixth resistor is connected to an output terminal of the second multiplexer, and a second terminal of the sixth resistor is connected to the second differential input terminal and the second detection terminal.

[0014] Optionally, the current detection module comprises a seventh resistor, an eighth resistor, a ninth resistor and a first capacitor, a first terminal of the seventh resistor is connected to the first differential input terminal; a first terminal of the eighth resistor is connected to a second terminal of the seventh resistor, and a second terminal of the eighth resistor is connected to a ground terminal; a first terminal of the ninth resistor is connected to the second terminal of the eighth resistor and the ground terminal, and a second terminal of the ninth resistor is connected to the second differential input terminal; a first terminal of the first capacitor is connected to the first differential input terminal, and a second terminal of the first capacitor is connected to the second differential input terminal; wherein a resistance value of the seventh resistor is equal to a resistance value of the ninth resistor.

[0015] In a second aspect, the present application provides a battery management system, comprising the current sampling self-checking circuit.

[0016] Optionally, the battery management system further comprises a current detection module and an analog front end, and the analog front end comprises an analog-to-digital converter.

[0017] The current sampling self-checking circuit and the battery management system provided by the application are connected with the first differential input end of the analog-to-digital converter and the first detection end of the current detection module through the first selection module, and connected with the second differential input end of the analog-to-digital converter and the second detection end of the current detection module through the second selection module. When the first selection module generates the first output voltage according to the first test voltage, and the second selection module generates the second output voltage according to the second test voltage, the voltage difference between the first differential input end and the second differential input end is the first differential voltage. When the first selection module generates the first output voltage according to the second test voltage, and the second selection module generates the second output voltage according to the first test voltage, the voltage difference between the first differential input end and the second differential input end is the second differential voltage. When the difference between the first differential voltage and the second differential voltage is not equal to the preset value, it indicates that at least one of the first selection module, the second selection module, the analog-to-digital converter and the current detection module fails. The self-checking can be realized by twice testing based on one circuit, so that the high cost and larger occupied area required by double circuits can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0018] The technical scheme and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application with reference to the accompanying drawings.

[0019] Figure 1 The principle block diagram of the current sampling self-checking circuit provided by the embodiment of the application is shown.

[0020] Figure 2 The principle block diagram of the first selection module provided by the embodiment of the application is shown.

[0021] Figure 3 The circuit principle diagram of the first selection module provided by the embodiment of the application is shown.

[0022] Figure 4 The principle block diagram of the second selection module provided by the embodiment of the application is shown.

[0023] Figure 5 The circuit principle diagram of the second selection module provided by the embodiment of the application is shown.

[0024] Figure 6 The circuit principle diagram of the current detection module provided by the embodiment of the application is shown.

[0025] Figure 7 The circuit principle diagram of the first self-checking state provided by the embodiment of the application is shown.

[0026] Figure 8 The circuit principle diagram of the second self-checking state provided by the embodiment of the application is shown.

[0027] Figure 9The circuit schematic of the battery management system provided in the embodiments of the present application is shown in the following. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without any creative work under the premise that the embodiments in the present application are within the scope of protection of the present application.

[0029] In addition, the terms "first", "second" are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, so that the features with "first" and "second" can explicitly or implicitly include one or more of the features, and in the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0030] For the current sampling circuit connected with the differential input type analog-to-digital converter, it can be used to detect the charging and discharging current of the battery. If it is a single current sampling circuit, when the reference fails, the ADC fails, the resistance and capacitance in the current sampling circuit fails, and the wire breaks, the system cannot be detected, and the fault cannot be diagnosed.

[0031] However, if it is two current sampling circuits, two identical current sampling circuits are compared with each other for self-diagnosis, two ADCs and two reference chips are required, and the cost of a high-precision ADC is higher. This not only leads to a very high cost, but also requires a larger area.

[0032] If the current sampling fails, it will cause a safety problem, which may cause the battery to overheat and catch fire.

[0033] The present application realizes self-checking by testing a circuit twice, which can not only realize real-time self-checking, but also has no time limit. This scheme has simple implementation method, low cost, small space on the circuit board, and high reliability.

[0034] As Figure 1As shown, the embodiment provides a current sampling self-checking circuit 100, which comprises a first selection module 10 and a second selection module 20, the first selection module 10 is connected with a first differential input end SRP of an analog-to-digital converter 220 and a first detection end of a current detection module 210, and the first selection module 10 is configured to generate a first output voltage to the first differential input end SRP according to one of a first test voltage VT1 and a second test voltage VT2; the second selection module 20 is connected with a second differential input end SRN of the analog-to-digital converter 220 and a second detection end of the current detection module 210, and the second selection module 20 is configured to generate a second output voltage to the second differential input end SRN according to the other of the first test voltage VT1 and the second test voltage VT2; wherein, when the first selection module 10 generates the first output voltage according to the first test voltage VT1, and the second selection module 20 generates the second output voltage according to the second test voltage VT2, a voltage difference between the first differential input end SRP and the second differential input end SRN is a first differential voltage; when the first selection module 10 generates the first output voltage according to the second test voltage VT2, and the second selection module 20 generates the second output voltage according to the first test voltage VT1, a voltage difference between the first differential input end SRP and the second differential input end SRN is a second differential voltage; when a difference between the first differential voltage and the second differential voltage is not equal to a preset value, it indicates that at least one of the first selection module 10, the second selection module 20, the analog-to-digital converter 220 and the current detection module 210 has a fault.

[0035] It can be understood that the current sampling self-checking circuit 100 provided by the embodiment, by connecting the first selection module 10 with the first differential input end SRP of the analog-to-digital converter 220 and the first detection end of the current detection module 210, and connecting the second selection module 20 with the second differential input end SRN of the analog-to-digital converter 220 and the second detection end of the current detection module 210, when the first selection module 10 generates the first output voltage according to the first test voltage VT1, and the second selection module 20 generates the second output voltage according to the second test voltage VT2, a voltage difference between the first differential input end SRP and the second differential input end SRN is a first differential voltage; when the first selection module 10 generates the first output voltage according to the second test voltage VT2, and the second selection module 20 generates the second output voltage according to the first test voltage VT1, a voltage difference between the first differential input end SRP and the second differential input end SRN is a second differential voltage; when a difference between the first differential voltage and the second differential voltage is not equal to a preset value, it indicates that at least one of the first selection module 10, the second selection module 20, the analog-to-digital converter 220 and the current detection module 210 has a fault, which can realize self-checking based on two tests of one circuit, thereby avoiding high cost and larger occupied area required by double circuits.

[0036] It should be noted that the first test voltage VT1 is different from the second test voltage VT2, for example, the first test voltage VT1 is lower or higher than the second test voltage VT2, and the application takes the first test voltage VT1 lower than the second test voltage VT2 as an example for description. The current detection module 210 is configured to detect the charging and discharging current of the battery, that is, IOUT.

[0037] In some embodiments, as shown in Figure 2 The first selection module 10 includes a first power supply unit 11, a second power supply unit 12, and a first selection unit 13. The first power supply unit 11 is configured to generate a first intermediate voltage according to the first test voltage VT1. The second power supply unit 12 is configured to generate a second intermediate voltage according to the second test voltage VT2. The first selection unit 13 is connected with the first power supply unit 11 and the second power supply unit 12, and is configured to generate a first output voltage according to one of the first intermediate voltage and the second intermediate voltage.

[0038] It should be noted that the first selection unit 13 can select one of the first intermediate voltage and the second intermediate voltage to generate the first output voltage.

[0039] In some embodiments, as shown in Figure 3 The first power supply unit 11 includes a first operational amplifier OP1 and a first resistor RT1. The first input end of the first operational amplifier OP1 is connected to the first test voltage VT1. The second input end of the first operational amplifier OP1 is connected with the output end of the first operational amplifier OP1. The first end of the first resistor RT1 is connected with the output end of the first operational amplifier OP1, and the second end of the first resistor RT1 is connected with the first selection unit 13.

[0040] It should be noted that the first input end and the second input end of the first operational amplifier OP1 can be a positive input end (+) and a negative input end (-) respectively. The first operational amplifier OP1 constitutes a voltage follower (unit gain buffer) to eliminate the impedance influence of the voltage dividing circuit and provide low output impedance driving. The first resistor RT1 serves as a current limiting protection resistor (for example, the resistance value is 10Ω~100Ω) to prevent damage to the operational amplifier when the latter stage is short-circuited. The embodiment cooperates the voltage follower and the current limiting resistor to maintain voltage precision while achieving high anti-load fluctuation capability (switching / short-circuit without downtime), ensuring the self-checking precision of the difference between the first differential voltage and the second differential voltage, and improving the accuracy of the self-checking result. It can provide a reliable reference voltage source with nanosecond transient response.

[0041] In other embodiments, the first resistor RT1 can also be omitted. In other embodiments, the first power supply unit 11 can further include a transient voltage suppression (TVS) diode (not shown) connected between the output terminal of the first operational amplifier OP1 and the ground terminal GND for improving the ability of electrostatic discharge (ESD) resistance.

[0042] In some embodiments, as shown in FIG. 2, the second power supply unit 12 includes a second operational amplifier OP2 and a second resistor RT2. The first input terminal of the second operational amplifier OP2 is connected to the second test voltage VT2, and the second input terminal of the second operational amplifier OP2 is connected to the output terminal of the second operational amplifier OP2. The first terminal of the second resistor RT2 is connected to the output terminal of the second operational amplifier OP2, and the second terminal of the second resistor RT2 is connected to the first selection unit 13. The resistance value of the second resistor RT2 is equal to the resistance value of the first resistor RT1. Figure 3

[0043] It should be noted that the first input terminal and the second input terminal of the second operational amplifier OP2 can be a positive input terminal (+) and a negative input terminal (-), respectively. The second operational amplifier OP2 constitutes a voltage follower (unit gain buffer) to eliminate the impedance influence of the voltage dividing circuit and provide low output impedance driving. The second resistor RT2 serves as a current limiting protection resistor (for example, with a resistance value of 10Ω-100Ω) to prevent damage to the operational amplifier when the subsequent stage is short-circuited. The present embodiment cooperatively designs the voltage follower and the current limiting resistor to maintain voltage accuracy while achieving high load fluctuation resistance (switching / short-circuit without downtime), ensuring the self-checking accuracy of the difference between the first differential voltage and the second differential voltage, and improving the accuracy of the self-checking result. The present embodiment can provide a reliable reference voltage source with nanosecond transient response.

[0044] In other embodiments, the second resistor RT2 can also be omitted. In other embodiments, the second power supply unit 12 can further include a transient voltage suppression (TVS) diode (not shown) connected between the output terminal of the second operational amplifier OP2 and the ground terminal GND for improving the ability of electrostatic discharge (ESD) resistance.

[0045] In some embodiments, as shown in FIG. 3, the first selection unit 13 includes a first multiplexer MUX1 and a third resistor R1. The first input terminal (IN1) of the first multiplexer MUX1 is connected to the second terminal of the first resistor RT1, and the second input terminal (IN4) of the first multiplexer MUX1 is connected to the second terminal of the second resistor RT2. The first terminal of the third resistor R1 is connected to the output terminal of the first multiplexer MUX1, and the second terminal of the third resistor R1 is connected to the first differential input terminal SRP and the first detection terminal. Figure 3

[0046] ​​It should be noted that the first multiplexer MUX1 can be a multiplexing chip connected with a power terminal VDD and a ground terminal GND, and a voltage of the power terminal VDD is exemplarily 5V. The first multiplexer MUX1 can further include suspended input terminals IN2 and IN3, so that a plurality of selection switches A0, A1, A2 and A3 can be formed between the input terminals and an output terminal, and the selection switches can be gated by the first logic (Logic1) according to selection signals S0, S1 and S2.

[0047] In other embodiments, the first selection unit 13 can further include a capacitor (not shown) connected in parallel with the third resistor R1, so as to filter out interference of high-frequency noise and improve stability of the voltage.

[0048] In some embodiments, as shown in FIG. 2, the second selection module 20 includes a third power supply unit 21, a fourth power supply unit 22 and a second selection unit 23. Figure 4 The third power supply unit 21 is configured to generate a third intermediate voltage according to the first test voltage VT1; the fourth power supply unit 22 is configured to generate a fourth intermediate voltage according to the second test voltage VT2; and the second selection unit 23 is connected with the third power supply unit 21 and the fourth power supply unit 22, and is configured to generate a second output voltage according to one of the third intermediate voltage and the fourth intermediate voltage.

[0049] It should be noted that the second selection unit 23 can select one of the third intermediate voltage and the fourth intermediate voltage to generate the second output voltage.

[0050] In some embodiments, as shown in FIG. 2, the third power supply unit 21 includes a third operational amplifier OP3 and a fourth resistor RTS1. Figure 5 The first input terminal of the third operational amplifier OP3 is connected with the first test voltage VT1, the second input terminal of the third operational amplifier OP3 is connected with an output terminal of the third operational amplifier OP3; the first terminal of the fourth resistor RTS1 is connected with the output terminal of the third operational amplifier OP3, and the second terminal of the fourth resistor RTS1 is connected with the second selection unit 23.

[0051] It needs to be explained that the first input end and the second input end of the third operational amplifier OP3 can be a positive input end (+) and a negative input end (-) respectively. The third operational amplifier OP3 constitutes a voltage follower (unit gain buffer) to eliminate the influence of the impedance of the voltage dividing circuit and provide low output impedance driving. The fourth resistor RTS1, as a current limiting protection resistor (for example, the resistance value is 10Ω-100Ω), prevents damage to the operational amplifier when the latter stage is short-circuited. Through the cooperative design of the voltage follower and the current limiting resistor in this embodiment, while maintaining voltage accuracy, high anti-load fluctuation capability (switching / short circuit without downtime) is realized, ensuring the self-checking accuracy of the difference between the first differential voltage and the second differential voltage, which is beneficial to improve the accuracy of the self-checking result, and can provide a reliable reference voltage source with nanosecond transient response.

[0052] In other embodiments, the fourth resistor RTS1 can also be omitted. In other embodiments, the third power supply unit 21 can further include a transient voltage suppression (TVS) diode (not shown) connected between the output end of the third operational amplifier OP3 and the ground end GND for improving the electrostatic discharge (ESD) resistance.

[0053] In some embodiments, as shown in Figure 5 The fourth power supply unit 22 includes a fourth operational amplifier OP4 and a fifth resistor RTS2. The first input end of the fourth operational amplifier OP4 is connected to the second test voltage VT2, and the second input end of the fourth operational amplifier OP4 is connected to the output end of the fourth operational amplifier OP4. The first end of the fifth resistor RTS2 is connected to the output end of the fourth operational amplifier OP4, and the second end of the fifth resistor RTS2 is connected to the second selection unit 23. The resistance value of the fifth resistor RTS2 is equal to the resistance value of the fourth resistor RTS1.

[0054] It needs to be explained that the first input end and the second input end of the fourth operational amplifier OP4 can be a positive input end (+) and a negative input end (-) respectively. The fourth operational amplifier OP4 constitutes a voltage follower (unit gain buffer) to eliminate the influence of the impedance of the voltage dividing circuit and provide low output impedance driving. The fifth resistor RTS2, as a current limiting protection resistor (for example, the resistance value is 10Ω-100Ω), prevents damage to the operational amplifier when the latter stage is short-circuited. Through the cooperative design of the voltage follower and the current limiting resistor in this embodiment, while maintaining voltage accuracy, high anti-load fluctuation capability (switching / short circuit without downtime) is realized, ensuring the self-checking accuracy of the difference between the first differential voltage and the second differential voltage, which is beneficial to improve the accuracy of the self-checking result, and can provide a reliable reference voltage source with nanosecond transient response.

[0055] In other embodiments, the fifth resistor RTS2 can also be omitted. In other embodiments, the fourth power supply unit 22 can further include a transient voltage suppression (TVS) diode (not shown) connected between the output of the fourth operational amplifier OP4 and the ground terminal GND for improving the electrostatic discharge (ESD) resistance.

[0056] In some embodiments, as shown in FIG. 2, the second selection unit 23 includes a second multiplexer MUX2 and a sixth resistor R2. The first input of the second multiplexer MUX2 is connected to the second terminal of the fourth resistor RTS1, and the second input of the second multiplexer MUX2 is connected to the second terminal of the fifth resistor RTS2. The first terminal of the sixth resistor R2 is connected to the output of the second multiplexer MUX2, and the second terminal of the sixth resistor R2 is connected to the second differential input SRN and the second detection terminal. Figure 5

[0057] It should be noted that the second multiplexer MUX2 can be a multiplexing chip connected to the power supply terminal VDD and the ground terminal GND. The voltage of the power supply terminal VDD is exemplarily 5V. The second multiplexer MUX2 can further include floating inputs IN2 and IN3, so that a plurality of selection switches A0, A1, A2, and A3 can be formed between the inputs and the output. These selection switches can be gated by the second logic (Logic2) according to the selection signals S0, S1, and S2.

[0058] In other embodiments, the second selection unit 23 can further include a capacitor (not shown) connected in parallel with the sixth resistor R2, so as to filter out high-frequency noise interference and improve the stability of the voltage.

[0059] In some embodiments, as shown in FIG. 2, the current detection module 210 includes a seventh resistor RD1, an eighth resistor RS, a ninth resistor RD2, and a first capacitor CD. The first terminal of the seventh resistor RD1 is connected to the first differential input SRP. The first terminal of the eighth resistor RS is connected to the second terminal of the seventh resistor RD1, and the second terminal of the eighth resistor RS is connected to the ground terminal GND. The first terminal of the ninth resistor RD2 is connected to the second terminal of the eighth resistor RS and the ground terminal GND, and the second terminal of the ninth resistor RD2 is connected to the second differential input SRN. The first terminal of the first capacitor CD is connected to the first differential input SRP, and the second terminal of the first capacitor CD is connected to the second differential input SRN. The resistance of the seventh resistor RD1 is equal to the resistance of the ninth resistor RD2. Figure 6

[0060] ​​It needs to be explained that the first capacitor CD is used to filter out differential noise and provide an electrostatic discharge path. The current flowing through the eighth resistor RS is the charging and discharging current (IOUT). The seventh resistor RD1 and the ninth resistor RD2 are used to establish the scaling factor of the charging and discharging current.

[0061] The non-self-checking state is the case where each selection switch of the first multiplexer MUX1 or the selection switches A0, A3 of the first multiplexer MUX1 are all disconnected, and each switch of the second multiplexer MUX2 or the selection switches A0, A3 of the second multiplexer MUX2 are all disconnected. Alternatively, at least one of the selection switches A1, A2 of the first multiplexer MUX1 can be enabled, and at least one of the selection switches A1, A2 of the second multiplexer MUX2 can be enabled.

[0062] The first multiplexer MUX1 and the second multiplexer MUX2 are analog switches. In the non-self-checking state, the leakage current of the analog switch is in the nA level, the equivalent impedance of the sampling port of the analog-to-digital converter 220 is in the KΩ level, and the resulting offset voltage error is in the uV level; the parasitic capacitance of the analog switch is in the pF level, which does not affect the system bandwidth and common-mode rejection ratio.

[0063] The resistance value of the eighth resistor RS is in the mΩ order of magnitude, and the resistance values of the first resistor RT1, the second resistor RT2, and the analog switch are all in the Ω order of magnitude.

[0064] Figure 7 The first self-checking state of the current sampling self-checking circuit 100 is shown. The selection switch A3 of the first multiplexer MUX1 and the selection switch A0 of the second multiplexer MUX2 are both turned on, providing an excitation voltage for the first differential input SRP and the second differential input SRN. At this time, the calculation formula 1-1 of the voltage VSRP1 of the first differential input SRP is as follows:

[0065] VSRP1=RD÷(RD+R1)×VT2+R1÷(RD+R1)×VSNS(1-1)

[0066] Wherein, R1 represents the resistance value of the third resistor R1, RD represents the resistance value of the seventh resistor RD1 or the ninth resistor RD2, VT2 represents the second test voltage VT2, and VSNS represents the voltage across the eighth resistor RS.

[0067] The calculation formula 1-2 of the voltage VSRN1 of the second differential input SRN is as follows:

[0068] VSRN1=RD÷(RD+R2)×VT1(1-2)

[0069] Wherein, R2 represents the resistance value of the sixth resistor R2, and VT1 represents the first test voltage VT1.

[0070] Let R1 = R2 = R, then the first differential voltage VSRPN1 collected by the analog-to-digital converter 220 is calculated by formula 1-3 as follows:

[0071] VSRPN1 = VSRP1 - VSRN1

[0072] = RD ÷ (RD + R) × (VT2 - VT1) + R1 ÷ (RD + R1) × VSNS (1-3)

[0073] Figure 8 The second self-checking state of the current sampling self-checking circuit 100 is shown, and the selection switch A0 of the first multiplexer MUX1 and the selection switch A3 of the second multiplexer MUX2 are both turned on to provide an excitation voltage for the first differential input terminal SRP and the second differential input terminal SRN. At this time, the voltage of the first differential input terminal SRP, i.e. VSRP2, is calculated by formula 2-1 as follows:

[0074] VSRP2 = RD ÷ (RD + R1) × VT2 + R1 ÷ (RD + R1) × VSNS (2-1)

[0075] The voltage of the second differential input terminal SRN, i.e. VSRN2, is calculated by formula 2-2 as follows:

[0076] VSRN2 = RD ÷ (RD + R2) × VT1 (2-2)

[0077] Let R1 = R2 = R, then the second differential voltage VSRPN2 collected by the analog-to-digital converter 220 is calculated by formula 2-3 as follows:

[0078] VSRPN2 = VSRP2 - VSRN2

[0079] = RD ÷ (RD + R) × (VT1 - VT2) + R1 ÷ (RD + R1) × VSNS (2-3)

[0080] Then the difference between the first differential voltage and the second differential voltage, i.e. VSRPN1 - VSRPN2, is calculated by formula 3-1 as follows:

[0081] VSRPN1 - VSRPN2 = 2RD ÷ (RD + R) × (VT2 - VT1) (3-1)

[0082] According to formula 3-1, VSRPN1 - VSRPN2 is independent of the sampling voltage.

[0083] In this test, the first test voltage VT1 can be 0.1V, the second test voltage VT2 can be 0.3V, and the resistance values ​​of the third resistor R1, the sixth resistor R2, the seventh resistor RD1, and the ninth resistor RD2 are all known. Therefore, VSRPN1-VSRPN2 are also known. VSRPN1 can be approximately 0.181V, and VSRPN2 can be approximately -0.181V.

[0084] If the difference between the two acquired differential voltages, i.e., VSRPN1-VSRPN2 or VSRPN2-VSRPN1, is not equal to the preset value (known quantity), it indicates a problem with the sampling circuit. This could be due to issues with Vt1, Vt2, or RD, or it could be a problem with the analog-to-digital converter 220 (sampling chip). Therefore, this provides the self-test result of the sampling chip.

[0085] In summary, the current sampling self-test circuit 100 provided in this application can perform self-tests in real time without requiring the system to stop working. That is, the value of VSNS does not affect the self-test result. Other circuits, however, require VSNS to be 0 to perform a self-test.

[0086] The self-test will affect the sampling results, but the operating voltage will not affect the self-test. Therefore, the self-test can be performed without shutting down the system. During the self-test, the sampling results are not used as actual data.

[0087] In some embodiments, such as Figure 9 As shown, this embodiment provides a battery management system 200, which includes the current sampling self-test circuit 100 described above.

[0088] It can be understood that, since the battery management system 200 provided by the embodiment includes the current sampling self-checking circuit 100 described above, the first selection module 10 is also connected with the first differential input end SRP of the analog-to-digital converter 220 and the first detection end of the current detection module 210, and the second selection module 20 is connected with the second differential input end SRN of the analog-to-digital converter 220 and the second detection end of the current detection module 210. When the first selection module 10 generates the first output voltage according to the first test voltage VT1, and the second selection module 20 generates the second output voltage according to the second test voltage VT2, the voltage difference between the first differential input end SRP and the second differential input end SRN is the first differential voltage. When the first selection module 10 generates the first output voltage according to the second test voltage VT2, and the second selection module 20 generates the second output voltage according to the first test voltage VT1, the voltage difference between the first differential input end SRP and the second differential input end SRN is the second differential voltage. When the difference between the first differential voltage and the second differential voltage is not equal to the preset value, it indicates that at least one of the first selection module 10, the second selection module 20, the analog-to-digital converter 220 and the current detection module 210 fails. The self-checking can be realized by twice testing based on one circuit, so that the high cost and larger occupied area required by double circuits can be avoided.

[0089] In some embodiments, as shown in FIG. 2, the battery management system 200 further includes a current detection module 210 and an analog front end 230, and the analog front end 230 includes an analog-to-digital converter 220. Figure 9

[0090] It should be noted that the analog-to-digital converter 220 in the present application can be a discrete ADC chip, or an ADC chip in the battery management system 200. It can be, but is not limited to, a Σ-△ type ADC, or other differential input type ADC.

[0091] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0092] The current sampling self-checking circuit 100 and the battery management system 200 provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.​

Claims

1. A current sampling self-test circuit, comprising: The current sampling self-checking circuit comprises: A first selection module is connected with a first differential input end of an analog-to-digital converter and a first detection end of a current detection module, and is configured to generate a first output voltage to the first differential input end according to one of a first test voltage and a second test voltage; A second selection module is connected with a second differential input end of the analog-to-digital converter and a second detection end of the current detection module, and is configured to generate a second output voltage to the second differential input end according to the other of the first test voltage and the second test voltage; When the first selection module generates the first output voltage according to the first test voltage and the second selection module generates the second output voltage according to the second test voltage, a voltage difference between the first differential input end and the second differential input end is a first differential voltage; when the first selection module generates the first output voltage according to the second test voltage and the second selection module generates the second output voltage according to the first test voltage, a voltage difference between the first differential input end and the second differential input end is a second differential voltage; when a difference between the first differential voltage and the second differential voltage is not equal to a preset value, it is indicated that at least one of the first selection module, the second selection module, the analog-to-digital converter and the current detection module is faulty.

2. The current sampling self-test circuit of claim 1, wherein, The first selection module comprises: A first power supply unit is configured to generate a first intermediate voltage according to the first test voltage; A second power supply unit is configured to generate a second intermediate voltage according to the second test voltage; A first selection unit is connected with the first power supply unit and the second power supply unit, and is configured to generate the first output voltage according to one of the first intermediate voltage and the second intermediate voltage.

3. The current sampling self-test circuit of claim 2, wherein, The first power supply unit comprises: A first operational amplifier, a first input end of the first operational amplifier is connected with the first test voltage, and a second input end of the first operational amplifier is connected with an output end of the first operational amplifier; A first resistor, a first end of the first resistor is connected with the output end of the first operational amplifier, and a second end of the first resistor is connected with the first selection unit.

4. The current sampling self-test circuit of claim 3, wherein, The second power supply unit comprises: A second operational amplifier, a first input end of the second operational amplifier is connected with the second test voltage, and a second input end of the second operational amplifier is connected with an output end of the second operational amplifier; A second resistor, a first end of the second resistor is connected with the output end of the second operational amplifier, and a second end of the second resistor is connected with the first selection unit; The resistance value of the second resistor is equal to the resistance value of the first resistor.

5. The current sampling self-test circuit of claim 4, wherein, The first selection unit comprises: A first multiplexer, a first input end of the first multiplexer is connected with the second end of the first resistor, and a second input end of the first multiplexer is connected with the second end of the second resistor; A third resistor, a first end of the third resistor being connected with an output end of the first multiplexer, a second end of the third resistor being connected with the first differential input end and the first detection end.

6. The current sampling self-test circuit of claim 5, wherein, The second selection module comprises: A third power supply unit configured to generate a third intermediate voltage according to the first test voltage; A fourth power supply unit configured to generate a fourth intermediate voltage according to the second test voltage; A second selection unit connected with the third power supply unit and the fourth power supply unit, and configured to generate the second output voltage according to one of the third intermediate voltage and the fourth intermediate voltage.

7. The current sampling self-test circuit of claim 6, wherein, The third power supply unit comprises: A third operational amplifier, a first input end of the third operational amplifier being connected with the first test voltage, a second input end of the third operational amplifier being connected with an output end of the third operational amplifier; A fourth resistor, a first end of the fourth resistor being connected with the output end of the third operational amplifier, a second end of the fourth resistor being connected with the second selection unit.

8. The current sampling self-test circuit of claim 7, wherein, The fourth power supply unit comprises: A fourth operational amplifier, a first input end of the fourth operational amplifier being connected with the second test voltage, a second input end of the fourth operational amplifier being connected with an output end of the fourth operational amplifier; A fifth resistor, a first end of the fifth resistor being connected with the output end of the fourth operational amplifier, a second end of the fifth resistor being connected with the second selection unit; Wherein, a resistance value of the fifth resistor is equal to a resistance value of the fourth resistor.

9. The current sampling self-test circuit of claim 8, wherein, The second selection unit comprises: A second multiplexer, a first input end of the second multiplexer being connected with the second end of the fourth resistor, a second input end of the second multiplexer being connected with the second end of the fifth resistor; A sixth resistor, a first end of the sixth resistor being connected with an output end of the second multiplexer, a second end of the sixth resistor being connected with the second differential input end and the second detection end.

10. The current sampling self-test circuit of any of claims 1-9, wherein, The current detection module comprises: A seventh resistor, a first end of the seventh resistor being connected with the first differential input end; An eighth resistor, a first end of the eighth resistor being connected with a second end of the seventh resistor, a second end of the eighth resistor being connected with a ground end; A ninth resistor, a first end of the ninth resistor being connected with the second end of the eighth resistor and the ground end, a second end of the ninth resistor being connected with the second differential input end; A first capacitor, a first end of the first capacitor being connected with the first differential input end, a second end of the first capacitor being connected with the second differential input end; Wherein, a resistance value of the seventh resistor is equal to a resistance value of the ninth resistor.

11. A battery management system, characterized by, The battery management system comprises the current sampling self-checking circuit according to any one of claims 1-10.

12. The battery management system of claim 11, wherein, The battery management system further comprises the current detection module and an analog front end, and the analog front end comprises the analog-to-digital converter.

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