Satellite-borne SAR real-time imaging method based on FPGA high-speed transposition

Abstract

The invention discloses a satellite-borne SAR (Synthetic Aperture Radar) real-time imaging method based on FPGA (Field Programmable Gate Array) high-speed transposition, which comprises the following steps of: in FPGA data writing operation, carrying out row splitting on SAR echo data in a matrix form to obtain a plurality of small matrix blocks with consistent row and column sizes, and forming a recombination matrix; writing the small matrix blocks into a memory in sequence; performing skip reading operation on the recombination matrix, and repeating the operation until the reading operation of the SAR echo data is completed; imaging is carried out based on the CS imaging algorithm, real-time output is carried out, according to the method, the transposition operation read-write efficiency of a memory is high, and the imaging real-time performance is guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of synthetic aperture radar imaging and relates to a spaceborne SAR real-time imaging method based on FPGA high-speed transposition. Background Technology

[0002] Synthetic Aperture Radar (SAR), with its all-weather, all-time imaging capabilities and sensitivity to the dielectric properties of the Earth's surface, has become the core of Earth observation systems. However, this has led to a surge in data volume and increasingly stringent real-time requirements, making real-time imaging technology crucial for addressing these challenges. SAR imaging involves large-scale matrix operations, and the serial architecture of traditional digital signal processors struggles to meet real-time demands. Compared to other hardware platforms, FPGAs, with their distributed computing units and reconfigurable logic, are highly compatible with the large data throughput and demanding real-time computing requirements of SAR imaging systems. Furthermore, the CS algorithm offers high imaging accuracy, making it particularly suitable for high-resolution scenarios.

[0003] During imaging, the main limitations on imaging timeliness are data transmission speed and memory read / write efficiency. Due to the massive amount of echo data, in actual hardware processing, the echo data is temporarily stored in DDR3 external memory in the form of a two-dimensional matrix, and data transposition is performed in DDR3. The CS imaging process includes three parts: FFT, complex multiplication, and data matrix transposition. The transposition of high-order matrices requires frequent row skipping operations to reactivate rows, making the transposition processing module the most time-consuming. This module must wait for a frame of data to be completely written to DDR3 before it can begin the transposition operation. The memory transposition read / write consumes a significant amount of processing time, severely impacting the real-time response of the system. Existing research mainly focuses on optimization at the imaging algorithm level, lacking systematic research on the collaborative optimization mechanism between the underlying storage architecture and matrix transposition. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention aims to provide a spaceborne SAR real-time imaging method based on FPGA high-speed transposition, so as to solve the problem that the transposition operation of memory in the existing imaging method leads to low read and write efficiency, thereby affecting the real-time performance of the system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A spaceborne SAR real-time imaging method based on FPGA high-speed transposition includes the following steps:

[0007] In the FPGA data writing operation, the matrix-form SAR echo data is decomposed into rows to obtain several small matrix blocks with the same row and column size, which are then reassembled into a matrix.

[0008] The small matrix blocks are written sequentially into memory;

[0009] The recombined matrix is ​​subjected to a skip read operation, which is repeated until the SAR echo data read operation is completed;

[0010] Imaging is performed and output in real time based on the CS imaging algorithm.

[0011] In one embodiment, the method for row-wise decomposition of the matrix-form SAR echo data and the reconstruction of the matrix is ​​as follows:

[0012] Reorganize matrix A, which contains 1024 data points per row, totaling 128 rows and a bit depth of 32 bits, into matrix B, which contains 16 smaller matrix blocks per row and totals 8 rows.

[0013] Each small matrix block is a 32×32 matrix composed of 1024 data points per row. Within each small matrix block, the 1024 data points per row are filled in the positions in the order of rows and columns.

[0014] In one embodiment, the small matrix blocks are sequentially written into memory, as follows:

[0015] For each small matrix block, the data in it is written to memory in row order. After each row of data in the small matrix block is written, a newline operation is performed. When a small matrix block is full, that is, one row of the original data matrix is ​​written to memory.

[0016] Perform the above operations sequentially on all small matrix blocks until all rows of the original data matrix have been written into memory, at which point the write operation is complete.

[0017] In one embodiment, the skip-read operation on the reconstructed matrix is ​​repeated until the SAR echo data reading operation is completed, and the method is as follows:

[0018] During reading, small matrix blocks are read sequentially by column. For the Nth column transpose read, the Nth element of each small matrix block is read sequentially from left to right and from top to bottom in the reconstructed matrix. After each column transpose read, the process moves to the next column transpose read. The Nth element of a small matrix block refers to the Nth data point counted sequentially from left to right and from top to bottom within a small matrix block.

[0019] For example, for the first column transpose read, the order is as follows:

[0020] First, read the data in the first row and first column of the first small matrix block in the first row and first column of the reconstructed matrix. After that, skip to the first row and first column of the first small matrix block in the first row and second column of the reconstructed matrix. After 16 skips within the row of the reconstructed matrix, close the current row of the reconstructed matrix and skip to the first row and first column of the second small matrix block in the second row and first column of the reconstructed matrix. After that, skip to the first row and first column of the second small matrix block in the second row and second column of the reconstructed matrix. After 16 skips within the row of the reconstructed matrix, close the current row of the reconstructed matrix and skip to the first row and first column of the third small matrix block in the reconstructed matrix. Repeat the operation until the first row and first column of the last small matrix block in the last row and last column of the reconstructed matrix is ​​read.

[0021] After the first column transpose read, the second column transpose read is performed, in the following order:

[0022] First, read the data in the first row and first column of the first small matrix block within the reconstructed matrix. After that, skip to the first row and second column of the first small matrix block within the same row. After 16 skips within the reconstructed matrix row, close the current row of the reconstructed matrix and skip to the first row and second column of the first small matrix block within the second row of the reconstructed matrix. After that, skip to the first row and second column of the first small matrix block within the second row of the reconstructed matrix. After 16 skips within the reconstructed matrix row, close the current row of the reconstructed matrix and skip to the first row and second column of the first small matrix block within the third row of the reconstructed matrix. Repeat this operation until the first row and second column of the last small matrix block within the last row of the reconstructed matrix is ​​read.

[0023] According to the above rules, execute them sequentially to complete the final column transpose read.

[0024] In one embodiment, the imaging based on the CS imaging algorithm is performed by using the complex multiplication module, Fourier operation module, and memory module in the FPGA module structure based on the CS imaging algorithm to perform SAR imaging processing, wherein the transformation process between the range and azimuth directions adopts a high-speed transposition method based on FPGA.

[0025] In one embodiment, the imaging based on the CS imaging algorithm is implemented as follows:

[0026] First, the echo data is subjected to azimuth-to-Fourier transform to the range-Doppler domain and then processed by Chirp Scaling.

[0027] Then, a range-direction Fourier transform is performed on the echo data to transform the azimuth data to the two-dimensional frequency domain, and range compression processing is performed on it.

[0028] Next, the echo data is subjected to range-to-Fourier inverse transform to the range-Doppler domain, and then subjected to azimuth compression and residual phase compensation processing.

[0029] Finally, the final imaging result can be obtained by performing an inverse Fourier transform of the data to the orientation.

[0030] The beneficial effects of this invention are as follows: Compared with conventional matrix transposition methods, the block matrix transposition method can theoretically improve the average efficiency of reading and writing to 85.19%, effectively balance the efficiency of reading and writing transmission, improve the DDR3 read and write bandwidth, and finally ensure the real-time imaging of spaceborne SAR based on FPGA high-speed transposition. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart of an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the large matrix decomposition according to an embodiment of the present invention.

[0034] Figure 3 This is the block matrix transpose DDR3 write order according to an embodiment of the present invention.

[0035] Figure 4 This is the block matrix transpose DDR3 read order in an embodiment of the present invention.

[0036] Figure 5 This is an overall block diagram of the high-speed transpose module according to an embodiment of the present invention.

[0037] Figure 6 This is a diagram illustrating the conventional matrix transpose DDR3 read / write sequence.

[0038] Figure 7 This is a MATLAB range profile under the same simulation parameters.

[0039] Figure 8 This is a MATLAB azimuth profile under the same simulation parameters.

[0040] Figure 9 This is a distance profile of the FPGA under the same simulation parameters in this invention example.

[0041] Figure 10 This is a MATLAB range profile diagram under the same simulation parameters in the example of this invention.

[0042] Figure 11This is a MATLAB image of a port scene under the same dataset and parameters.

[0043] Figure 12 These are MATLAB images of urban scenes under the same dataset and parameters.

[0044] Figure 13 This is an FPGA port scene imaging image of an example of the present invention under the same dataset and parameters.

[0045] Figure 14 This is an example of an FPGA-based urban scene imaging image based on the same dataset and parameters.

[0046] Figure 15 This is a schematic diagram of the time overhead of each process in the imaging system of this invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] refer to Figure 1 As shown in the figure, a spaceborne SAR imaging method based on FPGA high-speed transposition according to an embodiment of the present invention mainly includes the following steps:

[0049] The satellite receives SAR echo data, buffers the echo data, and then, during the FPGA data writing operation, the matrix-form SAR echo data is decomposed into rows to obtain several small matrix blocks of the same row and column size, which form a recombined matrix. Each small matrix block is written into memory in sequence.

[0050] In the FPGA data reading operation, the elements in each small matrix block of the reconstructed matrix are skipped and read repeatedly until the SAR echo data reading operation is completed.

[0051] Finally, imaging is performed based on the CS imaging algorithm and output in real time.

[0052] For ease of explanation, consider a data matrix A of size 128×1024×32 bits, with 1024 data points per row, totaling 128 rows and a bit depth of 32 bits. Each row of matrix A is decomposed along its row dimension, transforming the original 1024 data points into 32 smaller matrix blocks (32 rows, 32 columns), resulting in 16 smaller matrix blocks per row and a total of 8 rows. This decomposition and recombination process is then completed, and the resulting recombined matrix is ​​named matrix B.

[0053] Specifically, such as Figure 2As shown, the first row of matrix A contains data a. 1,1 ~a 1,1024 The data in line 128 is a 128,1 ~a 128,1024 The reorganized matrix B contains 16×8 small matrix blocks. For ease of description, these small matrix blocks are named sequentially from left to right and top to bottom: the small matrix block in the first row and first column is the first small matrix block, the small matrix block in the first row and second column is the second small matrix block, and so on, with the small matrix block in the first row and 16th column being the 16th small matrix block, the small matrix block in the second row and first column being the 17th small matrix block, and so on, with the small matrix block in the 8th row and 16th column being the last small matrix block. In the first small matrix block, the first row contains data 'a'. 1,1 ~a 1,32 The second row of data is a 1,33 ~a 1,64 ... and so on, the data in line 32 is a 1,993 ~a 1,1024 .

[0054] refer to Figure 3 The present invention performs write operations on each small matrix block to the DDR3 memory, and the specific steps are as follows:

[0055] The rows of matrix A are written to DDR3 in the form of small matrices as described above. A newline operation is required every 32 data entries. Once a small matrix is ​​filled, a row representing data matrix A is written to DDR3. The above operation is performed on all small matrix blocks in sequence until the 128th row of data matrix A is written, at which point the write operation is complete.

[0056] refer to Figure 4 When reading echo data from DDR3 to RAM, the small matrix blocks are read sequentially by column. Specifically, for the Nth column transpose read, the Nth row element of each small matrix block is read sequentially from left to right and from top to bottom in the reconstructed matrix B. After each column transpose read, the process moves to the next column transpose read.

[0057] Specifically, taking the first column transpose read as an example, firstly, the first data in the first row of the first small matrix block (i.e., a in the original echo matrix A) is read. 1,1 After reading, skip to the first element of the first row of the second small matrix block (i.e., a of the original echo matrix A). 2,1In this way, after 16 skip reads within a row, the current row (i.e., the first row) of the reconstructed matrix B is closed, and then the data of the first row and first column of the small matrix block in the next row (i.e., the second row) of the reconstructed matrix B is skipped. At this time, the number of rows to be skipped is the number of columns of the small matrix block, which is 32. The above skip read operation is repeated until the first element of the first row of all the small matrix blocks in the last row of the reconstructed matrix B is read out, which completes the transpose reading operation of the first column element of the data matrix A.

[0058] The remaining imaging processing steps are performed using the complex multiplication module, Fourier operation module, transpose module, and memory module in the FPGA module structure based on the CS imaging algorithm. The multiple range-to-azimuth transformations still employ a high-speed FPGA-based transpose method, as detailed below:

[0059] First, the echo data is subjected to azimuth-to-Fourier transform to the range-Doppler domain and then processed by Chirp Scaling.

[0060] Then, a range-direction Fourier transform is performed on the echo data to transform the azimuth data to the two-dimensional frequency domain, and range compression processing is performed on it.

[0061] Next, the echo data is subjected to range-to-Fourier inverse transform to the range-Doppler domain, and then subjected to azimuth compression and residual phase compensation processing.

[0062] Finally, the final imaging result can be obtained by performing an inverse Fourier transform of the data to the orientation.

[0063] The high-speed transpose module structure of the present invention is as follows: Figure 5 As shown, it mainly includes a FIFO module, a burst control module, a ping-pong read / write module, a DDR3 block address control module, and a single-channel data BRAM rearrangement module. The FIFO module is primarily used for cross-clock domain data processing and bit-width conversion. The burst control module generates DDR3 read / write commands and controls burst transmission timing. The ping-pong read / write module avoids read / write conflicts and enables pipelined operation. The DDR3 block address control module and the single-channel data BRAM rearrangement module are respectively used to generate optimized address sequences according to the block strategy and to finally transpose the block data read from DDR3.

[0064] The overall data flow sequence of the transpose module is as follows: Echo data is buffered in WR_FIFO for cross-clock domain processing and bit width conversion. Echo data is written to DDR3 according to the block matrix transpose method. Echo data is read from DDR3 into RD_FIFO according to the block matrix transpose method. The bit width conversion of the echo data in RD_FIFO is completed, and the data is read into RAM. The echo data in RAM undergoes data rearrangement, and the output is the transposed echo data.

[0065] Figure 6 The diagram illustrates existing conventional data matrix read / write methods. The red curve indicates the order of data writing, and the blue curve indicates the order of data reading. These methods involve writing data row-wise and then reading it from the DDR3 memory column-wise. Clearly, compared to this invention, these methods involve frequent row-crossing operations during data reading, increasing clock overhead and significantly reducing read efficiency.

[0066] A computational example illustrates the performance of real-time spaceborne SAR imaging based on FPGA high-speed transposition according to this invention. Simulation parameters are: center slant range of the imaging scene 20000m, effective speed of the radar platform 150m / s, radar carrier frequency 5.3GHz, beam angle 0°, transmit signal modulation frequency 200GHz, range sampling rate 60MHz, and transmit pulse duration 2.5μs. The simulation platform uses Xilinx's high-end FPGA chip XC7VX690TFFG761-3 as the core processing unit, which can accommodate four external DDR memory chips. MATLAB simulation results can be directly exported and plotted. Real-time imaging results require exporting the imaging data from the FPGA first, followed by analysis and processing using MATLAB. Target point profiles are plotted using dB as the amplitude unit. MATLAB range and azimuth profiles are shown below. Figure 7 and Figure 8 As shown, the FPGA range and azimuth profiles are respectively as follows: Figure 9 and Figure 10 As shown, the imaging quality of the two is basically the same. Due to the influence of factors such as FPGA truncation error and FFT rotation factor accuracy, there are some differences in the calculated results of peak sidelobe ratio and integral sidelobe ratio, but the differences are small, indicating that the FPGA real-time imaging results can meet the accuracy requirements of the algorithm. To verify the effectiveness of the system design, a radar imaging experiment was carried out based on satellite data. The experiment used radar echo data samples with a scale of 2048×2048 points, and the entire process was completed on a 300MHz main frequency FPGA platform. Figure 11 , Figure 12 The imaging results simulated using MATLAB in different scenarios are shown, and Figure 13 , Figure 14 These are the imaging results processed by FPGA under the same dataset and parameters. It can be observed that FPGA uses a calculation-preserving method to fill in data points where interpolation is not possible at the edges, while MATLAB uses zero-padding. Therefore, noise appears in this area in the FPGA imaging, while it is presented as black blocks in MATLAB. Furthermore, there are slight differences in the distribution of some noise points between the two, but the main target within the imaging area is basically the same, with only minor differences. Figure 15This diagram illustrates the time overhead of each step in the imaging system, including the time for echo data reception and the time for a single imaging session. The three transpositions involved in a single CS imaging session account for the majority of the system's clock overhead, with the remaining clock overhead used for complex multiplication and FFT operations. For 2048×2048×4B point data (0.16GB), a single DDR3 read / write operation takes 13.68ms, and the DDR3 SDRA takes a total of 41.04ms to complete the three data read / write operations. A single FFT and complex multiplication operation takes 0.3675ms, and completing four FFT and complex multiplication operations takes a total of 1.47ms. Therefore, processing a 2048×2048 point image takes a total of 2.72 seconds. At a pulse repetition frequency of 8000Hz, 16384×16384 points of raw data can be acquired every 2.048 seconds. Assuming a single-track operation time of 90 minutes for the spaceborne SAR platform, with continuous acquisition sessions lasting 30 minutes, and each data point having a bit width of 32 bits, approximately 878.906 GB of data can be generated. The processing time of the imaging system designed in this invention is approximately 2388.72 seconds (approximately 39.81 minutes). Considering that 25% data overlap needs to be reserved for subsequent image stitching and other operations during continuous acquisition and processing, the total processing time is approximately 49.765 minutes, which is lower than the time constraint for satellite single-track imaging. Therefore, the imaging system designed in this invention can meet the real-time requirements of spaceborne systems.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A spaceborne SAR real-time imaging method based on FPGA high-speed transposition, characterized in that, Includes the following steps: In the FPGA data writing operation, the matrix-form SAR echo data is decomposed into rows to obtain several small matrix blocks with the same row and column size, which are then reassembled into a matrix. The small matrix blocks are written sequentially into memory; The recombined matrix is ​​subjected to a skip read operation, which is repeated until the SAR echo data read operation is completed; Imaging is performed and output in real time based on the CS imaging algorithm.

2. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 1, characterized in that, The method for row-wise decomposition of matrix-form SAR echo data and reconstruction of the matrix is ​​as follows: Reorganize matrix A, which contains 1024 data points per row, totaling 128 rows and a bit depth of 32 bits, into matrix B, which contains 16 smaller matrix blocks per row and totals 8 rows. Each small matrix block is a 32×32 matrix composed of 1024 data points per row. Within each small matrix block, the 1024 data points per row are filled in the positions in the order of rows and columns.

3. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 1, characterized in that, The small matrix blocks are written sequentially into memory, as follows: For each small matrix block, the data in it is written to memory in row order. After each row of data in the small matrix block is written, a newline operation is performed. When a small matrix block is full, that is, one row of the original data matrix is ​​written to memory. Perform the above operations sequentially on all small matrix blocks until all rows of the original data matrix have been written into memory, at which point the write operation is complete.

4. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 1, characterized in that, The method for performing skip-read operations on the reconstructed matrix, repeating until the SAR echo data reading operation is completed, is as follows: During reading, small matrix blocks are read sequentially by column. For the Nth column transpose read, the Nth element of each small matrix block is read sequentially from left to right and from top to bottom in the reconstructed matrix. After each column transpose read, the process moves to the next column transpose read. The Nth element of a small matrix block refers to the Nth data point counted sequentially from left to right and from top to bottom within a small matrix block.

5. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 4, characterized in that, For the first column transpose read, the order is as follows: First, read the data in the first row and first column of the first small matrix block in the first row and first column of the reconstructed matrix. After that, skip to the first row and first column of the first small matrix block in the first row and second column of the reconstructed matrix. After 16 skips within the row of the reconstructed matrix, close the current row of the reconstructed matrix and skip to the first row and first column of the second small matrix block in the second row and first column of the reconstructed matrix. After that, skip to the first row and first column of the second small matrix block in the second row and second column of the reconstructed matrix. After 16 skips within the row of the reconstructed matrix, close the current row of the reconstructed matrix and skip to the first row and first column of the third small matrix block in the reconstructed matrix. Repeat the operation until the first row and first column of the last small matrix block in the last row and last column of the reconstructed matrix is ​​read.

6. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 5, characterized in that, After the first column transpose read, the second column transpose read is performed, in the following order: First, read the data in the first row and first column of the first small matrix block within the reconstructed matrix. After that, skip to the first row and second column of the first small matrix block within the same row. After 16 skips within the reconstructed matrix row, close the current row of the reconstructed matrix and skip to the first row and second column of the first small matrix block within the second row of the reconstructed matrix. After that, skip to the first row and second column of the first small matrix block within the second row of the reconstructed matrix. After 16 skips within the reconstructed matrix row, close the current row of the reconstructed matrix and skip to the first row and second column of the first small matrix block within the third row of the reconstructed matrix. Repeat this operation until the first row and second column of the last small matrix block within the last row of the reconstructed matrix is ​​read.

7. The spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 1, characterized in that, The imaging based on the CS imaging algorithm utilizes the complex multiplication module, Fourier operation module, and memory module in the FPGA module structure based on the CS imaging algorithm to perform SAR imaging processing. The transformation process between the range and azimuth directions adopts a high-speed transposition method based on FPGA.

8. A spaceborne SAR real-time imaging method based on FPGA high-speed transposition according to claim 1 or 7, characterized in that, The imaging based on the CS imaging algorithm is implemented as follows: First, the echo data is subjected to azimuth-to-Fourier transform to the range-Doppler domain and then processed by Chirp Scaling. Then, a range-direction Fourier transform is performed on the echo data to transform the azimuth data to the two-dimensional frequency domain, and range compression processing is performed on it. Next, the echo data is subjected to range-to-Fourier inverse transform to the range-Doppler domain, and then subjected to azimuth compression and residual phase compensation processing. Finally, the final imaging result can be obtained by performing an inverse Fourier transform of the data to the orientation.

Images