Register data processing method and device for fault processor core, equipment and medium

Abstract

The invention provides a register data processing method and device for a fault processor core, equipment and a medium, and relates to the technical field of processors, the method comprises the following steps: respectively obtaining the running state of each processor core in a plurality of processor cores; the operation state comprises a fault state or a normal operation state; obtaining first data in a first register of the fault processor core in response to the fact that the fault processor core of which the running state is the fault state exists in the plurality of processor cores; storing the first data into a first memory area corresponding to the fault processor core; instructing the target processor core to read the first data from the first memory area and output the first data; the running state of the target processor core is a normal running state. According to the method, the first data in the first register of the fault processor core can be timely and accurately obtained.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a method, apparatus, device and medium for processing register data of a faulty processor core. Background Technology

[0002] In multi-core processors, due to factors such as microarchitectural defects, bus arbitration anomalies, and cache coherence protocol deadlocks, a processor core may experience a prolonged period of stagnation. To pinpoint the cause of the processor core's stagnation, it is necessary to obtain the register data at the time of the stagnation.

[0003] In related technologies, data in the processor core registers can be obtained through methods such as system-level watchdog reset and triggering non-maskable interrupts (NMI).

[0004] However, the methods described above can only be successfully executed if the processor core has interrupt response or bus acknowledgement capabilities. If the processor core experiences a hard deadlock or a complete instruction flow halt, the methods described above cannot successfully retrieve data from the processor core's registers. In other words, the methods described above have the problem of difficulty in retrieving data from the registers of a faulty processor core. Summary of the Invention

[0005] This application provides a method, apparatus, device, and medium for processing register data of a faulty processor core, in order to solve the problem in the prior art that it is difficult to obtain data in the registers of a faulty processor core.

[0006] In a first aspect, embodiments of this application provide a register data processing method for a faulty processor core, comprising: acquiring the operating state of each of a plurality of processor cores; the operating state including a faulty state or a normal operating state; in response to identifying that a faulty processor core among the plurality of processor cores is in a faulty state, acquiring first data in a first register of the faulty processor core; storing the first data in a first memory segment corresponding to the faulty processor core; instructing a target processor core to read the first data from the first memory segment and output it; the operating state of the target processor core is a normal operating state.

[0007] Optionally, obtaining the running state of each of the multiple processor cores includes: obtaining the program counter value corresponding to each of the multiple processor cores; and for each processor core, obtaining the running state of the processor core based on the program counter value of the processor core.

[0008] Optionally, obtaining the program counter value corresponding to each of the plurality of processor cores includes: for each processor core, obtaining a plurality of program counter values ​​of the processor core in a plurality of consecutive time periods; wherein the program counter value and the time period correspond one-to-one.

[0009] Optionally, obtaining the operating state of each processor core based on its program counter value includes: for each processor core, if the program counter values ​​of the processor cores are equal to each other within a consecutive preset number of time periods, then the operating state of the processor core is determined to be a fault state; for each processor core, if at least one program counter value of the processor core is not equal to other program counter values ​​within a consecutive preset number of time periods, then the operating state of the processor core is determined to be a normal operating state.

[0010] Optionally, the method further includes: obtaining a normal processor core whose running state is normal from the plurality of processor cores; if there are multiple normal processor cores, obtaining the task priority of the task being executed by each normal processor core; and determining the normal processor core whose task priority is lower than other task priorities as the target processor core.

[0011] Optionally, the first register includes at least one of the following: a general-purpose register, a floating-point register, a vector register, and a control status register.

[0012] Optionally, instructing the target processor core to read and output the first data from the first memory segment includes: sending a preset interrupt number to the target processor core to instruct the target processor core to read and output the first data from the first memory segment based on the interrupt handler corresponding to the preset interrupt number.

[0013] Secondly, embodiments of this application provide a register data processing device for a faulty processor core, comprising: a first acquisition module, configured to acquire the operating state of each of a plurality of processor cores; the operating state includes: a faulty state or a normal operating state; a second acquisition module, configured to acquire first data in a first register of the faulty processor core in response to identifying a faulty processor core among the plurality of processor cores whose operating state is faulty; a data writing module, configured to store the first data into a first memory segment corresponding to the faulty processor core; and a control module, configured to instruct a target processor core to read the first data from the first memory segment and output it; the operating state of the target processor core is a normal operating state.

[0014] Thirdly, embodiments of this application also provide an electronic device, including a processor; A memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0016] In this embodiment, the operating state of each of the multiple processor cores is acquired; the operating state includes either a fault state or a normal operating state. In response to the identification of a faulty processor core among the multiple processor cores, the first data in the first register of the faulty processor core is acquired. This allows for timely acquisition of the first data in the first register of the faulty processor core, preventing system activity or reset from altering the first data in the first register and thus ensuring access to the first data in the first register at the time of the fault. After acquiring the first data in the first register, the first data is stored in the first memory segment corresponding to the faulty processor core, and the target processor core is instructed to read the first data from the first memory segment and output it. The registers of the processor core are private to the processor core; the target processor core cannot directly access the first register that does not belong to the target processor core. However, by storing the first data in the first memory segment, the target processor core can retrieve the first data from the first memory segment. Therefore, the process of obtaining the first data in the first register of the faulty processor core is independent of the faulty processor core. Even if the faulty processor core is unable to respond to interrupts or bus signals due to a fault (e.g., a hard freeze), the target processor core can directly obtain the first data from the first memory segment and output it, successfully obtaining and outputting the first data in the first register of the faulty processor core. This embodiment solves the problem of related technologies that cannot accurately and timely obtain the data in the registers of the faulty processor core.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating an application scenario of a register data processing method for a faulty processor core provided in an embodiment of this application; Figure 2 This is a flowchart of the steps of a register data processing method for a faulty processor core provided in an embodiment of this application; Figure 3 This is a flowchart of another method for processing register data of a faulty processor core provided in an embodiment of this application; Figure 4 This is a flowchart illustrating the steps of a method for determining the operating state of a processor core, as provided in an embodiment of this application. Figure 5 This is a flowchart of another method for processing register data of a faulty processor core provided in this application embodiment; Figure 6 This is a schematic diagram of the structure of a register data processing system for a fault processor core provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a register data processing device for a fault processor core provided in an embodiment of this application; Figure 8 This is a block diagram of an electronic device provided in an embodiment of this application; Figure 9 This is a block diagram of another electronic device according to another embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in this application are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0022] Figure 1 This is a schematic diagram illustrating an application scenario of a register data processing method for a faulty processor core provided in an embodiment of this application. The application scenario includes at least multiple processor cores and multiple memory regions. (Refer to...) Figure 1 Multiple processor cores may include processor core 0, processor core 1, and processor n; multiple memory regions may include memory region 0, memory region 1, and memory region n.

[0023] Memory slice 0, memory slice 1, and memory slice n correspond to processor 0, processor 1, and processor n, respectively. When a processor core malfunctions, the first data in the first register of the malfunctioning processor core is written into the first memory slice corresponding to the malfunctioning processor core, and the target processor core, which has not malfunctioned, reads the data from the first memory slice.

[0024] With the widespread application of multi-core processors in servers, embedded systems, and high-reliability scenarios, the stability of operating systems increasingly relies on the collaborative operation and observability of various Central Processing Unit (CPU) cores. During the operation of multi-core processors, factors such as microarchitectural defects, bus arbitration anomalies, cache coherence protocol deadlocks, ineffective firmware or kernel endpoint masking, and defects in non-maskable exception handling can cause some processor cores (such as CPU1) to experience prolonged periods of stagnation or suspension. For example, this may manifest as spin locks, failure to wake up from a Wait for Interrupt (WFI) state, or a stagnant program counter. When a processor core experiences a stagnation or suspension, it loses its ability to respond to external stimuli.

[0025] When a processor core freezes or hangs, losing its ability to respond externally, Inter-Processor Interrupt (IPI) technology, endpoint detection methods, and remote register read methods typically fail. Furthermore, internationally standardized debugging techniques (Joint Test Action Group, JTAG) and external debug modules may be disabled or unavailable in mass-production equipment, restricted environments, or hardened configurations. This prevents the successful acquisition of data from the faulty processor core's registers using these methods, rendering the faulty processor core's failure unrecoverable.

[0026] In related technologies, data in the registers of a faulty processor core can be obtained through a system-level watchdog reset method, status data can be collected in the interrupt context after triggering a non-maskable interrupt (NMI), or faulty data in the registers of a faulty processor core can be recorded through periodic software self-tests and heartbeats, firmware or kernel traces and performance counter recordings.

[0027] However, data from the faulty processor core can only be obtained through related technologies if the faulty processor core still possesses the most basic interrupt or bus response capabilities. Related technologies struggle to capture register context data when the processor core experiences a hard deadlock or the instruction flow completely stalls. While reset measures may restore service, they may destroy the initial context of the fault, failing to provide accurate information for fault location of the processor core.

[0028] Especially when a normal processor core (e.g., CPU0) cannot access the debug registers or context of a faulty processor core (CPU1), critical data such as the registers, program counter, and stack pointer (SP) of the frozen faulty processor core are difficult to preserve, greatly increasing the complexity of fault location. Existing techniques also suffer from the problem of not being able to accurately and promptly obtain the data in the registers of the faulty processor core.

[0029] To address the problems in related technologies, this application provides a method, apparatus, device, and medium for processing register data of a faulty processor core. The method includes: acquiring the operating state of each of a plurality of processor cores; the operating state includes a faulty state or a normal operating state; in response to identifying a faulty processor core among the plurality of processor cores whose operating state is faulty, acquiring first data in a first register of the faulty processor core; storing the first data in a first memory segment corresponding to the faulty processor core; instructing a target processor core to read the first data from the first memory segment and output it; the target processor core is the processor core among the plurality of processor cores whose operating state is normal operating state.

[0030] It should be noted that the above application scenarios are merely illustrative descriptions of the embodiments of this application. In this application, there may be two or more processor cores. The memory slice allocated to the same processor core is a continuous memory slice, but the memory slices between different processor cores may be continuous or discontinuous.

[0031] The data processing method of the processor core provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Figure 2 This is a flowchart illustrating the steps of a register data processing method for a faulty processor core provided in an embodiment of this application, as shown below. Figure 2 As shown, the method may include: Step 101: Obtain the running status of each processor core in the multiple processor cores.

[0033] The operating status includes either a fault status or a normal operating status.

[0034] For example, you can obtain the program counter (PC) value of the processor core and then use that value to determine the running status of the processor core.

[0035] For example, fault states can include stuck, and / or suspended states.

[0036] Step 102: In response to the identification of a faulty processor core in the running state among multiple processor cores, the first data in the first register of the faulty processor core is obtained.

[0037] As long as a faulty processor core is detected among multiple processor cores, the first data in the first register of the faulty processor core is retrieved. Therefore, at the moment the fault occurs, the first data in the first register of the faulty processor core can be preserved, preventing subsequent system activity or resets from corrupting the first data in the first register.

[0038] Compared to related technologies that rely on international standards for chip and circuit board testing and debugging (Joint Test Action Group, JTAG) or manual intervention, this embodiment can automatically acquire high-value debugging information on the production line or remote site, and successfully retain the first data of the first field in the first register when the faulty processor core cannot respond.

[0039] Step 103: Store the first data into the first memory segment corresponding to the faulty processor core.

[0040] For example, during the operating system startup phase, a contiguous memory slice is reserved for each processor core; this memory slice corresponds to a faulty processor core. The memory slice corresponding to the faulty processor core is the first memory slice in this step. The startup phase can be firmware startup, bootloader startup, and / or the early kernel startup phase.

[0041] During system startup, an independent reserved memory segment is allocated to each processor core. If a processor core freezes, the first data in the first register of the frozen processor core is directly written into its corresponding reserved memory segment (i.e., the first memory segment) via hardware. The first register can include all registers of the frozen processor. Therefore, even if the frozen processor core freezes, the first data in its first register will not be lost, and can be read by other normally functioning target processor cores through subsequent processing steps.

[0042] The method in this embodiment can be implemented in hardware. For example, after the hardware detects that the program counter value of the processor core remains unchanged within a preset time period, it can directly read and save the first data of the first register (e.g., including general-purpose registers and critical privilege registers) of the faulty processor core without the cooperation of the faulty processor core, and save the first data to the first memory area of ​​the faulty processor core.

[0043] Step 104: Instruct the target processor core to read the first data from the first memory segment and output it.

[0044] The target processor core is the processor core that is in a normal operating state among multiple processor cores.

[0045] The method in this embodiment can be implemented in hardware. For example, the hardware sends an interrupt number to the target processor core, instructing the target processor core to read and output the first data from the first memory segment according to the interrupt routine corresponding to the interrupt number.

[0046] For example, after detecting a freeze event, the hardware notifies the normally operating target processor core by triggering a special interrupt number. The target processor core can then immediately read and print the first data from the first register of the frozen processor core within its interrupt handler, enabling rapid fault location based on this first data.

[0047] Based on this, this embodiment implements a cross-core interrupt notification mechanism. When a stuck, faulty processor core cannot respond, by saving the first data and cooperating across cores through hardware execution, the information of the faulty thread in the faulty processor core can still be obtained promptly and successfully. This solves the problem in related technologies where methods for maintaining data in the processor core's registers rely on operating system scheduling or cross-core register access. This embodiment achieves the retention and output of the first data in the first register of the faulty processor core through a combination of hardware and software.

[0048] For example, a data read request can be sent to the target processor to instruct the target processor to read first data from the first memory segment and output it.

[0049] In a multi-core system, when a processor malfunctions and freezes, it may stop responding to interrupt signals or fail to acknowledge the bus. Since registers are private to the processor core, other processor cores cannot directly access the registers of a frozen, faulty processor core. For example, a normally functioning CPU0 cannot directly access the registers of a frozen CPU1. Therefore, in the event of a processor core failure, it is impossible to directly retrieve the first data from its first register using other normally functioning processor cores.

[0050] In this embodiment, the PC pointer of each processor core can be monitored by hardware. Based on the PC pointer, it can be determined whether each processor core has a stuck fault. The first data of the first register of the stuck processor core is written into the first memory segment reserved for it, and then read and output by the target processor core. Normal processor cores cannot access the private first register of the stuck processor core, but they can access its first memory segment. Therefore, this process does not depend on the access capabilities of other processor cores, thus solving the problem of access restrictions between processor cores.

[0051] At the moment a faulty processor core freezes, the hardware directly saves the first data in the first register of the faulty processor core, thus avoiding the loss of the first data in the first register due to subsequent operating system changes. The method in this embodiment can ensure the integrity and real-time nature of the acquired fault scene information (i.e., the first data in the first register) without waiting for a system restart or manual intervention for debugging.

[0052] When a target processor core in normal operation receives a special interrupt signal, it can immediately output the first data of the first register of the stuck, faulty processor core. This process does not rely on additional devices and can quickly obtain the first data of the first register at the fault location, which helps to locate problems such as deadlock and abnormal instruction flow in the faulty processor core. Based on this embodiment, the time for locating faulty processor core problems is reduced.

[0053] The method in this embodiment does not affect the operation of other processor cores, and can complete the acquisition of debug data (i.e., the first data in the first register) without interrupting the overall business, thus avoiding a complete system crash.

[0054] The method in this embodiment is applicable to high-availability scenarios such as servers, communication equipment, and embedded control systems. By obtaining the register data of a faulty processor core based on the method in this embodiment, the availability and security of the system are improved.

[0055] When a faulty processor core is unresponsive, methods for obtaining data from the registers of the faulty processor core in related technologies fail. However, the method of this embodiment can directly obtain the first data of the first register of the faulty processor core at the hardware level and write it into the first memory segment of the faulty processor core. The method of this embodiment does not rely on the faulty processor core executing any software path, thus it is operable in the event of a hard deadlock or instruction flow stagnation. The method of this embodiment does not rely on the faulty processor core's response to interrupt instructions or the bus, and is applicable to scenarios where the processor core is hard-locked, and the first data of the first register of the hard-locked faulty processor core is obtained.

[0056] Furthermore, in this embodiment, the operating state of each of the multiple processor cores is obtained; the operating state includes a fault state or a normal operating state. In response to the identification of a faulty processor core among the multiple processor cores, the first data in the first register of the faulty processor core is obtained. Compared to manually obtaining the first data or resetting the processor core and then obtaining the first data after reset, this embodiment can obtain the first data in the first register of the faulty processor core in a timely manner, preventing system activity or reset from changing the first data in the first register, thus avoiding the inability to accurately obtain the first data in the first register when the faulty processor core malfunctioned. After obtaining the first data in the first register, the first data is stored in the first memory segment corresponding to the faulty processor core, and the target processor core is instructed to read the first data from the first memory segment and output it. The registers of the processor core are private to the processor core; the target processor core cannot directly access the first register that does not belong to the target processor core. However, after storing the first data in the first memory segment, the target processor core can obtain the first data from the first memory segment. The process of obtaining the first data in the first register of the faulty processor core in this embodiment does not depend on the faulty processor core. Even if the faulty processor core is unable to respond to interrupts or bus signals due to a fault (e.g., a hard freeze), the target processor core can directly obtain the first data from the first memory segment and output it. This embodiment solves the problem of related technologies that cannot accurately and timely obtain the data in the registers of the faulty processor core.

[0057] Figure 3 This is a flowchart illustrating the specific steps of a register data processing method for a faulty processor core provided in an embodiment of this application. Figure 3 As shown, the method may include: Step 201: Obtain the program counter value corresponding to each processor core in the multiple processor cores.

[0058] For example, the PC value corresponding to a processor core can be obtained through a PC sampler used to collect PC values; the PC sampler is hardware. Multiple processor cores in a multi-core processor can share a PC sampler, or a PC sampler can be set up in each processor; the PC sampler is hardware.

[0059] For example, refer to Figure 4 Step 201 may include the following sub-steps: Sub-step A1: For each processor core, obtain multiple program counter values ​​of the processor core in multiple consecutive time periods; The program counter value and the time period are in a one-to-one correspondence.

[0060] In this embodiment, for each processor core, multiple PC values ​​are obtained for the processor core in multiple consecutive time periods. Based on the multiple PC values ​​in multiple consecutive time periods, the operating status of the processor core can be accurately determined.

[0061] Step 202: For each processor core, obtain the running status of the processor core based on the program counter value of the processor core.

[0062] Operating status includes: fault status or normal operating status.

[0063] The PC value is the address of the next instruction to be executed by the processor core in the computer's memory. The program counter value can reflect whether the processor core is in a forward state. By obtaining the PC value of each processor core in multiple processor cores, the running status of the processor core can be accurately determined.

[0064] For example, continue to refer to Figure 4 Step 202 may include the following sub-steps: Sub-step B1: For each processor core, if the number of consecutive time periods with the same program counter value is greater than or equal to a preset threshold, then the processor core is determined to be in a fault state.

[0065] PC values ​​and time periods are in one-to-one correspondence. A continuous time period with equal PC values ​​indicates that the PC values ​​corresponding to the time periods are equal, and the time periods with equal PC values ​​are continuous time periods.

[0066] The preset number threshold can be set based on empirical data. The PC value is the address of the next instruction to be executed by the processor core in the computer's memory. The processor core will not execute the next instruction until the current instruction has finished executing; therefore, the PC will not change while the currently executing instruction is incomplete. The system can obtain the number of time cycles used by the processor to process each historical instruction within a preset historical time period; compare the number of time cycles to obtain the maximum number of time cycles; and set the preset number threshold to a value greater than or equal to the maximum number of time cycles.

[0067] For example, if the preset threshold is 5, and the PC value of the processor core is 1236 in the first, second, third, fourth, and fifth time periods, then the number of consecutive time periods in which the program counter values ​​are equal is greater than or equal to the preset threshold.

[0068] Sub-step B2: For each processor core, if the number of consecutive time periods with equal program counter values ​​is less than a preset threshold, then the processor core is determined to be in normal operating state.

[0069] For example, if the preset threshold is 5, the PC value of the first time period is 1235, and the PC value of the processor core is 1236 in the second, third, fourth and fifth time periods, then the number of consecutive time periods in which the program counter values ​​are equal is less than the preset threshold.

[0070] For example, the processor core's PC value in the current time period is obtained, along with the PC value of each historical time period within multiple historical time periods adjacent to the current time period. If the PC value of each historical time period adjacent to the current time period is the same as the PC value of the current time period, and the sum of the number of such historical time periods and the value 1 is greater than or equal to a preset threshold, then the processor core's operating state is determined to be a fault state; otherwise, the processor core's operating state is determined to be a normal operating state. The sum of the number of such historical time periods and the value 1 represents the sum of the current time period and the number of such historical time periods.

[0071] For example, the running status of a processor core can be obtained as follows: In a multi-core system, the PC pointer of each processor core is periodically checked. If the PC pointer does not change within a set time window, the processor core is determined to be stuck. This hardware-level PC pointer detection mechanism uses a prolonged period of unchanged PC pointer as the criterion for determining a stuck state.

[0072] In this embodiment, for each processor core, if the number of consecutive time periods with equal program counter values ​​is greater than or equal to a preset threshold, it indicates that the processor core's program counter value has been stagnant for a relatively long time. This situation is usually caused by processor core freezing, hanging, or other faults. Therefore, in this case, the processor core's operating state is determined to be a fault state. For each processor core, if the number of consecutive time periods with equal program counter values ​​is less than a preset threshold, it indicates that even if the processor core has consecutive time periods with equal program counter values, the number of consecutive time periods is relatively small, meaning the program counter value stagnates for a short time. This situation may be due to the processor core taking a long time to process a certain instruction, rather than a processor core freezing or hanging. Therefore, in this case, the processor core's operating state is determined to be a normal operating state. Based on this embodiment, the situation where a brief PC pause during the execution of a certain instruction is misjudged as a processor core fault can be avoided. This embodiment improves the accuracy of obtaining the processor core's operating state.

[0073] Step 203: In response to the identification of a faulty processor core in the running state among multiple processor cores, the first data in the first register of the faulty processor core is obtained.

[0074] For example, the first register may include at least one of the following: a general-purpose register, a floating-point register, a vector register, and a control status register. Based on this, the first data in various first registers of the faulty processor core can be obtained, and based on this first data, the fault of the faulty processor can be accurately located.

[0075] Step 204: Store the first data into the first memory segment corresponding to the faulty processor core.

[0076] For example, each processor core has a corresponding memory slice. Based on the correspondence between processor cores and memory slices, the first memory slice of the faulty processor core is obtained, and the first data is stored in the first memory slice corresponding to the faulty processor core.

[0077] Step 205: Send a preset interrupt number to the target processor core to instruct the target processor core to read and output the first data from the first memory segment based on the interrupt handler corresponding to the preset interrupt number.

[0078] In this embodiment, sending a preset interrupt number to the target processor core can accurately instruct the target processor core to read and output the first data from the first memory segment based on the interrupt handler corresponding to the interrupt number.

[0079] For example, one or more can be randomly selected as the target processor core from normal processor cores that are in normal operating condition.

[0080] For example, the target processor core in the foregoing embodiments can be obtained by the following method: Step 206: From multiple processor cores, obtain the normal processor core whose running state is normal.

[0081] The method for determining whether the processor core is in a normal operating state has been described in the foregoing embodiments and will not be repeated here.

[0082] Step 207: If there are multiple normal processor cores, obtain the task priority of the task being executed by each normal processor core.

[0083] Step 208: Identify the normal processor cores whose task priority is lower than that of other tasks as the target processor cores.

[0084] In this embodiment, a normal processor core in a normal operating state is selected from multiple processor cores. If there are multiple normal processor cores, the task priority of the task being executed by each normal processor core is obtained. The normal processor core with a task priority lower than other task priorities is determined as the target processor core. After storing the first data of the first register of the faulty processor core into the first memory segment of the faulty processor core, the target processor interrupts its current task and reads the first data from the first memory segment. Thus, only tasks with lower priority are affected, avoiding impact on tasks with higher priority.

[0085] For example, the method also includes the following steps: Step 209: During the startup phase of the multi-core processor system, memory slices are allocated for each processor core of the multi-core processor.

[0086] Step 210: Determine the first memory slice corresponding to the faulty processor core from the memory slices allocated to the faulty processor core.

[0087] In this embodiment, during the system startup phase of the multi-core processor, a memory slice is allocated to each processor core. Therefore, if a faulty processor core is identified among the multiple processor cores, the memory slice allocated to the faulty processor core can be used to determine the first memory slice corresponding to that faulty processor core. The first data from the first register of the faulty processor core can then be written into its corresponding first memory slice. Allocating a separate memory slice to each processor core avoids the problem of multiple processor cores sharing a memory slice, which prevents the rapid and accurate determination of the first memory slice used to store the first data from the first register of the faulty processor core.

[0088] Reference Figure 5 The method for processing register data of a faulty processor core may include the following steps: Step S1: Configure the hardware monitoring module in the multi-core processor system.

[0089] Step S2: The program counter value of each processor core is periodically detected by the hardware monitoring module.

[0090] The time period for periodically detecting the PC value of the processor core can be determined based on empirical data; for example, it can be set to 10μs.

[0091] Step S3: Determine whether the PC value of the processor core has changed within the preset time window. Otherwise, proceed to step S4; otherwise, return to step S2.

[0092] Step S4: Determine that the processor core is in a frozen state.

[0093] If the processor core's PC pointer does not change within the preset time window, the processor core is determined to be in a frozen state.

[0094] In step S5, the hardware monitoring module saves the first data in all the first registers of the faulty processor core that is in a stuck state to the first memory area reserved by the system for the faulty processor core.

[0095] For example, during the system startup phase, a contiguous reserved memory segment is allocated for each processor core; the system startup phase may include the firmware, bootloader, and early kernel initialization (init) phases.

[0096] Step S6: Instruct the target processor core that is operating normally in the system to read the first data of the first memory segment and output it, so as to perform fault location core analysis based on the output first data.

[0097] For example, a processor core that is operating normally in the system (e.g., CPU0) can read the first data in the reserved memory of the faulty processor core after a fault occurs and output it, so as to locate and analyze the fault based on the first data, thereby obtaining its operating status information without relying on the response of the stuck core itself.

[0098] The register data processing method for the faulty processor core in this embodiment can be implemented through the processor core's data processing system. Each processor core can have its own dedicated data processing system, or multiple processor cores can share a single data processing system.

[0099] Reference Figure 6 The register data processing system 30 of the fault processor core may include a program counter value sampler 301, a stop determiner 302, and a context capture controller 303.

[0100] For each processor core, the PC sampler 301 samples the PC value of the processor core according to a preset time period (Tsample). The preset time period can be set according to user needs, for example, it can be set to 10μs.

[0101] Stagnation Detector 302 is a PC constant counter. The method for Stagnation Detector 302 to determine the running state of the processor core can be: obtain the duration Ttimeout when the PC value remains constant, and calculate the ratio K of the duration Ttimeout to the preset time period Tsample: K = Ttimeout / Tsample.

[0102] If k is greater than or equal to a preset value (e.g., 500), the processor core is determined to be in a frozen state. For example, if Ttimeout=5ms, Tsample=10μs, and K=500, the processor core is determined to be in a frozen state. As an example, if the processor core is determined to be in a frozen state, STALL_DETECTED is set.

[0103] After STALL_DETECTED is set, the context capture controller 303 performs the following operations on a stuck, faulty processor core: requests processor core debugging or suspends arbitration; this process does not depend on processor core interrupt responses. It reads data from the following registers in a preset order: General-Purpose Registers (GPRs), such as x0~x31 or a set of general-purpose registers; data from critical privilege registers, such as the Program Counter (PC), Supervisor Exception Program Counter (sepc), Stack Pointer (SP), Return Address Register (RA), Status Register, Cause Register, Trap Value Register (TVAL), Supervisor Address Translation and Protection (SATP), etc.; and optional floating-point / vector register summaries.

[0104] The data block read from the first register is written to the first memory segment corresponding to the fault register via the on-chip bus or Advanced eXtensible Interface (AXI). After the data is written to the first memory segment, a special interrupt signal is triggered by the hardware to any normal processor core that is not stuck, or to a specified normal processor core. The normal processor that triggered the interrupt signal prints the register information of the stuck faulty processor core in its interrupt function.

[0105] refer to Figure 7This document illustrates a register data processing device for a faulty processor core provided in an embodiment of this application. The register data processing device 40 for a faulty processor core includes: a first acquisition module 401, used to acquire the operating state of each processor core among a plurality of processor cores; the operating state includes: a faulty state or a normal operating state; a second acquisition module 402, used to acquire first data in the first register of the faulty processor core in response to the identification of a faulty processor core among the plurality of processor cores whose operating state is faulty; a data writing module 403, used to store the first data into a first memory segment corresponding to the faulty processor core; and a control module 404, used to read the first data from the first memory segment and output it to the target processor core; the target processor core is the processor core among the plurality of processor cores whose operating state is normal operating state.

[0106] Optionally, the first acquisition module 401 may include: a first acquisition submodule, used to acquire the program counter value corresponding to each processor core in the multiple processor cores; and a second acquisition submodule, used to acquire the running status of each processor core based on the program counter value of the processor core.

[0107] Optionally, the first acquisition submodule includes: a third acquisition submodule, used to acquire multiple program counter values ​​of each processor core in multiple consecutive time periods; wherein the program counter values ​​and time periods correspond one-to-one.

[0108] Optionally, the second acquisition submodule includes: a first determination submodule, used to determine the operating state of each processor core as a fault state if the number of consecutive time periods in which the program counter values ​​are equal is greater than or equal to a preset number threshold; and a second determination submodule, used to determine the operating state of each processor core as a normal operating state if the number of consecutive time periods in which the program counter values ​​are equal is less than a preset number threshold.

[0109] Optionally, the device 40 further includes: an allocation module for allocating memory slices for each processor core of the multi-core processor during the startup phase of the system; and a first determination module for determining a first memory slice corresponding to the faulty processor core from the memory slices allocated to the faulty processor core.

[0110] Optionally, the device 40 further includes: a third acquisition module, used to acquire a normal processor core whose running state is normal from multiple processor cores; a fourth acquisition module, used to acquire the task priority of the task being executed by each normal processor core if there are multiple normal processor cores; and a second determination module, used to determine the normal processor core whose task priority is lower than other task priorities as the target processor core.

[0111] Optionally, the first register may include at least one of the following: a general-purpose register, a floating-point register, a vector register, and a control status register.

[0112] Optionally, the control module 404 includes a control submodule, used to send a preset interrupt number to the target processor core to instruct the target processor core to read and output the first data from the first memory segment based on the interrupt handler corresponding to the preset interrupt number.

[0113] Compared to methods that obtain the first data manually or by resetting the processor core and then obtaining the first data after a reset, this embodiment can promptly obtain the first data from the first register of the faulty processor core. This prevents system activity or resets from altering the first data in the first register, thus ensuring accurate access to the data in the first register at the time of the faulty processor core's failure. The processor core's registers are private to the processor core; the target processor core cannot directly access registers that do not belong to it. However, after storing the first data in the first memory segment, the target processor core can retrieve the first data from that segment. The process of obtaining the first data from the first register of the faulty processor core in this embodiment is independent of the faulty processor core itself. Even if the faulty processor core is unable to respond to interrupts or bus signals due to a fault (e.g., a hard freeze), the target processor core can still directly obtain and output the first data from the first memory segment. This embodiment solves the problem of related technologies that cannot accurately and promptly obtain the data in the registers of the faulty processor core.

[0114] Figure 8 This is a block diagram illustrating an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0115] Reference Figure 8 The electronic device 500 may include one or more of the following components: processing component 502, memory 504, power supply component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514, and communication component 516.

[0116] Processing component 502 typically controls the overall operation of electronic device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 502 may include one or more processors 520 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 502 may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502.

[0117] Memory 504 is used to store various types of data to support the operation of electronic device 500. Examples of this data include instructions for any application or method operating on electronic device 500, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0118] Power supply component 506 provides power to various components of electronic device 500. Power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 500.

[0119] Multimedia component 508 includes a screen that provides an output interface between electronic device 500 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When electronic device 500 is in an operating mode, such as shooting mode or multimedia mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0120] Audio component 510 is used to output and / or input audio signals. For example, audio component 510 includes a microphone (MIC) used to receive external audio signals when electronic device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 504 or transmitted via communication component 516. In some embodiments, audio component 510 also includes a speaker for outputting audio signals.

[0121] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0122] Sensor assembly 514 includes one or more sensors for providing state assessments of various aspects of electronic device 500. For example, sensor assembly 514 may detect the on / off state of electronic device 500, the relative positioning of components such as the display and keypad of electronic device 500, changes in position of electronic device 500 or a component of electronic device 500, the presence or absence of user contact with electronic device 500, orientation or acceleration / deceleration of electronic device 500, and temperature changes of electronic device 500. Sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0123] Communication component 516 facilitates wired or wireless communication between electronic device 500 and other devices. Electronic device 500 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 4G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0124] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a register data processing method for a fault processor core provided in this application embodiment.

[0125] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, which can be executed by a processor 520 of an electronic device 500 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0126] Figure 9 This is a block diagram illustrating an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be provided as a server. (Refer to...) Figure 9 The electronic device 600 includes a processing component 622, which further includes one or more processors, and memory resources represented by memory 632 for storing instructions, such as application programs, that can be executed by the processing component 622. The application programs stored in memory 632 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 622 is configured to execute instructions to perform a register data processing method for a faulty processor core provided in embodiments of this application.

[0127] Electronic device 600 may also include a power supply component 626 configured to perform power management of electronic device 600, a wired or wireless network interface 650 configured to connect electronic device 600 to a network, and an input / output (I / O) interface 658. Electronic device 600 may operate on an operating system stored in memory 632, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0128] This application also provides a computer program product, including a computer program that, when executed by a processor, implements a method for processing register data of a faulty processor core.

[0129] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0130] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0131] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0132] The foregoing has provided a detailed description of the register data processing method, apparatus, electronic device, and computer-readable storage medium for a fault processor core provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for processing register data of a faulty processor core, characterized in that, include: The running status of each of the multiple processor cores is obtained separately; The operating status includes: fault status or normal operating status; In response to the identification of a faulty processor core among the plurality of processor cores, the first data in the first register of the faulty processor core is obtained; The first data is stored in the first memory segment corresponding to the faulty processor core; The target processor core is instructed to read the first data from the first memory segment and output it; the target processor core is the processor core in the normal operating state among the plurality of processor cores.

2. The method according to claim 1, characterized in that, The step of acquiring the operating state of each of the multiple processor cores includes: Obtain the program counter value corresponding to each of the plurality of processor cores; For each processor core, the running state of the processor core is obtained based on the program counter value of the processor core.

3. The method according to claim 2, characterized in that, Obtaining the program counter value corresponding to each of the plurality of processor cores, including: For each processor core, obtain multiple program counter values ​​of the processor core in multiple consecutive time periods; The program counter value and the time period are in one-to-one correspondence.

4. The method according to claim 3, characterized in that, The step of obtaining the running state of each processor core based on its program counter value includes: For each processor core, if the number of consecutive time periods in which the program counter values ​​are equal is greater than or equal to a preset threshold, then the operating state of the processor core is determined to be a fault state. For each processor core, if the number of consecutive time periods in which the program counter values ​​are equal is less than a preset threshold, then the running state of the processor core is determined to be a normal running state.

5. The method according to claim 1, characterized in that, The method further includes: During the startup phase of a multi-core processor system, a memory slice is allocated for each of the processor cores of the multi-core processor. The memory slice allocated to the faulty processor core is used to determine the first memory slice corresponding to the faulty processor core.

6. The method according to claim 1, characterized in that, The first register includes at least one of the following: a general-purpose register, a floating-point register, a vector register, and a control status register.

7. The method according to claim 1, characterized in that, The instruction to the target processor core to read the first data from the first memory region and output it includes: A preset interrupt number is sent to the target processor core to instruct the target processor core to read the first data from the first memory segment and output it based on the interrupt handler corresponding to the preset interrupt number.

8. A register data processing device for a faulty processor core, characterized in that, include: The first acquisition module is used to acquire the running status of each of the multiple processor cores; The operating status includes: fault status or normal operating status; The second acquisition module is used to acquire first data in the first register of the faulty processor core in response to the identification that there is a faulty processor core among the multiple processor cores whose running state is faulty. A data writing module is used to store the first data into a first memory segment corresponding to the faulty processor core; The control module is used to instruct the target processor core to read the first data from the first memory segment and output it; the target processor core is the processor core in the normal operating state among the multiple processor cores.

9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method as described in any one of claims 1 to 7.

Images