A design method based on multi-stage FPGA communication of a testing machine

Abstract

The application relates to the field of FPGA communication technology, and particularly discloses a design method for multistage FPGA communication based on a test machine, which comprises the following steps: setting a board card area, and respectively arranging a backboard and a motherboard in each board card area; respectively configuring a preset number of digital board cards and matched power supply board cards in each board card area; dividing all the board card areas into two continuous areas, and respectively defining the areas as a master area and a slave area; and connecting the universal input / output interface on the host computer / slave computer to an intermediate adapter board through the backboard, connecting the intermediate adapter board to the motherboard, connecting the interface board of the calibration board card through a cable, and finally reaching the main field programmable gate array of the calibration board card.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA communication technology, in particular to a design method based on multi-level FPGA communication of a test machine. BACKGROUND

[0002] With the development of the test machine and the continuous improvement of the precision of the instrument, the synchronization of the multi-channel digital signal is required, which is specifically manifested as: ensuring that the multi-channel digital signal is accurately applied to the device under test at the same time to ensure the accuracy and reliability of the test results. In order to achieve this goal, the industry often uses calibration board to AC calibrate digital signal, and through automatic calibration mechanism to eliminate the signal difference between multiple channels, so as to meet the technical requirement of synchronous application.

[0003] However, in the existing calibration board design based on field programmable gate array (FPGA) as a control chip, there is a prominent contradiction between hardware resources and design specifications. Specifically, the input and output (IO) port resources of the original FPGA control chip are in a saturated state, and cannot be additionally allocated IO port to realize the calibration function, resulting in that the calibration design is difficult to integrate into the existing hardware architecture. For this problem, the existing two conventional solutions have significant drawbacks and cannot meet the actual application requirements:

[0004] One is to replace the FPGA control chip with more IO ports. This scheme can fundamentally solve the problem of insufficient IO ports, but on the one hand it will significantly increase the cost of device procurement, and on the other hand it needs to carry out layout and wiring design of printed circuit board (PCB) based on new chip, which not only consumes a lot of human cost, but also prolongs the product development cycle, resulting in high time and economic expenses.

[0005] The second is to compile the calibration function and the test function into two independent firmware versions, and to burn the firmware in the calibration stage and the test stage of the device respectively. This scheme avoids the limitation of IO port resources, but directly violates the design specification of "single firmware version control and unified burning process" in the enterprise - the existence of multiple firmware versions will greatly increase the complexity of version management, and in the process of switching burning in different stages, it is easy to cause firmware misburning, missing burning and other problems, which significantly increases the debugging risk before the device is shipped and the difficulty of later maintenance. SUMMARY

[0006] The purpose of the present application is to provide a design method based on multi-level FPGA communication of a test machine to solve the above technical problems:

[0007] The purpose of the present application can be achieved by the following technical solutions:

[0008] A design method based on multi-level FPGA communication of a test machine, comprising the following steps:

[0009] Set the card area, each card area is provided with a backplane and a motherboard respectively;

[0010] Each card area is respectively configured with a preset number of digital cards and a power card matched therewith, wherein the signals of the digital cards are respectively plugged into the backplane and the motherboard of the corresponding card area;

[0011] All the card areas are divided into two continuous areas and are defined as a master area and a slave area respectively; the card areas in the master area share a synchronous card with a CPU for synchronization, and the synchronous card is defined as a host; the card areas in the slave area share a synchronous card with a CPU for synchronization, and the synchronous card is defined as a slave;

[0012] The general input / output interface on the host / slave is first connected to an intermediate adapter board through the backplane, then connected to the motherboard by the intermediate adapter board, then connected to the interface card of the calibration card through a cable, and finally reaches the main field programmable gate array of the calibration card.

[0013] As a further scheme of the application, the main field programmable gate array of the calibration card communicates with 16 calibration field programmable gate arrays, each of which can calibrate the digital signals of 2 digital cards, and each digital card corresponds to 640 channels.

[0014] As a further scheme of the application, the host / slave provides several general input / output interfaces, and the general input / output interface resources are divided into two types of uses:

[0015] Part of them is used for configuring the main field programmable gate array of the calibration card on the calibration card;

[0016] The other part interacts with the first-in-first-out memory interface of the main field programmable gate array of the calibration card to further distribute data to the calibration field programmable gate array, so as to realize the configuration operation of the calibration field programmable gate array.

[0017] As a further scheme of the application, a register module for controlling the mode of the general input / output interface is designed on the control chip on the host / slave, so as to realize the multiplexing function of the input / output interface, which is as follows:

[0018] With the support of the input / output interface multiplexing mechanism, part of the general input / output interfaces are not only used for configuration operation, but also support improved serial peripheral interface communication function;

[0019] The data of the digital board card is firstly transmitted to the calibration FPGA through the serial peripheral interface communication mode, the calibration FPGA interacts with the main FPGA of the calibration board card, and finally the data is transmitted back to the intermediate FPGA on the host / slave through the multiplexed general input / output interface;

[0020] Moreover, the intermediate FPGA uploads the data to the central processor through the high-speed serial computer expansion bus standard interface, and finally the data is received and processed by the host computer, so that the data interaction process of the whole multi-level FPGA is completed.

[0021] As a further scheme of the application, the configuration aspect communication process is specifically as follows:

[0022] The intermediate FPGA on the host / slave interacts with the central processor through the high-speed serial computer expansion bus standard interface, and is internally configured with a plurality of registers;

[0023] The host computer writes data to the register address, and the system extracts the low 8-bit data of the corresponding register and writes it into the FIFO of the main FPGA of the calibration board card;

[0024] Through the design of the serial configuration timing, the intermediate FPGA outputs 1-bit configuration data signal, 1-bit configuration clock signal and 1-bit configuration programming signal at its interface, and transmits these signals to the main FPGA of the calibration board card;

[0025] The main FPGA of the calibration board card outputs 1-bit configuration initialization signal and 1-bit configuration completion signal, and transmits them back to the intermediate FPGA, so as to complete the whole configuration.

[0026] As a further scheme of the application, the calibration aspect communication process is specifically as follows:

[0027] The intermediate FPGA is internally integrated with a plurality of registers, which are used for register read / write operation between the intermediate FPGA and the main FPGA of the calibration board card;

[0028] In the intermediate FPGA, an improved serial peripheral interface master module is instantiated, and in the improved serial peripheral interface master module, the intermediate FPGA performs shift processing on the content in the register and sends it in a serial manner.

[0029] The beneficial effects of the present application: the present application realizes an improved SPI communication mechanism for data interaction between multi-level FPGAs. With the help of the mechanism, only a CPU needs to be added to the original host board card, and the data collected by the calibration board card can be transmitted back to the host computer in real time and reliably, without the need for additional CPU configuration on each calibration board card. Compared with the traditional SPI protocol, the improved SPI supports multi-level communication topology on the one hand, and through the flexible master-slave mechanism, it can realize chain-like multi-level endpoint communication. On the other hand, the improved SPI communication protocol interface quantity can be flexibly changed, suitable for different application scenarios, and has strong universality and good portability.

[0030] The IO multiplexing scheme effectively avoids the redundant waste of hardware resources and PCB redesign, and the improved SPI communication greatly simplifies the system architecture, improves the data transmission efficiency and expandability, and the overall scheme takes into account the cost, reliability and maintenance convenience, and is more in line with the design specifications in mass production. BRIEF DESCRIPTION OF DRAWINGS

[0031] The present application will be further described below with reference to the accompanying drawings.

[0032] Figure 1 is the overall framework diagram of a design method based on multi-level FPGA communication of a test machine of the present application;

[0033] Figure 2 is a data flow diagram between multi-board cards in the embodiment of the present application;

[0034] Figure 3 is a communication diagram in the configuration aspect in the embodiment of the present application;

[0035] Figure 4 is a communication diagram in the calibration aspect in the embodiment of the present application Figure 1 ;

[0036] Figure 5 is a communication diagram in the calibration aspect in the embodiment of the present application Figure 2 ;

[0037] Figure 6 is a structure diagram of IO multiplexing in the embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0039] The overall framework of the test machine of the present application is as followsFigure 1 As shown, the entire design is divided into four areas, A, B, C, D, each area is equipped with 8 digital board cards HSU320, and optional power supply board cards PSU. Digital board cards and power supply board cards signal part of the plug-in backplane (BP Board), part of the plug-in motherboard (Mother Board). Among them, the A area and the B area are synchronized by a synchronous board card with CPU (master SCM024 Master); similarly, the C area and the D area are also synchronized by a synchronous board card with CPU (slave SCM024 Slave). Among them, 32 digital board cards need to be calibrated.

[0040] As shown in Figure 2 The general input / output interface (GPIO port) on the master / slave (SCM board card) is first connected to the intermediate adapter board (MBJ Board) via the backplane (BP Board), then connected to the motherboard (Mother Board) by the intermediate adapter board, and then connected to the interface board (LIF CON) of the calibration board (Calibration Board) through the cable (HI-FIX cable), and finally the signal is transmitted to the calibration board main field programmable gate array (CT FPGA). The calibration board main field programmable gate array (CT FPGA) communicates with 16 calibration field programmable gate arrays (CAL FPGA), and each calibration field programmable gate array (CAL FPGA) can calibrate the digital signals of 2 digital board cards (HSU320), and each digital board card (HSU320) corresponds to 640 channels (640ch).

[0041] Among them, the master / slave (SCM board card) provides 32 available general input / output interfaces (GPIO ports), which are divided into two main uses: part of them are used to configure the calibration board main field programmable gate array (CT FPGA) on the calibration board (Calibration); the other part interacts with the first-in-first-out memory interface (FIFO interface) of the calibration board main field programmable gate array (CT FPGA) to further distribute data to 16 calibration field programmable gate arrays (CAL FPGA), so as to realize the configuration operation of the calibration field programmable gate array (CAL FPGA).

[0042] In order to improve the utilization of general input / output interface (GPIO port) resources, reduce the cost of devices, and avoid the additional expenses caused by replacing control chips and redesigning printed circuit boards (PCB), a register module for controlling the mode of general input / output interface (GPIO port) is designed in the control chip (MID FPGA) of the host / slave (SCM board card) to realize the multiplexing function of input / output interface (IO port).

[0043] With the support of the input / output interface (IO) multiplexing mechanism, part of the general input / output interface is not only used for configuration operation, but also extended to support improved serial peripheral interface communication function. The data of the digital board card (HSU320) is first transmitted to the calibration field programmable gate array (CAL FPGA) through this improved serial peripheral interface communication mode, and then the calibration field programmable gate array interacts with the calibration board card main field programmable gate array (CT FPGA), and finally the data is transmitted back to the intermediate field programmable gate array (MID FPGA) on the host / slave (SCM board card) through the multiplexed general input / output interface. Then, the intermediate field programmable gate array uploads the data to the central processing unit through the high-speed serial computer expansion bus standard interface, and finally the data is received and processed by the upper computer (PC end), so as to complete the data interaction process of the whole multi-level field programmable gate array.

[0044] This design not only meets the multi-functional requirements under the limited general input / output interface resources, but also ensures the efficiency and scalability of the system communication process.

[0045] And the present application further comprises the following three aspects:

[0046] 1. The first is the configuration aspect of communication:

[0047] For example Figure 3As shown, the intermediate level field programmable gate array (MID FPGA) on the host / slave (SCM board card) can interact with the central processing unit (CPU) through the high-speed serial computer expansion bus standard (PCIe) interface, and is internally configured with a plurality of registers, wherein the register address for configuring the calibration board card main field programmable gate array (CT FPGA) is 0x0000_0804. The host computer (PC end) writes data to the address, and the system extracts the low 8-bit data of the register and writes it into the configuration calibration board card main field programmable gate array first-in-first-out memory (CFCT FIFO); by designing the slave serial (Slave Serial) configuration timing, the MID FPGA will output 1-bit configuration data signal (CONF_DATA, corresponding to general input / output interface GPIO

[31] ), 1-bit configuration clock signal (CONF_DCLK, corresponding to GPIO

[27] ), 1-bit configuration programming signal (CONF_nPROGRAM, corresponding to GPIO

[23] ) at its interface, and transmit these signals to the CT FPGA of the calibration board card (Calibration); at the same time, the CT FPGA will output 1-bit configuration initialization signal (CONF_nINIT, corresponding to GPIO

[24] ), 1-bit configuration completion signal (CONF_DONE, corresponding to GPIO

[28] ) back to the MID FPGA. At this point, the configuration work for the CT FPGA is completed.

[0048] 2. Secondly, the communication in the calibration aspect:

[0049] In the whole system, only the host / slave (SCM board card) integrates a central processing unit (CPU), and the host computer (PC end) and the central processing unit send and receive data through gigabit Ethernet. Therefore, if the calibration board card main field programmable gate array (CT FPGA) and the calibration field programmable gate array (CAL FPGA) need to interact with the host computer (PC end), they must complete the communication process through the intermediate level field programmable gate array (MID FPGA) relay. In this multi-level communication architecture, the improved serial peripheral interface (SPI) communication protocol in the application plays a key role and can efficiently support data transmission between multiple endpoints.

[0050] As Figure 4 and Figure 5As shown, the intermediate level field programmable gate array (MID FPGA) internally integrates a plurality of registers for control and data interaction. Among them, the CT_ADDR register with address 0x0000_0944, the CT_WDAT register with address 0x0000_0948, and the CT_RDAT register with address 0x0000_0960 are three registers specially used for register read-write operation between the intermediate level field programmable gate array (MID FPGA) and the calibration board card main field programmable gate array (CT FPGA). To realize this communication function, an improved serial peripheral interface master module (SPIMx) independently designed in the intermediate level field programmable gate array (MID FPGA) is instantiated. Inside the improved serial peripheral interface master module (SPIMx), the intermediate level field programmable gate array (MID FPGA) will perform shift processing on the contents in the CT_ADDR register and the CT_WDAT register, and send them in a serial manner.

[0051] Specifically: the highest bit of the CT_ADDR register is used as an operation type flag bit, which is used to clearly indicate whether this operation is a write operation (Write) or a read operation (Read); the remaining bits of the CT_ADDR register represent the address of the target register; and the CT_WDAT register stores the actual data content to be written into the calibration board card main field programmable gate array (CT FPGA) register. The shifted data is output to the calibration board card main field programmable gate array (CT FPGA) through the following four general input / output interface (GPIO) signal lines:

[0052] The calibration synchronization / chip select signal (CAL_nSYNC, corresponding to the general input / output interface GPIO[0]); the calibration serial clock signal (CAL_SCLK, corresponding to the general input / output interface GPIO[3]); the calibration master send / slave receive line (CAL_SDI, corresponding to the general input / output interface GPIO[4]); and the calibration master receive / slave send line (CAL_SDO, corresponding to the general input / output interface GPIO[7]).

[0053] The calibration master receiving / slave sending line (CAL_SDO) is a data back signal from the calibration card main field programmable gate array (CT FPGA) to the intermediate level field programmable gate array (MID FPGA), and the bit width is configurable. In this design, due to the limited general input / output interface (GPIO) resources, the calibration master receiving / slave sending line (CAL_SDO) is set to 1-bit transmission, although this affects the transmission rate to some extent, but still meets the current system data bandwidth requirements. At the calibration card main field programmable gate array (CT FPGA) end, the corresponding serial peripheral interface slave module (SPISx) is instantiated. This module is responsible for receiving serial signals from the serial peripheral interface master module (SPIMx), correctly splicing and parsing the serial data into complete register addresses and data, and finally realizing the write or read operation on the internal registers of the calibration card main field programmable gate array (CT FPGA).

[0054] Similarly, if the intermediate level field programmable gate array (MID FPGA) writes the corresponding address and data to the CAL_ADD register with address 0x0000_0901 and the CAL_WDAT register with address 0x0000_0902 of the calibration card main field programmable gate array (CT FPGA), then through the 16 serial peripheral interface master modules (SPIMx) instantiated by the calibration card main field programmable gate array (CT FPGA), the data can be written to the registers in the 16 calibration field programmable gate arrays (CAL FPGA) (each of the 16 calibration field programmable gate arrays (CAL FPGA) instantiates a serial peripheral interface slave module (SPISx) to receive serial data and splice and parse it into register address and data, which is consistent with the above principle). Similarly, the 16 calibration field programmable gate arrays (CAL FPGA) will transmit data back to the calibration card main field programmable gate array (CT FPGA) through the master receiving / slave sending line (SDO) signal to the CAL_RDAT0, CAL_RDAT1, …, CAL_RDAT15 registers with addresses 0x0000_0908, 0x0000_0909, …, 0x0000_0917, respectively. Through the improved serial peripheral interface (SPI) communication protocol, in the case of only one central processing unit (CPU), the registers of the multi-level field programmable gate array (FPGA) can be written or read, the control and data interaction of the whole system is realized, the whole design logic is clear, and the code reusability is high.

[0055] Although the improved serial peripheral interface (SPI) communication protocol can realize accurate control of registers of multi-stage field programmable gate arrays (FPGAs) such as a calibration field programmable gate array (CAL FPGA) and a calibration card main field programmable gate array (CT FPGA), for large-scale data transmission, the transmission efficiency is low by simply relying on register read and write, and it is difficult to meet the calibration bandwidth requirement. Especially in the current system architecture, each calibration field programmable gate array (CAL FPGA) corresponds to two digital cards (HSU320), and a large amount of data will be generated when performing calibration operation, and the data scale is as high as 32 bits x 640 channels, so a more efficient transmission mechanism must be used.

[0056] Therefore, in the design, a data interaction mechanism based on a first-in first-out memory (FIFO) is introduced to realize efficient return of a large amount of calibration data from the calibration field programmable gate array (CAL FPGA) to the intermediate field programmable gate array (MID FPGA). In the calibration field programmable gate array (CAL FPGA), a dedicated multi-channel transmission (MT) control module is designed, which divides each 32-bit calibration data into 8 sub-transmissions through internal state machine control, and transmits 4-bit data each time. Transmission is completed using the following signal lines:

[0057] Serial peripheral interface transmission control signal (SPI_TCT): transmission control signal (SPI_FCA in the calibration card main field programmable gate array (CT FPGA));

[0058] Serial peripheral interface data transmission line (SPI_DCT[3:0]): data transmission line (SPI_DCA[3:0] in the calibration card main field programmable gate array (CT FPGA));

[0059] Serial peripheral interface data read enable signal (SPI_FCT): data read enable signal (SPI_TCA in the calibration card main field programmable gate array (CT FPGA)), used to indicate that the target calibration data first-in first-out memory (MRCAL FIFO, FIFO1 to FIFO16) is not full and can receive data.

[0060] The above signals are used in cooperation to realize high-speed data writing from the calibration field programmable gate array (CAL FPGA) to the calibration card main field programmable gate array (CT FPGA) internal calibration data first-in first-out memory (MRCAL FIFO).

[0061] Subsequently, in order to further transmit the data back to the intermediate level field programmable gate array (MID FPGA) and upload to the host computer (PC end), the system selects the target calibration field programmable gate array (CAL FPGA) which needs to read data at present by controlling the CAL_SELECT register with address 0x0000_0904. The data transmission back is completed through the following general purpose input / output interface (GPIO port) signals:

[0062] Data write enable signal (RF_WEN, corresponding to general purpose input / output interface GPIO

[12] , SPI_TSC in the calibration board main field programmable gate array (CT FPGA)): data write enable signal; data write channel (RF_WEQ, corresponding to general purpose input / output interface GPIO

[15] , GPIO

[16] , GPIO

[19] , GPIO

[20] , SPI_DSC[3:0] in the calibration board main field programmable gate array (CT FPGA)): data write channel; system control module board card calibration data first-in-first-out memory not full indication signal (CT_REN, corresponding to general purpose input / output interface GPIO

[11] , SPI_FSC in the calibration board main field programmable gate array (CT FPGA)): calibration data first-in-first-out memory 0 (MRCAL FIFO0) not full indication signal in the system control module board card (SCM board card), used to inform the calibration board main field programmable gate array (CT FPGA) that the data can be sent to the intermediate level field programmable gate array (MID FPGA) at present.

[0063] After the calibration board main field programmable gate array (CT FPGA) receives the enable signal, it can read the calibration data from the calibration data first-in-first-out memory (MRCAL FIFO) of the selected calibration field programmable gate array (CAL FPGA), and transmit the data to the intermediate level field programmable gate array (MID FPGA) through the above-mentioned signal lines. Finally, these returned calibration data will be stored in the registers with addresses 0x0010_0000, 0x0010_0004, …, 0x0010_0280, etc. of the intermediate level field programmable gate array (MID FPGA) in turn. The host computer (PC end) can read out a large amount of calibration data in this area at one time through the peripheral component interconnect express (PCIe) interface, and perform subsequent analysis and processing.

[0064] 3. Finally, the IO port is multiplexed:

[0065] In combination with Figure 4 and Figure 5It can be known that the read and write operations of registers of field programmable gate arrays (FPGAs) at different levels can be realized by improving a serial peripheral interface (SPI) communication protocol. Specifically, when a PC end writes "CF" into a general input / output interface mode register (GPIO MODE register, address: 0x0000_067c) of a middle-level field programmable gate array (MID FPGA), a general input / output interface (GPIO port) will be switched to a configuration function: the general input / output interface GPIO

[11] is used as a first write valid signal (WF_VLD_SD); the general input / output interfaces GPIO

[15] , GPIO

[16] , GPIO

[19] and GPIO

[20] are used as first write data signals (WF_RDQ_SD[3:0]) for writing data into a second configuration and calibration first-in-first-out memory (CFCAL FIFO2) of a main field programmable gate array (CT FPGA) of a calibration board card, so as to complete the configuration of a calibration field programmable gate array (CAL FPGA); and the general input / output interface GPIO

[12] is used as a first read enable signal (WF_REN) for indicating that the CFCAL FIFO2 in the CT FPGA is empty, and data can be requested from a first configuration and calibration first-in-first-out memory (CFCAL FIFO1) of the MID FPGA.

[0066] If "CA" is written into the GPIO MODE register, the GPIO port is switched to a calibration function: at this time, the general input / output interface GPIO

[11] is used as a system control module card calibration data first-in-first-out memory not full indication signal (CT_REN) for indicating that a calibration data first-in-first-out memory 0 (MRCAL FIFO0) in the MID FPGA is empty, and data can be requested from calibration data first-in-first-out memories 1-15 (MRCAL FIFO1-15) of the CT FPGA; the general input / output interfaces GPIO

[15] , GPIO

[16] , GPIO

[19] and GPIO

[20] are used as data write channels (RF_WDQ[3:0]); and the general input / output interface GPIO

[12] is used as a data write enable signal (RF_REN), and the two signals work in cooperation to write calibration data into the MRCAL FIFO0 of the MID FPGA.

[0067] It can be seen that for the MID FPGA, the GPIO port is sometimes used as an output signal and sometimes used as an input signal, and a core component for controlling the input and output directions of the GPIO port is a general input / output interface direction register (GPIO DIRECTION register, address: 0x0000_0644): "1" is written into the register to indicate that the corresponding GPIO port is an output signal; and "0" is written into the register to indicate that the corresponding GPIO port is an input signal.

[0068] If no data is written to the GPIO MODE register, the GPIO port will be in the normal GPIO mode by default. At this time, the general input / output interface write data register (GPIO WDATA register, address 0x0000_0640) is used to control the output value of the GPIO port to be "1" or "0"; by reading the value of the general input / output interface read data register (GPIO RDATA register, address 0x0000_0648), the input value of the GPIO port can be obtained to be "1" or "0".

[0069] In addition, in order to ensure the consistency of communication and functional logic, the configuration of the mode selection register (MODE SELECT register, address 0x0000_091F) in the CT FPGA needs to be completely consistent with the configuration of the GPIO MODE register in the MID FPGA.

[0070] This mechanism fully utilizes the multiplexing capability of the GPIO port, greatly reduces the demand for independent signal lines, and can provide flexible and efficient data and control signal interaction capability in a system with tight input / output (IO) resources.

[0071] The above has carried out the detailed explanation to one embodiment of the application, but the content described is only the preferred embodiment of the application, cannot be considered for limiting the implementation scope of the application. All equivalent changes and improvements made according to the scope of the application should still belong to the scope of the application.

Claims

1. A design method based on multi-level FPGA communication of a tester, characterized in that, The method comprises the following steps: Set up card areas, and each card area is provided with a backboard and a motherboard; Each card area is provided with a preset number of digital cards and power supply cards matched with the digital cards, and the signals of the digital cards are inserted into the backboard and the motherboard of the corresponding card area; All the card areas are divided into two continuous areas, which are defined as a master area and a slave area; the card areas in the master area share a synchronous card with a CPU for synchronization, and the synchronous card is defined as a master; the card areas in the slave area share a synchronous card with a CPU for synchronization, and the synchronous card is defined as a slave; The general input / output interface on the master / slave is connected to an intermediate adapter board through the backboard, connected to the motherboard through the intermediate adapter board, connected to the interface card of the calibration card through a cable, and finally connected to the main field programmable gate array of the calibration card; The communication process in the configuration aspect is specifically as follows: The intermediate field programmable gate array on the master / slave exchanges data with the central processing unit through the high-speed serial computer expansion bus standard interface, and is internally provided with a plurality of registers; The host computer writes data to the register address, and the system extracts the low 8-bit data of the corresponding register and writes it into the first-in-first-out memory of the main field programmable gate array of the calibration card; Through the design of the serial configuration timing, the intermediate field programmable gate array outputs 1-bit configuration data signals, 1-bit configuration clock signals and 1-bit configuration programming signals, and transmits these signals to the main field programmable gate array of the calibration card; The main field programmable gate array of the calibration card outputs 1-bit configuration initialization signals and 1-bit configuration completion signals, and transmits them back to the intermediate field programmable gate array, completing all configurations.

2. The design method based on multi-level FPGA communication of a tester according to claim 1, characterized in that, The main field programmable gate array of the calibration card communicates with 16 calibration field programmable gate arrays, and each calibration field programmable gate array can calibrate the digital signals of 2 digital cards, and each digital card corresponds to 640 channels.

3. The design method based on multi-level FPGA communication of a tester according to claim 1, characterized in that, The master / slave provides a plurality of general input / output interfaces, and the general input / output interface resources are divided into two types of uses: Part of them is used for configuring the main field programmable gate array of the calibration card on the calibration card; The other part exchanges data with the first-in-first-out memory interface of the main field programmable gate array of the calibration card, and further distributes the data to the calibration field programmable gate array, so as to realize the configuration operation of the calibration field programmable gate array.

4. The design method based on multi-level FPGA communication of a tester according to claim 3, characterized in that, A register module for controlling the mode of the general input / output interface is designed on the control chip of the master / slave, so as to realize the multiplexing function of the input / output interface, which is specifically as follows: With the support of the input / output interface multiplexing mechanism, part of the general input / output interfaces are not only used for configuration operation, but also support improved serial peripheral interface communication function; The data of the digital board card is firstly transmitted to the calibration FPGA through the serial peripheral interface communication mode, the calibration FPGA interacts with the main FPGA of the calibration board card, and finally transmits the data back to the intermediate FPGA on the system host / slave through the multiplexed general input / output interface; Moreover, the intermediate FPGA uploads the data to the central processor through the high-speed serial computer expansion bus standard interface, and finally receives and processes the data by the upper computer, so as to complete the data interaction process of the whole multi-level FPGA.

5. The design method based on multi-level FPGA communication of a tester according to claim 1, characterized in that, The communication process in the calibration aspect is specifically as follows: The intermediate FPGA is internally integrated with a plurality of registers for register read / write operation between the intermediate FPGA and the main FPGA of the calibration board card; In the intermediate FPGA, an improved serial peripheral interface master module is instantiated, and in the improved serial peripheral interface master module, the intermediate FPGA performs shift processing on the content in the register and sends the content in a serial mode.

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