Data synchronization method based on 204B multi-chip asynchronous mode

Abstract

The invention discloses a data synchronization method based on a 204B multi-chip asynchronous mode, and belongs to the field of communication. For an ADC / DAC high-speed acquisition system which is connected through jesd204b and is integrated with a plurality of chips, sysref of a sample clock domain and a data sequence relation are packaged and solidified and then transferred to a frame clock domain, then unpacking and binding lmfc are carried out, and then error injection and retransmission are carried out, so that data synchronization among the chips is realized. According to the invention, the limitation that a sample clock and a frame clock need to have a deterministic relationship requirement is solved, and the synchronization of multiple pieces of data is realized by using the elastic buffer. For a high-speed acquisition system of a plurality of ADC / DAC connected by using jesd204b, the method enables the system to have greater flexibility, and brings beneficial effects in aspects of optimizing the capacity of the ADC / DAC and improving the bandwidth utilization rate.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a data synchronization method based on a multi-chip asynchronous mode using 204B. Background Technology

[0002] With the rapid development of information technology, signal bandwidth is increasing daily, and the sampling rate of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) is also constantly improving, leading to a surge in data throughput. The JESD204B has become a standard component in high-speed ADC / DAC products. As system performance requirements become increasingly demanding, using chip arrays to address system performance bottlenecks has become an effective approach.

[0003] Figure 1 This is a standard multi-chip data synchronization scheme based on 204b. In this scheme, the frame clock (a protocol-defined signal used for frame sequencing or monitoring frame alignment) and sample clock (a protocol-defined signal used to define intra-frame sampling boundaries) are generated by an external clock management chip, and their clock relationship is deterministic. The 204b protocol does not specify how sample clock data is transferred to the frame clock domain. The 204b protocol is a high-speed serial data link protocol used to connect converters (ADCs / DACs) and devices such as FPGAs and ASICs for gigabyte-level data transmission. Figure 1 As shown, the frame clock, sample clock, and device clock are in a down-clocking relationship, which can be handled by a frequency divider, thus ensuring that the relationship between these clocks is deterministic. The device clock is a protocol-defined signal, a master clock signal from which the device must generate its local clock, including device clocka, device clockb, device clockc, and device clockd. However, if the required relationship is not down-clocking but up-clocking, the frequency divider cannot handle it, and a circuit must be used to up-clock, which would lead to an uncertain relationship between the clocks. Summary of the Invention

[0004] The purpose of this invention is to provide a data synchronization method based on a 204B multi-chip asynchronous mode to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a data synchronization method based on a 204B multi-chip asynchronous mode, comprising the following steps: The system reference sysref and data of the sample clock domain are packaged and passed to the frame clock domain, then unpacked. The unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc on the tx side to achieve data sequence binding with the local multi-frame clock lmfc. When the tx end inserts an incorrect code into the data, it sends it to the rx end, triggering the resync signal on the rx end and causing the SYNC_B signal to become invalid. The tx client detected that the SYNC_B signal had failed and performed a resync operation based on the adjusted lmfc. The rx terminal outputs data based on the principle of elastic buffer and the local multi-frame clock lmfc of the logicclock clock domain.

[0006] In one implementation, the relative positional relationship between the unpacked system reference sysref and the data in the frame clock domain is maintained as it was in the sample clock domain before packing. The unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc, thus fixing the positions of the unpacked data and the local multi-frame clock lmfc.

[0007] In one implementation, the local multi-frame clocks (LMFCs) between the multiple chips are misaligned, but the data in the multiple chips and the delay of the local multi-frame clocks (LMFCs) are consistent; the data misalignment caused by the misalignment of the local multi-frame clocks (LMFCs) between the multiple chips is realigned using an elastic buffer at the RX end.

[0008] This invention provides a data synchronization method for multi-chip asynchronous mode based on the 204B. For high-speed acquisition systems integrating multiple ADC / DAC chips connected via the JESD204B, data synchronization between multiple chips is achieved by packaging and solidifying the sysref and data order relationship of the sample clock domain, transferring it to the frame clock domain, unpacking and binding it to the LMFC, and then injecting errors and retransmitting. This invention overcomes the limitation that the sample clock and frame clock need to have a deterministic relationship, and uses a flexible buffer to achieve multi-chip data synchronization. For high-speed acquisition systems using multiple ADC / DAC chips connected via the JESD204B, this method makes the system more flexible and has beneficial effects on optimizing chip ADC / DAC capacity and improving bandwidth utilization. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the principle of a traditional multi-chip solution.

[0010] Figure 2 This is a schematic diagram of the multi-chip solution provided by the present invention.

[0011] Figure 3 This is a diagram illustrating sysref and data passing through a domain.

[0012] Figure 4 This is a diagram illustrating the adjustment of LMFC after crossing the domain.

[0013] Figure 5 This is a schematic diagram showing the relationship between different chips' LMFCs after domain adjustment.

[0014] Figure 6 This is a diagram illustrating data synchronization across multiple chips on the RX terminal. Detailed Implementation

[0015] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the data synchronization method based on a 204B multi-chip asynchronous mode proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0016] Traditional methods require a deterministic clock relationship between the frame clock and the sample clock. This invention addresses... Figure 2 A proposed solution for multi-chip data synchronization when the clock relationship between the frame clock and the sample clock is uncertain.

[0017] Step 1: Pack the data into a domain, such as... Figure 3 As shown; Step 1.1, in the sample clock domain, at the tx end (Transmitter, i.e.) Figure 2 The top left corner) will pack the sysref (System Reference, a periodic, single, or "gap" periodic signal) and data together; Step 1.2: Unpack the data in the frame clock domain to obtain the sysref and data; Step 2: Use the unpacked sysref to adjust the LMFC (protocol-defined signal, local multi-frame clock, representing the chip's data transmission cycle, synchronized via sysref to achieve data synchronization between chips), such as... Figure 4 As shown; After unpacking, the relative positions of the sysref and data remain the same as before packing. The unpacked sysef is used to synchronize the LMFC, thus fixing the positions of the unpacked data and LMFC. Figure 5 As shown. The LMFCs between different TX terminals are not aligned, but the data latency within the chip and the LMFC latency are consistent, as... Figure 6 As shown. Data misalignment caused by LMFC misalignment between chips is addressed using the RX end (Receiver, i.e.) Figure 2 A flexible buffer (in the upper right corner) is used to resolve data alignment.

[0018] Step 3: The TX end sends incorrect data to the RX end, triggering the RX end's resync (resynchronization, controlling the SYNC_B signal to restart the entire connection) signal, thus disabling the SYNC_B signal. When the chip first starts working, this SYNC_B signal is invalid. The TX end sends a connection data stream to the RX end. After receiving confirmation, the RX end enables the SYNC_B signal, indicating that the TX end sees this signal as valid, and then sends the data to be transmitted. The SYNC_B signal is controlled by the receiving chip, indicating that the connection between the TX end and the RX end is complete and data transmission is possible. Step 4: The tx terminal detects that the SYNC_B signal has failed and performs resync processing based on the adjusted lmfc. Step 5: The RX terminal outputs data according to the elastic buffer principle and the logic clock (target clock) clock domain LMFC, such as... Figure 6 As shown; Step 5.1: The LMFC of multiple logic clock chips is controlled externally within the same clock domain; Traditional solutions impose deterministic requirements on the relationship between sample clock and frame clock in multi-chip JESD204B interconnection. On the other hand, the on-chip LMFC is synchronized by an external sysref, ensuring that the LMFCs of all chips in the entire system are synchronized. The relationship between data and LMFC is deterministic, achieving data synchronization between multiple chips.

[0019] This invention packages the sample clock domain's sysref and data, passes them to the frame clock domain via an asynchronous buffer, and then unpacks them. The unpacked sysref is used to synchronize the transport layer's LMFC (i.e., the LMFC on the TX side), thus binding the data sequence to the LMFC. When the TX side inserts an incorrect code into the data, it sends it to the RX side, triggering the RX side's resync signal, which disables the SYNC_B signal. The TX side detects the SYNC_B signal failure and re-establishes the link based on the new LMFC position. The 204b elastic buffer function achieves inter-chip data alignment.

[0020] The solution of this invention does not impose a deterministic requirement on the relationship between the sample clock and the frame clock in a multi-JESD204B interconnection. It does not require LMFC synchronization between chips. As long as the relationship between the sysref of the sample clock domain and the sampled data is fixed and bound to the LMFC of the frame clock, the flexible buffer at the RX end can be used to achieve data synchronization between multiple chips, thus avoiding the requirement for deterministic relationships between the sample clock and the frame clock.

[0021] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A data synchronization method based on 204B multi-chip asynchronous mode, characterized in that, Includes the following steps: The system reference sysref and data of the sample clock domain are packaged and passed to the frame clock domain, then unpacked. The unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc on the tx side to achieve data sequence binding with the local multi-frame clock lmfc. When the tx end inserts an incorrect code into the data, it sends it to the rx end, triggering the resync signal on the rx end and causing the SYNC_B signal to become invalid. The tx client detected that the SYNC_B signal had failed and performed a resync operation based on the adjusted lmfc. The rx terminal outputs data based on the principle of elastic buffer and the local multi-frame clock lmfc of the logicclock clock domain.

2. The data synchronization method based on 204B multi-chip asynchronous mode as described in claim 1, characterized in that, The relative positional relationship between the unpacked system reference sysref and the data in the frame clock domain is maintained as it was in the sample clock domain before packaging. The unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc, thus solidifying the positions of the unpacked data and the local multi-frame clock lmfc.

3. The data synchronization method based on 204B multi-chip asynchronous mode as described in claim 1, characterized in that, The local multi-frame clock LMFCs between the multiple chips are not aligned. The data delay in the multiple chips is consistent with the delay of the local multi-frame clock LMFCs. The data misalignment caused by the misalignment of the local multi-frame clock LMFCs between the multiple chips is realigned using the elastic buffer at the RX end.

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