A data synchronization method based on 204B multi-chip asynchronous mode

Abstract

The application discloses a kind of data synchronization methods based on 204B's multi-chip asynchronous mode, belong to communication field.For the high-speed acquisition system of integrated multiple chips ADC / DAC connected by jesd204b, the application is packaged and solidified sysref and data sequence relationship in sample clock clock domain, and then transferred to frame clock clock domain, and then unpacked and bound lmfc, and then retransmission of error correction is noted, to realize the data synchronization between multiple chips.The application solves the limitation that sample clock clock and frame clock clock need to have a certain relationship requirement, and uses flexible buffer to realize multi-chip data synchronization.For the high-speed acquisition system of multiple ADC / DAC connected by using jesd204b, this method makes the system more flexible, and brings beneficial effects in optimizing chip ADC / DAC capacity and improving bandwidth utilization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a data synchronization method based on 204B multi-chip asynchronous mode. BACKGROUND

[0002] With the rapid development of information technology, the signal bandwidth is increasingly wide, and the sampling rate of analog-to-digital conversion ADC / digital-to-analog conversion DAC is also continuously improved, resulting in a surge in data throughput. JESD204B becomes the standard of high-speed analog-to-digital conversion ADC / digital-to-analog conversion DAC products. With the increasing requirement of system performance, solving the system performance pain point through chip array has become an effective means.

[0003] Figure 1 It is a conventional 204b-based multi-chip data synchronization scheme. In the implementation of multi-chip data synchronization, the frame clock clock (a protocol-defined signal used for frame ordering or monitoring frame alignment) and the sample clock (a protocol-defined signal used to define the sample boundary within the frame) are generated by an external clock management chip, and the clock relationship is determined. The 204b protocol does not specify the transfer of sample clock data to the frame clock clock domain; wherein the 204b protocol is a high-speed serial data link protocol used for data transmission between converters (ADC / DAC) and FPGA, ASIC and other devices of several GB. Figure 1 As shown in the figure, the frame clock, the sample clock and the device clock are in a frequency reduction relationship, which can be handled by a frequency divider, so that the relationship of the three clocks is determined. The device clock is a protocol-defined signal and a master clock signal, and the device must generate a local clock from it, including device clocka, device clockb, device clockc and device clockd. However, if the relationship is not frequency reduction but frequency increase, the frequency divider cannot handle it, and a circuit is needed to increase the frequency, which will result in an uncertain relationship between the clocks. SUMMARY

[0004] The purpose of the present application is to provide a data synchronization method based on 204B multi-chip asynchronous mode to solve the problems in the background art.

[0005] To solve the above technical problems, the present application provides a data synchronization method based on 204B multi-chip asynchronous mode, comprising the following steps:

[0006] The system reference sysref and data in the sample clock clock domain are packaged and delivered to the frame clock clock domain, and then unpacked,

[0007] Synchronize the local multi-frame clock lmfc of the tx end with the unpacked system reference sysref, so as to realize the binding of the data sequence and the local multi-frame clock lmfc;

[0008] The tx end sends the data with the error code inserted to the rx end, triggers the resync signal of the rx end, and invalidates the SYNC_B signal;

[0009] The tx end monitors the invalidation of the SYNC_B signal, and performs resync processing according to the adjusted lmfc;

[0010] The rx end outputs data according to the elastic buffer principle and the local multi-frame clock lmfc in the logic clock clock domain.

[0011] In an embodiment, the relative position relationship between the unpacked system reference sysref and the data in the frame clock clock domain remains the relationship before packaging in the sample clock clock domain, the local multi-frame clock lmfc is synchronized with the unpacked system reference sysref, and the positions of the unpacked data and the local multi-frame clock lmfc are fixed.

[0012] In an embodiment, the local multi-frame clocks lmfc between the multiple chips are not aligned, and the delays of the data and the local multi-frame clocks lmfc in the multiple chips are consistent; the data misalignment caused by the misalignment of the local multi-frame clocks lmfc between the multiple chips is aligned by using the elastic buffer of the rx end.

[0013] The application provides a data synchronization method based on a 204B multi-chip asynchronous mode, which is used for a high-speed acquisition system of an integrated ADC / DAC with multiple chips connected through a jesd204b, realizes the data synchronization between multiple chips by fixing and packaging the sequence relationship between sysref and data in a sample clock clock domain, transferring the sequence relationship to a frame clock clock domain, unpacking and binding lmfc, and then retransmitting the error code, and solves the limitation of the requirement of a certain relationship between the sample clock and the frame clock. The elastic buffer is used to realize the data synchronization between multiple chips. For a high-speed acquisition system of multiple ADC / DACs connected through a jesd204b, the method makes the system more flexible, and is beneficial to optimizing the capacity of the chip ADC / DAC and improving the bandwidth utilization. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a traditional multi-chip scheme.

[0015] Figure 2Figure 1 is a schematic diagram of a multi-chip solution principle according to the present application.

[0016] Figure 3 Figure 2 is a schematic diagram of sysref and data over domain.

[0017] Figure 4 Figure 3 is a schematic diagram of adjusting lmfc after over domain.

[0018] Figure 5 Figure 4 is a schematic diagram of lmfc relationship of different chips after adjusting over domain.

[0019] Figure 6 Figure 5 is a schematic diagram of implementing data synchronization at rx end of multiple chips. DETAILED DESCRIPTION

[0020] The present application provides a multi-chip asynchronous mode data synchronization method based on 204B. The advantages and features of the present application will be more apparent from the following description in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0021] The traditional scheme requires certainty for the clock relationship of frame clock and sample clock. The present application provides a scheme for multi-chip data synchronization in the case of uncertainty for the clock relationship of frame clock and sample clock. Figure 2

[0022] Step 1, data packaging over domain, as shown in Figure 2. Figure 3

[0023] Step 1.1, in the sample clock clock domain, the tx end (Transmitter, the sending end, i.e. the upper left corner of Figure 1) packs sysref (System Reference, system reference, periodic, single or “gap” periodic signal) and data. Figure 2

[0024] Step 1.2, unpacking in the frame clock clock domain to obtain sysref and data.

[0025] Step 2, adjusting the lmfc (protocol-defined signal, local multi-frame clock, indicating the beat of chip data transmission, synchronized through sysref to realize inter-chip data synchronization) of the tx end with the unpacked sysref, as shown in Figure 3. Figure 4

[0026] ​​​​The relative position relationship between the unpacked sysref and data remains the same as before packing, the lmfc is synchronized with the unpacked sysref, and the position relationship between the unpacked data and the lmfc is fixed, as shown in Figure 5 The lmfc between different tx ends is not aligned, but the delay of data and the lmfc in the chip is consistent, as shown in Figure 6 The data misalignment caused by the lmfc misalignment between chips is solved by using the elastic buffer of the rx end (Receiver, receiving end, i.e. Figure 2 The upper right corner).

[0027] Step 3, the tx end sends error data to the rx end to trigger the resync (re-synchronization, control SYNC_B signal, restart the whole link) signal of the rx end, so that the SYNC_B signal is invalid; when the chip just starts to work, the SYNC_B signal is invalid, the tx end will send the connection data stream to the rx end, and the rx end will set the SYNC_B signal valid after receiving the confirmation, indicating that the tx end sees the signal valid, and then sends the data to be transmitted; wherein the SYNC_B signal is controlled by the receiving end chip, indicating that the connection between the tx end and the rx end is completed, and the data can be transmitted;

[0028] Step 4, the tx end monitors the SYNC_B signal invalid, and performs resync processing according to the adjusted lmfc;

[0029] Step 5, the rx end outputs data according to the elastic buffer principle and the logicclock (target clock) clock domain lmfc, as shown in Figure 6

[0030] Step 5.1: The lmfc of multiple logicclocks is controlled by an external clock in the same clock domain;

[0031] The traditional scheme has a deterministic requirement for the relationship between the sample clock and the frame clock in the multi-chip jesd204b connection. The lmfc in the chip is synchronized with the sysref outside the chip, which ensures that the lmfc of the whole system chip is synchronized, and the relationship between the data and the lmfc is determined, so as to realize the data synchronization between multiple chips.

[0032] ​The sysref and data of the sample clock clock domain are packaged and transmitted to the frame clock clock domain through an asynchronous buffer, and then unpacked, the unpacked sysref is used to synchronize the transport layer lmfc (i.e. the lmfc of the tx end), the data sequence and the lmfc are bound, the tx end sends the data with error codes inserted to the rx end, the resync signal of the rx end is triggered to make the SYNC_B signal invalid, the tx end monitors the invalidation of the SYNC_B signal, reestablishes the link according to the position of the new lmfc, and the elastic buffer function of the 204b realizes the data alignment between chips.

[0033] The scheme of the application does not have the limitation of the determinacy requirement of the relationship between the sample clock and the frame clock in the multi-chip connection of the jesda204b, does not require the inter-chip lmfc synchronization, as long as the relationship between the sysref of the sample clock clock domain and the sampling data is fixed and bound with the lmfc of the frame clock, the elastic buffer of the rx end is used to realize the data synchronization between the multi-chips, and the limitation of the requirement of the determinacy between the sample clock and the frame clock is avoided.

[0034] The above description is only the description of the preferred embodiments of the application, and does not limit the scope of the application, any change and modification of the application by the ordinary skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for data synchronization in a 204B-based multi-chip asynchronous mode, characterized in that, The method comprises the following steps: The system reference sysref and data in the sample clock clock domain are packaged and transmitted to the frame clock clock domain for unpacking, The unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc at the tx end, so that the data sequence and the local multi-frame clock lmfc are bound; The tx end inserts an error code into the data and sends the data to the rx end, so as to trigger the resync signal of the rx end and disable the SYNC_B signal; The tx end monitors the disabled SYNC_B signal, and performs resync processing according to the adjusted lmfc; The rx end outputs data according to the elastic buffer principle and the local multi-frame clock lmfc in the logic clock clock domain; The relative position relationship between the unpacked system reference sysref and data in the frame clock clock domain remains the same as that in the sample clock clock domain before packaging, the unpacked system reference sysref is used to synchronize the local multi-frame clock lmfc, and the positions of the unpacked data and the local multi-frame clock lmfc are fixed; The local multi-frame clocks lmfc between the multiple chips are not aligned, the delay of the data in the multiple chips and the delay of the local multi-frame clock lmfc are consistent, and the data misalignment caused by the misalignment of the local multi-frame clocks lmfc between the multiple chips is aligned by the elastic buffer at the rx end.

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