Memory pool device fusing extended network and management method

Abstract

The invention discloses a memory pool device fusing an extended network and a management method, and the device comprises a super network card chip which is in communication connection with an intelligent computing cluster network through a network port, and provides a shared memory service for the intelligent computing cluster network based on a remote direct memory access protocol; the intelligent computing cluster network comprises a transverse expansion network and a longitudinal expansion network; the central controller is connected with the super network card chip; the CXL memory unit is connected with the super network card chip, and the FPGA expansion unit and / or the XPU expansion unit are / is connected with the super network card chip. According to the invention, through efficient communication between the super network card chip and the intelligent computing cluster networking, flexible scheduling and sharing of memory resources in the cluster are realized. Wherein the super network card chip is used as a core component, not only is responsible for communication of a transverse expansion network, but also realizes bridging access of a high-bandwidth domain of a longitudinal expansion network, so that the data transmission efficiency and the memory utilization rate can be improved, and high-bandwidth and low-delay data transmission and sharing are realized.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a memory pool device and management method for an integrated extended network. Background Technology

[0002] In the current data center field, network architectures can be broadly categorized into two types based on the types of tasks they support. One type is the general computing network, also known as the traditional data center network, which primarily serves traditional computing tasks and applications, such as enterprise IT systems, website hosting, and email services. The other type is the intelligent computing network, specifically designed to support artificial intelligence (AI) and machine learning (ML) tasks. This type of network has higher requirements for computing power and latency to process massive amounts of data and perform complex computational operations.

[0003] Within the intelligent computing network, there are two key networks. One is a network that enables RDMA (Remote Direct Memory Access) between XPUs / GPUs via Ethernet (or InfiniBand), often referred to as the Scale Out network. The other is a high-speed interconnect network between XPUs / GPUs that enables memory read and write operations across GPUs within the intelligent computing cluster, often referred to as the Scale Up network.

[0004] However, in existing computer systems, memory expansion schemes (such as CXL based on the PCIe bus) and distributed caching (such as Key-Value Cache based on RDMA) belong to different software technology stacks, lacking a unified architecture. Furthermore, the current Scale-Up and Scale-Out networks have certain limitations; they require significant XPU / GPU hardware resources for communication processing, such as moving data between the two networks, and handling protocol and control plane processing in RDMA networks, memory management of data chunking, data reduction operations, and data type conversions.

[0005] Furthermore, in the era of artificial intelligence, MoE (Mixture of Experts) models, represented by DeepSeek, have rapidly emerged. These models possess a larger number of experts, enabling them to handle more complex and diverse tasks, and bringing significant performance improvements to numerous applications such as natural language processing and image recognition. However, the separation of Prefill and Decode in the inference phase of MoE models poses unprecedented challenges to network architecture. Prefill nodes require a large amount of data transmission, thus relying on greater network bandwidth to ensure rapid data acquisition; while Decode nodes have extremely high real-time requirements, needing lower network latency to ensure timely responses. Faced with these stringent demands, traditional scale-out networks prove inadequate and struggle to meet the needs of efficient MoE model operation. Summary of the Invention

[0006] This invention provides a memory pool device and management method for a converged extended network, aiming to achieve high-bandwidth, low-latency data transmission and sharing.

[0007] This invention provides a memory pool device for merging extended networks, comprising:

[0008] A super network interface card (NIC) chip, which communicates with the intelligent computing cluster network through a network port and provides shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol (RDP); wherein, the intelligent computing cluster network includes a horizontally expandable network and a vertically expandable network.

[0009] The central controller is connected to the super network card chip;

[0010] The CXL memory unit is connected to the super network card chip;

[0011] An FPGA expansion unit and / or an XPU expansion unit are connected to the super network card chip.

[0012] Furthermore, the super network interface card chip communicates with the horizontally expanded network through the network port of the leaf layer switch.

[0013] Furthermore, the super network card chip communicates with the high-bandwidth domain port of the vertically extended network via a network port.

[0014] Furthermore, the super network card chip communicates with the high-bandwidth domain port of the vertically extended network through an FPGA expansion unit and / or an XPU expansion unit.

[0015] Furthermore, when the super network card chip communicates with the horizontally expandable network, it uses a Key-ValueCache high-speed cache pool to provide shared memory services to the intelligent computing cluster network.

[0016] Furthermore, when the super network card chip communicates with the vertically extended network, it uses Ethernet protocol or proprietary protocol to provide shared memory services to the intelligent computing cluster network.

[0017] Furthermore, when the super network card chip is connected to the vertically extended network, the FPGA expansion unit or XPU expansion unit is a node in the high-frequency bandwidth network.

[0018] This invention also provides a memory pool management method for converged extended networks, applied to the memory pool apparatus of the converged extended network as described in any of the preceding embodiments, the method comprising:

[0019] Based on the super network card chip, it connects to the intelligent computing cluster network through the network port and provides shared memory services to the intelligent computing cluster network based on the remote direct memory access protocol.

[0020] Furthermore, the step of establishing a network communication connection with the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access protocol includes:

[0021] A key-value cache pool is used to provide shared memory services to the intelligent computing cluster network.

[0022] Furthermore, the step of connecting to the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol also includes:

[0023] The system uses Ethernet or proprietary protocols to provide shared memory services to the intelligent computing cluster network, and supports the memory semantics of proprietary protocols to provide shared memory services to the vertically scaled network.

[0024] This invention provides a memory pool device and management method for a converged extended network. Through efficient communication between a super network interface card (NIC) chip and an intelligent computing cluster network, it achieves flexible scheduling and sharing of memory resources within the cluster. The super NIC chip, as a core component, is responsible not only for horizontal network communication but also for bridging access to the high-bandwidth domain of the vertical network. Based on proprietary protocol memory access semantics, it provides shared content services and shared memory services based on Remote Direct Memory Access (RDMA), thus significantly improving data transmission efficiency and memory utilization. Furthermore, the central controller in this embodiment monitors and manages the entire memory pool device's operational status, ensuring its stability and reliability. The central controller, connected to the super NIC chip, dynamically allocates and reclaims memory resources through precise control commands. The CXL memory unit provides high-performance, low-latency memory access capabilities. Its connection to the super NIC chip enables memory resources to cross network boundaries, achieving unified scheduling and efficient access across memory levels. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of the architecture of a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0027] Figure 2 A diagram of the network architecture of existing technologies;

[0028] Figure 3 This is another network architecture diagram of existing technology;

[0029] Figure 4 This is a schematic diagram of the first network connection of a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the second network connection of a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of a third network connection for a memory pool device with a converged extended network provided in an embodiment of the present invention;

[0032] Figure 7 A fourth network connection diagram of a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0033] Figure 8 A schematic diagram of memory sharing in a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0034] Figure 9 A policy routing diagram of a memory pool device for a converged extended network provided in an embodiment of the present invention;

[0035] Figure 10 This is an application example diagram of a memory pool device for a converged extended network provided in an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0038] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0039] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0040] Please see below. Figure 1 This invention provides a memory pool device for merging extended networks, comprising:

[0041] A super network interface card (NIC) chip, which communicates with the intelligent computing cluster network through a network port and provides shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol (RDP); wherein, the intelligent computing cluster network includes a horizontally expandable network and a vertically expandable network.

[0042] The central controller is connected to the super network card chip;

[0043] The CXL memory unit is connected to the super network card chip;

[0044] An FPGA expansion unit and / or an XPU expansion unit are connected to the super network card chip.

[0045] This embodiment achieves flexible scheduling and sharing of memory resources within the cluster through efficient communication between the super network interface card (NIC) chip and the intelligent computing cluster network. The super NIC chip, as the core component, is responsible not only for horizontally scaling network communication but also for bridging access to the high-bandwidth domain of the vertically scaling network. It provides shared content services based on proprietary protocol memory access semantics and shared memory services based on Remote Direct Memory Access (RDMA), thus significantly improving data transmission efficiency and memory utilization. Furthermore, the central controller in this embodiment can monitor and manage the operational status of the entire memory pool device, ensuring its stability and reliability. The central controller, connected to the super NIC chip, enables dynamic allocation and reclamation of memory resources through precise control commands. The CXL memory unit provides high-performance, low-latency memory access capabilities. Its connection with the super NIC chip allows memory resources to cross network boundaries, achieving unified scheduling and efficient access across memory levels.

[0046] It's important to note that CXL (Compute Express Link) technology is a new type of high-speed interconnect technology designed to provide higher data throughput and lower latency to meet the needs of modern computing and storage systems. The background of CXL technology can be traced back to PCIe (Peripheral Component Interconnect Express) technology, a standard interface technology used to connect internal computer components. PCIe devices can initiate a DMA to access memory, provided the target physical address is known. The CXL.mem mode in the CXL protocol allows external devices to be used as main memory, thereby achieving larger memory capacity. This mode allows external devices to be treated as extended memory, thus storing more data and improving system reliability; that is, even if a memory failure occurs, the CPU can still continue to run through the external device. Furthermore, as... Figure 1 As shown, the super network card chip can also be connected to an Ethernet switch via an Ethernet interface, and to a computer via interfaces such as PCIe.

[0047] Currently, there are two solutions for memory pool expansion devices based on CXL. One is through the CXL switch chip, using PCIe interfaces and protocols for interconnection. This solution belongs to the scale-up vertical expansion network, such as... Figure 2As shown; the second is interconnection via Ethernet using the RDMA protocol. This solution belongs to the scale-out horizontal scaling network, such as... Figure 3 As shown.

[0048] To address this, this embodiment employs a novel SuperNIC chip to design a complete device. This device simultaneously supports Ethernet and PCIe interfaces, and through a built-in dedicated module (FPGA or customized XPU card), it supports various dedicated Scale-Up interface protocols (including but not limited to UALink, SUE, etc.). This embodiment optimizes network transmission paths to construct a novel Scale-Up and Scale-Out network convergence architecture, meeting the urgent needs of multi-XPU (including GPU, CPU, etc.) systems in AI, ML, and HPC fields for high-bandwidth, low-latency data transmission and sharing.

[0049] Furthermore, this embodiment enhances the flexibility and scalability of the memory pool device by incorporating FPGA expansion units and XPU expansion units. The FPGA expansion unit, as a programmable logic device, can be flexibly configured according to different application scenarios to achieve efficient data processing and memory expansion functions. The XPU expansion unit, on the other hand, is optimized for specific computing tasks, providing powerful computing capabilities and memory access speeds to meet the needs of high-performance computing scenarios such as AI and ML.

[0050] In practical applications, FPGA expansion units and XPU expansion units can work together according to actual needs to achieve dynamic allocation and efficient utilization of memory resources. For example, during the training of AI models, a large amount of data needs to be transferred and shared between different XPUs. At this time, FPGA expansion units can leverage their flexible configuration advantages to optimize data transmission paths and improve data transmission efficiency. Meanwhile, XPU expansion units can provide high-performance computing capabilities, accelerating the AI ​​model training process.

[0051] Furthermore, the FPGA expansion unit and / or XPU expansion unit in this embodiment can also efficiently collaborate with the super network interface card (NIC) chip to achieve remote sharing and access to memory resources. The super NIC chip, as a core component, is responsible not only for network communication but also provides shared memory services based on the Remote Direct Memory Access (RDMA) protocol. The FPGA expansion unit and / or XPU expansion unit, through their connection to the super NIC chip, can extend local memory resources to remote nodes, enabling flexible scheduling and sharing of memory resources. This not only improves memory resource utilization but also reduces data transmission latency, enhancing the overall system performance.

[0052] In one embodiment, such as Figure 4As shown, the super network card chip communicates with the horizontally expanded network through the network port of the leaf layer switch.

[0053] In this embodiment, the memory pool device is connected to the Scale Out network through a network port, which is generally a leaf layer switch port, thus enabling interconnection bandwidth of 8×400G or 4×800G or more, totaling 3.2T bps or even higher.

[0054] In a specific embodiment, when the super network card chip communicates with the horizontally expandable network, it uses a key-value cache high-speed cache pool to provide shared memory services to the intelligent computing cluster network.

[0055] This embodiment is based on the RDMA protocol and uses a Key-Value Cache high-speed cache pool to provide shared memory services to server nodes in the intelligent computing cluster.

[0056] like Figure 6 As shown, in practical applications, the host (and GPU) accesses the external network (read / write) via the network interface card (NIC) and RDMA protocol. Uplink and downlink data are forwarded through a leaf switch, then through the Ethernet access network port of the memory pool device (SuperNIC 400 / 800G port). Through internal address translation (pre-configured by the controller), the SuperNIC forwards the corresponding memory access request to the corresponding CXL controller and the corresponding CXL.mem device, and accesses the memory in real time according to the translated address. The results of the read / write access are returned to the host (GPU) via the SuperNIC and Ethernet back to the original source.

[0057] In a specific embodiment, such as Figure 9As shown, the steps for providing shared memory services to server nodes in the intelligent computing cluster using the Key-Value Cache (KV-Cache) are as follows: ① The large model application (Application) accesses the KV-Cache (Key-Value Cache) via an API interface; ② The KV-Cache local service creates or retrieves an Index based on the Key value from the API call, obtains the corresponding data buffer, and performs data read / write operations; ③ Data block read / write I / O is performed via the RDMA protocol stack to access the corresponding remote address on the server; ④ RDMA read / write operations are implemented via network access through the driver and network interface card (NIC); ⑤ The server-side SuperNIC provides an external Ethernet access path; ⑥ The data buffer corresponding to the RDMA write operation is temporarily stored in the virtual queue; ⑦ The RDMA protocol stack in the central controller CPU parses the RDMA instructions and forwards them to the Key index module; ⑧ Key... The Index module is responsible for key indexing, translating the corresponding RDMA address into a local physical address; the CXL memory management module resolves memory physical address access requests to the CXL device address; the controller writes (or reads) data buffer blocks in the queue to the CXL.mem device based on the obtained CXL device address; after completing the operation, the controller generates corresponding event instructions or read data buffers based on the operation results according to the controller configuration. The read data buffer is temporarily stored in the egress virtual queue. The generated event or operation result is converted into a specific response result by the RDMA protocol stack; The return response of an RDMA write operation, or the data buffer corresponding to a read operation, is returned to the Client in the format of an RDMA packet. The client-side RDMA protocol stack processes the returned response and writes data to the local memory address. At this point, the data cache buffer completes the read / write update. It should be noted that data consistency in this distributed system is maintained and guaranteed by dedicated application-layer protocols and algorithms, and is not reflected in this process.

[0058] In one embodiment, such as Figure 5 As shown, the super network card chip communicates with the high-bandwidth domain port of the vertically extended network through a network port;

[0059] Alternatively, the super network card chip can communicate with the high-bandwidth domain port of the vertically extended network via an FPGA expansion unit and / or an XPU expansion unit.

[0060] In this embodiment, when connecting to the Scale Up network, the corresponding HBD (High Bandwidth Domain) network uses an Ethernet network. The memory pool device is connected to the HBD Ethernet switch port through a network port or an FPGA expansion unit or XPU expansion unit, thus achieving an interconnect bandwidth of 3.2T bps or even higher.

[0061] In a specific embodiment, when the super network interface card chip communicates with the vertically extended network, it uses Ethernet protocol or proprietary protocol to provide shared memory services to the intelligent computing cluster network.

[0062] This embodiment is based on Ethernet protocols (e.g., ETH-X, Broadcom SUE, custom X-LINK, etc.), supports memory semantics, and directly provides memory load / store services to the XPUs of the intelligent computing cluster server nodes.

[0063] like Figure 7 As shown, in practical applications, the host (and GPU) remotely accesses memory by connecting to the HBD domain through the GPU's high-speed interconnect interface. Uplink and downlink data are forwarded via an HBD switch (based on an Ethernet solution, such as SUE), and then via Ethernet to access the network port of the memory pool device (SuperNIC 400 / 800G port). The communication protocol here is not RDMA, but a dedicated high-speed interconnect protocol, such as SUE or ETH-X. Through internal address translation (pre-configured by the controller), SuperNIC translates the corresponding memory semantics (Load / Store, etc.) requests into basic memory instructions and forwards them to the corresponding CXL controller and the corresponding CXL.mem device, accessing the memory in real time according to the translated address. The results of read and write access are returned to the host (GPU) via SuperNIC and the dedicated high-speed protocol.

[0064] Furthermore, when the super network card chip is connected to the vertically extended network, the FPGA expansion unit or XPU expansion unit is a node in the high-frequency bandwidth network.

[0065] When connecting to a Scale Up network, the dedicated HBD network corresponding to the Scale Up network uses a dedicated protocol (e.g., NVLink, UALink, or various custom X-Links).

[0066] The memory pool device, via an FPGA expansion card or a dedicated XPU ASIC, serves as a node in the HBD (High Bandwidth Domain) networking fabric, supporting specific XPU private interconnection methods. Each expansion card can achieve bandwidth of 400G or even higher. Furthermore, this embodiment, based on proprietary protocols (e.g., UALink, custom X-Link, etc.), supports memory semantics, directly providing memory load / store services to the XPUs of the intelligent computing cluster server nodes.

[0067] like Figure 8 As shown, in practical applications, the host (and GPU) remotely accesses memory via the GPU's high-speed interconnect interface and connects to the HBD domain. Uplink and downlink data are forwarded through the HBD Fabric (a privately defined network such as Mesh / Torus). Dedicated high-speed interconnect protocols, such as UALink and X-Link, are used here. The FPGA card (or XPU chip) converts the dedicated protocol into internal memory access requests. The target of memory access can be DDR memory, HBM memory on the FPGA card, or other CXL memory devices connected to the SuperNIC. The results of read / write access are returned to the host (GPU) via the FPGA / XPU and the dedicated high-speed protocol.

[0068] It should be noted that when networking the intelligent computing cluster, this device deploys the above-mentioned components simultaneously. It can connect to both the Scale Out and Scale Up networks entering the cluster at the same time, achieving unified memory expansion, supporting basic memory swapping functions, and also supporting policy-based routing (memory load balancing). The dedicated network communication coprocessor is implemented through a SuperNIC chip.

[0069] In a specific embodiment, such as Figure 9 As shown, the specific process of policy routing is as follows:

[0070] (1) When the host-side XPU / GPU needs to access data in the Key-Value Cache, it can do so either through the Scale-Out network (following the paths ①②③④⑤⑥⑦ in the diagram) or through the Scale-Up dedicated high-bandwidth network (①⑧⑨⑩ in the diagram). ⑦ Sequential Paths). The optimal access path can be selected based on the parallel algorithm strategy, the access latency and bandwidth of different paths, and either pre-configuration or dynamic algorithms.

[0071] Pre-configured algorithms refer to explicitly specifying the access path of the Key-Value Cache in the current computing task;

[0072] Dynamic algorithms refer to:

[0073] (a) In a Scale-Out network, there are multipath paths between the RDMA network, the NIC and the Ethernet switch (③④⑤). It is necessary to maintain the RTT latency and bandwidth utilization data of each path in real time in the Key Index of the Client and Server, and calculate the access cost. In addition, the network data packets adopt a load balancing strategy based on RDMA queues. When an access request is generated, the corresponding RDMA queue is selected and sent according to the principle of minimum cost.

[0074] (b) In a scale-up network, a routing strategy is calculated using a dedicated high-bandwidth network and the corresponding FPGA / XPU card. Simultaneously, the bandwidth utilization and task queuing length of the current path are calculated in real time, and the access cost is also calculated.

[0075] The host-side XPU / GPU comprehensively considers the access costs of (a) and (b) and dynamically selects the optimal Scale-Out or Scale-Up route.

[0076] like Figure 10 As shown, in practical applications, a 32-GPU extended-CXL memory pool and extended shared system is built based on the memory pool device. Each GPU node is connected to the SuperNIC via a Leaf switch, and memory sharing and high-speed access between GPU nodes are achieved through the RDMA protocol stack. The SuperNIC within the system, based on the RDMA protocol, constructs a Key-Value Cache high-speed cache pool to provide shared memory services for the GPU nodes in the cluster. Simultaneously, the system also supports dedicated high-speed interconnection between GPU nodes through the HBD (High Bandwidth Domain), further improving data transmission efficiency and memory access speed.

[0077] In summary, this embodiment proposes a memory pool device that supports the fusion of scale-up and scale-out, and this memory pool device has the following characteristics:

[0078] (1) Based on the SuperNIC chip design, the latency of moving memory data between the Scale Up and Scale Out networks can be reduced, and the transmission bandwidth and efficiency can be greatly improved.

[0079] (2) It provides memory sharing and efficient communication methods for XPUs in intra-node Scale Up networks and inter-node Scale Out networks; it does not require the main control CPU to participate in DMA transfer, reducing the communication transmission latency of data sharing between XPUs;

[0080] (3) Through the built-in module (FPGA expansion card or dedicated XPU ASIC), it serves as a node of the HBD (High Bandwidth Domain) networking Fabric, enabling support for specific XPU private interconnection methods, with each expansion card achieving 400G or even higher bandwidth;

[0081] (4) Through the central controller (CPU), deploy unified protocol software, based on the RDMA protocol, and use the Key-ValueCache high-speed cache pool to provide shared memory services to the server nodes in the intelligent computing cluster; the memory uses unified PGAS global addressing to realize the consistency check of the entire intelligent computing cluster access to the memory pool.

[0082] (5) Expand HBM memory and on-card DDR memory resources through FPGA. All these memories are uniformly included in memory management and globally addressed.

[0083] This invention also provides a memory pool management method for converged extended networks, applied to the memory pool device of the converged extended network described above, characterized in that the method includes:

[0084] Based on the super network card chip, it connects to the intelligent computing cluster network through the network port and provides shared memory services to the intelligent computing cluster network based on the remote direct memory access protocol.

[0085] In one embodiment, the step of establishing a network communication connection with the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access protocol includes:

[0086] A key-value cache pool is used to provide shared memory services to the intelligent computing cluster network.

[0087] In one embodiment, the step of establishing a network communication connection with the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol further includes:

[0088] The intelligent computing cluster network is provided with shared memory services using Ethernet protocol or proprietary protocol.

[0089] Since the embodiments of the method section correspond to the embodiments of the apparatus section, please refer to the description of the embodiments of the apparatus section for the embodiments of the method section, and they will not be repeated here.

[0090] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0091] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A memory pool device for merging extended networks, characterized in that, include: A super network interface card (NIC) chip, which communicates with the intelligent computing cluster network through a network port and provides shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol (RDP); wherein, the intelligent computing cluster network includes a horizontally expandable network and a vertically expandable network. The central controller is connected to the super network card chip; The CXL memory unit is connected to the super network card chip; An FPGA expansion unit and / or an XPU expansion unit are connected to the super network card chip.

2. The memory pool device for the converged extended network according to claim 1, characterized in that, The super network card chip communicates with the horizontally expanded network through the network port of the leaf layer switch.

3. The memory pool device for the converged extended network according to claim 1, characterized in that, The super network card chip communicates with the high-bandwidth domain port of the vertically extended network through the network port.

4. The memory pool device for the converged extended network according to claim 1, characterized in that, The super network card chip communicates with the high-bandwidth domain port of the vertically extended network through an FPGA expansion unit and / or an XPU expansion unit.

5. The memory pool device for the converged extended network according to claim 1, characterized in that, When the super network card chip communicates with the horizontally expandable network, it uses a key-value cache high-speed cache pool to provide shared memory services to the intelligent computing cluster network.

6. The memory pool device for the converged extended network according to claim 1, characterized in that, When the super network card chip communicates with the vertically extended network, it uses Ethernet protocol or proprietary protocol to provide shared memory services to the intelligent computing cluster network.

7. The memory pool device for the converged extended network according to claim 4, characterized in that, When the super network card chip is connected to the vertically extended network, the FPGA expansion unit or XPU expansion unit is a node in the high-frequency bandwidth network.

8. A memory pool management method for a converged extended network, applied to the memory pool apparatus for a converged extended network as described in any one of claims 1-7, characterized in that, The method includes: Based on the super network card chip, it connects to the intelligent computing cluster network through the network port and provides shared memory services to the intelligent computing cluster network based on the remote direct memory access protocol.

9. The memory pool management method for converged extended networks according to claim 8, characterized in that, The process of establishing a network communication connection with the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol includes: A key-value cache pool is used to provide shared memory services to the intelligent computing cluster network.

10. The memory pool management method for a converged extended network according to claim 8, characterized in that, The method of connecting to the intelligent computing cluster network via a network port and providing shared memory services to the intelligent computing cluster network based on the Remote Direct Memory Access Protocol also includes: The system uses Ethernet or proprietary protocols to provide shared memory services to the intelligent computing cluster network, and supports the memory semantics of proprietary protocols to provide shared memory services to the vertically scaled network.

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