Hybrid dimension protection structure generation method and device facing multiple physical attacks

Abstract

The invention discloses a mixed dimension protection structure generation method and device oriented to multiple physical attacks, and the method comprises the steps: dispersing a to-be-protected region of a chip into grids, dividing the to-be-protected region into a key region, a single-layer region and an obstacle region, and recording the corresponding partition attributes and layer domain marks of each grid; each area of each layer takes a grid point as fish and a plurality of initial random Hamiltonian paths as an artificial fish swarm, and an artificial fish swarm algorithm is independently operated to form a complete rewiring path of the to-be-protected area; using an enhanced greedy algorithm to select candidate points capable of maximizing the interlayer synergistic effect as through hole positions, and setting corresponding through holes; calculating a direction entropy and a through hole distribution entropy, judging whether the shielding quality is qualified or not according to the direction entropy and the through hole distribution entropy, and returning to the above steps for iterative adjustment until the shielding quality is qualified under the condition that the shielding quality is unqualified; the method has the advantage that the balance requirement of chip safety and resource efficiency is met.

Description

Technical Field

[0001] This invention relates to the field of hardware security, specifically to a method and apparatus for generating hybrid-dimensional protection structures against multiple physical attacks. Background Technology

[0002] With the widespread application of integrated circuits in critical fields such as aerospace, financial payments, military equipment, and key infrastructure, the physical security of chips is becoming increasingly prominent. Malicious attackers can obtain sensitive information inside chips through physical means, threatening data security and system integrity. For example, attackers can launch invasive attacks on encrypted memory, monitoring the microprocessor's data bus with microprobes and successfully obtaining all the stored data in the memory. Such attacks can bypass software-level security measures and directly steal or tamper with information at the hardware level, posing a serious threat to information systems. Therefore, developing efficient hardware physical security protection technologies, especially protection mechanisms capable of resisting various advanced physical attacks, is of great significance for ensuring the security of critical chips.

[0003] Physical attacks targeting integrated circuits are mainly divided into two categories: invasive and non-invasive. Non-invasive attacks primarily utilize side-channel analysis to steal critical data by analyzing information such as power consumption, electromagnetic radiation, and setup time generated during operation, without damaging the physical structure of the device, and then relating this information to the algorithm key. Invasive attacks, on the other hand, require depackaging the chip first, and then using techniques such as reverse engineering, microprobes, and focused ion beam (FIB) to obtain chip layout information or modify chip traces. Among these, rewiring attacks are an advanced invasive attack technique, such as... Figure 1 As shown, attackers create an operational space by precisely cutting the metal shielding wire above the target area, identifying and extracting key signals, and then using the FIB's metal deposition function to reconnect the severed shielding wire, thereby monitoring internal signals without triggering an alarm. Another threat is a high aspect ratio tilted FIB attack, such as... Figure 2 As shown, by precisely controlling the tilt angle (θ) and rotation angle (φ) of the FIB milling, attackers can exploit the weaknesses in the shielding layer wiring geometry in three-dimensional space to create deep and narrow microchannels directly to the lower layer signal lines carrying sensitive information without cutting the top layer shielding. At a specific tilt angle θ, the critical cut width required to cut the shielding reaches its minimum, significantly increasing the likelihood of an attack successfully circumventing a single layer of shielding.

[0004] Active shields are currently the primary technology for defending against invasive attacks. They utilize a specially designed metal network deployed on the top layer of the chip to monitor and respond to physical intrusions in real time. Their basic working principle includes a signal generator producing a random or preset test signal sequence; a metal shielding network covering the sensitive circuitry; a signal detection circuit monitoring for changes in the signal passing through the shielding network; and a response mechanism triggering protective measures when an anomaly is detected. With the development of protection technology, the concept of a double-layer shielding structure has been proposed to enhance protection capabilities. For example... Figure 3 As shown, the double-layer shielding structure utilizes both the top and second-to-top metal layers as wiring layers. Metal wires randomly interweave between the top and second-to-top layers, forming a highly complex double-layer, fully random wiring network. For tilted FIB attacks, the double-layer shielding structure creates a three-dimensional protection network through a three-dimensional barrier effect. The upper metal wires are typically wider, and the FIB and the double-layer shielding wires must each maintain a safety margin, imposing more stringent requirements on the tilt angle. Strategically placed interlayer vias further increase the attack complexity. For rewiring attacks, the double-layer shielding structure uses interlayer dependency to tightly couple the two shielding layers through vias, making it difficult for attackers to modify either layer while maintaining electrical integrity. The cross-validation mechanism sets up a complex signal exchange pattern between the two layers; any modification to a single layer will result in cross-validation failure.

[0005] Existing research on active shielding layers mainly focuses on two aspects: optimization of shielding layer topology and improvement of wiring algorithms. The paper by Feng T et al., "Ting Feng, Kenli Li, Yunchuan Qin, and Siyang Yu. 2016. A dynamic active shield against shield rerouting attack. Int. J. HighPerform. Comput. Netw. 9, 5–6 (2016), 462–469," utilizes a switching control circuit to enable more complex dynamic switching modes in the metal shielding layer, designing a reconfigurable shielding structure. This successfully increases the complexity of the metal shielding layer by dynamically configuring its connection relationships. In terms of routing algorithms, the paper "Briais, S. et al. (2012). 3D Hardware Canaries. In: Prouff, E., Schaumont, P. (eds) Cryptographic Hardware and Embedded Systems – CHES2012. CHES2012. Lecture Notes in Computer Science, vol 7428. Springer, Berlin, Heidelberg." first used random Hamiltonian routing structure as shielding geometry, which is more complex and difficult to identify than traditional topology. They also transformed the module-level shielding problem into the traveling salesman problem and used a fast algorithm to solve it. The paper "Xin, R., Yuan, Y., He, J. et al. High-efficient generation algorithm for large random active shield. Sci. China Inf. Sci. 62, 39108 (2019)." published by Xin Ruishan et al. improved the CMA algorithm to be suitable for the generation of shielding structures for large-scale chips [8]. However, due to the inherent limitations of single-layer structures, these structures or algorithms still find it difficult to simultaneously protect against rewiring attacks and advanced physical attacks such as tilted FIB. Therefore, it is crucial to develop new protection schemes against advanced attacks.

[0006] Research on dual-layer active shielding suffers from the following limitations, hindering its application: existing research approaches employ a comprehensive dual-layer shielding strategy, resulting in significant area and power consumption overhead; and in terms of algorithm efficiency, such as... Figure 4As shown, the closer the physical shielding layer's mesh size is to the minimum linewidth, the better the protection effect. However, existing double-layer shielding generation algorithms have high computational complexity, making it difficult to complete the design of low-mesh-scale double-layer shielding for large-scale chips within a reasonable timeframe. Furthermore, current research has not focused sufficient on the design and optimization of interlayer vias, failing to fully leverage the three-dimensional protection potential of double-layer structures. These limitations make it difficult for existing double-layer shielding technologies to meet the balance requirements of chip security and resource efficiency. Summary of the Invention

[0007] The technical problem to be solved by this invention is that existing double-layer shielding technology is difficult to meet the balance between chip security and resource efficiency.

[0008] This invention solves the above-mentioned technical problems through the following technical means: a method for generating hybrid-dimensional protective structures for multi-physical attacks, comprising:

[0009] S1. Determine the grid granularity, discretize the chip's protected area into a grid, and divide the protected area into a critical area requiring double-layer protection, a single-layer area requiring single-layer protection, and an obstacle area. The obstacle area is the critical circuit area that needs to be avoided. Each grid records the corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the grid belongs to the top or second-to-top layer of the double-layer protection structure.

[0010] S2. Each region of each layer uses grid points as fish and multiple initial random Hamiltonian paths as artificial fish swarms. The artificial fish swarm algorithm is run independently to output path sequences and direction statistics. Paths in adjacent regions are spliced ​​together to form a complete rewire path for the region to be protected.

[0011] S3. Based on the spatial proximity and orthogonal overlap of the rewiring paths of the top and second-to-top layers, enumerate the grid alignment points corresponding to the rewiring paths of the top and second-to-top layers as candidate points. Use an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as via locations, set the corresponding vias, and connect each via to the monitoring circuit. If the via is damaged, trigger the monitoring circuit to issue an alarm.

[0012] S4. Calculate the directional entropy and via distribution entropy based on the directional statistics output by the artificial fish swarm algorithm and the via position. Then, determine whether the shielding quality is qualified based on the directional entropy and via distribution entropy. If the shielding quality is not qualified, return to S2 to S3 to iterate and adjust the rewiring path or via position until the shielding quality is qualified.

[0013] This invention utilizes a double-layer cross-shielding structure with shared wiring between the top and second-to-top layer metals, creating a three-dimensional protection network through interlayer vias. The interlayer dependency design ensures tight coupling between the two shielding layers, making it difficult for attackers to modify either layer while maintaining electrical integrity. Simultaneously, leveraging the three-dimensional barrier effect, strategically placing vias increases attack complexity, ensuring that any damage to a via immediately triggers the monitoring circuit. Employing a zoned protection strategy, protective resources are deployed differently based on the security sensitivity of different chip regions. This significantly reduces area and power consumption while maintaining high security, providing a more practical and efficient solution for chip physical security protection, thus meeting the balance between chip security and resource efficiency.

[0014] Furthermore, the obstacle zone includes the VDD / VSS traces of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries.

[0015] Further, S3 includes:

[0016] Based on the spatial overlap of the two-layer paths, all possible intersections and interlayer proximity points are analyzed to identify candidate points. These candidate points are then screened according to process design rules, eliminating those that do not conform to the rules. Simultaneously, differentiated via density targets are set for areas with different safety levels. Areas corresponding to sensitive circuit sections are given higher via density than other areas to enhance protection. In transition areas between critical and single-layer areas, between critical and obstacle areas, and between single-layer and obstacle areas, a gradually decreasing via density distribution pattern is designed. The process design rules include specifications for minimum via spacing, via size, and via density.

[0017] Based on the set of candidate points, the via selection problem is formalized as a constrained optimization problem, with the optimization objective of maximizing inter-layer synergy. First, according to the target number of vias k, the overall region is divided into n sub-regions, and k / n via slots are allocated to each sub-region. Then, according to the process design rules, candidate points that meet the constraints in each sub-region are selected to form a candidate set. Subsequently, candidate points are randomly selected in each sub-region. After selection, the gain effect of the candidate point set on the quality index is calculated. If it meets the preset threshold, the candidate point set is confirmed; otherwise, it is discarded and new candidate points are tried until the index of the sub-region is met. If the candidate points in a certain sub-region are insufficient or cannot meet the index requirements, the slots of adjacent sub-regions are adjusted. The gain effect on the quality index is evaluated by the via distribution entropy. Throughout the process, all confirmed via positions are aligned with the manufacturing grid during placement to ensure that the process grid and safety spacing requirements are met.

[0018] Furthermore, the formula for the directional entropy is:

[0019]

[0020] Where, d i P(d) represents the i-th direction. i () represents the probability of a path segment in the i-th direction;

[0021] The formula for the entropy of the through-hole distribution is:

[0022]

[0023] Where j represents the j-th grid, m 2 P represents the total number of grid cells. j This represents the probability of finding a through hole in the j-th grid.

[0024] Furthermore, the step of determining whether the shielding quality is qualified based on directional entropy and via distribution entropy includes:

[0025] If the double-layer path direction entropy and via distribution entropy in the critical area are both higher than 0.95, and the single-layer path direction entropy in the single-layer area is higher than 0.95, it indicates that the shielding quality is qualified; otherwise, the shielding quality is unqualified.

[0026] Furthermore, the step of returning to S2 to S3 to iterate and adjust the redistribution path or via position includes:

[0027] When the directional entropy does not meet the requirements, the number of algorithm iterations is increased and the redistribution path is adjusted; when the via distribution entropy does not meet the requirements, the via distribution density is adjusted. The method of adjusting the redistribution path is to first optimize the top-level redistribution path in the area to be protected to achieve the maximum directional entropy, and then generate the second-to-top-level redistribution path based on the top-level structure in the critical area; finally, the relative positions of the two paths are adjusted to maximize the number and distribution of effective via locations.

[0028] Furthermore, the monitoring circuit is configured as follows:

[0029] A differential detection circuit is designed for the double-layer shielded structure in the critical area. The differential detection circuit is connected to the redistribution paths of the top layer and the second-to-top layer, as well as each via, to monitor the signal integrity of both layers and the vias. A single-layer detection circuit is set for the single-layer area to monitor the signal integrity of the single-layer area. The differential detection circuit and the single-layer detection circuit are connected to the central safety control unit, which is used to realize a unified alarm response.

[0030] Furthermore, the method for generating a hybrid-dimensional protective structure against multiple physical attacks also includes S5:

[0031] The optimized design is converted to generate a GDSII file that meets the requirements of EDA tools, as well as a DEF format output for routing.

[0032] This invention also provides a hybrid-dimensional protection structure generation device for multiple physical attacks, comprising:

[0033] The input processing module is used to determine the grid granularity, discretize the chip's protected area into a grid, and divide the protected area into a critical area requiring double-layer protection, a single-layer area requiring single-layer protection, and an obstacle area. The obstacle area is the critical circuit area that needs to be avoided. Each grid records the corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the grid belongs to the top or second-to-top layer of the double-layer protection structure.

[0034] A two-layer path generator is used to treat each region of each layer as a fish, with multiple initial random Hamiltonian paths as artificial fish swarms. The artificial fish swarm algorithm is run independently, and the path sequence and direction statistics are output. The paths of adjacent regions are spliced ​​together to form a complete rewire path for the area to be protected.

[0035] The via placement optimizer is used to enumerate the grid alignment points corresponding to the rewire paths of the top and second-top layers as candidate points based on the spatial proximity and orthogonal overlap relationship of the rewire paths of the top and second-top layers. It uses an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as the via positions, sets the corresponding vias, and connects each via to the monitoring circuit. If a via is damaged, the monitoring circuit is triggered to issue an alarm.

[0036] The evaluation feedback module is used to calculate the directional entropy and via distribution entropy based on the directional statistics output by the artificial fish swarm algorithm and the via position, respectively. Based on the directional entropy and via distribution entropy, it determines whether the shielding quality is qualified. If the shielding quality is not qualified, it returns to the execution of the dual-layer path generator to the via placement optimizer to re-iterate and adjust the rewiring path or via position until the shielding quality is qualified.

[0037] Furthermore, the obstacle zone includes the VDD / VSS traces of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries.

[0038] Furthermore, the via placement optimizer is also used for:

[0039] Based on the spatial overlap of the two-layer paths, all possible intersections and interlayer proximity points are analyzed to identify candidate points. These candidate points are then screened according to process design rules, eliminating those that do not conform to the rules. Simultaneously, differentiated via density targets are set for areas with different safety levels. Areas corresponding to sensitive circuit sections are given higher via density than other areas to enhance protection. In transition areas between critical and single-layer areas, between critical and obstacle areas, and between single-layer and obstacle areas, a gradually decreasing via density distribution pattern is designed. The process design rules include specifications for minimum via spacing, via size, and via density.

[0040] Based on the set of candidate points, the via selection problem is formalized as a constrained optimization problem, with the optimization objective of maximizing inter-layer synergy. First, according to the target number of vias k, the overall region is divided into n sub-regions, and k / n via slots are allocated to each sub-region. Then, according to the process design rules, candidate points that meet the constraints in each sub-region are selected to form a candidate set. Subsequently, candidate points are randomly selected in each sub-region. After selection, the gain effect of the candidate point set on the quality index is calculated. If it meets the preset threshold, the candidate point set is confirmed; otherwise, it is discarded and new candidate points are tried until the index of the sub-region is met. If the candidate points in a certain sub-region are insufficient or cannot meet the index requirements, the slots of adjacent sub-regions are adjusted. The gain effect on the quality index is evaluated by the via distribution entropy. Throughout the process, all confirmed via positions are aligned with the manufacturing grid during placement to ensure that the process grid and safety spacing requirements are met.

[0041] Furthermore, the formula for the directional entropy is:

[0042]

[0043] Where, d i P(d) represents the i-th direction. i () represents the probability of a path segment in the i-th direction;

[0044] The formula for the entropy of the through-hole distribution is:

[0045]

[0046] Where j represents the j-th grid, m 2 P represents the total number of grid cells. j This represents the probability of finding a through hole in the j-th grid.

[0047] Furthermore, the step of determining whether the shielding quality is qualified based on directional entropy and via distribution entropy includes:

[0048] If the double-layer path direction entropy and via distribution entropy in the critical area are both higher than 0.95, and the single-layer path direction entropy in the single-layer area is higher than 0.95, it indicates that the shielding quality is qualified; otherwise, the shielding quality is unqualified.

[0049] Furthermore, the step of returning to the execution of the two-layer path generator to the via placement optimizer to iteratively adjust the redistribution path or via position includes:

[0050] When the directional entropy does not meet the requirements, the number of algorithm iterations is increased and the redistribution path is adjusted; when the via distribution entropy does not meet the requirements, the via distribution density is adjusted. The method of adjusting the redistribution path is to first optimize the top-level redistribution path in the area to be protected to achieve the maximum directional entropy, and then generate the second-to-top-level redistribution path based on the top-level structure in the critical area; finally, the relative positions of the two paths are adjusted to maximize the number and distribution of effective via locations.

[0051] Furthermore, the monitoring circuit is configured as follows:

[0052] A differential detection circuit is designed for the double-layer shielded structure in the critical area. The differential detection circuit is connected to the redistribution paths of the top layer and the second-to-top layer, as well as each via, to monitor the signal integrity of both layers and the vias. A single-layer detection circuit is set for the single-layer area to monitor the signal integrity of the single-layer area. The differential detection circuit and the single-layer detection circuit are connected to the central safety control unit, which is used to realize a unified alarm response.

[0053] Furthermore, the hybrid-dimensional protection structure generation device for multiple physical attacks also includes an output generation module, which is used for:

[0054] The optimized design is converted to generate a GDSII file that meets the requirements of EDA tools, as well as a DEF format output for routing.

[0055] The advantages of this invention are:

[0056] (1) This invention utilizes a double-layer cross-shielding structure with shared wiring between the top and second-to-top layer metals, creating a three-dimensional protection network through interlayer vias. The interlayer dependency design ensures tight coupling between the two shielding layers, making it difficult for attackers to modify either layer while maintaining electrical integrity. Simultaneously, leveraging the three-dimensional barrier effect, the strategic placement of vias increases attack complexity, ensuring that a monitoring circuit is triggered immediately upon breach of a via. A zoned protection strategy is adopted, deploying protection resources differently based on the security sensitivity of different chip regions. This significantly reduces area and power consumption while maintaining high security, providing a more practical and efficient solution for chip physical security protection, thereby meeting the balance between chip security and resource efficiency.

[0057] (2) This invention improves the artificial fish swarm algorithm to develop a more efficient optimization algorithm that is more suitable for two-layer structures. It generates an optimized Hamiltonian path by simulating the foraging, swarming, following and random behavior of fish swarms. It also proposes an optimization strategy for through-hole placement, which combines an enhanced greedy algorithm and random exploration capability to achieve the best through-hole distribution while ensuring manufacturing feasibility.

[0058] (3) This invention achieves automated generation of hybrid-dimensional active protection structures. Based on the different security requirements of different chip regions, this method automatically generates a shielding structure that balances security and resource efficiency, effectively defending against multiple physical attack threats, including tilted FIB attacks and rewiring attacks. It provides enhanced dual-layer protection in critical areas while employing a resource-efficient single-layer solution in non-critical areas, thus satisfying security requirements while avoiding excessive resource consumption.

[0059] (4) The artificial fish swarm algorithm of this invention divides the overall large loop into several independently solvable small loops and uses a dynamic programming algorithm for smooth transition in the intermediate region between loops, achieving a combination of divide-and-conquer and transition optimization. This strategy supports parallel execution and significantly improves the overall path generation efficiency. A sub-feedback mechanism is established with shielding quality as the guide. When the current loop generation quality is detected to be below the preset index, the random selection rule of the loop can be dynamically intervened to guide the algorithm to prioritize the selection of path segments that are conducive to improving shielding quality in the search space, thereby maximizing the overall shielding structure quality. In the design of the double-layer shielding structure, the top layer path is optimized first, and then the second-layer path is optimized with the top layer result as a constraint to ensure that the two layers of paths have a higher degree of overlap and a higher density of via candidates in spatial distribution. This collaborative principle not only improves the protection performance but also ensures the integrity and consistency of the two-layer structure under manufacturing constraints.

[0060] (5) At the structural level, this invention proposes a “hybrid dimension” partitioned protection framework—dividing the layout into three levels: high, medium, and low, based on security sensitivity. Critical areas are double-layered cross-shielded, general areas are single-layered, and non-critical areas can be simplified or unshielded. Through interlayer dependence (electrical / geometric coupling between vias and two-layer paths), a three-dimensional barrier and cross-verification are formed, providing differentiated protection against tilted FIBs and rewiring. In contrast, existing technologies (such as Chinese Patent Publication No. CN112182667A) are only homogeneous multi-layered random connections, without regional differentiation and collaborative detection design.

[0061] At the algorithmic level, this invention uses an improved artificial fish swarm algorithm (D-AFSA) to generate a two-layer Hamiltonian path and measures randomness and isotropic equilibrium using directional entropy; it optimizes the via distribution using an enhanced greedy algorithm combined with random exploration and evaluates uniformity using via distribution entropy; an iterative feedback loop is established between the two. In contrast, existing technologies (such as Chinese Patent Publication No. CN112182667A) do not provide a substantial algorithm or quantifiable quality indicators.

[0062] At the detection level, the high-security zone of this invention implements dual-layer differential detection + via integrity monitoring, and all detections converge to the central security control unit for unified response, achieving high security; existing technologies mainly rely on traditional input / output consistency detection and do not reflect inter-layer collaborative triggering. Attached Figure Description

[0063] Figure 1 This is a schematic diagram illustrating the principle of a rewiring attack.

[0064] Figure 2 This is a schematic diagram illustrating the principle of a tilted FIB attack.

[0065] Figure 3 A schematic diagram of the double-layer shielding structure;

[0066] Figure 4 This is a schematic diagram illustrating the impact of the linewidth of the physical protective layer on the protective effect. Figure 4 (a) is a schematic diagram showing the impact of the large linewidth of the physical protective layer on the protective effect. Figure 4 (b) is a schematic diagram showing the impact of small linewidth of the physical protective layer on the protective effect;

[0067] Figure 5 This is a schematic diagram of a hybrid-dimensional protection structure against multiple physical attacks disclosed in an embodiment of the present invention;

[0068] Figure 6 This is a flowchart of a method for generating a hybrid-dimensional protective structure against multiple physical attacks, as disclosed in an embodiment of the present invention.

[0069] Figure 7 This is a schematic diagram of the hybrid-dimensional active protection structure in the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in this embodiment of the invention, wherein... Figure 7 (a) is a three-dimensional schematic diagram of a hybrid-dimensional active protection structure. Figure 7 (b) is a top view of the hybrid-dimensional active protection structure;

[0070] Figure 8 The circuit layout diagrams before and after security level identification are shown for the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in this embodiment of the invention. Figure 8 (a) Circuit layout diagram prior to security level labeling. Figure 8 (b) Circuit layout diagram prior to security level labeling;

[0071] Figure 9 This is a schematic diagram of the path generation method in the hybrid-dimensional protection structure generation method for multi-physical attacks disclosed in the embodiments of the present invention, wherein... Figure 9 (a) is a schematic diagram of the path generation method for a single region. Figure 9 (b) is the intention to stitch together paths for multiple regions.

[0072] Figure 10 This is a schematic diagram of the shielding layer's resistance to physical attacks in the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in the embodiments of the present invention.

[0073] Figure 11 This is a comparison diagram of the AES circuit layout before and after hybrid-dimensional protection in the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in the embodiments of the present invention. Figure 11 (a) is the AES circuit layout before hybrid dimension protection. Figure 11 (b) is the AES circuit layout after hybrid dimension protection;

[0074] Figure 12 This is a comparison diagram of the AES circuit before and after protection at typical attack points in the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in the embodiments of the present invention, under a tilted FIB attack. Figure 12 (a) is a schematic diagram of the AES circuit before protection at a typical attack point under a tilted FIB attack. Figure 12 (b) is a schematic diagram of the AES circuit after protection at a typical attack point under a tilted FIB attack.

[0075] Figure 13 This is a comparison diagram of the AES circuit before and after protection under rewiring attack in the hybrid-dimensional protection structure generation method for multiple physical attacks disclosed in the embodiments of the present invention. Figure 13 (a) is a schematic diagram of the AES circuit under a rewiring attack before protection. Figure 13 (b) is a schematic diagram of the protected AES circuit under a rewiring attack;

[0076] Figure 14 This is a comparative report on the metal overhead of various shielding methods in the hybrid-dimensional protective structure generation method for multiple physical attacks disclosed in the embodiments of the present invention. Figure 14 (a) is a single-layer shield. Figure 14 (b) is a double-layer shielding. Figure 14 (c) is a mixed-dimensional mask. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] Example 1

[0079] like Figure 5 and Figure 6 As shown, Embodiment 1 of the present invention provides a method for generating a hybrid-dimensional protective structure for multiple physical attacks, including the following steps:

[0080] S1. Determine the mesh granularity. Discretize the area to be protected on the chip into a mesh, dividing the area into critical areas requiring double-layer protection, single-layer areas requiring single-layer protection, and obstacle areas. Obstacle areas are critical circuit areas that need to be avoided. Each mesh records its corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the mesh belongs to the top or second-to-top layer of the double-layer protection structure. It should be noted that large-scale areas of the same security level can also be divided into smaller scales. The specific process is as follows:

[0081] This step corresponds to the input processing module, which receives and processes initial design information, including chip boundary definitions in GDSII format or manually entered coordinate data. This step parses process parameters and design constraints, simultaneously identifying critical areas requiring double-layer protection and areas requiring single-layer protection, converting this information into a mesh structure suitable for path generation. During this process, critical circuit areas that need to be avoided, such as power distribution networks, are marked as obstacle areas. Figure 7 As shown, Figure 7 (a) is a three-dimensional schematic diagram of a hybrid-dimensional active protection structure. Figure 7 (b) is a top view of the hybrid-dimensional active protection structure.

[0082] The inputs are layout boundaries (GDSII / coordinates), process parameters (minimum linewidth / spacing, via design rules), safety zone markings (high / medium / low, i.e., critical area, single-layer area, obstacle area), and obstacle boundaries (PDN, clock tree, IP boundary, test point, etc.).

[0083] The mesh granularity g is determined by the minimum process size. The area to be protected with size L×W is discretized into a directed mesh of (L / g)×(W / g). The mesh cells record attributes: type∈{critical area, single-layer area, unshielded area, barrier}, and retain layer domain labels (M6 / M7, etc.). M6 represents the layer number of the second-to-top layer to be routed, and M7 represents the layer number of the top layer to be routed. Depending on different processes and designs, the layer numbers of the top and second-to-top layers may also differ. For example, in a 55nm process, the top layer can be M8 and the second-to-top layer can be M7. Here, M6 / M7 refers to a 180nm process.

[0084] In critical areas, the objective is a double-layer path direction entropy ≥ 0.95, and candidate intersection points are reserved for through-hole optimization; in single-layer areas, the objective is a single-layer path direction entropy ≥ 0.95; obstacle areas are marked as impassable nodes / edges.

[0085] Process rules (line width / spacing / via spacing and enclosure, etc.) are reflected in mesh accessibility determination and candidate set filtering, which restricts the path and via candidate set from the source.

[0086] Based on the above principles, in a specific implementation scenario, this embodiment imports the GDSII file of the AES encryption circuit into the system and extracts the chip's physical layout information. Taking a 128-bit AES encryption circuit under the 180nm standard process library as an example, the total area of ​​this circuit is approximately 0.5mm². 2 The system includes key functional areas such as the key processing unit, S-Box, and round function module. It also inputs process parameters, including metal layer specifications (M6, M7), minimum linewidth, minimum spacing, and via design rules. The system parses the input GDSII file and establishes a coordinate mapping table for each functional area of ​​the AES circuit, preparing for subsequent security area partitioning.

[0087] Based on functional importance and security risk assessment, the system divides the AES circuit into three security zones: the high-security zone includes the key register, S-Box, and key expansion unit, with a total area of ​​approximately 0.2 mm². 2 It requires double-layer shielding protection; the medium security zone includes the round function operation unit and control logic, with a total area of ​​approximately 0.1 mm². 2 It employs single-layer shielding protection; the low-security area includes I / O interfaces and auxiliary logic circuits, with a total area of ​​approximately 0.2 mm². 2 Simplified shielding or no shielding may be used.

[0088] like Figure 8 As shown, Figure 8 (a) Circuit layout diagram prior to security level labeling. Figure 8 (b) For the circuit layout diagram before security level identification, the system generates a security area boundary file, records the coordinate range and security level identification of each area, and uses different colors to mark the circuit layout diagram (red for high security area, yellow for medium security area, and green for low security area).

[0089] The chip protection area is converted into a discrete mesh structure. The mesh cell size is set according to the expected shielding layer density to form a mesh matrix. The system automatically identifies and marks obstacle areas, specifically including: VDD / VSS traces of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries. Obstacle areas are marked as "impassable" cells in the mesh matrix, and the system generates an obstacle distribution map, visually displaying the areas that the shielding path needs to bypass.

[0090] S2. For each region of each layer, grid points are treated as fish, and multiple initial random Hamiltonian paths are used as artificial fish swarms. The artificial fish swarm algorithm is run independently, outputting path sequences and direction statistics. Paths from adjacent regions are spliced ​​together to form a complete rewire path for the region to be protected. The specific process is as follows:

[0091] This step corresponds to a two-layer path generator. After receiving the mesh structure and constraints from the input processing module, it begins generating Hamiltonian paths for regions with different security levels. This step uses an improved Artificial Fish Swarm Algorithm (D-AFSA) to optimize path randomness and directional balance, ensuring path continuity between regions with different security levels. The generated preliminary path schemes are then passed to the via placement optimizer and the evaluation feedback module, and iteratively adjusted based on feedback from these steps. Figure 9 As shown, Figure 9 (a) is a schematic diagram of the path generation method for a single region. Figure 9 (b) This refers to the intent of stitching multiple regions together. Stitching multiple regions together is not only about stitching together regions of different security levels, but also about breaking down large-scale regions of the same security level into smaller ones, generating protection for each, and then stitching them together.

[0092] The input parameters for the artificial fish swarm algorithm include the region boundary polygon, the layer region (high region: M6+M7; middle region: M7; low region: optional), and the algorithm parameters (population size N, number of iterations Max_Iter, line distance Visual, step size Step). The recommended default values ​​are: N = (L / Visual) × (W / Visual), Max_Iter = 200, Visual = 3, Step = 1.5 (related to line spacing).

[0093] The algorithm creates multiple initial random Hamiltonian paths as artificial fish swarms, each path representing a potential solution in the problem space. A "fish" represents a candidate unit cell (within a layer) of all grid points in the region capable of creating Hamiltonian paths; the fish swarm represents a sequence of Hamiltonian paths continuously expanded by a single initial fish through four behavioral patterns. These "fish" optimize paths through four behavioral patterns: foraging behavior moves individual fish to better states; swarming behavior causes surrounding fish to move towards the center; following behavior causes fish to follow neighbors with higher fitness; and random behavior helps the population avoid getting trapped in local optima. The quality of the paths is evaluated using directional entropy to ensure a balanced directional distribution.

[0094] During path modification, the algorithm ensures that the Hamiltonian property is still satisfied after the path modification through segment swapping operations, meaning that each grid vertex is visited exactly once. As the optimization progresses, the algorithm dynamically adjusts the look-ahead distance and step size parameters until the maximum number of iterations is reached or the preset quality threshold is met. The segment swapping operation refers to the randomness of each selection of fish from the new feasible set into the fish group; this randomness can be considered to be intervened when the quality requirement is not met. Each update is only performed within the feasible set of the same layer and region, and is verified in real time. The path, as a permutation, still requires "each grid point to be visited exactly once" after the update, which is an inherent Hamiltonian property of the algorithm.

[0095] The generation of dual-layer paths employs a hierarchical coordination strategy. First, the top-layer metal path is optimized in the area to be routed to maximize its directional entropy. Then, in critical regions, secondary-layer paths are generated based on the main-layer structure, considering inter-layer coordination. Finally, the relative positions of the two paths are adjusted to maximize the number and distribution of effective via locations. For large-scale chips, the algorithm uses a region decomposition strategy, dividing the large protection area into multiple sub-regions, generating paths in parallel, and then integrating them, while ensuring the continuity and natural transition of paths at boundaries.

[0096] In actual execution, entry / exit gate points (reachable grid points near the zone boundary) are automatically selected in each sub-region according to the grid scanning rules. In the high-level region, gate points need to be assigned to both layers simultaneously to facilitate subsequent via coupling. D-AFSA is run independently in each region to obtain the intra-layer Hamiltonian path (two layers are generated in the high-level region; a single layer is generated in the middle region). The output path sequence (in grid point order) and direction statistics (used for direction entropy) are shown below. Figure 9 As shown, at the boundary of adjacent areas, several gate points are reserved for the transition zone and the paths are spliced; the smooth transition between the high zone and the middle zone is achieved through a dynamic programming strategy.

[0097] The artificial fish swarm algorithm of this invention divides the overall large loop into several independently solvable smaller loops and uses dynamic programming to smoothly transition between the loops, achieving a combination of divide-and-conquer and transition optimization. This strategy supports parallel execution, significantly improving the overall path generation efficiency. A sub-feedback mechanism is established with shielding quality as the guide. When the current loop generation quality is detected to be below a preset standard, the random selection rule of the loop can be dynamically intervened, guiding the algorithm to prioritize path segments in the search space that are conducive to improving shielding quality, thereby maximizing the overall shielding structure quality. In the double-layer shielding structure design, the top-layer path is optimized first, and then the second-layer path is optimized using the top-layer result as a constraint, ensuring that the two layers of paths have a higher degree of overlap and a higher density of via candidates in spatial distribution. This collaborative principle not only improves the protective performance but also ensures the integrity and consistency of the two-layer structure under manufacturing constraints.

[0098] Based on the above principles, in specific implementation scenarios, based on the security area division results, the system initiates a hybrid-dimensional path generation algorithm to simultaneously plan shielding paths for each region of the AES circuit. The high-security area uses M6 / M7 double-layer metal wiring, the medium-security area uses M7 single-layer metal wiring, and the low-security area is either unshielded or uses simplified shielding. Key algorithm parameters include: population size N = 2^16 * 2^16 (N = (L / Visual) × (W / Visual)), maximum number of iterations Max_Iter = 200, line-of-sight parameter Visual = 3 (distance between the artificial fish to be merged and the already merged artificial fish), and step size parameter Step = 1.5 (spacing between shielding structure lines). The improved D-AFSA algorithm generates a globally optimal solution for the entire shielding structure while handling the transition relationships at region boundaries. For the high-security area, the algorithm simultaneously optimizes the path direction entropy of both M6 / M7 metal layers, with a target value ≥ 0.95; for the medium-security area, it only optimizes the M7 single-layer path, with a target direction entropy ≥ 0.95. The algorithm ultimately outputs a hybrid-dimensional shielding path scheme for the entire AES module. The high-security region forms a two-layer, three-dimensional protection network, while the medium-security region forms a single-layer, highly random protection layer. The directional entropy formula, as shown below, reflects the degree of disorder in the shielding structure.

[0099]

[0100] Where, d i P(d) represents the i-th direction. i ) represents the probability of a path segment in the i-th direction. In this embodiment of the invention, the calculation of directional entropy is defined as calculating the entropy value after the loop of each sub-region is generated before splicing. If the target directional entropy requirement is not met, it is regenerated. This can improve efficiency compared to calculating after the entire loop is generated. Since the two-dimensional plane has only two directions, x and y, the maximum value of i is 2 when calculating directional entropy.

[0101] S3. Based on the spatial proximity and orthogonal overlap of the rewire paths of the top and second-to-top layers, enumerate the grid alignment points corresponding to the rewire paths of the top and second-to-top layers as candidate points. Use an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as via locations, set the corresponding vias, and connect each via to the monitoring circuit. If a via is damaged, the monitoring circuit is triggered to issue an alarm. The specific process is as follows:

[0102] This step corresponds to the via placement optimizer, which focuses on the design of interlayer connections and is crucial for achieving 3D protection. It receives dual-layer path information from the path generator, identifies candidate via locations that conform to design rules, and then applies a combination of an enhanced greedy algorithm and random exploration to select the via configuration that maximizes interlayer synergy. Simultaneously, it designs special via connection strategies for single- and dual-layer transition regions to ensure the continuity of protection. In dual-layer regions, vias serve a dual function of electrical connectivity and protection coupling triggering: once a via is damaged / rewritten, differential detection and via integrity monitoring can directly trigger an alarm; vias also ensure the geometric and electrical continuity of layer switching / cascading.

[0103] Via placement is performed after the two-layer Hamiltonian map is determined. First, a greedy algorithm is used to find a feasible set of possible perforations (satisfying manufacturing constraints), and then a point is randomly selected to maximize shielding quality. If the quality of the finally selected point is still insufficient, feedback is sent back to the path generator to consider creating more intersecting paths to generate perforation points. Specifically, this invention adopts an "enhanced greedy algorithm + random exploration" optimization method to maximize inter-layer collaborative efficiency and distribution entropy while ensuring dual-layer conductivity and detection reachability. Specifically, based on the spatial overlap of the two-layer paths, all possible intersections and interlayer proximity points are analyzed to identify candidate points. These candidate points are then screened according to process design rules, eliminating those that do not conform to the rules. Simultaneously, differentiated via density targets are set for areas with different safety levels. Areas corresponding to sensitive circuit sections have higher via densities than other areas to enhance protection. In transition areas between critical and single-layer areas, critical and obstacle areas, and single-layer and obstacle areas, a gradually decreasing via density distribution pattern is designed, requiring higher via densities in high-safety areas to strengthen interlayer coupling. Electrical continuity and geometric integrity of layer transitions are ensured in single- and double-layer transition areas. The process design rules include specifications for minimum via spacing, via size, and via density.

[0104] Based on the set of candidate points, the via selection problem is formalized as a constrained optimization problem, with the optimization objective of maximizing inter-layer synergy. First, according to the target number of vias k, the overall region is divided into n sub-regions, and k / n via slots are allocated to each sub-region. Then, according to the process design rules, candidate points that meet the constraints in each sub-region are selected to form a candidate set. Subsequently, candidate points are randomly selected in each sub-region. After selection, the gain effect of the candidate point set on the quality index is calculated. If it meets the preset threshold, the candidate point set is confirmed; otherwise, it is discarded and new candidate points are tried until the index of the sub-region is met. If the candidate points in a certain sub-region are insufficient or cannot meet the index requirements, the slots of adjacent sub-regions are adjusted. The gain effect on the quality index is evaluated by the via distribution entropy. Throughout the process, all confirmed via positions are aligned with the manufacturing grid during placement to ensure that the process grid and safety spacing requirements are met, thereby forming a via layout scheme that is evenly distributed and conforms to the process rules.

[0105] The via distribution optimization employs a two-level collaborative control approach: global and local. At the global level, the protected area is evenly divided into several sub-regions, and the total number of vias is rationally allocated based on area and safety level to avoid excessive concentration or sparseness in certain areas. At the local level, the via positions are further optimized within each sub-region to maintain uniformity and non-clustering characteristics. The transition area between single and double layers ensures electrical continuity and geometric shielding integrity.

[0106] The via optimization process and the dual-layer path generation process form a closed-loop feedback mechanism. After each round of via optimization, the system feeds back the current distribution quality indicators to the path generator, triggering adjustments to the local structure of the path or the interlayer overlap. For high-security areas, the path overlap ratio can be dynamically increased to increase the density of via candidate points. The convergence of the optimization process is determined by the improvement in quality through continuous iterations. When all indicators meet the preset thresholds or reach the iteration limit, the final dual-layer shielding structure design is output. This design balances manufacturability and protective performance, forming a globally optimal via layout scheme. Figure 10 This is a schematic diagram illustrating the shielding layer's resistance to physical attacks.

[0107] Based on the above principles, in specific implementation scenarios, the system executes a via placement algorithm to optimize interlayer connectivity in the double-layer shielded area. The via placement process first scans the double-layer path in the high-security area, identifying candidate via locations that conform to process rules, thus forming valid candidate points. To achieve uniform distribution, the algorithm divides the high-security area into k... 2Each region is divided into equal sub-regions. An enhanced greedy algorithm is used for optimization, selecting locations that maximize the via distribution entropy while maintaining the minimum distance between vias to satisfy constraints. For sensitive circuitry such as the key register, the via density is increased to enhance protection. In transition regions, a gradually decreasing via density distribution pattern is designed, forming a "zigzag" irregular boundary. Ultimately, a highly uniform via distribution entropy of 0.95 is achieved. The via distribution entropy formula is as follows, reflecting the degree of disorder in the via distribution.

[0108]

[0109] Where j represents the j-th grid, m 2 P represents the total number of grid cells. j This represents the probability of finding a through hole in the j-th grid.

[0110] Step S4 corresponds to the evaluation feedback module. Based on the directional statistics output by the artificial fish swarm algorithm and the via positions, it calculates the directional entropy and via distribution entropy. This determines whether the shielding quality is acceptable. If the shielding quality is unacceptable, it returns to steps S2 and S3 to iterate and adjust the redistribution path or via positions until the shielding quality is acceptable. This step provides real-time evaluation and optimization guidance, calculating and analyzing the directional distribution characteristics of the two-layer path, evaluating the uniformity and effectiveness of the via distribution, and verifying the connection integrity of the transition area. This step also analyzes the overall structure's protection effectiveness against tilted FIB attacks and redistribution attacks, generates optimization suggestions, and feeds them back to the path generator and via placement optimizer to ensure the coordinated operation and continuous optimization of the entire system. Specifically, in high-security areas, both the directional entropy of the two-layer path and the via distribution entropy are higher than 0.95, and in medium-security areas, the directional entropy of the single-layer path is higher than 0.95 bits, indicating that the structure has high disorder and the shielding quality is acceptable. If the results do not meet the standards, the system initiates negative feedback optimization: if the directional entropy is insufficient, the number of algorithm iterations is increased; if the via distribution is uneven, the density allocation strategy is modified. The evaluation results met the preset indicators, and the system confirmed that the shielding quality was qualified. Through this evaluation and feedback mechanism, the system can adaptively adjust the generation strategy to ensure that the shielding structure simultaneously meets safety and manufacturability requirements.

[0111] The detection circuit can effectively identify any physical interference to the shielding structure. It is designed and integrated with the integrity detection circuit for mixed-dimensional shielding structures: a differential detection circuit is designed for the double-layer shielding in the high-security zone to monitor the integrity of both layers of signals and vias simultaneously; a simplified detection circuit is designed for the single-layer shielding in the medium-security zone to monitor the integrity of only the single-layer signal; all monitoring circuits are connected to the central safety control unit to achieve a unified alarm response.

[0112] S5. This step corresponds to the output generation module, which converts the optimized design into a manufacturable format, generating a GDSII file that meets EDA tool requirements, a DEF format output for routing, and the netlist and control logic for the shielding layer detection circuit. Detailed technical documentation is also provided to ensure seamless integration of the design results into the chip design flow. In this embodiment, the shielding structure is generated in the layout design tool using a SKILL script and integrated with the detection circuit and the circuit to be protected in the above design. The system converts the AES circuit layout with the optimized mixed-dimensional shielding design into a manufacturable format, such as... Figure 11 As shown, Figure 11 (a) is the AES circuit layout before hybrid dimension protection. Figure 11 (b) The AES circuit layout after hybrid dimension protection; the layout file contains the top layer metal of the routing areas, the second-to-top layer shielding metal of critical areas, via connections, detection circuits, and GDSII data of the original AES circuit. Perform a DRC check to ensure that all design rules are met.

[0113] Continue reading Figure 1 These five modules are not a simple linear workflow, but rather form an interactive network with interconnected relationships. The evaluation module maintains bidirectional communication with other modules, the path generator and the via optimizer form an iterative optimization loop, and the input and output modules serve as the system's entry and exit points, respectively, ensuring standardized data processing and effective output of results.

[0114] The following section verifies the effectiveness of physical attack protection. First, the security of the generated hybrid-dimensional shielding structure is verified:

[0115] 1. Simulation analysis of tilted FIB attack:

[0116] A 3D model of the shielding structure was constructed using the GDS3D tool. Ten potential attack points were selected, and FIB attacks at different tilt angles (60°-75°) were simulated. The difference in attack success rate between double-layer and single-layer regions was analyzed. Some verification results are shown below. Figure 12 This image shows a comparison of the AES circuit before and after protection at typical attack points under a tilted FIB attack. Figure 12 (a) is a schematic diagram of the AES circuit before protection at a typical attack point under a tilted FIB attack. Figure 12 (b) is a schematic diagram of an AES circuit protected at a typical attack point under a tilted FIB attack. In a single-layer shielding structure, the high aspect ratio tilted FIB beam can cleverly pass through the gaps between the shielding wires and successfully contact the underlying target metal wire without triggering an alarm. The double-layer structure, through its interlaced three-dimensional protection network, forms a more robust protection system, significantly reducing the likelihood of a successful attack. Compared to a single-layer area, the double-layer region effectively eliminates the successful angle of a FIB attack.

[0117] 2. Rewiring Attack Simulation Analysis:

[0118] The difficulty of simulating a rewiring attack by an attacker in different areas is analyzed, along with the complexity and time cost of identifying connectivity relationships. The verification results are as follows: Figure 13 As shown, Figure 13 (a) is a schematic diagram of the AES circuit under a rewiring attack before protection. Figure 13 (b) Schematic diagram of the protected AES circuit under a rewiring attack; under a high-powered microscope, in a single-layer shielded structure, attackers can easily identify the start and end points of the shielded lines, thus creating exploitable attack vectors. In contrast, in a double-layered area, due to the large number of intersecting port points in the top-level view and the complex connections between ports hidden in the multi-layered structure, attackers find it difficult to determine effective rewiring attack points.

[0119] Then, a resource cost assessment is performed:

[0120] Compared to the full double-layer shielding scheme, the hybrid dimension scheme reduces metal wire resource overhead by approximately 40%, significantly lowers power consumption, and keeps timing impact within acceptable limits. Verification results are as follows: Figure 14 As shown, where, Figure 14 (a) is a single-layer shield. Figure 14 (b) is a double-layer shielding. Figure 14 (c) Hybrid dimensional shielding: The hybrid dimensional shielding structure maintains high security in critical areas while significantly optimizing resource utilization efficiency, providing a balanced physical security protection scheme for AES encryption circuits.

[0121] Through the above steps, this invention achieves the complete deployment of a hybrid-dimensional active protection structure on AES encryption circuits, forming a differentiated protection strategy for areas with different security levels. While maintaining high security in critical areas, this solution achieves an optimal balance between security and resource consumption by employing a resource-efficient single-layer scheme in non-critical areas, providing a practical and efficient technical route for integrated circuit physical security protection. It addresses the inherent limitations of traditional single-layer active protection structures against tilted FIB attacks and redistribution attacks by innovatively proposing a hybrid-dimensional active protection structure and its automated generation method, achieving differentiated protection for critical chip areas. The invention specifically improves the double-layer shielding generation algorithm, optimizes the via distribution strategy, and adopts a partitioned protection mechanism based on attack sensitivity, providing a more efficient and resource-friendly physical security protection solution for integrated circuits. Compared with existing technologies, in terms of security, the hybrid-dimensional shielding structure can eliminate the effective attack angle of tilted FIB attacks, while reducing the success rate of redistribution attacks and improving the time and manpower costs of various types of physical attacks. In terms of resource efficiency, compared with full double-layer shielding, the hybrid-dimensional solution of this invention reduces metal resource overhead by approximately 40% while maintaining a similar level of security protection. Furthermore, this invention enables large-scale chip (3×3mm) processing. 2 The automated shielding design with low net size, with a generation time of less than 1 hour and support for multiple process nodes (55nm to 180nm), provides a reliable way for the engineering and practical application of chip physical security protection technology.

[0122] Example 2

[0123] Based on Embodiment 1, Embodiment 2 of the present invention also provides a hybrid-dimensional protection structure generation device for multiple physical attacks, consisting of five functional modules to form a complete solution. These modules cooperate to convert the input protection area specifications into a hybrid-dimensional shielding design that meets manufacturing requirements, specifically including:

[0124] The input processing module is used to determine the grid granularity, discretize the chip's protected area into a grid, and divide the protected area into a critical area requiring double-layer protection, a single-layer area requiring single-layer protection, and an obstacle area. The obstacle area is the critical circuit area that needs to be avoided. Each grid records the corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the grid belongs to the top or second-to-top layer of the double-layer protection structure.

[0125] A two-layer path generator is used to treat each region of each layer as a fish, with multiple initial random Hamiltonian paths as artificial fish swarms. The artificial fish swarm algorithm is run independently, and the path sequence and direction statistics are output. The paths of adjacent regions are spliced ​​together to form a complete rewire path for the area to be protected.

[0126] The via placement optimizer is used to enumerate the grid alignment points corresponding to the rewire paths of the top and second-top layers as candidate points based on the spatial proximity and orthogonal overlap relationship of the rewire paths of the top and second-top layers. It uses an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as the via positions, sets the corresponding vias, and connects each via to the monitoring circuit. If a via is damaged, the monitoring circuit is triggered to issue an alarm.

[0127] The evaluation feedback module is used to calculate the directional entropy and via distribution entropy based on the directional statistics output by the artificial fish swarm algorithm and the via position, respectively. Based on the directional entropy and via distribution entropy, it determines whether the shielding quality is qualified. If the shielding quality is not qualified, it returns to the execution of the dual-layer path generator to the via placement optimizer to re-iterate and adjust the rewiring path or via position until the shielding quality is qualified.

[0128] Specifically, the obstacle zone includes the VDD / VSS routing of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries.

[0129] Specifically, the via placement optimizer is also used for:

[0130] Based on the spatial overlap of the two-layer paths, all possible intersections and interlayer proximity points are analyzed to identify candidate points. These candidate points are then screened according to process design rules, eliminating those that do not conform to the rules. Simultaneously, differentiated via density targets are set for areas with different safety levels. Areas corresponding to sensitive circuit sections are given higher via density than other areas to enhance protection. In transition areas between critical and single-layer areas, between critical and obstacle areas, and between single-layer and obstacle areas, a gradually decreasing via density distribution pattern is designed. The process design rules include specifications for minimum via spacing, via size, and via density.

[0131] Based on the set of candidate points, the via selection problem is formalized as a constrained optimization problem, with the optimization objective of maximizing inter-layer synergy. First, according to the target number of vias k, the overall region is divided into n sub-regions, and k / n via slots are allocated to each sub-region. Then, according to the process design rules, candidate points that meet the constraints in each sub-region are selected to form a candidate set. Subsequently, candidate points are randomly selected in each sub-region. After selection, the gain effect of the candidate point set on the quality index is calculated. If it meets the preset threshold, the candidate point set is confirmed; otherwise, it is discarded and new candidate points are tried until the index of the sub-region is met. If the candidate points in a certain sub-region are insufficient or cannot meet the index requirements, the slots of adjacent sub-regions are adjusted. The gain effect on the quality index is evaluated by the via distribution entropy. Throughout the process, all confirmed via positions are aligned with the manufacturing grid during placement to ensure that the process grid and safety spacing requirements are met.

[0132] Specifically, the formula for the directional entropy is:

[0133]

[0134] Where, d i P(d) represents the i-th direction. i () represents the probability of a path segment in the i-th direction;

[0135] The formula for the entropy of the through-hole distribution is:

[0136]

[0137] Where j represents the j-th grid, m 2 P represents the total number of grid cells. j This represents the probability of finding a through hole in the j-th grid.

[0138] Specifically, determining whether the shielding quality is qualified based on directional entropy and via distribution entropy includes:

[0139] If the double-layer path direction entropy and via distribution entropy in the critical area are both higher than 0.95, and the single-layer path direction entropy in the single-layer area is higher than 0.95, it indicates that the shielding quality is qualified; otherwise, the shielding quality is unqualified.

[0140] More specifically, the step of returning to the execution of the two-layer path generator to the via placement optimizer to iterate and adjust the redistribution path or via position includes:

[0141] When the directional entropy does not meet the requirements, the number of algorithm iterations is increased and the redistribution path is adjusted; when the via distribution entropy does not meet the requirements, the via distribution density is adjusted. The method of adjusting the redistribution path is to first optimize the top-level redistribution path in the area to be protected to achieve the maximum directional entropy, and then generate the second-to-top-level redistribution path based on the top-level structure in the critical area; finally, the relative positions of the two paths are adjusted to maximize the number and distribution of effective via locations.

[0142] Specifically, the monitoring circuit is configured as follows:

[0143] A differential detection circuit is designed for the double-layer shielded structure in the critical area. The differential detection circuit is connected to the redistribution paths of the top layer and the second-to-top layer, as well as each via, to monitor the signal integrity of both layers and the vias. A single-layer detection circuit is set for the single-layer area to monitor the signal integrity of the single-layer area. The differential detection circuit and the single-layer detection circuit are connected to the central safety control unit, which is used to realize a unified alarm response.

[0144] Specifically, the hybrid-dimensional protection structure generation device for multiple physical attacks further includes an output generation module, which is used for:

[0145] The optimized design is converted to generate a GDSII file that meets the requirements of EDA tools, as well as a DEF format output for routing.

[0146] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating hybrid-dimensional protective structures against multiple physical attacks, characterized in that, include: S1. Determine the grid granularity, discretize the chip's protected area into a grid, and divide the protected area into a critical area requiring double-layer protection, a single-layer area requiring single-layer protection, and an obstacle area. The obstacle area is the critical circuit area that needs to be avoided. Each grid records the corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the grid belongs to the top or second-to-top layer of the double-layer protection structure. S2. Each region of each layer uses grid points as fish and multiple initial random Hamiltonian paths as artificial fish swarms. The artificial fish swarm algorithm is run independently to output path sequences and direction statistics. Paths in adjacent regions are spliced ​​together to form a complete rewire path for the region to be protected. S3. Based on the spatial proximity and orthogonal overlap of the rewiring paths of the top and second-to-top layers, enumerate the grid alignment points corresponding to the rewiring paths of the top and second-to-top layers as candidate points. Use an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as via locations, set the corresponding vias, and connect each via to the monitoring circuit. If the via is damaged, trigger the monitoring circuit to issue an alarm. S4. Calculate the directional entropy and via distribution entropy based on the directional statistics output by the artificial fish swarm algorithm and the via position. Then, determine whether the shielding quality is qualified based on the directional entropy and via distribution entropy. If the shielding quality is not qualified, return to S2 to S3 to iterate and adjust the rewiring path or via position until the shielding quality is qualified.

2. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, The obstacle zone includes the VDD / VSS cabling of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries.

3. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, S3 includes: Based on the spatial overlap of the two-layer paths, all possible intersections and interlayer proximity points are analyzed to identify candidate points. These candidate points are then screened according to process design rules, eliminating those that do not conform to the rules. Simultaneously, differentiated via density targets are set for areas with different safety levels. Areas corresponding to sensitive circuit sections are given higher via density than other areas to enhance protection. In transition areas between critical and single-layer areas, between critical and obstacle areas, and between single-layer and obstacle areas, a gradually decreasing via density distribution pattern is designed. The process design rules include specifications for minimum via spacing, via size, and via density. Based on the set of candidate points, the via selection problem is formalized as a constrained optimization problem, with the optimization objective of maximizing inter-layer synergy. First, according to the target number of vias k, the overall region is divided into n sub-regions, and k / n via slots are allocated to each sub-region. Then, according to the process design rules, candidate points that meet the constraints in each sub-region are selected to form a candidate set. Subsequently, candidate points are randomly selected in each sub-region. After selection, the gain effect of the candidate point set on the quality index is calculated. If it meets the preset threshold, the candidate point set is confirmed; otherwise, it is discarded and new candidate points are tried until the index of the sub-region is met. If the candidate points in a certain sub-region are insufficient or cannot meet the index requirements, the slots of adjacent sub-regions are adjusted. The gain effect on the quality index is evaluated by the via distribution entropy. Throughout the process, all confirmed via positions are aligned with the manufacturing grid during placement to ensure that the process grid and safety spacing requirements are met.

4. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, The formula for the directional entropy is: Where, d i P(d) represents the i-th direction. i () represents the probability of a path segment in the i-th direction; The formula for the entropy distribution of through-holes is: Where j represents the j-th grid, m 2 P represents the total number of grid cells. j This represents the probability of finding a through hole in the j-th grid.

5. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, The method of determining whether the shielding quality is qualified based on directional entropy and via distribution entropy includes: If the double-layer path direction entropy and via distribution entropy in the critical area are both higher than 0.95, and the single-layer path direction entropy in the single-layer area is higher than 0.95, it indicates that the shielding quality is qualified; otherwise, the shielding quality is unqualified.

6. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 5, characterized in that, The step of returning to S2 to S3 to iterate and adjust the redistribution path or via position includes: When the directional entropy does not meet the requirements, the number of algorithm iterations is increased and the redistribution path is adjusted; when the via distribution entropy does not meet the requirements, the via distribution density is adjusted. The method of adjusting the redistribution path is to first optimize the top-level redistribution path in the area to be protected to achieve the maximum directional entropy, and then generate the second-to-top-level redistribution path based on the top-level structure in the critical area; finally, the relative positions of the two paths are adjusted to maximize the number and distribution of effective via locations.

7. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, The monitoring circuit is configured as follows: A differential detection circuit is designed for the double-layer shielded structure in the critical area. The differential detection circuit is connected to the redistribution paths of the top layer and the second-to-top layer, as well as each via, to monitor the signal integrity of both layers and the vias. A single-layer detection circuit is set for the single-layer area to monitor the signal integrity of the single-layer area. The differential detection circuit and the single-layer detection circuit are connected to the central safety control unit, which is used to realize a unified alarm response.

8. The method for generating a hybrid-dimensional protective structure against multiple physical attacks according to claim 1, characterized in that, Also includes S5: The optimized design is converted to generate a GDSII file that meets the requirements of EDA tools, as well as a DEF format output for routing.

9. A hybrid-dimensional protective structure generation device for multiple physical attacks, characterized in that, include: The input processing module is used to determine the grid granularity, discretize the chip's protected area into a grid, and divide the protected area into a critical area requiring double-layer protection, a single-layer area requiring single-layer protection, and an obstacle area. The obstacle area is the critical circuit area that needs to be avoided. Each grid records the corresponding partition attributes and layer domain markers. The layer domain markers indicate whether the grid belongs to the top or second-to-top layer of the double-layer protection structure. A two-layer path generator is used to treat each region of each layer as a fish, with multiple initial random Hamiltonian paths as artificial fish swarms. The artificial fish swarm algorithm is run independently, and the path sequence and direction statistics are output. The paths of adjacent regions are spliced ​​together to form a complete rewire path for the area to be protected. The via placement optimizer is used to enumerate the grid alignment points corresponding to the rewire paths of the top and second-top layers as candidate points based on the spatial proximity and orthogonal overlap relationship of the rewire paths of the top and second-top layers. It uses an enhanced greedy algorithm to select the candidate points that maximize the inter-layer synergy effect as the via positions, sets the corresponding vias, and connects each via to the monitoring circuit. If a via is damaged, the monitoring circuit is triggered to issue an alarm. The evaluation feedback module is used to calculate the directional entropy and via distribution entropy based on the directional statistics output by the artificial fish swarm algorithm and the via position, respectively. Based on the directional entropy and via distribution entropy, it determines whether the shielding quality is qualified. If the shielding quality is not qualified, it returns to the execution of the dual-layer path generator to the via placement optimizer to re-iterate and adjust the rewiring path or via position until the shielding quality is qualified.

10. The hybrid-dimensional protective structure generation device for multiple physical attacks according to claim 9, characterized in that, The obstacle zone includes the VDD / VSS cabling of the power distribution network, the backbone of the clock tree network, reserved test access points, and immovable IP core boundaries.

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