Sparse convolution kernel-based FPGA efficient accelerator design method and system

Abstract

The invention discloses an FPGA efficient accelerator design method and system based on a sparse convolution kernel, and relates to the technical field of accelerator design. Comprising the steps of optimizing sparse weight storage and management, designing a sparse convolution kernel storage structure and adopting a data organization scheme oriented to output channel optimization; designing a sparse convolution kernel index and scheduling mode, including dynamic row coordinate index storage and an intelligent dynamic scheduling mechanism; and constructing a sparse convolutional layer, wherein the sparse convolutional layer comprises an output channel serial computing architecture and an optimized MAC module. Through collaborative optimization of weight pruning and convolution kernel pruning, an efficient storage mechanism based on a non-zero weight and coordinates thereof is established, the storage requirement is remarkably reduced, and the calculation efficiency is improved; a serial / parallel configurable calculation mode of an output channel is designed, and the time division multiplexing technology of a single MAC module is combined, so that efficient utilization of FPGA logic resources is realized.

Description

Technical Field

[0001] This invention relates to the field of accelerator design technology, and specifically to a method and system for designing an efficient FPGA accelerator based on sparse convolution kernels. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence technology, Convolutional Neural Networks (CNNs) have become core algorithms in fields such as image recognition, object detection, and natural language processing. However, CNN models typically contain a large number of convolutional and fully connected layers, resulting in deep network structures, numerous parameters, and high computational complexity. Taking the classic LeNet-5 network as an example, its multi-layered structure of convolutional, pooling, and fully connected layers has demonstrated outstanding performance in tasks such as handwritten digit recognition. With the evolution of deep learning models, deeper and more complex networks such as VGG and ResNet have been widely adopted, placing higher demands on hardware computing power and storage resources.

[0003] In practical deployments, especially on resource-constrained platforms such as edge computing and embedded devices, the massive computational and storage requirements of CNN models have become a significant factor restricting their widespread adoption. To address this issue, model compression and acceleration techniques have gained widespread attention from researchers in recent years. Among these, network pruning, as an effective model sparsity reduction method, significantly reduces the model's storage and computational requirements by removing redundant parameters and connections, making it an indispensable part of hardware accelerator design. However, pruned models often contain a large number of zero-valued weights. If the hardware still stores and computes them in a dense matrix manner, it will lead to a serious waste of storage and computational resources. Therefore, how to efficiently map the sparsified CNN to FPGA and achieve coordinated optimization of storage and computation has become a current research hotspot and challenge.

[0004] In terms of storage optimization, traditional dense matrix storage methods are insufficient to meet the high-efficiency requirements of sparse CNNs. When the network sparsity is high, a large number of zero-value weights not only occupy redundant storage space but also increase memory access bandwidth and power consumption. Therefore, adopting a sparse convolution kernel storage format that stores only non-zero weights and their corresponding indices has become a key technology for solving this problem. Furthermore, to further improve the computational performance of sparse convolutions, the index scheduling mechanism needs to be deeply optimized in conjunction with the storage structure to achieve dynamic loading and efficient scheduling of sparse convolution kernels, thereby avoiding invalid computation of all-zero convolution kernels and maximizing the utilization of FPGA computing resources.

[0005] In terms of computational models, sparse convolutional layers need to be redesigned for high sparsity scenarios. Traditional parallel computing methods often fail to fully utilize computing resources under sparse conditions, potentially leading to resource idleness and wasted power. Therefore, a serial computation mode for the output channel becomes an effective solution for the hardware implementation of sparse convolutional kernels. By using a single MAC module to serially process sparse convolutional kernels, combined with an index scheduling module and zero-jump control logic, it is possible to significantly improve FPGA hardware utilization, reduce dynamic power consumption, and simplify the overall design complexity while ensuring computational efficiency.

[0006] Furthermore, to ensure the numerical accuracy of the model and the efficiency of hardware implementation, fixed-point quantization technology is widely used in FPGA design. By converting floating-point numbers to fixed-point numbers, not only can storage resources and computational complexity be reduced, but it can also better adapt to the hardware characteristics of FPGAs. However, fixed-point quantization also brings problems such as loss of numerical precision and overflow management, requiring careful design of bit width, shifting, and fixed-point format in the convolution calculation module to ensure the accuracy of inference results.

[0007] Despite existing research proposing various implementation schemes for sparse convolution accelerators, the following key challenges remain in practical hardware deployment:

[0008] (1) Insufficient optimization of storage and computation. Although existing methods emphasize the compressed storage of sparse weights, they fail to effectively solve the problems of index management and dynamic scheduling of sparse convolution kernels in hardware data streams, resulting in low data access efficiency and severely restricting overall performance.

[0009] (2) The sparse convolution kernel scheduling mechanism has defects. Due to the uneven distribution of sparsity in each layer after pruning, the existing solution is difficult to achieve efficient dynamic loading and fast switching of sparse convolution kernels under the constraint of limited storage resources of FPGA, forming a system performance bottleneck;

[0010] (3) Insufficient adaptability of MAC modules. Most studies still use the traditional multiply-accumulate computation unit architecture of dense matrices, lacking efficient integration schemes for zero-jumping optimization logic and activation units for sparse computation, resulting in low utilization of FPGA computing resources;

[0011] (4) There is a significant contradiction between FPGA resource constraints and algorithm requirements. Due to the limited DSP and BRAM resources of the FPGA platform, the existing architecture is unable to achieve efficient sparse convolution operations while ensuring computational accuracy, and there is an urgent need to develop more targeted hardware optimization design schemes. Summary of the Invention

[0012] The purpose of this invention is to propose a design method and system for an efficient FPGA accelerator based on sparse convolution kernels. Through multi-level collaborative optimization, it achieves high energy efficiency and low power consumption acceleration for deep learning inference.

[0013] According to a first aspect of the present disclosure, a method for designing an efficient FPGA accelerator based on sparse convolution kernels is provided, comprising the following steps:

[0014] Optimize sparse weight storage and management, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel;

[0015] Design sparse convolution kernel indexing and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanism;

[0016] Construct sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

[0017] In one embodiment, the sparse convolution kernel storage structure adopts a sparse storage format with row and column index encoding, which retains only non-zero weights and their corresponding position information, effectively eliminating the storage space occupied by a large number of zero values ​​generated after pruning, and avoiding invalid operations in subsequent calculation processes.

[0018] In one embodiment, the data organization scheme for the output channel optimization is as follows: based on the output channel priority index sorting mechanism, the convolution kernel data is reorganized according to the output channel dimension, while maintaining the correlation of the input channel dimension, so that the data arrangement matches the pipeline processing characteristics of the MAC module, and achieves efficient execution of sparse computing.

[0019] In one embodiment, the dynamic row coordinate index storage method is as follows: a dual register group architecture is adopted to record the output channel labels of the current cycle and the previous cycle respectively. In conjunction with the index management module, the convolution kernel index data and status information are stored and updated in real time. This scheme ensures that the dynamic index of sparse convolution kernels can achieve single-cycle response through a pipelined index management mechanism, which significantly improves the index query efficiency.

[0020] In one embodiment, the intelligent dynamic scheduling mechanism is as follows: construct an output channel label comparator and an auxiliary address mapping array, and trigger the preloading and seamless switching of convolutional kernel data by detecting output channel switching requests in real time, so as to ensure uninterrupted continuous execution.

[0021] In one embodiment, the serial computing architecture for the output channel is implemented as follows: first, the feature map data input to the sparse convolutional layer is preprocessed with zero padding, and then the feature map data is loaded into a single MAC module in an orderly manner according to the computing requirements through the channel selection module. The MAC module adopts a time-division multiplexing mechanism, and processes the sparse convolutional kernel corresponding to a single output channel in each clock cycle. This design not only ensures the computing accuracy, but also significantly improves the utilization of hardware resources.

[0022] In one embodiment, the MAC module integrates zero-jumping calculation logic at its front end to achieve intelligent detection of zero-value weights. The multiply-accumulate unit performs pipelined accumulation operations based on the product results output by the multiplier. Simultaneously, the completion status of effective convolution kernel operations in the output channel is monitored in real time through the calcu_finish status signal. The module is equipped with a ReLU6 activation unit at its end to ensure the calculation accuracy of nonlinear transformations. Through multiplexers and register arrays, the MAC module possesses the calculation capabilities of conventional convolution and the zero-jumping optimization characteristics in sparse computing scenarios, ultimately maximizing the utilization of computing resources.

[0023] According to a second aspect of the present disclosure, a high-efficiency FPGA accelerator design system based on sparse convolution kernels is provided, comprising:

[0024] The storage module optimizes the storage and management of sparse weights, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel.

[0025] The scheduling module designs sparse convolution kernel indexes and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanisms.

[0026] The computation module constructs sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

[0027] According to a third aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and running on the memory, wherein the processor executes the program to implement the aforementioned method for designing an efficient FPGA accelerator based on sparse convolution kernels.

[0028] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the aforementioned method for designing an efficient FPGA accelerator based on sparse convolution kernels.

[0029] The technical solution adopted in this invention has the following advantages compared with the prior art: This invention addresses the three major performance bottlenecks in FPGA hardware acceleration of deep convolutional neural networks (CNNs): sparse convolutional kernel storage redundancy, low computational resource utilization, and insufficient dynamic scheduling efficiency. Specifically:

[0030] 1. By coordinating the optimization of weight pruning and convolution kernel pruning, an efficient storage mechanism based on non-zero weights and their coordinates is established, which significantly reduces storage requirements and improves computational efficiency;

[0031] 2. Design a serial / parallel configurable computing mode for the output channel, and combine it with the time-division multiplexing technology of a single MAC module to achieve efficient utilization of FPGA logic resources;

[0032] 3. An optimization method combining zero-jump computation and fixed-point quantization is adopted to effectively reduce system power consumption while ensuring computational accuracy, thereby comprehensively improving energy efficiency ratio and inference speed. Attached Figure Description

[0033] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0034] Figure 1 This is a schematic diagram of the storage structure of sparse convolution kernels in a convolutional layer.

[0035] Figure 2 Design a schematic diagram of a row coordinate indexed storage structure for an FPGA;

[0036] Figure 3 Schematic diagram of the output channel tag comparator structure;

[0037] Figure 4 Implementation process diagram for the serial computing architecture of the output channel;

[0038] Figure 5 The schematic diagram for the optimized MAC module. Detailed Implementation

[0039] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0040] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0041] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0042] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and systems according to various embodiments of this disclosure. It should be noted that each block in a flowchart or block diagram may represent a module, segment, or portion of code, which may include one or more executable instructions for implementing the logical functions specified in the various embodiments. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutively represented blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, may be implemented using a dedicated hardware-based system that performs the specified functions or operations, or using a combination of dedicated hardware and computer instructions.

[0043] Example 1:

[0044] This embodiment provides a method for designing an efficient FPGA accelerator based on sparse convolution kernels, including the following steps:

[0045] Step 1. Optimize sparse weight storage and management

[0046] Step 1.1 Design a sparse convolution kernel storage structure to solve the problem of a large number of zero values ​​generated after pruning deep convolutional neural networks.

[0047] like Figure 1 As shown, the left half illustrates the connection relationship between the input and output channels in a convolutional layer. Each output channel corresponds to multiple input channel convolutional kernels. After pruning, some convolutional kernels input to the output channel have all-zero weights (all-zero kernels), and these invalid kernels can be skipped directly in hardware computation. The remaining non-zero kernels are compressed and stored in dedicated memory for subsequent convolutional computations. This design effectively improves storage efficiency and computational performance by distinguishing between zero-value and non-zero-value convolutional kernels.

[0048] Step 1.2 employs a data organization scheme optimized for output channels, which arranges sparse convolutional kernels in a structured manner according to Row (output channel label) and Col (input channel label). This storage scheme is highly compatible with the hardware pipeline architecture: during MAC operations, the Row-Col dual-index mechanism can quickly locate and extract the corresponding input feature map data, realizing the pipelined execution of multiply-accumulate operations, thereby ensuring efficient processing of sparse computation. This design significantly improves data access efficiency, enabling the computing unit to maintain high throughput continuously.

[0049] Step 2. Design sparse convolution kernel index and scheduling method

[0050] Step 2.1 Dynamic row coordinate index storage is used to implement row coordinate management and fast indexing of sparse convolution kernels, effectively avoiding invalid convolution operations in hardware.

[0051] like Figure 1 As shown, it stores the output channel labels (Row coordinates) of the convolutional kernels in the current and previous cycles through the `mask_row_pre` and `mask_row_pre_last` registers, respectively, and compares and detects the switching status of the output channels in real time. When a change in the output channel is detected, the `mask_row_pre_last_index` register automatically saves the convolutional kernel index of the previous output channel, ensuring that the MAC module can seamlessly load the convolutional kernel data of the new row coordinates. In addition, it also includes storage units such as `out_ch_num` (array), `out_ch_mask` (array), `out_ch_mask_compare`, and `out_ch_loss` (array), which record the number of convolutional kernels, channel labels, and comparison results of each output channel, respectively. This mechanism realizes efficient indexing of sparse convolutional kernels and intelligent switching of output channels, significantly improving hardware processing efficiency while avoiding redundant calculations of all-zero convolutional kernels.

[0052] Step 2.2 Intelligent dynamic scheduling mechanism, which efficiently records the index information of sparse convolution kernels to support hardware scheduling.

[0053] Figure 3As shown, in this mechanism, the mask_row_pre register records the row coordinates of the convolution kernels processed in the current clock cycle, while the mask_row_pre_last register stores the row coordinate information of the previous clock cycle. Through real-time comparison of these two registers, the hardware can accurately determine whether to switch to the next output channel (Row label). When a change in the output channel is detected, the out_ch_num array immediately updates the sparse convolution kernel count information of the current output channel (e.g., out_ch_num[1] = 2, out_ch_num[2] = 6, out_ch_num[3] = 9), providing the MAC module with accurate convolution kernel distribution data. At the same time, the out_ch_mask array completely saves the output channel label information and works in conjunction with the out_ch_mask_compare module to realize the dynamic discrimination of output channel switching. The out_ch_loss array records the status information of each channel to ensure the orderly loading of convolution kernels. This design enables the MAC module to intelligently skip all-zero convolution kernels, realize efficient scheduling and continuous calculation of sparse convolution kernels, thereby significantly improving hardware processing efficiency.

[0054] Step 3. Construct sparse convolutional layers

[0055] Step 3.1 Output channel serial computing architecture enables efficient processing of sparse convolutional layers and effectively avoids the waste of a large number of zero-value calculations caused by the high sparsity of weights after pruning.

[0056] like Figure 4 As shown, this architecture first performs zero-padding preprocessing on the input data of the sparse convolutional layers. Then, through precise control of the channel select module, the input feature map data is loaded sequentially into a single MAC module according to computational requirements. This MAC module employs a time-division multiplexing mechanism, focusing on processing the sparse convolutional kernel corresponding to a single output channel each clock cycle. It dynamically schedules non-zero weights through an intelligent multiplexer, sequentially performing multiplication-accumulation operations and ReLU6 activation. This serial output channel processing architecture requires only a single MAC module to complete the computation of all output channels, significantly reducing the FPGA's logic resources and DSP occupancy. In particular, this serial output channel computation architecture works deeply with the aforementioned index scheduling mechanism, dynamically managing the loading of sparse convolutional kernels for output channels through real-time index information, intelligently avoiding invalid computations of all-zero convolutional kernels. This significantly improves the overall computational efficiency of the sparse CNN model on the FPGA platform while ensuring computational accuracy.

[0057] Step 3.2's optimized MAC module includes core components such as a 16-bit multiplier, a 16-bit adder, an accumulator register, a ReLU6 activation unit, and zero-jump control logic. For example... Figure 5As shown, the specific implementation scheme of the MAC module is as follows:

[0058] (1) Zero-jumping computation optimization: The zero-value state of the input feature map data and the convolution kernel weights is detected in parallel through AND logic gates. When any input is zero, the multiplier enable signal is immediately turned off to avoid invalid computation from the source.

[0059] (2) Fixed-point multiplication and addition: A 16-bit multiplier generates a 32-bit product result, and a 12-bit arithmetic right shift operation is used to achieve precise decimal point alignment. Subsequently, the shifted product value and the intermediate result stored in the accumulator register are accumulated by a 16-bit adder, supporting pipelined execution of continuous multiplication and addition operations. In particular, during the first output stage of the convolution kernel, the module selector automatically feeds the pre-stored bias value directly into the adder to ensure that the bias term is accurately superimposed on each output channel at the end of the convolution calculation cycle, thereby ensuring the theoretical correctness of the neural network calculation. This design maximizes computational efficiency while maintaining numerical accuracy through bit width optimization and pipeline coordination.

[0060] (3) Intelligent state detection: The effective convolution kernel operation status of the output channel is monitored in real time through the calcu_finish signal. When the signal detects that all convolution kernels in the current channel are zero, the optimized calculation path is immediately started: the multiplexer is controlled to directly output the preset bias value to the accumulator register, which completely avoids the waste of computing resources caused by invalid multiplication and addition operations in the traditional architecture, and ensures that the computing efficiency is maximized while maintaining the computing accuracy.

[0061] (4) Nonlinear activation processing: The ReLU6 activation unit uses a 16-bit fixed-point number to implement the nonlinear activation function. This module compares the accumulated result with two thresholds, 0 and 6, in real time through a parallel comparator: when the input value is less than 0, the output is forced to be 0; when it is greater than 6, the output is limited to 6; otherwise, the original value is maintained. This hardware-based threshold limiting mechanism ensures that the output data range conforms to the quantization specification requirement of [0,6], achieving the nonlinear expressive capability of the neural network while adapting to the fixed-point number computation architecture.

[0062] (5) Dual-mode computing support: The MAC module maintains the complete functionality of conventional convolution operations while implementing zero-jumping optimization in sparse computing scenarios through the coordinated control of multiplexers and registers. This dual-mode computing mechanism optimizes the utilization of FPGA computing resources while ensuring computational accuracy through dynamic reuse of hardware resources.

[0063] Example 2:

[0064] This embodiment provides a high-efficiency FPGA accelerator design system based on sparse convolution kernels, including:

[0065] The storage module optimizes the storage and management of sparse weights, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel.

[0066] The scheduling module designs sparse convolution kernel indexes and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanisms.

[0067] The computation module constructs sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

[0068] Example 3:

[0069] An electronic device includes a memory, a processor, and a computer program stored in the memory and running thereon. When the processor executes the program, it implements the aforementioned method for designing a high-efficiency FPGA accelerator based on sparse convolution kernels, comprising:

[0070] Optimize sparse weight storage and management, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel;

[0071] Design sparse convolution kernel indexing and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanism;

[0072] Construct sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

[0073] Example 4:

[0074] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned method for designing an efficient FPGA accelerator based on sparse convolution kernels, comprising:

[0075] Optimize sparse weight storage and management, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel;

[0076] Design sparse convolution kernel indexing and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanism;

[0077] Construct sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

[0078] Those skilled in the art will understand that the modules or steps described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, which can then be stored in a storage device for execution by a computer device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. This disclosure is not limited to any particular combination of hardware and software.

[0079] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0080] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A method for designing a high-efficiency FPGA accelerator based on sparse convolution kernels, characterized in that, Includes the following steps: Optimize sparse weight storage and management, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel; Design sparse convolution kernel indexing and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanism; Construct sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

2. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The sparse convolution kernel storage structure adopts a sparse storage format with row and column index encoding, retaining only non-zero weights and their corresponding position information.

3. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The optimized data organization scheme for the output channel is as follows: based on the output channel-priority index sorting mechanism, the convolution kernel data is reorganized according to the output channel dimension, while maintaining the correlation of the input channel dimension, so that the data arrangement matches the pipeline processing characteristics of the MAC module.

4. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The dynamic row coordinate index storage method is as follows: a dual register group architecture is adopted to record the output channel labels of the current period and the previous period respectively, and the index management module is used to realize the real-time storage and updating of convolution kernel index data and status information.

5. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The intelligent dynamic scheduling mechanism is as follows: construct an output channel label comparator and an auxiliary address mapping array, and trigger the preloading and seamless switching of convolutional kernel data by detecting output channel switching requests in real time.

6. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The serial computing architecture for the output channel is implemented as follows: First, the feature map data input to the sparse convolutional layer is preprocessed with zero padding. Then, the feature map data is loaded into a single MAC module in an orderly manner according to the computing requirements through the channel selection module. The MAC module adopts a time-division multiplexing mechanism, and processes the sparse convolutional kernel corresponding to a single output channel in each clock cycle.

7. The FPGA high-efficiency accelerator design method based on sparse convolution kernels according to claim 1, characterized in that, The MAC module integrates zero-jumping calculation logic at its front end to achieve intelligent detection of zero-value weights. The multiply-accumulate unit performs pipelined accumulation operations based on the product results output by the multiplier. Simultaneously, the completion status of effective convolution kernel operations in the output channel is monitored in real time through the calcu_finish status signal. The module is equipped with a ReLU6 activation unit at its end to ensure the calculation accuracy of nonlinear transformations. Through multiplexers and register arrays, the MAC module has the calculation capabilities of conventional convolution and zero-jumping optimization characteristics in sparse computing scenarios.

8. A high-efficiency FPGA accelerator design system based on sparse convolution kernels, characterized in that, include: The storage module optimizes the storage and management of sparse weights, including designing a sparse convolution kernel storage structure and adopting a data organization scheme optimized for the output channel. The scheduling module designs sparse convolution kernel indexes and scheduling methods, including dynamic row coordinate index storage and intelligent dynamic scheduling mechanisms. The computation module constructs sparse convolutional layers, including an output channel serial computation architecture and an optimized MAC module.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and running thereon, wherein the processor executes the program to implement the FPGA high-efficiency accelerator design method based on sparse convolution kernels as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the FPGA high-efficiency accelerator design method based on sparse convolution kernels as described in any one of claims 1-7.

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