Shielding counting statistical system and method, graphics processor and electronic equipment

Abstract

The invention relates to the technical field of graphics processors, and provides an occlusion counting statistical system and method, a graphics processor and electronic equipment. According to the system, a first cache is shared by a plurality of cores, the first cache is arranged outside the cores and comprises a first buffer area, and any one core is used for performing depth detection on a primitive input into the core to obtain a shielding count of the primitive, generating a first write request and transmitting the first write request to the first cache; and the first cache is used for operating the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, and writing the occlusion count obtained by operation into the address included in the first write request. According to the embodiment of the invention, any one core can update the shielding count stored in the first cache through the first write request after obtaining the shielding count, and shielding count statistics does not need to be started after rendering of all cores is finished, so that the delay between the time for obtaining the final shielding count and the time for finishing rendering is reduced, and the performance of the GPU is improved.

Description

Technical Field

[0001] This disclosure relates to the field of graphics processor technology, and in particular to an occlusion counting system, method, graphics processor, and electronic device. Background Technology

[0002] In the field of Graphics Processing Unit (GPU) technology, when rendering a 3D scene as a 2D image, some primitives may be occluded by other primitives. Whether a primitive is occluded depends on the depth of its pixels or sampling points. When a pixel or sampling point is covered by two primitives simultaneously, if the first primitive has a lower depth value at that pixel or sampling point, and the second primitive has a higher depth value, then for that pixel, the second primitive will be occluded by the first primitive. The occluded portion does not actually need to be drawn. Therefore, in the GPU rendering pipeline, during depth testing, occlusion counts are usually also performed. These occlusion counts are used to determine whether a primitive is completely occluded so that it can be culled or retained in subsequent rendering processes.

[0003] In existing technologies, multi-core GPUs perform occlusion counting by using firmware to obtain the occlusion counts stored in each core after all cores have finished rendering, and then summing these counts to obtain the final occlusion count. Because the computation and data transfer operations are time-consuming, there is a significant delay between obtaining the final occlusion count and the end of rendering, which reduces GPU performance. How to reduce the delay between obtaining the final occlusion count and the end of rendering, thereby improving GPU performance, has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] In view of this, this disclosure proposes an occlusion counting system, method, graphics processor, and electronic device. This system, by setting up a first cache shared by multiple cores outside the cores, allows any core to update the occlusion count stored in the first cache via a first write request after obtaining the occlusion count, without waiting for all cores to finish rendering before starting occlusion counting. This reduces the latency between obtaining the final occlusion count and the end of rendering, thereby improving GPU performance.

[0005] According to one aspect of this disclosure, an occlusion counting system is provided. The system is disposed in a graphics processor and includes multiple cores and a first cache shared by the multiple cores. The first cache is disposed outside the cores and includes a first buffer for counting occlusion. Any core is configured to perform depth detection on a primitive input to itself to obtain an occlusion count for that primitive, generate a first write request including the occlusion count and an address of the first buffer, and transmit the first write request to the first cache. The first cache is configured to, in response to the first write request from any core, perform calculations on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the calculated occlusion count to the address included in the first write request, and overwrite the occlusion count originally stored at that address.

[0006] In one possible implementation, the core includes at least one processing unit and a second cache. Any processing unit is configured to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the second cache in the core. The second cache is configured to forward the first write request from any processing unit to the first cache.

[0007] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The i-th first position corresponds to the i-th occlusion counting round. N is a positive integer, 0 < i ≤ N and is an integer. Any processing unit is specifically used to perform depth detection on the input primitive in the i-th occlusion counting round to obtain the occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position.

[0008] In one possible implementation, the core includes at least one processing unit and a second cache. The second cache includes a second buffer for counting occlusion. Any processing unit is configured to perform depth detection on its own primitives to obtain the occlusion count of the primitives, generate a second write request including the occlusion count and the address of the second buffer in the core, and transmit the second write request to the second cache in the core. The second cache is configured to, in response to the second write request from any processing unit, perform calculations on the occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, write the calculated occlusion count to the address included in the second write request and overwrite the occlusion count originally stored at that address; and, in response to the end of rendering in the core, generate a first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer, and transmit the first write request to the first cache.

[0009] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The second buffer includes N second positions, and the address of the second buffer includes the addresses of the N second positions. The i-th second position of each core corresponds to the i-th first position and the i-th occlusion count round. N is a positive integer, 0 < i ≤ N and is an integer. Any processing unit is specifically used to perform depth detection on the input primitive in the i-th occlusion count round to obtain the occlusion count of the primitive, and generate a second write request including the occlusion count and the address of the i-th second position in the core. The second buffer is specifically used to generate a first write request including the occlusion count stored at the address of the i-th second position and the address of the i-th first position in response to the end of rendering of the core.

[0010] In one possible implementation, any processing unit is specifically configured to rasterize the input primitive itself, determine the pixels or sampling points covered by the primitive, calculate the depth value of the pixel or the sampling point, and increment the occlusion count of the primitive by one for each pixel or sampling point whose depth value is greater than a preset threshold.

[0011] In one possible implementation, the first cache is specifically used to, in response to a first write request from any core, perform an atomic operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request; and through an atomic write operation, write the operation result to the address included in the first write request and overwrite the occlusion count originally stored at that address.

[0012] In one possible implementation, the first write request further includes an operation type, which includes any one of addition, subtraction, multiplication, division, finding the maximum value, and finding the minimum value.

[0013] In one possible implementation, the system further includes memory, the first buffer corresponds to a preset storage area on the memory, and the first buffer is further configured to write the occlusion count stored in the first buffer into the preset storage area after confirming that the occlusion count has been completed.

[0014] According to another aspect of this disclosure, an occlusion counting method is provided, the method being applied to an occlusion counting system, the system being configured in a graphics processor, the system including multiple cores and a first cache shared by the multiple cores, the first cache being configured outside the cores and including a first buffer for counting occlusions, the method comprising: any core performing depth detection on a primitive input to itself to obtain an occlusion count for the primitive, generating a first write request including the occlusion count and an address of the first buffer, and transmitting the first write request to the first cache; the first cache responding to the first write request from any core performing a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, writing the calculated occlusion count to the address included in the first write request and overwriting the occlusion count originally stored at that address.

[0015] In one possible implementation, the core includes at least one processing unit and a second cache. Each core performs depth detection on its own input primitives to obtain an occlusion count for the primitives, generates a first write request including the occlusion count and the address of the first buffer, and transmits the first write request to the first cache. This includes: each processing unit performing depth detection on its own input primitives to obtain an occlusion count for the primitives, generating a first write request including the occlusion count and the address of the first buffer, and transmitting the first write request to the second cache in its core; the second cache forwards the first write request from any processing unit to the first cache.

[0016] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The i-th first position corresponds to the i-th occlusion counting round. N is a positive integer, 0 < i ≤ N and is an integer. Any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive and generates a first write request including the occlusion count and the address of the first buffer. This includes: in the i-th occlusion counting round, any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive and generates a first write request including the occlusion count and the address of the i-th first position.

[0017] In one possible implementation, the core includes at least one processing unit and a second cache. The second cache includes a second buffer for counting occlusion. Each core performs depth detection on its own primitives to obtain an occlusion count, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the first cache. This includes: each processing unit performing depth detection on its own primitives to obtain an occlusion count, generating a second write request including the occlusion count and an address of the second buffer in its core, and transmitting the second write request to the second cache in its core; the second cache, in response to the second write request from any processing unit, performs a calculation on the occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, writes the calculated occlusion count to the address included in the second write request, and overwrites the occlusion count originally stored at that address; in response to the end of rendering in its core, it generates a first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer, and transmits the first write request to the first cache.

[0018] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The second buffer includes N second positions, and the address of the second buffer includes the addresses of the N second positions. The i-th second position of each core corresponds to the i-th first position and the i-th occlusion count counting round. N is a positive integer, 0 < i ≤ N, and is an integer. Each processing unit performs depth detection on its own primitive to obtain the occlusion count of the primitive, and generates a location including the occlusion count and the second buffer in the core. The second write request for the address includes: any processing unit, in the i-th occlusion counting round, performs depth detection on its own primitive to obtain the occlusion count of the primitive, and generates a second write request including the occlusion count and the address of the i-th second position in the core; the first write request generated in response to the end of rendering of the core includes: in response to the end of rendering of the core, generating a first write request including the occlusion count stored at the address of the i-th second position and the address of the i-th first position.

[0019] In one possible implementation, any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive, including: rasterizing the input primitive to determine the pixels or sampling points covered by the primitive; calculating the depth value of the pixel or the sampling point, and incrementing the occlusion count of the primitive by one for each pixel or sampling point whose depth value is greater than a preset threshold.

[0020] In one possible implementation, the first cache, in response to a first write request from any core, performs a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, including: the first cache, in response to a first write request from any core, performs an atomic operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request; and through an atomic write operation, writes the calculation result to the address included in the first write request and overwrites the occlusion count originally stored at that address.

[0021] In one possible implementation, the first write request further includes an operation type, which includes any one of addition, subtraction, multiplication, division, finding the maximum value, and finding the minimum value.

[0022] In one possible implementation, the system further includes memory, the first buffer corresponding to a preset storage area on the memory, and the method further includes: after confirming that the occlusion count has been completed, the first buffer writes the occlusion count stored in the first buffer into the preset storage area.

[0023] According to another aspect of this disclosure, a graphics processor is provided, including the occlusion counting system described above.

[0024] According to another aspect of this disclosure, an electronic device is provided, including the graphics processor described above.

[0025] According to the occlusion counting system of this disclosure, a first cache shared by multiple cores is set up outside of multiple cores. The first cache includes a first buffer for counting occlusions, so that the occlusion count obtained by each core can be directly calculated with the occlusion count stored in the first cache. Any core is used to perform depth detection on its own primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the first cache. The first cache can determine the two source operands to be calculated and the storage address of the destination operand based on the first write request. The first cache is used to respond to the first write request from any core, calculate the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the calculated occlusion count to the address included in the first write request and overwrite the occlusion count originally stored at that address. Therefore, the occlusion count of each core can be counted without firmware. According to this system, once the occlusion count is obtained on any core, the occlusion count stored in the first cache can be updated through the first write request, without having to wait for all cores to finish rendering before starting the occlusion count statistics. This reduces the latency between obtaining the final occlusion count and the end of rendering, thereby improving GPU performance.

[0026] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0028] Figure 1 This diagram illustrates the use of an occlusion counter to determine the number of occluded pixels.

[0029] Figure 2 A schematic diagram of a prior art occlusion counting statistical method is shown.

[0030] Figure 3a This illustrates an exemplary application scenario of the occlusion counting system according to embodiments of the present disclosure.

[0031] Figure 3b This illustrates an exemplary application scenario of the occlusion counting system according to embodiments of the present disclosure.

[0032] Figure 4 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0033] Figure 5 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0034] Figure 6 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0035] Figure 7 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0036] Figure 8 A schematic diagram illustrating the flow of an occlusion counting method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0037] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0038] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0039] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0040] The occlusion count requires the use of an occlusion counter. The principle of the occlusion counter is explained below. Figure 1 This diagram illustrates the use of an occlusion counter to determine the number of occluded pixels.

[0041] like Figure 1As shown, the depth buffer stores the depth values ​​of pixels (or sampling points). Before depth detection begins, the depth values ​​of each pixel (or sampling point) stored in the depth buffer can be default initial values. The occlusion counter buffer stores the occlusion count, that is, the number of occluded pixels (or sampling points). Before occlusion counting begins, the occlusion count stored in the occlusion counter buffer can be 0x0000.

[0042] Depth detection identifies which pixels (or sampling points) a primitive covers and the depth values ​​of those covered pixels (or sampling points). If the depth value of the primitive at any pixel (or sampling point) is greater than the depth value of that pixel (or sampling point) stored in the depth buffer, then the pixel (or sampling point) is considered to have passed depth detection. The depth value of the corresponding pixel (or sampling point) in the depth buffer is updated to the depth value of the primitive at that pixel (or sampling point), and the number of pixels (or sampling points) that have passed depth detection is added to the occlusion count stored in the occlusion counter buffer. If the primitive does not cover any pixels (or sampling points), or if the depth value of every pixel (or sampling point) covered by the primitive is less than the depth value of that pixel stored in the depth buffer, then the primitive is considered to have no pixels (or sampling points) that have passed depth detection. The depth buffer and the occlusion counter buffer will not be updated.

[0043] See Figure 1 Assuming the initial depth value of each pixel in the depth buffer is 0.1 before the depth test, and the depth value of all pixels covered by primitive A is 1.0, which is greater than the initial value of 0.1, therefore, no pixels of primitive A pass the depth test. After the depth test, neither the depth buffer nor the occlusion counter buffer is updated. The depth value of all pixels covered by primitive B is 0.0, which is less than the initial value of 0.1. Therefore, all 24 pixels covered by primitive B pass the depth test. After the depth test, the depth values ​​corresponding to the 24 pixels covered by primitive B in the depth buffer are updated to 0.0, and the occlusion count stored in the occlusion counter buffer is updated to 0x0024.

[0044] Figure 2 A schematic diagram of the occlusion counting statistics method of the related technology is shown.

[0045] like Figure 2As shown, in existing multi-core GPU implementations of occlusion counting, a buffer needs to be allocated in the cache of each core to store the occlusion count of primitives rendered by that core. During rendering, multiple processing units within each core update the occlusion count stored in the cache of their respective core. After all cores have finished rendering, the firmware obtains the occlusion counts stored in each core, sums them, obtains the final occlusion count, and then reports it to the application programming interface (API).

[0046] The drawbacks of the occlusion counting methods in related technologies are as follows: First, the calculation is performed by the firmware, which involves more complex data transfer from the core to the firmware, resulting in significant computation time. Furthermore, firmware calculation only begins after all core rendering is complete, leading to a substantial delay between obtaining the final occlusion count and the end of rendering, thus reducing GPU performance. Second, a buffer is allocated on the cache within each core. When there are N rounds of occlusion counting, each buffer needs to include N occlusion count storage locations, increasing the hardware logic for managing the buffers and consuming more virtual address space. Third, the system also includes memory. The cache within the core is designed to speed up core access to memory. When allocating buffers in the core cache, a mapping relationship between the buffer and memory needs to be established, with each buffer needing to be mapped to an independent storage area in memory. When there are N rounds of occlusion counting, each independent storage area needs to include N occlusion count storage locations, resulting in high memory resource utilization.

[0047] In view of this, this disclosure proposes an occlusion counting system, method, graphics processor, and electronic device. This system, by setting up a first cache shared by multiple cores outside the cores, allows any core to update the occlusion count stored in the first cache via a first write request after obtaining the occlusion count, without waiting for all cores to finish rendering before starting occlusion counting. This reduces the latency between obtaining the final occlusion count and the end of rendering, thereby improving GPU performance.

[0048] Furthermore, the occlusion count obtained by any processing unit in the core of this system can be directly calculated with the occlusion count stored in the first cache, without needing to store it in the core cache. Therefore, there is no need to allocate a buffer in the core for storing occlusion counts, simplifying the hardware logic for managing the buffer and reducing the use of virtual address space. The total space for storing occlusion counts in the first cache is much smaller than the total space of the buffers allocated in the caches of each core in related technologies. Therefore, less space needs to be reserved in memory, resulting in less memory resource consumption.

[0049] Figure 3a and Figure 3b This illustrates an exemplary application scenario of the occlusion counting system according to embodiments of the present disclosure.

[0050] like Figure 3a As shown, the electronic device may include a CPU and a GPU. The GPU is equipped with an occlusion counting system, and the CPU runs software that requires image rendering.

[0051] like Figure 3b As shown, before starting primitive rendering, the software first creates an occlusion counting task on the CPU and drives the GPU to allocate a buffer (such as the first buffer described below) to store the occlusion counts. Then, the software submits a rendering command (Render Cmd), which is transmitted to the GPU and executed by the GPU. During the rendering process, depth detection is completed. At the same time, the occlusion counting system is also responsible for performing the occlusion counting task, counting the occlusion counts, and storing them in the allocated buffer. Finally, after the occlusion counting task is completed, the occlusion counting system reports the final occlusion count to the software via API. The software then determines whether the rendered primitive is completely occluded so that it can be removed or retained in subsequent rendering processes.

[0052] Figure 4 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0053] like Figure 4 As shown, in one possible implementation, this disclosure proposes an occlusion counting system, which is set in a graphics processing unit (GPU). The system includes multiple cores and a first cache shared by the multiple cores. The first cache is located outside the cores and includes a first buffer for counting occlusions.

[0054] Any core is used to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the first buffer;

[0055] The first cache is used to, in response to a first write request from any core, perform a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the calculated occlusion count to the address included in the first write request and overwrite the occlusion count originally stored at that address.

[0056] For example, a system may include multiple cores, each capable of rendering primitives. Therefore, while the graphics processor renders the primitives, each core can perform depth detection on the primitives it inputs. During depth detection, an occlusion counter is used to obtain the occlusion count of the primitives. The occlusion count can represent the number of occluded pixels or sampling points. The method for obtaining the occlusion count by performing depth detection on primitives is described in... Figure 1 As already described, I will not repeat it here.

[0057] Since the occlusion count is ultimately stored in the first buffer of the first cache, any core, after obtaining the occlusion count, can generate a first write request that includes the occlusion count and the address of the first buffer, and then transfer the first write request to the first cache. Details of generating and transferring the first write request are given later.

[0058] Upon receiving a first write request from any core, the first cache can determine that the occlusion count included in the first write request is one source operand to be used in the operation, the occlusion count stored at the address included in the first write request is another source operand to be used in the operation, and the address where the destination operand is stored is the address included in the first write request. The first cache can perform the operation on the two source operands, write the resulting occlusion count (i.e., the destination operand) to the address included in the first write request, and overwrite the occlusion count originally stored at that address. The operation details of the first cache and the details of writing the occlusion count to the first buffer are given later.

[0059] In this scenario, as each core continuously sends the first write request to the first buffer, the occlusion count stored in the first buffer will be continuously updated until the first buffer completes the response to the first write requests from all cores. At this point, the occlusion count stored in the first buffer will be the final occlusion count.

[0060] According to the occlusion counting system of this disclosure, a first cache shared by multiple cores is set up outside of multiple cores. The first cache includes a first buffer for counting occlusions, so that the occlusion count obtained by each core can be directly calculated with the occlusion count stored in the first cache. Any core is used to perform depth detection on its own primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the first cache. The first cache can determine the two source operands to be calculated and the storage address of the destination operand based on the first write request. The first cache is used to respond to the first write request from any core, calculate the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the calculated occlusion count to the address included in the first write request and overwrite the occlusion count originally stored at that address. Therefore, the occlusion count of each core can be counted without firmware. According to this system, once the occlusion count is obtained on any core, the occlusion count stored in the first cache can be updated through the first write request, without having to wait for all cores to finish rendering before starting the occlusion count statistics. This reduces the latency between obtaining the final occlusion count and the end of rendering, thereby improving GPU performance.

[0061] In one possible implementation, the first cache is specifically used for,

[0062] In response to a first write request from any core, perform atomic operations on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request.

[0063] The atomic write operation writes the result of the operation to the address included in the first write request and overwrites the occlusion count originally stored at that address.

[0064] For example, the first cache will successively receive first write requests from different cores. If the next first write request is executed before the previous one has finished, it will disrupt data consistency and lead to inaccurate calculation results. Global atomic operations, however, are uninterrupted; therefore, the first cache can be configured to respond to first write requests in an atomic manner by default. That is, upon receiving a first write request, the first cache can perform atomic operations and write and overwrite the result through atomic write operations.

[0065] In this scenario, once the first cache begins responding to any first write request, it will not respond to any other first write requests until the first write request has been completed (i.e., the calculation result is stored in the address included in the first write request), thereby ensuring the accuracy of the calculation result.

[0066] For example, the first write request may also carry an atomic operation identifier. In this case, the first cache can determine that the response to the first write request should be performed atomically based on the identifier carried by the first write request. This disclosure does not limit whether the first write request must carry an atomic operation identifier.

[0067] In one possible implementation, the first write request further includes an operation type, which may include any one of addition, subtraction, multiplication, division, finding the maximum value, or finding the minimum value. When responding to the first write request, the operation is performed according to the operation type included in the first write request. Those skilled in the art will understand that the operation type may also include more types, such as logical AND, logical OR, etc. This disclosure does not limit the operation types that the cache can support.

[0068] The following is an example of how the core of this disclosure generates and transmits the first write request.

[0069] Figure 5 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0070] like Figure 5 As shown, in one possible implementation, the core includes at least one processing unit and a second cache.

[0071] Any processing unit is used to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the second buffer in the core.

[0072] The second cache is used to forward the first write request from any processing unit to the first cache.

[0073] For example, a single core may include multiple processing units, each of which independently renders primitives; that is, it performs depth detection on the primitives it takes as input to obtain the occlusion count of those primitives. In this case, each processing unit may generate a first write request that includes its own obtained occlusion count and the address of a first buffer.

[0074] The core may also include a second cache for interaction between in-core and out-of-core objects. For example, a processing unit can transfer a first write request to a second cache within its core. The second cache then forwards the received first write request to the first cache.

[0075] In this scenario, the second cache only needs to forward the first write request; it does not need to store the occlusion count. Therefore, there is no need to allocate a buffer on the second cache for storing the occlusion count, simplifying the hardware logic for managing the buffer and reducing the use of virtual address space. Furthermore, the occlusion count obtained by each processing unit is calculated in real-time against the occlusion count stored in the first cache. Thus, by the end of rendering, the final occlusion count is also calculated, significantly reducing the latency between obtaining the final occlusion count and the end of rendering, greatly improving GPU performance.

[0076] The occlusion counting system disclosed herein also supports multiple rounds of occlusion counting based on user needs. Figure 6 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0077] like Figure 6 As shown, in one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of N first positions. The i-th first position corresponds to the i-th occlusion counting round, where N is a positive integer, 0 < i ≤ N, and is an integer.

[0078] Any processing unit is specifically used to perform depth detection on the input primitive in the i-th occlusion counting round to obtain the occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position.

[0079] For example, the user can pre-set the total number of occlusion counts, such as N. Correspondingly, the first buffer can be divided into N first slots, and the address of the first buffer can include the addresses of the N first slots. The i-th first slot corresponds to the i-th occlusion count round, can be used in the i-th occlusion count round, and is used to store the occlusion count obtained in the i-th occlusion count round.

[0080] For example, any processing unit is specifically used to, in the i-th occlusion counting round, perform depth detection on the input primitive to obtain the occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position. In the i-th occlusion counting round, after the first cache receives the first write request, it performs a calculation on the occlusion count stored at the i-th first position and the occlusion count included in the first write request, and the calculation result is also written to the i-th first position.

[0081] In other words, in the first round of occlusion counting, all first write requests include the address of the first first position s1, and other first positions are not used in the first round of occlusion counting; in the second round of occlusion counting, all first write requests include the address of the second first position s2, and other first positions are not used in the second round of occlusion counting; ...; in the Nth round of occlusion counting, all first write requests include the address of the Nth first position sN, and other first positions are not used in the Nth round of occlusion counting. After N rounds of occlusion counting, the N first positions store the occlusion counts obtained from the N rounds of occlusion counting, respectively.

[0082] In this way, the occlusion counting system disclosed herein can support multiple rounds of occlusion counting during a single rendering process, thereby improving the capabilities of the occlusion counting system.

[0083] In one possible implementation, any processing unit is specifically used for,

[0084] Rasterize the input primitives themselves to determine the pixels or sampling points covered by the primitives;

[0085] Calculate the depth value of a pixel or sampling point. For each pixel or sampling point whose depth value is greater than a preset threshold, increment the occlusion count of the primitive by one.

[0086] For details on how the processing unit calculates the occlusion count, please refer to [link / reference]. Figure 1 The relevant descriptions will not be repeated here. It should be understood that the method by which each processing unit calculates the occlusion count should be consistent, for example, by comparing the depth value of the pixel with a preset threshold, or by comparing the depth value of the sample point with a preset threshold.

[0087] Figure 7 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0088] like Figure 7 As shown, in one possible implementation, the system further includes memory, a first buffer corresponding to a preset storage area in memory, and the first buffer is also used to write the occlusion count stored in the first buffer into the preset storage area after confirming that the occlusion count has been completed.

[0089] For example, the system may also include memory, with a first cache set up to speed up memory access. The first buffer corresponds to a preset storage area in memory; the first buffer can be mapped to the preset storage area. The first buffer and the preset storage area can have the same size, meaning the preset storage area also includes N occlusion count storage locations. When the user presets the total number of occlusion counts to N, the occlusion count is considered complete after the Nth round of occlusion count statistics. After confirming the completion of the occlusion count statistics, the first cache can write the occlusion counts stored in the first buffer to the preset storage area.

[0090] Those skilled in the art will understand that, in practical applications, the first cache can write the occlusion count to the preset storage area at more times, for example, once after each round of occlusion count statistics. This disclosure does not limit the frequency or timing of the first cache writing data to memory.

[0091] In this case, only N occlusion counting positions need to be reserved in memory to complete the occlusion counting, reducing the use of memory resources.

[0092] This disclosure also provides a method for counting and statistically analyzing occlusion. Figure 8 A schematic diagram illustrating the flow of an occlusion counting method according to an embodiment of the present disclosure is shown.

[0093] like Figure 8 As shown, in one possible implementation, the method is applied to an occlusion counting system, the system being configured in a graphics processor, the system including multiple cores and a first cache shared by the multiple cores, the first cache being located outside the cores and including a first buffer for counting occlusions, the method comprising:

[0094] Step S71: Any core performs depth detection on the primitives input to itself to obtain the occlusion count of the primitives, generates a first write request including the occlusion count and the address of the first buffer, and transmits the first write request to the first buffer.

[0095] In step S72, the first cache responds to a first write request from any core by performing a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, and writes the calculated occlusion count to the address included in the first write request and overwrites the occlusion count originally stored at that address.

[0096] In one possible implementation, the core includes at least one processing unit and a second cache. Each core performs depth detection on its own input primitives to obtain an occlusion count for the primitives, generates a first write request including the occlusion count and the address of the first buffer, and transmits the first write request to the first cache. This includes: each processing unit performing depth detection on its own input primitives to obtain an occlusion count for the primitives, generating a first write request including the occlusion count and the address of the first buffer, and transmitting the first write request to the second cache in its core; the second cache forwards the first write request from any processing unit to the first cache.

[0097] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The i-th first position corresponds to the i-th occlusion counting round. N is a positive integer, 0 < i ≤ N and is an integer. Any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive and generates a first write request including the occlusion count and the address of the first buffer. This includes: in the i-th occlusion counting round, any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive and generates a first write request including the occlusion count and the address of the i-th first position.

[0098] In one possible implementation, the core includes at least one processing unit and a second cache. The second cache includes a second buffer for counting occlusion. Each core performs depth detection on its own primitives to obtain an occlusion count, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the first cache. This includes: each processing unit performing depth detection on its own primitives to obtain an occlusion count, generating a second write request including the occlusion count and an address of the second buffer in its core, and transmitting the second write request to the second cache in its core; the second cache, in response to the second write request from any processing unit, performs a calculation on the occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, writes the calculated occlusion count to the address included in the second write request, and overwrites the occlusion count originally stored at that address; in response to the end of rendering in its core, it generates a first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer, and transmits the first write request to the first cache.

[0099] In one possible implementation, the first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The second buffer includes N second positions, and the address of the second buffer includes the addresses of the N second positions. The i-th second position of each core corresponds to the i-th first position and the i-th occlusion count counting round. N is a positive integer, 0 < i ≤ N, and is an integer. Each processing unit performs depth detection on its own primitive to obtain the occlusion count of the primitive, and generates a location including the occlusion count and the second buffer in the core. The second write request for the address includes: any processing unit, in the i-th occlusion counting round, performs depth detection on its own primitive to obtain the occlusion count of the primitive, and generates a second write request including the occlusion count and the address of the i-th second position in the core; the first write request generated in response to the end of rendering of the core includes: in response to the end of rendering of the core, generating a first write request including the occlusion count stored at the address of the i-th second position and the address of the i-th first position.

[0100] In one possible implementation, any processing unit performs depth detection on the input primitive to obtain the occlusion count of the primitive, including: rasterizing the input primitive to determine the pixels or sampling points covered by the primitive; calculating the depth value of the pixel or the sampling point, and incrementing the occlusion count of the primitive by one for each pixel or sampling point whose depth value is greater than a preset threshold.

[0101] In one possible implementation, the first cache, in response to a first write request from any core, performs a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, including: the first cache, in response to a first write request from any core, performs an atomic operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request; and through an atomic write operation, writes the calculation result to the address included in the first write request and overwrites the occlusion count originally stored at that address.

[0102] In one possible implementation, the first write request further includes an operation type, which includes any one of addition, subtraction, multiplication, division, finding the maximum value, and finding the minimum value.

[0103] In one possible implementation, the system further includes memory, the first buffer corresponding to a preset storage area on the memory, and the method further includes: after confirming that the occlusion count has been completed, the first buffer writes the occlusion count stored in the first buffer into the preset storage area.

[0104] This disclosure also proposes a graphics processor including the occlusion counting system described above.

[0105] This disclosure also proposes an electronic device including the graphics processor described above.

[0106] Exemplary architectures of graphics processors and electronic devices can be seen in... Figure 3a .

[0107] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0108] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An occlusion counting and statistics system, characterized in that, The system is located within a graphics processor and includes multiple cores and a first cache shared by the multiple cores. The first cache is located outside the cores and includes a first buffer for counting occlusions. Any core is used to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the first buffer; The first cache is used to, in response to a first write request from any core, perform a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the calculated occlusion count to the address included in the first write request and overwrite the occlusion count originally stored at that address.

2. The system according to claim 1, characterized in that, The core includes at least one processing unit and a second cache. Any processing unit is configured to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the second cache in the core. The second cache is used to forward a first write request from any processing unit to the first cache.

3. The system according to claim 2, characterized in that, The first buffer includes N first positions, and the address of the first buffer includes the addresses of the N first positions. The i-th first position corresponds to the i-th occlusion counting round. N is a positive integer, 0 < i ≤ N, and is an integer. Any processing unit is specifically used to perform depth detection on the input primitive in the i-th occlusion counting round to obtain the occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position.

4. The system according to claim 2 or 3, characterized in that, Any processing unit is specifically used for, Rasterize the input primitives themselves to determine the pixels or sampling points covered by the primitives; Calculate the depth value of the pixel or the sampling point. For each pixel or sampling point whose depth value is greater than a preset threshold, increment the occlusion count of the primitive by one.

5. The system according to claim 1, characterized in that, The first cache is specifically used for, In response to a first write request from any core, perform an atomic operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request. The atomic write operation writes the result of the operation to the address included in the first write request and overwrites the occlusion count originally stored at that address.

6. The system according to claim 1, characterized in that, The first write request also includes an operation type, which includes any one of addition, subtraction, multiplication, division, finding the maximum value, and finding the minimum value.

7. The system according to claim 3, characterized in that, The system also includes memory, and the first buffer corresponds to a preset storage area in the memory. The first cache is further configured to write the occlusion count stored in the first buffer into the preset storage area after confirming that the occlusion count has been completed.

8. A method for counting and statistically analyzing occlusions, characterized in that, The method is applied to an occlusion counting system, the system being configured in a graphics processor, the system including multiple cores and a first cache shared by the multiple cores, the first cache being located outside the cores and including a first buffer for counting occlusions, the method comprising: Any core performs depth detection on the primitives it inputs to obtain the occlusion count of the primitives, generates a first write request including the occlusion count and the address of the first buffer, and transmits the first write request to the first buffer; In response to a first write request from any core, the first cache performs a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, writes the calculated occlusion count to the address included in the first write request and overwrites the occlusion count originally stored at that address.

9. A graphics processor, characterized in that, The occlusion counting system includes any one of claims 1-7.

10. An electronic device, characterized in that, Includes the graphics processor as described in claim 9.

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