Method for detecting a via defect

Abstract

The application provides a via hole defect detection method, and belongs to the technical field of semiconductors. The method first acquires a first pattern density of an upper conductive pattern and a second pattern density of a lower conductive pattern around each via hole pattern in a layout to be analyzed. When the first pattern density or the second pattern density corresponding to the via hole pattern exceeds a predetermined range, the length proportion of the via hole pattern is acquired. Whether the via hole pattern is a suspected defective via hole pattern is determined according to the length proportion of the via hole pattern. The application detects via hole defects in combination with the pattern density around the via hole pattern and the length proportion of the via hole pattern before switching the upper conductive pattern and after switching the lower conductive layer. The via hole pattern prone to defects in the layout to be analyzed can be quickly and accurately positioned, the time for subsequent defect analysis is saved, the process or layout revision can be optimized in time, and the product yield and stability are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for detecting through-hole defects. Background Technology

[0002] With the development of semiconductor integrated circuit manufacturing processes, chip feature sizes are becoming smaller, the integration density per unit area is increasing, the number of conductive layers in the back-end is increasing, and the density of conductive patterns is also increasing. During chip internal layout design, different conductive layers are arranged alternately in a crisscross pattern, and the upper and lower conductive layers are electrically connected through vias to form a mesh-like interconnect network to ensure signal transmission within the chip. Via defects have become a significant cause of chip malfunctions.

[0003] As layout designs become increasingly complex and the number of vias increases, locating via defects becomes more difficult. How to accurately and quickly locate via patterns that are prone to defects in the layout is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a method for detecting through-hole defects, so as to solve the problem that it is difficult to locate through-hole defects in the prior art.

[0005] This application provides a method for detecting through-hole defects, including:

[0006] A layout to be analyzed is provided, which includes via patterns, upper conductive patterns, and lower conductive patterns;

[0007] Obtain a first pattern density and a second pattern density corresponding to each of the via patterns, wherein the first pattern density is the pattern density of the upper conductive pattern surrounding the via pattern, and the second pattern density is the pattern density of the lower conductive pattern surrounding the via pattern.

[0008] When the density of the first pattern or the density of the second pattern corresponding to the via pattern exceeds a predetermined range, the transition length ratio of the via pattern is obtained. This transition length ratio is the ratio of a first distance to a second distance. The first distance is the distance between the via pattern and the first end of its overlapping lower conductive pattern, and the second distance is the distance between the via pattern and the first end of its overlapping upper conductive pattern. The first end of the upper conductive pattern is the end furthest from its overlapping via pattern.

[0009] The through-hole pattern is judged to be a suspected defective through-hole pattern based on the transition length ratio of the through-hole pattern.

[0010] In some embodiments, the lower conductive pattern extends along a first direction, the upper conductive pattern has a first portion and a second portion, the first portion extends along the first direction, the second portion extends along a second direction, the first portion overlaps with any of the lower conductive patterns, the via pattern is located within the first portion, and the first direction is perpendicular to the second direction.

[0011] In some embodiments, the distance between the first end of the lower conductive pattern and its adjacent via pattern is a third distance, and the distance between the second end of the lower conductive pattern and its adjacent via pattern is a fourth distance, wherein the third distance is greater than the fourth distance.

[0012] In some embodiments, when the first portion is located at one end of the second portion, the first end of the upper conductive pattern is the end of the second portion away from the first portion; or,

[0013] When the first part is located at both ends of the second part, for any one of the through-hole patterns in the first part, the first end of the upper conductive pattern is the end of the other first part.

[0014] In some embodiments, the step of obtaining the first pattern density and the second pattern density corresponding to the through-hole pattern includes:

[0015] A detection window of a predetermined size is established centered on the through-hole pattern; and,

[0016] The pattern densities of the upper conductive pattern and the lower conductive pattern within the detection window are obtained to obtain the first pattern density and the second pattern density corresponding to the via pattern.

[0017] In some embodiments, the step of obtaining the first pattern density and the second pattern density corresponding to the through-hole pattern includes:

[0018] The layout to be analyzed is meshed with a predetermined mesh size and step size;

[0019] Select all grids containing the through-hole pattern; and,

[0020] The pattern density of the upper conductive pattern in each selected grid is obtained and averaged to obtain the first pattern density corresponding to the via pattern. The pattern density of the lower conductive pattern in each selected grid is obtained and averaged to obtain the second pattern density corresponding to the via pattern.

[0021] In some embodiments, the grid size is greater than or equal to the step size.

[0022] In some embodiments, the predetermined range includes 0.01 to 0.9.

[0023] In some embodiments, when the absolute value of the difference between the transition length ratio of the through hole pattern and 1 is greater than a first predetermined value, the through hole pattern is determined to be a suspected defective through hole pattern.

[0024] In some embodiments, after determining whether the via pattern is a suspected defective via pattern, a defect analysis is performed on the suspected defective via pattern; or, after determining whether the via pattern is a suspected defective via pattern, a fifth distance is obtained between the suspected defective via pattern and the second end of the underlying conductive pattern that overlaps with it, and a defect analysis is performed on the suspected defective via pattern whose fifth distance is greater than a second predetermined value.

[0025] This application provides a method for detecting via defects. The method first obtains the first pattern density of the upper conductive layer and the second pattern density of the lower conductive layer surrounding each via pattern in the layout to be analyzed. When the first or second pattern density corresponding to the via pattern exceeds a predetermined range, the transition length ratio of the via pattern is then obtained. Based on the transition length ratio, it is determined whether the via pattern is a suspected defective via pattern. An unexpected benefit is that this application, by combining the pattern density surrounding the via pattern with the transition length ratio of the upper conductive layer before and after the transition, can quickly and accurately locate via patterns prone to defects in the layout to be analyzed, saving time in subsequent defect analysis. This facilitates timely optimization of processes or layout modifications, improving product yield and stability. Attached Figure Description

[0026] Figure 1 A flowchart illustrating a method for detecting through-hole defects provided in an embodiment of this application.

[0027] Figure 2 This is a schematic diagram of the layout to be analyzed provided in an embodiment of this application.

[0028] Figure 3 This is a schematic diagram showing the establishment of a detection window centered on the first through-hole pattern, as provided in an embodiment of this application.

[0029] Figure 4 This is a schematic diagram of all the grids containing the first through-hole pattern provided in an embodiment of this application.

[0030] Figures 5-8 These are schematic diagrams of four grids containing a first through-hole pattern provided in the embodiments of this application.

[0031] Figure 9This is a schematic diagram showing the results of EBAC testing on the third and fourth through-hole patterns provided in an embodiment of this application.

[0032] Figure 10 This is a schematic diagram showing the results of EBAC testing on the first and second through-hole patterns provided in an embodiment of this application.

[0033] Figure 11 This is a schematic diagram showing the results of EBAC testing on the first through-hole pattern alone, as provided in an embodiment of this application.

[0034] Figure 12 This is a schematic diagram showing the results of EBAC testing on the second through-hole pattern separately, as provided in an embodiment of this application.

[0035] Figure 13 This is a TEM slice diagram of the second through-hole pattern provided in an embodiment of this application.

[0036] Figure 14 This is a TEM slice diagram of the third through-hole pattern provided in an embodiment of this application.

[0037] Figure 15 This is a structural block diagram of a through-hole defect detection system provided in an embodiment of this application.

[0038] Figure 16 A structural block diagram of an electronic device provided in an embodiment of this application.

[0039] Point1 - First through-hole pattern; Point2 - Second through-hole pattern; Point3 - Third through-hole pattern; Point4 - Fourth through-hole pattern; Um - Lower conductive pattern; Um+1 - Upper conductive pattern; W - Detection window; 10 - Layout supply module; 20 - Pattern density acquisition module; 30 - Distance measurement module; 40 - Defect location module; 301 - Processor; 302 - Memory; 303 - Communication interface; 304 - Communication bus; X - First direction; Y - Second direction. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Figure 1 This is a flowchart of a method for detecting through-hole defects. Figure 1 As shown, the detection methods for through-hole defects include:

[0042] Step S100: Provide the layout to be analyzed, which includes via patterns, upper conductive patterns, and lower conductive patterns;

[0043] Step S200: Obtain the first pattern density and the second pattern density corresponding to each through-hole pattern. The first pattern density is the pattern density of the upper conductive pattern around the through-hole pattern, and the second pattern density is the pattern density of the lower conductive pattern around the through-hole pattern.

[0044] Step S300: When the density of the first pattern or the density of the second pattern corresponding to the through hole pattern exceeds the predetermined range, the transition length ratio of the through hole pattern is obtained. The transition length ratio is the ratio of the first distance to the second distance. The first distance is the distance between the through hole pattern and the first end of the lower conductive pattern that it overlaps with. The second distance is the distance between the through hole pattern and the first end of the upper conductive pattern that it overlaps with. The first end of the upper conductive pattern is the end that is far away from the through hole pattern that it overlaps with.

[0045] Step S400: Determine whether the through-hole pattern is a suspected defective through-hole pattern based on the transition length ratio of the through-hole pattern.

[0046] First, step S100 is executed, providing the layout to be analyzed. This layout can be a local area in the original design layout that requires defect analysis. For example, after chip probing (also known as wafer testing) of a chip sample, if a failure is found in a specific area, circuit tracing (path tracing) of the failed area is required. This involves finding the area corresponding to the failed area in the original design layout as the layout to be analyzed, and then using this layout to locate potential failure points (via patterns prone to defects). As another example, after the original chip design layout is completed, defect analysis needs to be performed on the area surrounding key circuit modules to determine if there are any process optimizations or layout redesigns required. In this case, the key area requiring defect analysis can also be found in the original design layout as the layout to be analyzed, and then the potential failure points can be located using this layout.

[0047] Figure 2 This is a schematic diagram of the layout to be analyzed provided in this embodiment, such as... Figure 2As shown, the layout to be analyzed has 4 via patterns (Point1, Point2, Point3, and Point4), 3 upper conductive patterns Um+1, and 2 lower conductive patterns Um, where m can be greater than or equal to 1. For example, if the lower conductive pattern Um and the upper conductive pattern Um+1 are both metal layer patterns, when m=3, the lower conductive pattern Um is the pattern of the third metal layer, and the upper conductive pattern Um+1 is the pattern of the fourth metal layer. The first via pattern Point1, the second via pattern Point2, the third via pattern Point3, and the fourth via pattern Point4 are vias (also known as vias) that electrically connect the third and fourth metal layers.

[0048] Of course, in some embodiments, the upper conductive pattern Um+1 and the lower conductive pattern Um are not limited to patterns of metal layers, but can also be patterns of other conductive structures such as polysilicon layers, source and drain regions; in addition, the upper conductive pattern Um+1 and the lower conductive pattern Um are not limited to conductive structures that play a real interconnect role, but can also be dummy patterns used to play a supporting role or increase pattern density.

[0049] Please continue reading. Figure 2 The lower conductive patterns Um all extend along the first direction X, forming a straight line. The upper conductive patterns Um+1 each consist of a first part and a second part, which are an integral structure. The first part of the upper conductive pattern Um+1 extends along the first direction X, and the second part extends along the second direction Y. The first part can be located at one end of the second part, in which case the upper conductive pattern Um+1 is L-shaped; the first part can also be located at both ends of the second part, in which case the upper conductive pattern Um+1 is C-shaped. The first part of the upper conductive pattern Um+1 overlaps with any lower conductive pattern Um, and the via pattern is located within the first part. Thus, the via pattern overlaps with both the upper conductive pattern Um+1 and the lower conductive pattern Um. Alternatively, it can be described that each overlapping area of ​​the first part and the lower conductive pattern Um contains a via pattern. In some embodiments, the via pattern has at least two twin patterns, each twin pattern corresponding to a via in the actual fabrication process. For example, when the via pattern has two twin patterns, two twin vias will be formed in the actual fabrication process. These two twin vias are close together and have the same function, both being used to connect the corresponding upper metal layer and the lower metal layer.

[0050] Generally, the first direction X and the second direction Y are perpendicular, but this should not be a limitation.

[0051] It should be understood that the number and arrangement of via patterns, upper conductive patterns Um+1 and lower conductive patterns Um in the layout to be analyzed are merely examples to illustrate the scheme of this application and should not be construed as limiting this application.

[0052] Execute step S200 to obtain the first pattern density and the second pattern density corresponding to each via pattern. Specifically, the first pattern density corresponding to the first via pattern Point1 is the pattern density of its surrounding upper conductive pattern Um+1, and the second pattern density corresponding to Point1 is the pattern density of its surrounding lower conductive pattern Um; the first pattern density corresponding to the second via pattern Point2 is the pattern density of its surrounding upper conductive pattern Um+1, and the second pattern density corresponding to Point2 is the pattern density of its surrounding lower conductive pattern Um; the first pattern density corresponding to the third via pattern Point3 is the pattern density of its surrounding upper conductive pattern Um+1, and the second pattern density corresponding to Point3 is the pattern density of its surrounding lower conductive pattern Um; the first pattern density corresponding to the fourth via pattern Point4 is the pattern density of its surrounding upper conductive pattern Um+1, and the second pattern density corresponding to Point4 is the pattern density of its surrounding lower conductive pattern Um.

[0053] In some embodiments, the first pattern density and the second pattern density corresponding to each through-hole pattern can be obtained by the following steps:

[0054] Step S211: Establish a detection window of a predetermined size centered on the through-hole pattern;

[0055] Step S212: Obtain the pattern density of the upper conductive pattern Um+1 and the lower conductive pattern Um within the detection window to obtain the first pattern density and the second pattern density corresponding to the through hole pattern.

[0056] Next, we will take the acquisition of the first pattern density and the second pattern density corresponding to the first through-hole pattern Point1 as an example to explain in detail a specific method (hereinafter referred to as Scheme 1) for acquiring the first pattern density and the second pattern density corresponding to the through-hole pattern.

[0057] Figure 3 This is a schematic diagram illustrating the establishment of a detection window W centered on the first through-hole pattern Point1, as provided in this embodiment. Figure 3 As shown, in step S211, a detection window W of a predetermined size is established centered on the first through-hole pattern Point1 (e.g., ...). Figure 3 (As shown in the dashed box in the image), because the size of the first through-hole pattern Point1 is relatively small compared to the size of the detection window W. Figure 3The first through-hole pattern Point1 is abstracted as a single point, while the widths of the upper conductive pattern Um+1 and the lower conductive pattern Um are relatively small compared to the size of the detection window W. Figure 3 The upper conductive pattern Um+1 and the lower conductive pattern Um are abstracted as a single line.

[0058] It should be noted that the size of the detection window W can be set empirically, for example, it can be 5μm*5μm, 10μm*10μm or 40μm*40μm, etc., and this application does not impose any restrictions. In addition, in order to facilitate the calculation of pattern density, the detection window W can usually be square, but it can also be rectangular or other possible shapes.

[0059] In step S212, the pattern density of the upper conductive pattern Um+1 within the detection window W is obtained, thereby obtaining the first pattern density corresponding to the first via pattern Point1. The pattern density of the lower conductive pattern Um within the detection window W is obtained, thereby obtaining the second pattern density corresponding to the first via pattern Point1. The method for obtaining the pattern density within the detection window W can be any of the existing technologies, and will not be elaborated here.

[0060] The steps for obtaining the first and second pattern densities corresponding to the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 can refer to the steps for obtaining the first and second pattern densities of the first through-hole pattern Point1. Examples will not be given here.

[0061] In some embodiments, the first pattern density and the second pattern density corresponding to each through-hole pattern can also be obtained by the following steps:

[0062] Step S221: Mesh the layout to be analyzed with a predetermined mesh size and step size;

[0063] Step S222: Select all grids containing through-hole patterns;

[0064] Step S223: Obtain the upper conductive pattern Um+1 in each selected grid and take the average value to obtain the first pattern density corresponding to the through hole pattern; obtain the lower conductive pattern Um in each selected grid and take the average value to obtain the second pattern density corresponding to the through hole pattern.

[0065] Next, we will take the acquisition of the first and second pattern densities corresponding to the first through-hole pattern Point1 as an example to explain in detail another specific method (hereinafter referred to as Scheme 2) for acquiring the first and second pattern densities corresponding to the through-hole pattern.

[0066] First, step S221 is executed to mesh the layout to be analyzed with a predetermined mesh size and step size. The meshing process can be specifically as follows: First, a mesh is created at the top corner of the layout to be analyzed, with a predetermined mesh size. Then, this mesh is copied according to a predetermined step size until the layout to be analyzed is meshed. It can be understood that if the predetermined mesh size equals the predetermined step size, the meshes on the layout to be analyzed are closely spaced with no gaps between adjacent meshes; if the predetermined mesh size is greater than the predetermined step size, there are overlapping areas between adjacent meshes; if the predetermined mesh size is less than the predetermined step size, there are certain gaps between adjacent meshes.

[0067] It should be noted that the grid size and step size can be set empirically. For example, the grid size can be 5μm*5μm, 10μm*10μm, or 40μm*40μm, etc. This application does not impose any restrictions. The grid is usually square. The predetermined grid size is preferably greater than or equal to the predetermined step size. For example, the step size can be set to half of the grid size, thereby improving the calculation accuracy of the first and second graphic densities without excessively increasing the complexity of subsequent calculations.

[0068] In step S222, all grids containing the first through-hole pattern Point1 are selected. In this embodiment, the predetermined grid size is 10μm*10μm, and the predetermined step size is 5μm. Figure 4 This is a schematic diagram of all the grids including the first through-hole pattern Point1 provided in this embodiment, as shown below. Figure 4 As shown, the grid containing the first through-hole pattern Point1 has 4 grids. Figures 5-8 These are schematic diagrams of the four grids containing the first through-hole pattern Point1.

[0069] In step S223, the pattern density of the upper conductive pattern Um+1 within the selected four grids is obtained and averaged to obtain the first pattern density corresponding to the first via pattern Point1. The pattern density of the lower conductive pattern Um within the selected four grids is obtained and averaged to obtain the second pattern density corresponding to the first via pattern Point1. The method for obtaining the pattern density within the detection window W can be any of the existing technologies, and will not be elaborated here.

[0070] The steps for obtaining the first and second pattern densities corresponding to the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 can refer to the steps for obtaining the first and second pattern densities of the first through-hole pattern Point1. Examples will not be given here.

[0071] Table 1 shows the first and second pattern densities corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 obtained using Scheme 1 and Scheme 2. Scheme 1 uses three different sizes of detection windows, while Scheme 2 uses three different combinations of grid sizes and step sizes. As can be seen from Table 1, both Scheme 1 and Scheme 2 can obtain the first and second pattern densities corresponding to each through-hole pattern. However, Scheme 1 requires less computation and is faster, but its accuracy may be lower. Scheme 2 requires more computation but may have higher accuracy.

[0072] Furthermore, as shown in Table 1, when the size of the detection window changes, the first and second pattern densities corresponding to each through-hole pattern obtained using Scheme 1 also change slightly. Similarly, when the combination of grid size and step size changes, the first and second pattern densities corresponding to each through-hole pattern obtained using Scheme 2 also change slightly. Therefore, the first and second pattern densities calculated by different detection window sizes and different combinations of grid size and step size may not be completely consistent. It cannot be absolutely assumed that a larger detection window size or grid size is always better (or a smaller size is always better). When designing the size of the detection window or the combination of grid size and step size, the actual situation, accuracy requirements, and efficiency requirements should be comprehensively considered. Alternatively, to further improve accuracy, multiple combinations of detection window sizes or grid size and step size can be set, utilizing each combination to calculate multiple first and second pattern densities corresponding to each through-hole pattern. Then, based on experience, the most suitable first and second pattern densities (or the minimum value) can be selected for each through-hole pattern.

[0073] Table 1: First and Second Pattern Densities for Each Through-hole Pattern Obtained Using Scheme 1 and Scheme 2

[0074]

[0075] Understandably, pattern density significantly impacts etching and chemical mechanical polishing (CMP) processes during chip manufacturing. Both excessively high and low pattern densities can impair process performance and potentially lead to chip failures, particularly in double martensitic processes where pattern density is highly sensitive. Specifically, in areas with low pattern density, fewer supports make vias more susceptible to exposure during etching, potentially leading to over-etching or sidewall damage, increasing the likelihood of open circuits. Furthermore, CMP processes often produce unforeseen via defects, ranging from reduced chip reliability to defective chips. In some cases, layout designers must make special adjustments to the original design. For example, insufficient or no dummy patterns around timing-critical analog and RF circuit modules result in low pattern density, leading to more via defects and reduced product yield. Conversely, in areas with high pattern density, overly dense patterns may hinder complete etching or result in insufficient CMP, affecting via opening sizes and potentially causing open circuits or short circuits. It is evident that when the density of the upper conductive pattern Um+1 or the lower conductive pattern Um around the via pattern is too low or too high, it can be predicted that the via pattern is more likely to produce defects.

[0076] Based on this, step S300 is executed. When the first or second pattern density corresponding to the via pattern exceeds a predetermined range, these via patterns can be considered to be via patterns prone to defects. When the pattern density is less than 1%, it can be considered that the pattern density is too low; when the pattern density is greater than 90%, it can be considered that the pattern density is too high. Therefore, the predetermined range can be 0.01~0.9. When the first or second pattern density corresponding to the via pattern is less than 0.01, it can be determined that the pattern density of the upper conductive pattern Um+1 or the lower conductive pattern Um around the via pattern is too low, and the via pattern is prone to defects. When the first or second pattern density corresponding to the via pattern is greater than 0.9, it can be determined that the pattern density of the upper conductive pattern Um+1 or the lower conductive pattern Um around the via pattern is too high, and the via pattern is also prone to defects.

[0077] Taking the first and second pattern densities obtained by Scheme 2 with a grid size of 10*10 and a step size of 5 in Table 1 as an example, the first pattern densities corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, and the third through-hole pattern Point3 are all less than 0.01, while the first and second pattern densities corresponding to the fourth through-hole pattern Point4 are both between 0.01 and 0.9. Therefore, it can be considered that the probability of defects in the first through-hole pattern Point1, the second through-hole pattern Point2, and the fourth through-hole pattern Point4 is greater than the probability of defects in the third through-hole pattern Point3. At this time, the third through-hole pattern Point3 can be excluded.

[0078] However, the occurrence of through-hole defects does not depend entirely on the pattern density around the through-hole. If the through-hole defects are located solely based on the pattern density, the number of through-hole patterns located may be large, the positioning accuracy may not be high, and the subsequent defect analysis time may be extended.

[0079] Understandably, each via pattern typically overlaps with a lower conductive pattern Um and an upper conductive pattern Um+1. In actual manufacturing processes, the via corresponding to this pattern connects two conductive layers. For example, Figure 1 In the diagram, the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 each have their own overlapping lower conductive pattern Um and upper conductive pattern Um+1. Specifically, the first through-hole pattern Point1, the second through-hole pattern Point2, and the third through-hole pattern Point3 overlap with the same lower conductive pattern Um, while the second through-hole pattern Point2 and the fourth through-hole pattern Point4 overlap with the same upper conductive pattern Um+1. For ease of description, the lower conductive pattern Um can be considered the main circuit pattern, and the upper conductive pattern Um+1 can be considered the branch circuit pattern. The first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 are located at the transition points between the main circuit pattern and the branch circuit pattern, used to transfer the main circuit pattern to the branch circuit pattern, forming a multi-branched circuit trace.

[0080] Understandably, if the lengths of the main circuit pattern before and after the transition are not significantly different, the resulting through-hole pattern will have a relatively uniform main and branch circuit pattern, leading to more stable fabrication and reducing the likelihood of defects. Conversely, if the lengths of the main circuit pattern before and after the transition are significantly different, the resulting through-hole pattern will be less uniform, potentially being top-heavy or bottom-light, resulting in unstable fabrication and a higher risk of defects.

[0081] Based on this, such as Figure 1As shown, the transition length ratio of the via pattern is obtained. The transition length ratio is the ratio of a first distance to a second distance. The first distance is the distance between the first end of the via pattern and its overlapping lower conductive pattern Um, which represents the length of the main circuit pattern of the via pattern before the transition. The second distance is the distance between the first end of the via pattern and its overlapping upper conductive pattern Um+1, which represents the length of the branch circuit pattern of the via pattern after the transition. The difference in length between the main circuit pattern before the transition and the branch circuit pattern after the transition can be measured by the ratio of the first distance to the second distance.

[0082] Furthermore, both the upper conductive pattern Um+1 and the lower conductive pattern Um have two ends. When calculating the first distance and the second distance, it is necessary to determine the first end of the lower conductive pattern Um and the first end of the upper conductive pattern Um+1.

[0083] Specifically, the first end of the lower conductive pattern Um can be any end of the pattern. In some embodiments, the end farther from the adjacent via pattern can also be selected. That is, the distance between the first end of the lower conductive pattern and its adjacent via pattern is the third distance, and the distance between the second end of the lower conductive pattern and its adjacent via pattern is the fourth distance. The third distance can be greater than the fourth distance. Taking the lower conductive pattern Um that overlaps the first via pattern Point1, the second via pattern Point2, and the third via pattern Point3 as an example, since the right end of the lower conductive pattern Um (only for...) Figure 1 The distance between the orientation in the diagram and the first through-hole pattern Point1 is greater than its left end (only for the orientation in the diagram). Figure 1 The distance between the orientation of the pattern (in the image) and the third via pattern Point3 can be used to select the right end of the lower conductive pattern Um (only for...). Figure 1 The first end is located at the position in the middle, and the left end of the lower conductive pattern Um (only for the position in the middle) is located at the position in the middle. Figure 1 The orientation in the middle is its second end.

[0084] Furthermore, the first end of the upper conductive pattern Um+1 is the end away from the via pattern it overlaps with. It should be noted that if the upper conductive pattern Um+1 includes only one first part, and this first part is located at one end of the second part, then the first end of the upper conductive pattern Um+1 is the end of the second part away from the first part; if the upper conductive pattern Um+1 includes two first parts, and the first parts are located at both ends of the second part, then for any via pattern within one first part, the first end of the upper conductive pattern is the end of the other first part. For example, for the first via pattern Point1, the first ends of both the first via pattern Point1 and its overlapping upper conductive pattern Um+1 are the ends of the upper conductive pattern Um+1 away from the first via pattern Point1. Figure 1 The lower end of the corresponding upper conductive pattern Um+1); for the second through-hole pattern Point2, the first end of the second through-hole pattern Point2 and the upper conductive pattern Um+1 that overlaps with it is the end of the upper conductive pattern Um+1 that is far away from the second through-hole pattern Point2 ( Figure 1 The lower end of the corresponding upper conductive pattern Um+1); for the fourth through hole pattern Point4, the first end of the fourth through hole pattern Point4 and the upper conductive pattern Um+1 that overlaps is the end of the upper conductive pattern Um+1 that is far away from the fourth through hole pattern Point4 ( Figure 1 The upper end of the corresponding upper conductive pattern Um+1 in the middle.

[0085] It should be noted that since both the upper conductive pattern Um+1 and the lower conductive pattern Um are relatively large in aspect ratio, the ends of the upper conductive pattern Um+1 and the lower conductive pattern Um refer to their ends along their length. For example, the two ends of the lower conductive pattern Um are its two ends in the first direction X, and the two ends of the upper conductive pattern Um+1 are its two ends in the second direction Y.

[0086] In step S400, the via pattern is judged to be a suspected defective via pattern based on the transition length ratio. Specifically, the closer the transition length ratio is to 1, the smaller the difference between the first distance and the second distance, the smaller the difference in length between the main circuit pattern before the transition and the branch circuit pattern after the transition, and the less likely the via pattern is to have defects. Conversely, the further the transition length ratio is from 1, the larger the difference between the first distance and the second distance, the larger the difference in length between the main circuit pattern before the transition and the branch circuit pattern after the transition, and the more likely the via pattern is to have defects.

[0087] It should be noted that, compared to methods such as directly using the difference between the first distance and the second distance to measure the length difference between the main circuit diagram before the transition and the branch circuit diagram after the transition, this application measures the length difference between the main circuit diagram before the transition and the branch circuit diagram after the transition by using the transition length ratio obtained by comparing the first distance and the second distance, which can eliminate the influence of data units.

[0088] For the sake of convenience in the following description, it is assumed that the first pattern density and the second pattern density corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3 and the fourth through-hole pattern Point4 do not exceed the predetermined range.

[0089] Table 2 shows the first distance, second distance, and transition length ratios corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 calculated under two layout modes in this embodiment. The two layout modes are AG layout (layout in AG format) and GDS layout (layout in GDS format). The AG layout is obtained from the GDS layout through logical operations. The graphics of the two layouts are exactly the same, and the graphic sizes are in a certain proportional relationship. As can be seen from Table 2, the absolute value of the difference between the ratio of the transition lengths of the first through-hole pattern Point1 and the second through-hole pattern Point2 and 1 is relatively large. This indicates that the length difference between the main circuit pattern before the transition and the branch circuit pattern after the transition is relatively large, and the probability of defects in the first through-hole pattern Point1 and the second through-hole pattern Point2 is relatively high. On the other hand, the absolute value of the difference between the ratio of the transition lengths of the third through-hole pattern Point3 and the fourth through-hole pattern Point4 and 1 is relatively small. This indicates that the length difference between the main circuit pattern before the transition and the branch circuit pattern after the transition is relatively small, and the probability of defects in the third through-hole pattern Point3 and the fourth through-hole pattern Point4 is relatively low.

[0090] By combining the first and second pattern densities corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4, it can be easily determined that the probability of defects in the first through-hole pattern Point1 and the second through-hole pattern Point2 is greater than the probability of defects in the fourth through-hole pattern Point4. The probability of defects in the fourth through-hole pattern Point4 is greater than the probability of defects in the third through-hole pattern Point3. Therefore, the third through-hole pattern Point3 and the fourth through-hole pattern Point4 can be excluded.

[0091] Table 2: Ratio of First Distance, Second Distance and Transition Length for Each Through-Hole Pattern

[0092]

[0093] Of course, for accurate quantification, it can be set that when the absolute value of the difference between the transition length ratio corresponding to the through-hole pattern and 1 is greater than a first predetermined value, the through-hole pattern is judged as a suspected defective through-hole pattern. The first predetermined value can be an empirical value, for example, the first predetermined value can be greater than or equal to 3.

[0094] For ease of the following description, it is assumed that the absolute value of the difference between the transition length ratios of the first through-hole pattern Point1 and the second through-hole pattern Point2 and 1 is greater than a first predetermined value, and the absolute value of the difference between the transition length ratios of the third through-hole pattern Point3 and the fourth through-hole pattern Point4 and 1 is less than or equal to the first predetermined value. Therefore, the first through-hole pattern Point1 and the second through-hole pattern Point2 are determined to be suspected defective through-hole patterns.

[0095] In some embodiments, defect analysis can be performed directly on all suspected defective via patterns (first via pattern Point1 and second via pattern Point2) to accurately find the actual defective via pattern.

[0096] It is understandable that, since the lower conductive pattern Um has two ends, when calculating the first distance, only the distance between the via pattern and the first end of the overlapping lower conductive pattern Um is calculated. If the via pattern transitions near the first end of the lower conductive pattern Um, then although the first distance between the via pattern and the first end of the lower conductive pattern Um is small, and the calculated transition length ratio is large, the distance between the via pattern and the second end of the lower conductive pattern Um is still large. Therefore, it can still be considered that the length difference between the main circuit pattern before the transition and the branch circuit pattern after the transition is small. Simultaneously, since patterns are prone to concavity during chemical mechanical polishing (CMP), and the concavity is larger closer to the pattern center, the closer the via pattern is to the end of the lower conductive pattern Um, the less likely it is to produce defects; conversely, the closer the via pattern is to the center of the lower conductive pattern Um, the more likely it is to produce defects.

[0097] Based on this, in order to avoid misjudging suspected defective via patterns and further locate via patterns that are prone to defects, in some embodiments, after determining the suspected defective via pattern according to the transition length ratio, a fifth distance can be obtained between the second end of the suspected defective via pattern and the second end of the underlying conductive pattern Um that overlaps with it. The suspected defective via pattern with a fifth distance greater than a second predetermined value is then subjected to defect analysis.

[0098] Table 3 shows the fifth distances corresponding to the first via pattern Point1, the second via pattern Point2, the third via pattern Point3, and the fourth via pattern Point4 calculated under two layout modes in this embodiment. It should be noted that the third via pattern Point3 and the fourth via pattern Point4 are not suspected defective via patterns, and their corresponding fifth distances do not need to be calculated; they are only used here for comparison with the first via pattern Point1 and the second via pattern Point2. As can be seen from Table 3, the fifth distances corresponding to the first via pattern Point1 and the second via pattern Point2 are both relatively large, indicating that the first via pattern Point1 and the second via pattern Point2 are far from the end of the underlying conductive pattern Um. Therefore, the first via pattern Point1 and the second via pattern Point2 have a higher probability of defects, and defect analysis can be performed on the first via pattern Point1 and the second via pattern Point2. The fifth distances corresponding to the third through-hole pattern Point3 and the fourth through-hole pattern Point4 are both small, indicating that the third through-hole pattern Point3 and the fourth through-hole pattern Point4 are close to the end of the lower conductive pattern Um. Therefore, the probability of defects in the third through-hole pattern Point3 and the fourth through-hole pattern Point4 is small, which further confirms the judgment in the previous text.

[0099] Table 3: Fifth Distance Corresponding to Each Suspected Through-hole Pattern

[0100]

[0101] Of course, for accurate quantification, we set up a defect analysis process for via patterns with suspected defects where the fifth distance is greater than the second predetermined value, and exclude via patterns with suspected defects where the fifth distance is less than or equal to the second predetermined value, thus saving time in subsequent defect analysis. The second predetermined value can also be an empirical value.

[0102] To verify the accuracy of this application, fixed-point photographs were taken of the through-hole structures corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4. These photographs were then scanned using special equipment. The defect probabilities of the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 are shown in Table 4. As can be seen from Table 4, the first through-hole pattern Point1 and the second through-hole pattern Point2 have a higher probability of defects, while the third through-hole pattern Point3 and the fourth through-hole pattern Point4 have a lower probability. Therefore, defect analysis can be performed only on the first through-hole pattern Point1 and the second through-hole pattern Point2. Therefore, the defect probabilities of the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4 measured by the testing equipment are basically consistent with the defect probabilities derived in this application. This application can quickly and accurately locate through-hole patterns in the layout to be analyzed that are prone to defects, saving time for subsequent defect analysis, which is conducive to timely optimization of the process or layout modification, and improving product yield and stability.

[0103] Table 4: Defect probability of each through-hole pattern

[0104]

[0105] Next, EBAC (Electrical Failure Analysis System) was used to perform EBAC tests on the through-hole structures corresponding to the first through-hole pattern Point1, the second through-hole pattern Point2, the third through-hole pattern Point3, and the fourth through-hole pattern Point4. Figure 9 This is a schematic diagram showing the results of EBAC testing on the third through-hole pattern Point3 and the fourth through-hole pattern Point4. Figure 10 This is a schematic diagram showing the results of EBAC testing on the first through-hole pattern Point1 and the second through-hole pattern Point2. Figure 11 This is a schematic diagram showing the results of EBAC testing on the first through-hole pattern Point1 alone. Figure 12 This is a schematic diagram showing the results of EBAC testing on the second through-hole pattern Point2 alone. The test revealed that the third through-hole pattern Point3 and the fourth through-hole pattern Point4 are open circuits, indicating that they did not exhibit significant defects. However, the first through-hole pattern Point1 and the second through-hole pattern Point2 are open circuits, indicating significant defects in both.

[0106] Furthermore, TEM samples were prepared and analyzed for the through-hole structures corresponding to the second through-hole pattern Point2 and the third through-hole pattern Point3. Figure 13 This is a schematic TEM slice of the second through-hole pattern Point2. Figure 14 This is a schematic diagram of a TEM slice of the third through-hole pattern Point3, as shown below. Figure 13 and Figure 14 As shown, the via structure corresponding to the second via pattern Point2 has too shallow an etching depth, resulting in an open circuit, while the via structure corresponding to the third via pattern Point3 has a good connection.

[0107] As can be seen, the via patterns that are prone to defects identified in this application are completely consistent with the via patterns that actually produce defects as determined by testing. The via defect detection method provided in this application can accurately locate via patterns that are prone to defects, saving time for subsequent defect analysis. This is beneficial for timely optimization of processes or layout modifications, thereby improving product yield and stability.

[0108] Corresponding to the embodiments of the above-described method for detecting through-hole defects, this embodiment also provides a system for detecting through-hole defects. Figure 15 This is a structural block diagram of the through-hole defect detection system provided in this embodiment. Figure 15 As shown, the through-hole defect detection system includes:

[0109] The layout supply module 10 is used to provide the layout to be analyzed, which includes via patterns, upper conductive patterns, and lower conductive patterns.

[0110] The pattern density acquisition module 20 is used to acquire the first pattern density and the second pattern density corresponding to each through-hole pattern. The first pattern density is the pattern density of the upper conductive pattern around the through-hole pattern, and the second pattern density is the pattern density of the lower conductive pattern around the through-hole pattern.

[0111] The distance measurement module 30 is used to obtain the transition length ratio of the through-hole pattern when the density of the first pattern or the density of the second pattern corresponding to the through-hole pattern exceeds a predetermined range. The transition length ratio is the ratio of the first distance to the second distance. The first distance is the distance between the first ends of the lower conductive pattern that overlaps with the through-hole pattern, and the second distance is the distance between the first end of the through-hole pattern and the first end of the upper conductive pattern that overlaps with it. The first end of the upper conductive pattern is the end away from the through-hole pattern that overlaps with it.

[0112] The defect location module 40 is used to determine whether a through-hole pattern is a suspected defective through-hole pattern based on the transition length ratio of the through-hole pattern.

[0113] Furthermore, this embodiment also provides an electronic device that can be used for the detection of through-hole defects. Figure 16This is a structural block diagram of the electronic device provided in this embodiment, such as... Figure 16 As shown, the electronic device includes:

[0114] One or more processors 301;

[0115] Memory 302 is used to store one or more programs;

[0116] When one or more programs are executed by one or more processors 301, the one or more processors 301 implement the through-hole defect detection method as described in the above embodiments.

[0117] In this embodiment, there is one processor 301 and one memory 302. The electronic device also includes a communication interface 303. The processor 301, memory 302, and communication interface 303 communicate with each other through a communication bus 304. The communication bus 304 mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus 304 can be divided into an address bus, a data bus, a control bus, etc.

[0118] The memory 302, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the via defect detection method in this embodiment. The processor 301 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the memory 302, thereby implementing the aforementioned via defect detection method.

[0119] The memory 302 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 302 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 302 may further include memory remotely located relative to the processor 301, which can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0120] The electronic device proposed in this embodiment and the through-hole defect detection method proposed in the above embodiments belong to the same inventive concept. Technical details not described in detail in this embodiment can be found in the above embodiments, and this embodiment has the same beneficial effects as the above embodiments.

[0121] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor 301, implements the through-hole defect detection method proposed in the above embodiment.

[0122] This embodiment also provides a computer program product, which includes instructions that, when executed by a processor, implement the above-described method for detecting through-hole defects.

[0123] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0124] In summary, this embodiment provides a method for detecting via defects. This method first obtains the first pattern density of the upper conductive pattern and the second pattern density of the lower conductive pattern surrounding each via pattern in the layout to be analyzed. When the first or second pattern density corresponding to the via pattern exceeds a predetermined range, the transition length ratio of the via pattern is then obtained. Based on the transition length ratio, it is determined whether the via pattern is a suspected defective via pattern. An unexpected effect is that this application combines the pattern density surrounding the via pattern with the transition length ratio of the upper conductive pattern before and the lower conductive layer after the transition to detect via defects. This allows for rapid and accurate location of via patterns prone to defects in the layout to be analyzed, saving time in subsequent defect analysis and facilitating timely optimization of processes or layout modifications, thereby improving product yield and stability. It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to in the method section.

[0125] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0126] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0127] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method of detecting a via defect, the method comprising: The method comprises: providing a layout to be analyzed, the layout to be analyzed comprising via hole patterns, upper layer conductive patterns and lower layer conductive patterns; obtaining a first pattern density and a second pattern density corresponding to each of the via hole patterns, the first pattern density being a pattern density of the upper layer conductive patterns around the via hole pattern, the second pattern density being a pattern density of the lower layer conductive patterns around the via hole pattern; when the first pattern density or the second pattern density corresponding to the via hole pattern exceeds a predetermined range, obtaining a transition length ratio of the via hole pattern, the transition length ratio being a ratio of a first distance and a second distance, the first distance being a distance between the via hole pattern and a first end of the lower layer conductive pattern overlapping the via hole pattern, the second distance being a distance between the via hole pattern and a first end of the upper layer conductive pattern overlapping the via hole pattern, the first end of the upper layer conductive pattern being an end away from the via hole pattern; and determining whether the via hole pattern is a suspected defective via hole pattern according to the transition length ratio of the via hole pattern. A distance between the first end of the lower layer conductive pattern and the via hole pattern adjacent to the first end of the lower layer conductive pattern is a third distance, and a distance between a second end of the lower layer conductive pattern and the via hole pattern adjacent to the second end of the lower layer conductive pattern is a fourth distance, the third distance being greater than the fourth distance.

2. The method of detecting a via defect according to claim 1, wherein The lower layer conductive patterns extend along a first direction, the upper layer conductive patterns have first portions and second portions, the first portions extend along the first direction, the second portions extend along a second direction, the first portions overlap any of the lower layer conductive patterns, and the via hole patterns are located in the first portions, the first direction being perpendicular to the second direction.

3. The method of detecting a via defect according to claim 2, wherein When the first portion is located at one end of the second portion, the first end of the upper layer conductive pattern is an end of the second portion away from the first portion; or When the first portion is located at two ends of the second portion, for any of the via hole patterns in the first portion, the first end of the upper layer conductive pattern is an end of another first portion.

4. The method of detecting a via defect according to claim 1, wherein The step of obtaining the first pattern density and the second pattern density corresponding to the via hole pattern comprises: establishing a detection window of a predetermined size with the via hole pattern as a center; and obtaining pattern densities of the upper layer conductive patterns and the lower layer conductive patterns in the detection window to obtain the first pattern density and the second pattern density corresponding to the via hole pattern.

5. The method of detecting a via defect according to claim 1, wherein The step of obtaining the first pattern density and the second pattern density corresponding to the via hole pattern comprises: gridizing the layout to be analyzed with a predetermined grid size and a step length; selecting all grids containing the via hole pattern; and obtaining pattern densities of the upper layer conductive patterns in each selected grid and taking an average value to obtain the first pattern density corresponding to the via hole pattern, and obtaining pattern densities of the lower layer conductive patterns in each selected grid and taking an average value to obtain the second pattern density corresponding to the via hole pattern.

6. The method of detecting a via defect according to claim 5, wherein The grid size is greater than or equal to the step length.

7. The method of detecting a via defect according to any one of claims 1, 4, 5 or 6, wherein, The predetermined range is 0.01-0.

9.

8. The method of detecting a via defect according to claim 1, wherein When the absolute value of the difference between the ratio of the transition length of the via pattern and 1 is greater than a first predetermined value, the via pattern is determined as a suspected defective via pattern.

9. The method of detecting a via defect according to Claim 1, wherein After determining whether the via pattern is a suspected defective via pattern, defect analysis is performed on the suspected defective via pattern; or after determining whether the via pattern is a suspected defective via pattern, a fifth distance between the suspected defective via pattern and a second end of the lower-layer conductive pattern overlapping the suspected defective via pattern is obtained, and defect analysis is performed on the suspected defective via pattern corresponding to the fifth distance greater than a second predetermined value.

Images