Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention provides a memory, an operation method of the memory, a memory system and electronic equipment. The memory includes a memory cell array, and a peripheral circuit coupled to the memory cell array through a word line and a bit line, the peripheral circuit configured to: apply a first read voltage to a selected word line; charging a sensing node corresponding to the memory cell coupled to the selected word line; the memory cells coupled with the selected word line are divided into a plurality of memory cell groups to execute sensing operation, and the sensing operation comprises the steps that a plurality of sensing nodes corresponding to the memory cells in the memory cell groups are controlled to discharge twice, and the initial voltage of the second discharge is determined based on the first discharge; the discharge durations of different storage unit groups are set to be different; based on each discharge result of the plurality of sensing nodes corresponding to each storage unit group, a first statistical number of each storage unit group is obtained, and the first statistical number is used for indicating the number of the storage units of which the threshold voltages are located in a preset threshold voltage interval in the storage unit group.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, a memory system, and an electronic device. Background Technology

[0002] With the continuous development of science and technology, semiconductor memories are widely used in various electronic devices and products. For example, NAND flash memory, as a type of non-volatile memory, is a commonly used semiconductor memory device in computers. How to improve the accuracy of NAND flash memory read operations has always been a key research topic for those skilled in the art. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory and its operation method, a memory system, and an electronic device.

[0004] According to a first aspect of this disclosure, a memory is provided, comprising:

[0005] A storage cell array, comprising multiple storage cells;

[0006] Word lines and bit lines are coupled to the plurality of memory cells;

[0007] Peripheral circuitry, coupled to the word line, the peripheral circuitry including a page buffer, the sensing node of the page buffer being coupled to the bit line, the peripheral circuitry being configured as follows:

[0008] Apply the first read voltage to the selected character line;

[0009] Charge the sensing node corresponding to the memory cell coupled to the selected word line;

[0010] The selected word line-coupled storage cell is divided into multiple storage cell groups for sensing operations. Each storage cell group includes multiple storage cells. The sensing operations include controlling multiple sensing nodes corresponding to the storage cell group to perform two discharges, wherein the starting voltage of the second discharge is determined based on the first discharge. The discharge duration of different storage cell groups is set differently.

[0011] Based on the discharge results of each of the multiple sensing nodes corresponding to each of the storage cell groups, a first statistical number is obtained for each of the storage cell groups; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the first statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

[0012] According to a second aspect of this disclosure, a method for operating a memory is provided. The memory includes a memory cell array, word lines, bit lines, and peripheral circuitry. The memory cell array includes a plurality of memory cells. The word lines and the bit lines are coupled to the plurality of memory cells. The peripheral circuitry is coupled to the word lines. The peripheral circuitry includes a page buffer, and a sensing node of the page buffer is coupled to the bit lines. The method of operation includes:

[0013] Apply the first read voltage to the selected character line;

[0014] Charge the sensing node corresponding to the memory cell coupled to the selected word line;

[0015] The selected word line-coupled storage cell is divided into multiple storage cell groups for sensing operations. Each storage cell group includes multiple storage cells. The sensing operations include controlling multiple sensing nodes corresponding to the storage cell group to perform two discharges, wherein the starting voltage of the second discharge is determined based on the first discharge. The discharge duration of different storage cell groups is set differently.

[0016] Based on the discharge results of each of the multiple sensing nodes corresponding to each of the storage cell groups, a first statistical number is obtained for each of the storage cell groups; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the first statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

[0017] According to a third aspect of this disclosure, a memory system is provided, comprising: one or more memories as described in any of the first aspects of this disclosure;

[0018] A memory controller is coupled to the memory and configured to control the memory.

[0019] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a memory system as described in a third aspect of this disclosure.

[0020] The memory provided in this embodiment divides the selected word-coupled memory cells into multiple memory cell groups for sensing operations. The discharge durations of the multiple memory cell groups differ to determine the number of memory cells in different threshold voltage ranges. Since the sensing operations on multiple memory cell groups can overlap, for example, sensing operations can be performed on multiple memory cell groups simultaneously. This allows the number of memory cells in multiple threshold voltage ranges to be determined within the same time period, thereby saving the operation time for determining valley values.

[0021] Furthermore, when performing sensing operations on the memory cell group, the sensing node is charged once and then discharged twice. The sensing node does not need to be recharged before the second discharge; instead, the second discharge is performed based on the first discharge. In other words, the starting voltage for the second discharge is determined based on the first discharge. This reduces the charging time, shortens the total AVD operation time, and simplifies the AVD operation process. Attached Figure Description

[0022] Figure 1a A schematic diagram of an electronic device including a memory, provided for an embodiment of this disclosure;

[0023] Figure 1b A schematic diagram of a memory card including a memory provided for an embodiment of this disclosure;

[0024] Figure 1c A schematic diagram of a solid-state drive including a memory, provided for an embodiment of this disclosure;

[0025] Figure 1d A schematic diagram of a memory including peripheral circuitry provided for an embodiment of this disclosure;

[0026] Figure 1e This is a schematic diagram of a storage cell array including storage strings, provided as an embodiment of the present disclosure;

[0027] Figure 1f A schematic diagram of a peripheral circuit provided for an embodiment of this disclosure;

[0028] Figure 2 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of this disclosure;

[0029] Figure 3a A schematic diagram of a storage unit and a sensing node provided in an embodiment of this disclosure;

[0030] Figure 3b For sensing the voltage V at node SO SO A diagram illustrating the changes over time;

[0031] Figure 4 A schematic diagram illustrating a method for detecting the valley value of a threshold voltage distribution using BL modulation, provided in an embodiment of this disclosure;

[0032] Figure 5 A schematic diagram of an AVD method provided in an embodiment of this disclosure;

[0033] Figure 6 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0034] Figure 7A schematic diagram of yet another AVD method provided in an embodiment of this disclosure;

[0035] Figure 8 A schematic diagram of a page buffer provided in an embodiment of this disclosure;

[0036] Figure 9 A schematic diagram illustrating yet another AVD method provided in an embodiment of this disclosure;

[0037] Figure 10 A schematic diagram of another AVD method provided in an embodiment of this disclosure;

[0038] Figure 11 A schematic diagram of yet another page buffer provided in an embodiment of this disclosure;

[0039] Figure 12 A flowchart illustrating an operation method for determining a valley value provided in an embodiment of this disclosure;

[0040] Figure 13 A flowchart illustrating another method for determining a valley value provided in this embodiment of the present disclosure;

[0041] Figure 14 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0047] Figure 1a This is a block diagram of an electronic device including memory, provided for embodiments of the present disclosure. The electronic device 10 may include a host 20 and a memory system 30. The electronic device 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory 34 therein; the host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)).

[0048] In one embodiment of this disclosure, the host 20 may be configured to send data to or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memories 34. The memories 34 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0049] In one embodiment of this disclosure, a memory controller 32 may be coupled to the memory 34 and the host 20 and is used to control the memory 34. Exemplarily, the memory controller 32 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 32 may also be designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0050] Furthermore, the memory controller 32 can manage the data in the memory 34 and communicate with the host 20. The memory controller 32 can be configured to control operations such as reading, erasing, and programming of the memory 34; it can also be configured to manage various functions related to data stored or to be stored in the memory 34, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to process error checking and correction codes (ECC) for data read from or written to the memory 34. In addition, the memory controller 32 can perform any other suitable functions, such as formatting the memory 34, or communicating with external devices (e.g., the host 20 in Figure 1) according to a specific communication protocol. For example, the memory controller 32 can communicate with an external host through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0051] In one embodiment of this disclosure, the memory controller 32 and one or more memories 34 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 can be implemented and packaged into different types of end electronic products. Figure 1bAs shown, the memory controller 32 and the individual memory 34 can be integrated together to form a memory card 40. The memory card 40 may include a PC card (Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 40 may also include a memory card connector 41 that couples the memory card 40 to a host (e.g., host 20 in Figure 1). Figure 1c In another embodiment shown, the memory controller 32 and a plurality of memories 34 may be integrated together to form an SSD 50. The SSD 50 may also include an SSD connector 51 that couples the SSD 220 to a host (e.g., host 110 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0052] Figure 1d A schematic diagram of a memory including peripheral circuitry is provided for an embodiment of this disclosure, wherein the memory may be... Figures 1a to 1c Any of the memory locations 34. For example... Figure 1d As shown, the memory may include a memory cell array 61 and peripheral circuitry 62 coupled to the memory cell array 61. Here, the memory cell array 61 may be a NAND flash memory cell array, wherein the memory cell array 61 is arranged in the form of a memory string array, with each memory string 63 extending vertically above the substrate. In some embodiments, each memory string 63 may include a plurality of memory cells 64 coupled in series and stacked vertically. Each memory cell 64 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the memory cell region. Additionally, each memory cell 64 in the aforementioned memory cell array 61 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0053] like Figure 1d As shown, each memory string 63 may include a lower select tube 66 at its source end and an upper select tube 65 at its drain end. The lower select tube 66 and the upper select tube 65 may be configured to activate the selected NAND memory string 63 (column of the array) during read and program operations.

[0054] In some implementations, the sources of NAND flash strings 63 within the same memory block (referred to as a "block") 67 are coupled via a common source line (SL) 71 (e.g., a common source line). In other words, according to some implementations, all flash strings 63 within the same block 67 have an array common source (ACS). According to some implementations, the select transistor 65 of each flash string 63 is coupled to a corresponding bit line 72, allowing data to be read from or written to the bit line 72 via an output bus (not shown).

[0055] In some embodiments, each memory string 63 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage having the upper select transistor 65) or a deselection voltage (e.g., 0V) to the gate of the corresponding upper select transistor 65 via one or more top select gate (TSG) lines 73; and / or by applying a selection voltage (e.g., higher than the threshold voltage having the lower select transistor 66) or a deselection voltage (e.g., 0V) to the gate of the corresponding lower select transistor 66 via one or more bottom select gate (BSG) lines 74. Memory strings 63 can thus be distinguished as selected memory strings or unselected memory strings.

[0056] like Figure 1d As shown, the memory string 63 can be organized into multiple blocks 67, each of which can have a common source line 71 (e.g., coupled to ground). In some embodiments, each block 67 is a basic data unit for an erase operation, i.e., all memory cells 64 on the same block 67 are erased simultaneously. To erase memory cells 64 in a selected block, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source line 71 of the selected block and the unselected blocks on the same plane as the selected block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0057] Memory cells 64 of adjacent memory strings 63 can be coupled via word lines 75, which select which row of memory cells 64 is affected by read and program operations. In some embodiments, each word line 75 is coupled to a page 68 of memory cells 64, which is a basic unit of data used for programming operations. The size of a page 68, in bits, can be related to the number of memory strings 63 coupled by word lines 75 in a block 67. Each word line 75 may include multiple control gates (gate electrodes) at each memory cell 64 in the corresponding page 68 and gate lines coupling the control gates.

[0058] Figure 1e This is a schematic diagram of a storage cell array including storage strings, provided as an embodiment of this disclosure. Figure 1e As shown, the memory string 63 can extend vertically through the stacked layer 81 above the substrate 80. The stacked layer 81 can include alternating gate conductive layers 82 and dielectric layers 83, wherein the number of pairs of gate conductive layers 82 and dielectric layers 83 determines the number of memory cells 64 in the memory cell array 61. The gate conductive layer 82 can extend laterally at the top of the memory stacked layer 81 as an upper select gate line 73, laterally at the bottom of the stacked layer 81 as a lower select gate line 74, or laterally between the upper select gate line 73 and the lower select gate line 74 as a word line 75. It should be understood that, although Figure 1d The diagram shows a lower select gate line 74 and an upper select gate line 73, but the number of lower select gate lines 74 and the number of upper select gate lines 73 (as well as the number of lower select tubes 66 and upper select tubes 65 coupled to the lower select gate line 74 and the upper select gate line 73, respectively) can vary in other examples.

[0059] like Figure 1e As shown, the memory string 63 includes a channel structure 84 extending vertically through the stacked layer 81. In some embodiments, the channel structure 84 includes a channel 85 and a memory film 86. In some embodiments, the channel 85 is made of a semiconductor material, including silicon, for example, polycrystalline silicon. In some embodiments, the memory film 86 is a composite dielectric layer including a tunneling layer 86a, a storage layer 86b (also referred to as a "charge trapping layer"), and a barrier layer 86c. The channel structure 84 may have a pillar shape (e.g., a cylindrical shape). According to some embodiments, the channel 85, tunneling layer 86a, storage layer 86b, and barrier layer 86c are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 86a may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 86b may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 86c may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 86 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0060] In some embodiments, such as Figure 1e As shown, a well 87 (e.g., a P-well and / or an N-well) is formed in the substrate 80, and the source terminal of the memory string 63 contacts the well 87. For example, a source line 71 may be coupled to the well 87 to apply an erase voltage to the well 87 (i.e., the source of the memory string 63) during an erase operation. In some embodiments, the memory string 63 also includes a channel plug 88 at the drain terminal of the memory string 63, for example, as part of the drain terminal of the memory string 63. It should be understood that... Figure 1e The structure of channel 84 depicted is for illustrative purposes only and may be modified in other examples. It should be understood that, although in Figure 1e Additional components, not shown, may also form the memory cell array 61. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0061] Return to reference Figure 1d The peripheral circuitry 62 can be coupled to the memory cell array 61 via bit lines 72, word lines 75, source lines 71, lower select gate lines 74, and upper select gate lines 73. The peripheral circuitry 62 can include any suitable analog, digital, and mixed-signal circuitry for implementing write and read operations on the memory cell array 61 by applying voltage and / or current signals to each target memory cell 64 via bit lines 72, word lines 75, source lines 71, lower select gate lines 74, and upper select gate lines 73, and by sensing voltage and / or current signals from each target memory cell 64. The peripheral circuitry 62 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 1f The schematic diagram of the peripheral circuitry provided in this embodiment of the disclosure shows that peripheral circuitry 62 includes a page buffer 91, a column decoder / BL driver 92, a row decoder / WL driver 93, a voltage generator 94, control logic 95, a register 96, an interface (I / F) 97, and a data bus 98. It should be understood that in some examples, it may also include... Figure 1f Additional peripheral circuitry not shown.

[0062] Page buffer 91 can be configured to read data from memory cell array 61 and program (write) data to memory cell array 61 according to control signals from control logic 95.

[0063] The column decoder / BL driver 92 can be configured to be controlled by control logic 95 and to select one or more NAND memory strings 63 by applying a bit line voltage generated from voltage generator 94.

[0064] The line decoder / WL driver 93 can be configured to be controlled by control logic 95, and to select / deselect block 67 of memory cell array 61 and word line 75 in block 67 according to control signals generated by the control logic. The line decoder / WL driver 93 can also be configured to drive word line 75 using different word line voltages generated from voltage generator 94.

[0065] Control logic 95 can be coupled to each of the peripheral circuit sections described above and is configured to control the operation of each peripheral circuit section. Register 96 can be coupled to control logic 95 and includes a status register, a command register, and an address register to store status information, command opcodes, and command addresses for controlling the operation of the peripheral circuits. In some embodiments, control logic 95 can receive programming commands from a memory controller (e.g., memory controller 32 in FIG. 1) and send control signals to various peripheral circuit sections to perform read operations, programming operations, and erase operations, etc.

[0066] Interface 97 can be coupled to control logic 95 and act as a buffer to buffer control commands (e.g., programming commands) received from the memory controller or host and relay them to control logic 95, as well as to buffer status information received from control logic 95 and relay it to the memory controller or host.

[0067] Figure 2 This is a schematic diagram illustrating the threshold voltage distribution of a storage cell according to an embodiment of the present disclosure. The storage cell can store more than 2 bits of data. For example, an MLC (Multi-Level Cell) can store 2 bits of data, a TLC (Triple-Level Cell) can store 3 bits of data, and a QLC (Quad-Level Cell) can store 4 bits of data. In this embodiment, the case where the storage cell stores 3 bits of data, i.e., a TLC, will be described as an example.

[0068] The 3-bit data consists of lower, middle, and upper bits. If the upper bit is designated "X", the middle bit "Y", and the lower bit "Z", then the 3-bit data can be represented as "XYZ". When storing 3 bits of data in a memory cell, the memory cell can be in any of eight states corresponding to the threshold voltage. These eight states, from lowest to highest, are named "Er", "P1", "P2", "P3", "P4", "P5", "P6", and "P7". The eight states can be assigned the data "111", "110", "100", "000", "010", "011", "001", and "101". The correspondence between the states and data for the threshold voltage distribution can be arbitrarily set, and this disclosure does not impose any restrictions. Figure 2One of the correspondence methods is shown. Specifically, the states “Er”, “P1”, “P2”, “P3”, “P4”, “P5”, “P6” and “P7” correspond to the data “111”, “110”, “100”, “000”, “010”, “011”, “001” and “101” respectively.

[0069] Within a given state, not all memory cells have the same threshold voltage. In fact, the threshold voltages of all memory cells within a state exhibit a probability distribution. Multiple states correspond to multiple relatively independent probability distributions, with a trough between adjacent probability distributions. To read data from a memory cell, the state to which the cell's threshold voltage belongs can be determined. To determine the state, read voltages Vrd1, Vrd2, Vrd3, Vrd4, Vrd5, Vrd5, and Vrd7 are used to perform the read operation, where the read voltages lie at multiple troughs in the threshold voltage distribution curve.

[0070] State "Er" represents, for example, the erase state where data is erased. The threshold voltage of a memory cell in state "Er" is lower than the read voltage Vrd1. States "P1" to "P7" represent, for example, the non-erasure state (also known as the programming state) where charge is injected into the charge storage layer to write data to the memory cell. The threshold voltage of a memory cell in state "P1" is higher than the read voltage Vrd1 and lower than the read voltage Vrd2. The threshold voltage of a memory cell in state "P2" is higher than the read voltage Vrd2 and lower than the read voltage Vrd3. And so on, with the threshold voltage of a memory cell in state "P7" being higher than the read voltage Vrd7.

[0071] like Figure 2 As shown, each memory cell is configured to store 3 bits of data in one of eight states. By performing a read operation using two read voltages, Vrd1 and Vrd5, it can be determined whether the lower-order bit in the memory cell is a data "1" or a data "0". By performing a read operation using three read voltages, Vrd2, Vrd4, and Vrd6, it can be determined whether the middle-order bit in the memory cell is a data "1" or a data "0". By performing a read operation using two read voltages, Vrd3 and Vrd7, it can be determined whether the higher-order bit in the memory cell is a data "1" or a data "0". That is, by performing seven reads using seven read voltages on the selected page, the 3 bits of data stored in the memory cell are determined.

[0072] However, memory cells may lose charge over time, a phenomenon known as hold charge loss. Due to hold charge loss, the threshold voltage distribution of a memory cell may shift over time. For example, hold charge loss may cause the threshold voltage of the memory cell to decrease, leading to a negative shift in the threshold voltage distribution corresponding to the non-erased state (i.e.,...). Figure 2 The left side of the memory cell is shifted. As a result, the initial read voltage set based on, for example, the threshold voltage distribution of the memory cell obtained from post-manufacturing chip testing may no longer be at the valley of the two shifted threshold voltage distributions, thus potentially increasing read errors in read operations.

[0073] To improve the accuracy of read operations, it is necessary to first identify the valleys between adjacent threshold voltage distributions. One method for determining the valleys between adjacent threshold voltage distributions is Automatic Valley Detection (AVD). AVD algorithms need to balance accuracy and algorithm time; one of the mainstream AVD algorithms currently is the BLmodulation (bit line adjustment) method.

[0074] Before describing the method of using BL modulation to detect the valley of the threshold voltage distribution, this article first introduces a reading operation process. Figure 3a This is a schematic diagram of a storage unit and a sensing node provided in an embodiment of the present disclosure. Figure 3b For sensing the voltage V at node SO SO A diagram illustrating the changes over time. See also... Figure 1f and Figure 3a The sensing node SO of the page buffer 91 is coupled to a memory string 63 via bit line 72. During a read operation, the row decoder / WL driver 93 applies a read voltage (any one of Vrd1 to Vrd7) to the selected word line among multiple word lines. The page buffer 91 first charges the sensing node and bit line 72, and then controls the sensing node to discharge through the channel of bit line 72 and memory string 63.

[0075] See Figure 3b The sensing node SO is first charged to a preset voltage V. pre Then, it gradually discharges. The sensing node discharges at different rates depending on the threshold voltage of the memory cell 64 to be read. Taking the applied read voltage Vrd1 as an example, if the threshold voltage of the memory cell to be read is located in the threshold voltage distribution corresponding to the Er state, then the memory cell to be read is turned on, making the amplification rate of the sensing node SO fast, and its discharge curve can correspond to... Figure 3bThe black solid line with a steeper slope. If the threshold voltage of the memory cell 64 to be read is located in the threshold voltage distribution corresponding to the P0 state, then the memory cell to be read is weakly conducting or not conducting, resulting in a slow amplification rate of the sensing node SO, and its amplification curve can correspond to... Figure 3b A gray solid line with a moderate slope.

[0076] After the sensing node discharges for a period of time, the voltage of the sensing node SO and the switching voltage V are compared. trip The magnitude of the voltage across the sensing node can be used to determine whether the memory cell is conducting or not. Specifically, if the voltage of the sensing node is less than the switching voltage V... trip To determine if the memory cell is on, if the voltage at the sensing node is greater than the switching voltage V. trip This indicates that the memory cell is not conducting (Cell off).

[0077] The discharge duration of the sensing node during a read operation is called the sensing duration. The setting of the sensing duration affects the determination of the memory cell's state. With a constant read voltage, if the sensing duration is too long, some memory cells may be falsely identified as conducting, meaning these cells are incorrectly classified as being in the threshold voltage distribution to the left of the valley. If the sensing duration is too short, some memory cells may be falsely identified as not conducting, meaning these cells are incorrectly classified as being in the threshold voltage distribution to the right of the valley. Only with an appropriate sensing duration can the correct threshold voltage distribution of the memory cell be determined.

[0078] Figure 4 This diagram illustrates a principle of detecting valleys in a threshold voltage distribution using BL modulation, as provided in an embodiment of this disclosure. Figure 4 As shown, a read voltage Vrd is applied to the selected word line. The sensing node is charged to a preset voltage V. pre Then, the control sensing node begins to discharge. The first time, the control sensing node discharges from the preset voltage for a period T1, then stops, counting the number of conducting memory cells, which is recorded as the first data. The first data indicates that the threshold voltage is less than the first threshold voltage V. th1 The number of memory cells. Secondly, the control sensing node discharges from the preset voltage for (T1+T2) time and then stops, counting the number of conducting memory cells, which is recorded as the second data. The second data indicates that the threshold voltage is less than the second threshold voltage V. th2 The number of memory cells. The difference between the second data and the first data indicates the number of memory cells whose threshold voltage falls within the D1 threshold voltage range (hereinafter referred to as the D1 range). The upper limit of the D1 range is the second threshold voltage V. th2 The lower limit of the D1 interval is the first threshold voltage V. th1 .

[0079] Similarly, by controlling the sensing node to discharge from a preset voltage for a period of (T1+T2+T3) and then stopping, the number of conducting memory cells is counted and recorded as the third data. The third data indicates that the threshold voltage is less than the third threshold voltage V. th3 The number of memory cells, and the difference between the third and second data, indicate the number of memory cells whose threshold voltage falls within the D2 threshold voltage range (hereinafter referred to as the D2 range). By controlling the sensing node to discharge from a preset voltage for a period of (T1+T2+T3+T4) and then stopping, the number of conducting memory cells is counted and recorded as the fourth data. The fourth data indicates when the threshold voltage is less than the fourth threshold voltage V. th4 The number of storage cells is denoted as the fourth data. The difference between the fourth data and the third data represents the number of storage cells whose threshold voltage is in the D3 threshold voltage range (hereinafter referred to as the D3 range).

[0080] The valley of the threshold voltage distribution can be determined based on the number of memory cells in intervals D1, D2, and D3. For example, if the number of memory cells in interval D2 is less than the number of memory cells in interval D1 and also less than the number of memory cells in interval D3, then the valley is determined to be in interval D2. As another example, if the number of memory cells in intervals D1, D2, and D3 increases sequentially, then the valley is determined to be in interval D1; or, by further examining the number of memory cells in the D0 threshold voltage interval to the left of interval D1, and combining this with the number of memory cells in the D0 threshold voltage interval, the location of the valley can be determined. As yet another example, if the number of memory cells in intervals D1, D2, and D3 decreases sequentially, then the valley is determined to be in interval D3; or, by further combining this with the number of memory cells in the D4 threshold voltage interval to the right of interval D3, the location of the valley can be determined.

[0081] Figure 5 This is a flowchart illustrating an AVD method provided in an embodiment of the present disclosure. Figure 5 Let's take determining the number of storage units in the D2 interval as an example. Figure 5 As shown, a read voltage Vrd is applied to the selected word line, and the sensing node SO is charged to the preset voltage V for the first time. pre Then, the sensing node is controlled to perform the first discharge operation, with a discharge duration of (T1+T2+T3). After the first discharge is completed, the result of the first discharge is stored. Afterwards, the sensing node SO and the bit line are charged a second time, i.e. Figure 5 The bit line voltage is set in the configuration. Then, the sensing node is controlled to perform a second discharge operation, with a discharge duration of (T1+T2). After the second discharge, the number of memory cells in the D2 interval can be obtained based on the results of the two discharges.

[0082] The operations for determining the number of memory cells in interval D1 and interval D3 are the same, and will not be repeated here. Although this method can determine the number of memory cells in intervals D1, D2, and D3, it can only determine the number of memory cells in one interval at a time. This results in a longer processing time for the more threshold voltage intervals used to determine the valley values. Furthermore, the bit lines and sensing nodes need to be charged before each discharge operation, further extending the operation time and hindering memory efficiency.

[0083] This disclosure provides a memory for executing the operation method provided in this disclosure to shorten the time required to determine the valley value of the threshold voltage distribution using the BL modulation method. Figure 6 A schematic diagram of a memory provided in an embodiment of this disclosure, such as... Figure 6 As shown, the memory 100 includes a memory cell array 200, multiple word lines 310, multiple bit lines 320, and peripheral circuitry. The memory cell array 200 includes multiple memory cells 210, and the multiple word lines 310 and multiple bit lines 320 are all coupled to the multiple memory cells. The peripheral circuitry is coupled to the multiple word lines 310 and includes a page buffer 91, wherein the sensing node SO of the page buffer 91 is coupled to the bit lines 320.

[0084] The peripheral circuitry is configured as follows:

[0085] A first read voltage is applied to the selected word line 311 among the multiple word lines 310;

[0086] Charge the sensing node SO corresponding to the storage unit 210 coupled to the selected word line 311;

[0087] The selected word line 311 is coupled to a memory cell and the sensing operation is performed in multiple memory cell groups. Each memory cell group includes multiple memory cells. The sensing operation performed on each memory cell group includes controlling multiple sensing nodes corresponding to multiple memory cells in the memory cell group to discharge twice. The starting voltage of the second discharge is determined based on the first discharge, and the discharge duration is set differently for different memory cell groups.

[0088] Based on the discharge results of multiple sensing nodes corresponding to each storage cell group, a first statistical number is obtained for each storage cell group; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the first statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

[0089] The peripheral circuit in this embodiment can be Figure 1fThe peripheral circuit 62 is shown. For example, the line decoder / WL driver 93 in the peripheral circuit is used to apply a first read voltage to the selected word line 311. The selected word line 311 is any one of the multiple word lines 310; in other words, any word line can be used as the selected word line.

[0090] The peripheral circuitry includes multiple page buffers 91, each of which can be coupled to a bit line 320. In other words, multiple page buffers 91 and multiple bit lines 320 are connected in a one-to-one correspondence. The page buffers 91 can charge the sensing nodes and perform sensing operations. It should be noted that... Figure 6 This is only used to illustrate the coupling method of the peripheral circuits and memory cell array, and does not restrict their actual location.

[0091] Multiple storage cells 210 coupled to the selected word line are divided into multiple storage cell groups 400 for sensing operations. If the storage cells 210 coupled to the selected word line are sequentially numbered, the numbers of the multiple storage cells within a storage cell group 400 can be consecutive or non-consecutive. Taking the division of storage cells numbered 0 to 98 into three storage cell groups as an example: Consecutive groups could be: the first storage cell group includes storage cells numbered 0 to 32, the second storage cell group includes storage cells numbered 33 to 65, and the third storage cell group includes storage cells numbered 66 to 98. Non-consecutive groups could be: the first storage cell group includes storage cells whose numbers leave a remainder of 0 when divided by 3, the second storage cell group includes storage cells whose numbers leave a remainder of 1 when divided by 3, and the third storage cell group includes storage cells whose numbers leave a remainder of 2 when divided by 3. In summary, this disclosure does not restrict whether the multiple storage cells 210 within a storage cell group 400 need to be adjacent; the arrangement can be customized according to actual needs.

[0092] For example, the number of storage cells 210 in each of the multiple storage cell groups 400 is the same. That is, each storage cell group 400 includes the same number of storage cells 210. In this way, when counting the number of storage cells in different threshold voltage ranges, the sample size corresponding to each threshold voltage range (i.e., the number of storage cells participating in the statistics) is the same, and the number of storage cells in different threshold voltage ranges can be directly compared, making the comparison method simple. It should be understood that the number of storage cells in multiple storage cell groups may not be exactly the same. In this case, it may be necessary to use other parameters such as ratios (e.g., the ratio of conducting storage cells to storage cells participating in the statistics) for comparison. In summary, the number of storage cells in a storage cell group can be set according to actual needs.

[0093] For example, all memory cells coupled to the selected word line can participate in the sensing operation, that is, all memory cells coupled to the selected word line can be divided into multiple memory cell groups to perform the sensing operation. Also, for example, only some memory cells coupled to the selected word line can participate in the sensing operation, that is, a portion of memory cells can be selected from all memory cells coupled to the selected word line, and these portion of memory cells can be divided into multiple memory cell groups to perform the sensing operation.

[0094] Multiple memory cell groups are used to determine the number of memory cells in multiple threshold voltage ranges. In one embodiment of this disclosure, all memory cells coupled to the selected word line can be divided into four memory cell groups, and three of these groups are selected to determine the number of memory cells in ranges D1, D2, and D3, respectively. The sensing operations performed on the three memory cell groups can overlap. For example, sensing operations can be performed on the three memory cell groups simultaneously. This allows the number of memory cells in multiple threshold voltage ranges to be determined within the same time period, thereby saving the operation time for determining valley values.

[0095] Charging the sensing nodes corresponding to the memory cells coupled to the selected word line to a preset voltage means charging the sensing nodes corresponding to at least the memory cells for which the following sensing operations are to be performed to the preset voltage. The charging operations performed on the sensing nodes corresponding to memory cells in multiple memory cell groups can overlap. For example, charging can be performed simultaneously on the sensing nodes corresponding to multiple memory cell groups. In a specific embodiment, the sensing nodes corresponding to all memory cells coupled to the selected word line can be charged to the preset voltage simultaneously, which simplifies the control scheme and avoids negative impacts.

[0096] In some embodiments, the peripheral circuitry is further configured to charge bit lines coupled to memory cells coupled to the selected word line. For example, the bit lines are charged to a preset voltage. Charging the bit lines reduces the impact of the bit line voltage on the accuracy of the sensing results. The bit lines and sensing nodes can be charged simultaneously, i.e., the bit lines and sensing nodes are on during charging to charge both to the preset voltage simultaneously. In another embodiment, the bit lines and sensing nodes can also be charged to the preset voltage separately. For example, the bit lines and sensing nodes can be disconnected, and each can be charged to the preset voltage separately.

[0097] This disclosure does not limit the operation of applying the first read voltage to the selected character line first, or charging the sensing node first. For example, the first read voltage can be applied to the selected character line first, and then the sensing node can be charged to a preset voltage. Also for example, the sensing node can be charged to a preset voltage first, and then the first read voltage can be applied to the selected character line.

[0098] Figure 7 This is a flowchart illustrating yet another AVD method provided in an embodiment of the present disclosure. Figure 7This illustrates the process of determining the number of memory cells in intervals D1, D2, and D3 using the first, second, and third memory cell groups, respectively. Here, numbering the memory cell groups is only for distinguishing different groups and does not restrict their location. The following explanation uses the first memory cell group Q0 to determine the number of memory cells in interval D1 as an example. Figure 7 As shown, a preset voltage V is applied to the selected word line to charge the sensing node SO and the bit line. pre Then, the multiple sensing nodes corresponding to multiple storage cells in the first storage cell group Q0 are controlled to perform a first discharge, and the result is stored. Next, the sensing node SO is controlled to directly perform a second discharge, and the result is stored. Before the second discharge, it is not necessary to recharge the sensing node and bit line; instead, the second discharge is performed based on the first discharge. In other words, the starting voltage of the second discharge is determined based on the first discharge, which reduces one charging time, shortens the total AVD operation time, and simplifies the AVD operation process. In one specific embodiment, it has been verified that reducing one charging time can shorten the entire AVD time by at least 8µs.

[0099] For example, the starting voltage of the second discharge is equal to the ending voltage of the first discharge. (Combined) Figure 4 and Figure 7 To understand, when the control sensing node is switched from a preset voltage V pre After the first discharge begins, the threshold voltage is found to be less than the first threshold voltage V. th1 The number of storage units, i.e., the first data. Then, the termination voltage after the first discharge is used as the starting voltage for the second discharge. Since the second discharge is based on the first discharge, it is equivalent to starting from the preset voltage V. pre The discharge continues from the beginning until the end of the second discharge; therefore, the threshold voltage can be obtained as being less than the second threshold voltage V. th2 The number of memory cells, also known as the second data, is the value of the first data. The difference between the second data and the first data represents the number of memory cells whose threshold voltage falls within the D1 range.

[0100] like Figure 7 As shown, the discharge duration is set differently for different memory cell groups. This is because different memory cell groups correspond to different... Figure 4 The threshold voltage ranges differ. Based on these different threshold voltage ranges, different discharge duration settings can be applied to different memory cell groups.

[0101] In some embodiments, each group of memory cells begins to discharge from a preset voltage, wherein the first discharge duration of different groups of memory cells is different, and the second discharge duration is the same.

[0102] In this embodiment, the second discharge duration is the same, which makes the threshold voltage range widths of different memory cell groups the same. Therefore, the location of the valley value can be determined by directly comparing the number of memory cells in different threshold voltage ranges, making the operation simpler and more efficient, and shortening the AVD time. Here, the width of the threshold voltage range refers to the difference between the upper and lower limits of the threshold voltage range. In other embodiments, the widths of the threshold voltage ranges of different memory cell groups may not be exactly the same. In this case, it may not be possible to directly compare the number of memory cells in different threshold voltage ranges, and it is necessary to use methods such as normalization to convert them into the same threshold voltage range before comparison.

[0103] It should be noted that the second discharge duration of different memory cell groups in this disclosure is the same, and error is allowed. That is, the second discharge duration of different memory cell groups is the same within the allowable error range.

[0104] The first discharge of different memory cell groups is used to determine the lower limit of the threshold voltage range, or in other words, to determine the position of the threshold voltage range within the threshold voltage distribution. Therefore, the first discharge duration of different memory cell groups is different, which ensures that the threshold voltage ranges corresponding to different memory cell groups are different, so that the valley of the threshold voltage distribution can be determined by the number of memory cells in multiple threshold voltage ranges.

[0105] It should be understood that, considering only a single memory cell group, the preset voltage does not affect the number of memory cells within the corresponding threshold voltage range. Therefore, different memory cell groups can use different preset voltages, and the number of memory cells within the corresponding threshold voltage range can be determined by adjusting the first discharge duration. However, in this embodiment, charging all memory cell groups to the same preset voltage simplifies the operation and improves the efficiency of AVD. This disclosure does not limit the magnitude of the preset voltage; the preset voltage can be set according to actual needs.

[0106] In some embodiments, different memory cell groups are sorted from shortest to longest first discharge duration, wherein the first discharge duration of the latter in two adjacent memory cell groups is equal to the sum of the first discharge duration and the second discharge duration of the former.

[0107] See Figure 4 and Figure 7After sorting the different memory cell groups 400 according to the length of their first discharge in ascending order, the latter group has a longer first discharge duration, resulting in a larger lower limit of its threshold voltage range. The former group has a shorter first discharge duration, resulting in a smaller lower limit of its threshold voltage range. The first discharge duration of the latter group is equal to the sum of the first and second discharge durations of the former group. Therefore, the termination voltage after the first discharge of the latter group is equivalent to the termination voltage after the second discharge of the former group. Alternatively, the starting voltage of the second discharge of the latter group can be understood as the termination voltage of the second discharge of the former group. This allows the boundaries of their corresponding threshold voltage ranges to coincide. In other words, the lower limit of the threshold voltage range corresponding to the latter group is equal to the upper limit of the threshold voltage range corresponding to the former group.

[0108] according to Figure 4 and Figure 7 It can be seen that the first discharge duration (T1+T2) of the second memory cell group Q1 is equal to the sum of the first discharge duration T1 and the second discharge duration T2 of the first memory cell group Q0, causing the lower limit of the D2 interval to coincide with the upper limit of the D1 interval. The first discharge duration (T1+T2+T3) of the third memory cell group Q2 is equal to the sum of the first discharge duration (T1+T2+) and the second discharge duration T3 of the second memory cell group Q1, causing the lower limit of the D3 interval to coincide with the upper limit of the D2 interval.

[0109] It should be understood that if the first discharge duration of the second memory cell group Q1 is greater than the sum of the first and second discharge durations of the first memory cell group Q0, then the lower limit of the D2 interval does not coincide with the upper limit of the D1 interval. Specifically, the lower limit of the D2 interval is greater than the upper limit of the D1 interval. Similarly, if the first discharge duration of the third memory cell group Q2 is greater than the sum of the first and second discharge durations of the second memory cell group Q1, then the lower limit of the D3 interval does not coincide with the upper limit of the D2 interval. Specifically, the lower limit of the D3 interval is greater than the upper limit of the D2 interval. This setting can also determine the valley value based on the number of memory cells in the D1, D2, and D3 intervals. However... Figure 7 In this scheme, multiple threshold voltage ranges are set continuously without interruption, which can more accurately determine the location of the valley value.

[0110] It should be noted that, in the above disclosure, the first discharge duration of the latter in two adjacent memory cell groups is equal to the sum of the first and second discharge durations of the former, and this is subject to error. That is, the first discharge duration of the latter is approximately equal to the sum of the first and second discharge durations of the former.

[0111] In some embodiments, the first discharge duration of a memory cell group includes one or more unit durations, and the second discharge duration includes one unit duration. The first discharge durations of multiple memory cell groups increase in increments of one unit duration.

[0112] See back Figure 4 and Figure 7 The first discharge duration of the memory cell group with the shortest first discharge duration can include one unit duration, and the second discharge duration also includes one unit duration. The first discharge duration of all other memory cell groups includes two or more units of duration. Increasing the first discharge duration of multiple memory cell groups in increments of one unit duration allows the boundaries of the threshold voltage ranges corresponding to adjacent memory cell groups to overlap after sorting by first discharge duration from shortest to longest. For example, Figure 7 In this process, the first discharge duration of the first, second, and third memory cell groups includes one, two, and three unit durations (T), respectively, and their second discharge durations each include one unit duration, so that the boundaries of the D1 and D2 intervals coincide, and the boundaries of the D2 and D3 intervals coincide, that is, the threshold voltages corresponding to the D1, D2, and D3 intervals are continuously set.

[0113] The following details how to use page buffers to determine the number of memory cells in the threshold voltage range.

[0114] In some embodiments, the peripheral circuitry includes a plurality of page buffers, each page buffer having a sensing node coupled to a bit line. Each page buffer is configured as follows:

[0115] Based on the first discharge result of the sensing node, a first value is obtained; wherein, the first value is used to indicate whether the threshold voltage of the memory cell is less than a first preset threshold voltage;

[0116] Based on the second discharge result of the sensing node, a second value is obtained; wherein, the second value is used to indicate whether the threshold voltage of the memory cell is less than a second preset threshold voltage;

[0117] A third value is obtained by performing logical operations on the first and second values; wherein the third value indicates whether the threshold voltage of the storage cell is within a preset threshold voltage range, the preset threshold voltage range being the range that is less than the second preset threshold voltage and greater than or equal to the first preset threshold voltage.

[0118] The peripheral circuitry also includes control logic coupled to the page buffer, which is configured to obtain a first statistic based on multiple third values ​​from multiple memory cells.

[0119] The following is combined with Figure 6The following explanation uses a group of memory cells as an example. Multiple memory cells 210 of the memory cell group 400 are coupled to the sensing nodes SO of the corresponding page buffer 91 via bit lines 320. During AVD operation, each sensing node and its coupled bit line are charged to a preset voltage, and the sensing node is controlled to perform a first discharge through the bit lines and memory string. The page buffer 91 obtains a first value based on the first discharge result and stores the first value. The first value can be a logic value "0" or "1", used to indicate whether the threshold voltage of the memory cell coupled to the page buffer is less than a first preset threshold voltage. For example, a first value of "1" indicates that the threshold voltage of the memory cell is less than the first preset threshold voltage, and a first value of "0" indicates that the threshold voltage of the memory cell is greater than or equal to the first preset threshold voltage. Conversely, the opposite is also possible.

[0120] After storing the first value, the control sensing node performs a second discharge. The page buffer 91 obtains a second value based on the result of the second discharge. The second value can be a logic value "0" or "1", used to indicate whether the threshold voltage of the memory cell coupled to the page buffer is less than a second preset threshold voltage. For example, a first value of "1" can indicate that the threshold voltage of the memory cell is less than the second preset threshold voltage, and a first value of "0" can indicate that the threshold voltage of the memory cell is greater than or equal to the second preset voltage. The reverse is also possible.

[0121] After obtaining the first and second values, the page buffer performs logical operations on them to obtain a third value. This third value can be either a logical "0" or "1," and it indicates whether the threshold voltage of the memory cell coupled to the page buffer is within a preset threshold voltage range. In other words, the third value indicates that the threshold voltage of the memory cell is greater than or equal to the first preset threshold voltage and less than the second preset threshold voltage.

[0122] This disclosure does not limit the specific content of the "logical operation". In specific embodiments, the values ​​of the first, second, and third values ​​can be set according to the relationship between the indicated content and the values ​​of the first, second, and third values. In one embodiment, the first value of "0" indicates that the threshold voltage of the memory cell is less than a first preset voltage, and the second value of "0" indicates that the threshold voltage of the memory cell is less than a second preset voltage. The logical operation can be an XOR operation, and correspondingly, the third value of "1" indicates that the threshold voltage of the memory cell is within the preset threshold voltage range.

[0123] The control logic can obtain the third value from all page buffers corresponding to the memory cell group, and based on the value of the third value, a first statistic can be obtained. Continuing with the above embodiment, the control logic counts the number of "1"s in the third value output by all page buffers corresponding to the memory cell group to obtain the first statistic. Therefore, the first statistic can indicate the number of memory cells in the memory cell group whose threshold voltage is within a preset threshold voltage range.

[0124] In some embodiments, the page buffer obtains the first value based on the first discharge result as follows: The first voltage of the sensing node after the first discharge is compared with a first reference voltage, and the first value is obtained based on the comparison result. Wherein, if the first voltage is less than the first reference voltage, it indicates that the memory cell is turned on, and the threshold voltage of the memory cell is less than a first preset threshold voltage. If the first voltage is greater than or equal to the first reference voltage, it indicates that the memory cell is not turned on or weakly turned on, and the threshold voltage of the memory cell is greater than or equal to the first preset threshold voltage.

[0125] Similarly, the specific implementation of the page buffer obtaining the second value based on the second discharge result can be as follows: compare the second voltage of the sensing node after the second discharge with the second reference voltage, and obtain the second value based on the comparison result; wherein, if the second voltage is less than the second reference voltage, it indicates that the memory cell is turned on, and the threshold voltage of the memory cell is less than the second preset threshold voltage. If the second voltage is greater than or equal to the second reference voltage, it indicates that the memory cell is not turned on or weakly turned on, and the threshold voltage of the memory cell is greater than or equal to the second preset threshold voltage.

[0126] For example, the second reference voltage is equal to the first reference voltage; both are collectively referred to as reference voltages. The reference voltage can be the switching voltage V during the read operation. trip .

[0127] See Figure 8 The page buffer includes a sensing circuit 510 coupled to a sensing node SO. For example, the sensing circuit 510 may include a MOS transistor, with the sensing node SO coupled to the gate of the MOS transistor. The reference voltage or switching voltage may be the threshold voltage of the MOS transistor. Taking an NMOS transistor as an example, when the voltage of the sensing node (a first voltage or a second voltage) is less than the threshold voltage of the NMOS transistor, the NMOS transistor is closed, and the value sensed by the sensing circuit (a first value or a second value) is "0". When the voltage of the sensing node is greater than or equal to the threshold voltage of the NMOS transistor, the NMOS transistor is turned on, and the value sensed by the sensing circuit is "1". It should be understood that the specific circuit structure for the sensing circuit to compare the voltage of the sensing node with the reference voltage and obtain the first and second values ​​is not limited in the embodiments of this disclosure. Different designs may be used in different embodiments.

[0128] In some embodiments, the page buffer 91 further includes a sense D-Latch (DS) 520, a logic operation circuit 530, and a first data latch (No.1 D-Latch, D1) 540, wherein the sense latch 520 is coupled to the sense circuit 510, the logic operation circuit 530 is coupled to the sense circuit 510 and the sense latch 520, and the first data latch 540 is coupled to the logic operation circuit 530. During AVD operation, one configuration of the sense circuit 510, the sense latch 520, the logic operation circuit 530, and the first data latch 540 is as follows:

[0129] After the sensing node discharges for the first time, the sensing circuit 510 is configured to obtain a first value. The sensing latch 520 is configured to receive the first value output by the sensing circuit 510 and store the first value.

[0130] After the sensing node discharges for the second time, the sensing circuit 510 is configured to obtain a second value. The logic operation circuit 530 is configured to receive the second value output by the sensing circuit 510 and perform a logic operation based on the first and second values ​​to obtain a third value. The first data latch 540 is configured to receive the third value output by the logic operation circuit 530 and store the third value.

[0131] This disclosure does not limit when the logic operation circuit acquires the first value. For example, the logic operation circuit 530 may receive the first value output by the sensing latch 520 after the sensing node discharges for the first time.

[0132] In some embodiments, page buffers for different memory cell groups can be controlled individually. For example... Figure 7 As shown, the page buffer simultaneously charges the sensing nodes SO, which are coupled to multiple memory cell groups, to a preset voltage V. pre The system controls the sensing nodes to simultaneously begin their first discharge. The second discharge of different memory cell groups can occur simultaneously or at different times. Figure 7 In this system, the second discharge of different memory cell groups is controlled independently, and the second discharges of different memory cell groups do not occur simultaneously. The start time of the second discharge also depends on the end time of the first discharge. For example, the time it takes for different memory cell groups to obtain the first value and store the first value after the first discharge can be approximately equal. In other words, the time from the end of the first discharge to the start of the second discharge for different memory cell groups can be approximately equal. Figure 7 In the diagram, the time from discharge T1 to discharge T2 for the first memory cell group Q0 is approximately equal to the time from discharge T2 to discharge T3 for the second memory cell group Q1, and approximately equal to the time from discharge T3 to discharge T4 for the third memory cell group. Therefore, the memory cell group that completes its first discharge first can undergo its second discharge after storing the results.

[0133] In some embodiments, the first discharge includes a pre-discharge and a main discharge, with the pre-discharge duration being the same for different memory cell groups; the page buffer is configured as follows:

[0134] The control sensor node is pre-discharged starting from a preset voltage, and the read value of the storage unit is obtained based on the pre-discharge result of the sensor node; the control sensor node is then used for main discharge; wherein the starting voltage of the main discharge is the ending voltage of the pre-discharge.

[0135] The read value of a memory cell refers to the data stored in that cell. This read value can be any of the high-order, mid-order, and low-order bits, depending on the read voltage (Vrd1 to Vrd7). Controlling the sensing node to pre-discharge from a preset voltage essentially performs a regular read operation; the pre-discharge duration is the sensing duration in the read operation. After the read operation, the AVD operation is performed. In other words, this embodiment combines the read and AVD operations into a single operation, reducing the AVD operation time and thus improving memory efficiency.

[0136] Figure 9 This is a flowchart illustrating another AVD method provided in this disclosure. The following details the method of combining the read operation and the AVD operation into a single operation. Figure 9 As shown, the first discharge of the first memory cell group Q0, the second memory cell group Q1, and the third memory cell group Q2 all include a pre-discharge and a main discharge. For example, their pre-discharge durations each include a unit duration T.

[0137] For example, the pre-discharge operation of multiple memory cell groups is performed synchronously, that is, the synchronous control sensing nodes start discharging from a preset voltage and stop discharging synchronously after a unit time. It should be understood that all memory cells coupled to the selected word line need to be pre-discharged, including those not participating in the AVD operation, in order to determine the read value in the memory cell. For example, all memory cells coupled to the selected word line are pre-discharged synchronously to obtain the read value of each memory cell.

[0138] After pre-discharge, multiple memory cell groups begin main discharge. The main discharge durations of different memory cell groups are different, resulting in different first discharge durations for each group. In this embodiment, the main discharge durations of the first memory cell group Q0, the second memory cell group Q1, and the third memory cell group Q2 are one unit duration, two unit durations, and three unit durations, respectively. After the main discharge, the sensing circuit can obtain the first value.

[0139] It should be understood that since the main discharge is performed based on the pre-discharge, the voltage of the sensing node after the main discharge is equal to the voltage of the sensing node after the continuous discharge from the preset voltage for the pre-discharge duration plus the main discharge duration. Therefore, the pre-discharge does not affect the first value. The first value is still used to indicate whether the threshold voltage of the memory cell is less than the first preset threshold voltage.

[0140] In some embodiments, such as Figure 9 As shown, the time taken for different memory cell groups to obtain and store the read value after pre-discharge can be approximately equal. In other words, the time from the end of pre-discharge to the start of main discharge can be approximately equal for different memory cell groups. Similarly, the time taken for different memory cell groups to obtain and store the first value after main discharge can be approximately equal. In other words, the time taken from the end of main discharge to the start of the second discharge can be approximately equal for different memory cell groups.

[0141] In the first discharge, the duration of the main discharge can be 0. For example, the first discharge duration of the memory cell group with the shortest first discharge duration is equal to the pre-discharge duration, and the main discharge duration is 0. In this case, the read value and the first value can be determined based on the result of the pre-discharge.

[0142] Figure 10 This is a flowchart illustrating another AVD method provided in an embodiment of this disclosure. Figure 10 As shown, the pre-discharge duration of the first memory cell group Q0 is equal to the first discharge duration T1, and the main discharge duration is 0. The first memory cell group Q0 obtains the read value and the first value in the memory cell through pre-discharge; the first value and the read value are the same. The pre-discharge duration of the second memory cell group Q1 includes one unit duration T1, and the main discharge duration includes one unit duration T2. ​​The second memory cell group Q1 obtains the read value after pre-discharge and the first value after main discharge. The pre-discharge duration of the third memory cell group Q2 includes one unit duration T1, and the main discharge duration includes two unit durations (T2+T3). The third memory cell group Q2 also obtains the read value after pre-discharge and the first value after main discharge.

[0143] In this embodiment, if we rephrase it and do not include the pre-charge in the first discharge, it can be described as follows: In addition to the memory cell group with the shortest first discharge duration, the other memory cell groups also include pre-discharge. The pre-discharge is performed before the first discharge, and the starting voltage of the first discharge is the ending voltage of the pre-discharge. The first discharge of the memory cell group with the shortest first discharge duration also serves as its pre-discharge.

[0144] In some embodiments, such as Figure 10As shown, the time from the end of the pre-discharge of the first memory cell group Q0 to the start of the second discharge can be approximately equal to the sum of the time from the end of the pre-discharge to the start of the main discharge and the time from the end of the main discharge to the start of the second discharge for the other memory cell groups (Q1, Q2). In other words, the time for different memory cell groups to obtain and store the read value after the pre-discharge can be approximately equal, and the time for obtaining and storing the first value after the main discharge (the main discharge time for the first memory cell group Q0 can be 0) can be approximately equal.

[0145] In some embodiments, see Figure 11 The page buffer 91 also includes a bias latch (DL) 550 and a cache latch (DC) 560, wherein the bias latch 550 is coupled to the sensing circuit 510, and the cache latch 560 is coupled to the bias latch 550. During read and AVD operations, one configuration of the sensing circuit 510, sensing latch 520, logic operation circuit 530, first data latch 540, bias latch 550, and cache latch 560 is as follows:

[0146] After the sensing node is pre-discharged, the sensing circuit 510 is configured to obtain a read value. The bias latch 550 is configured to receive the read value output by the sensing circuit 510 and store the read value.

[0147] After the main discharge of the sensing node, the sensing circuit 510 is configured to obtain a first value. The sensing latch 520 is configured to receive the first value output by the sensing circuit 510 and store the first value.

[0148] After the sensing node discharges for the second time, the sensing circuit 510 is configured to obtain a second value. The logic operation circuit 530 is configured to receive the second value output by the sensing circuit 510 and obtain a third value based on the first and second values. The first data latch 540 is configured to receive the third value output by the logic operation circuit and store the third value. The bias latch 550 is also configured to send the read value to the buffer latch 560. The buffer latch 560 is configured to store the read value.

[0149] Finally, after the read operation and AVD operation are completed, the read value is stored in the cache latch 560, and the third value is stored in the first data latch 540.

[0150] In some embodiments, the page buffer 91 further includes a sense control switch 580 coupled between the sense node SO and the bit line 320. The sense control switch 580 is configured to control the sense node SO to be on or off from the bit line 320; wherein, when the sense node SO is on, the sense node SO discharges, and when the sense node SO is off, the sense node SO stops discharging. During the period when the sense node SO stops discharging, the sensing circuit 510 determines the state of the memory cell based on the discharge result.

[0151] Specifically, during the power outage period following the pre-discharge of the sensing node, the sensing circuit determines the read value. During the power outage period following the main discharge of the sensing node, the sensing circuit determines the first value. During the power outage period following the second discharge of the sensing node, the sensing circuit determines the third value.

[0152] For example, the sensing control switch includes a MOSFET having a first terminal, a second terminal, and a control terminal. The first terminal of the MOSFET is connected to bit line 320, the second terminal is connected to sensing node SO, and the control terminal is used to receive a control signal. The sensing control switch 580 is configured to control the sensing node to be turned on or off from the bit line in response to the control signal, thereby controlling the sensing node to discharge or stop discharging. The gate terminal of the sensing control switch 580 can be coupled to control logic 95 in an external circuit, and the control logic 95 sends a control signal to control the sensing node to discharge or stop discharging.

[0153] Figure 12 This is a flowchart illustrating a method for determining a valley value according to an embodiment of this disclosure. The following is in conjunction with... Figure 12 The illustrated embodiments are described in detail. Figure 12 As shown, the first step is to apply a prepulse to the selected word line WL to increase the voltage of the selected word line before the read operation.

[0154] The second step is to set the voltage of the selected word line (WL setup). For example, a first read voltage is applied to the selected word line. The voltage settings for the selected word line in both steps can be performed by the line decoder / WL driver 93 in the external circuitry.

[0155] The third step is to set the voltage of all bit lines (All BL Setup, ABL). Specifically, this involves charging the bit lines and sensor nodes corresponding to all memory cells coupled to the selected word line to the preset voltage. The bit lines and sensor nodes can be charged synchronously or separately.

[0156] The fourth step is to control the pre-discharge of the sensing node. In steps three and four, the sensing node SO can be charged by connecting the charging circuit 570. After charging to the preset voltage, the charging circuit is disconnected, and the sensing node is connected to the bit line, allowing the sensing node to begin discharging through the bit line. After a preset pre-discharge time, the sensing node and bit line are disconnected, stopping the sensing node from discharging.

[0157] The fifth step involves the page buffer (PB) acquiring and storing the read value (PB operation). Specifically, during the period when the sensing node stops discharging, the sensing circuit compares the voltage of the sensing node with the switching voltage to obtain the read value, which is then output to the bias latch DL. The bias latch stores the read value.

[0158] Step 6: Control the sensing node to perform main discharge (sensing). Specifically, the sensing node is connected to the bit line for the second time, and the sensing node continues to discharge based on the pre-discharge. After the preset main discharge duration, the sensing node and bit line are disconnected, causing the sensing node to stop discharging for the second time. The first discharge duration is equal to the sum of the main discharge duration and the pre-discharge duration.

[0159] Step 7: The page buffer acquires and stores the first value (PB operation). Specifically, during the period after the sensing node stops discharging for the second time, the sensing circuit compares the voltage of the sensing node with the reference voltage to obtain the first value, which is then output to the sensing latch DS. The sensing latch stores the first value.

[0160] Step 8: Control the sensing node to perform a second discharge (sensing). Specifically, connect the sensing node to the bit line for the third time, and the sensing node continues to discharge a second time based on the pre-discharge. After the preset second discharge duration, disconnect the sensing node from the bit line, causing the sensing node to stop discharging for the third time.

[0161] In the ninth step, the page buffer obtains and stores the third value (PB operation). Specifically, during the period after the sensing node stops discharging for the third time, the sensing circuit compares the voltage of the sensing node with the reference voltage to obtain a second value, which is then output to the logic operation circuit. After obtaining the first value from the sensing latch DS, the logic operation circuit obtains the third value based on the first and second values ​​and outputs it to the first data latch D1. The first data latch D1 stores the third value. The bias latch DL outputs the read value to the cache latch DC, which stores the read value.

[0162] It should be noted that if the memory cell group with the shortest first discharge duration (e.g., Figure 10The pre-discharge duration of the first memory cell group (Q0) is equal to the first discharge duration, and the main discharge duration is zero. Therefore, step six is ​​omitted in the operation flow of the memory cell group with the shortest first discharge duration. In step seven, the sensing circuit uses the read value as the first value and outputs it to the sensing latch DS.

[0163] The control logic obtains the third value of multiple memory cells in the memory cell group to obtain the first statistic regarding the number of memory cells in the threshold voltage range.

[0164] Since different memory cell groups synchronously execute the operations including the first to ninth steps mentioned above, the control logic can simultaneously obtain multiple first statistics corresponding to multiple threshold voltage intervals between two adjacent threshold voltage distributions.

[0165] In some embodiments, the peripheral circuitry is further configured to: correct the sensing duration in a read operation performed based on a first read voltage based on a plurality of first statistics of a plurality of memory cell groups.

[0166] During a read operation, factors affecting the threshold voltage determination of a memory cell include the read voltage and the sensing duration. Therefore, adjusting the sensing duration can improve read accuracy.

[0167] In this embodiment, the specific steps for correcting the sensing duration in the read operation based on the first read voltage, based on multiple first statistics of multiple memory cell groups, are as follows: Based on the first statistics of multiple memory cell groups, determine the threshold voltage range to which the valley threshold voltage belongs; and use the discharge duration corresponding to the threshold voltage range to which the valley voltage belongs as the corrected sensing duration.

[0168] Combination Figure 4 and Figure 6 Analysis shows that if the first statistic corresponding to the second memory cell group Q1 is less than the first statistic corresponding to the first memory cell group Q0 and the first statistic corresponding to the third memory cell group Q2, then the D2 interval is determined to be the threshold voltage interval to which the valley threshold voltage belongs. The amplification duration corresponding to the D2 interval can be used as the corrected sensing duration. Here, the D2 interval corresponds to a discharge duration interval, for example... Figure 4 In the D2 interval, the shortest discharge duration is 2 units (T1+T2), and the longest discharge duration is 3 units (T1+T2+T3). One of these discharge duration intervals can be selected as the corrected sensing duration. For example, the corrected sensing duration could be 2 units or 2.5 units. This disclosure does not impose any limitations on this.

[0169] It should be noted that if the corrected sensing duration is too long, it may affect the reading rate. In this case, the reading voltage can be adjusted again, for example, by increasing the reading voltage, and then the AVD operation method provided in this embodiment can be re-executed to determine a new sensing duration. In other words, after obtaining the valley between adjacent threshold distributions, both the reading voltage and the sensing duration can be adjusted to improve the accuracy of the reading operation.

[0170] Storage cells can be used to store multi-bit data. For example, a TLC storage cell is used to store 3 bits of data. The threshold voltage distribution of an N-order storage memory includes 2... N -1 valley value, where N is a positive integer. For example, the threshold voltage distribution of a TCL memory cell includes 7 valley values. Therefore, for a memory cell storing multi-bit data, the above operation needs to be performed multiple times to determine its multiple valley values.

[0171] In some embodiments, the peripheral circuitry is further configured to: apply a second read voltage to the selected word line; wherein the second read voltage and the first read voltage are used to determine the same bit data in multi-bit data; apply a read-disable voltage to a portion of the bit lines based on the read value of the memory cell under the first read voltage; charge the sensing nodes coupled to the bit lines to which the read-disable voltage is not applied; divide the memory cells coupled to the selected word line into multiple memory cell groups and perform a sensing operation to obtain a second statistic for each memory cell group; and correct the sensing duration in the read operation performed based on the second read voltage based on the multiple second statistics of the multiple memory cell groups.

[0172] The second read voltage differs from the first read voltage. Both the second and first read voltages are used to determine the same bit of data within a multi-bit dataset. Taking a TLC memory cell as an example, the second and first read voltages can be Vrd1 and Vrd5, used to determine the low-order bits. The second and first read voltages can be any two of Vrd2, Vrd4, and Vrd6, used to determine the middle-order bits. The second and first read voltages can be Vrd3 and Vrd7, used to determine the high-order bits.

[0173] When determining any valley value, the valley value determination method described above can be used. However, in this embodiment, to reduce interference and improve the accuracy of the results, it is proposed that if the second read voltage and the first read voltage are used to determine the same bit data in multi-bit data, then a read-prohibit voltage can be applied to some bit lines based on the read value of the storage cell under the first read voltage.

[0174] Specifically, a read-disable voltage is applied to the bit line coupled to the memory cell whose read value at the first read voltage indicates that it is on. Taking Vrd1 as the first read voltage and Vrd5 as the second read voltage as an example: If the read value of the memory cell at the first read voltage is 1, indicating that the memory cell is on, then a read-disable voltage is applied to the bit line corresponding to that memory cell. If the read value of the memory cell at the first read voltage is 0, indicating that the memory cell is not on, then no read-disable voltage is applied to the bit line corresponding to that memory cell.

[0175] Applying a read-disable voltage to some bit lines based on the read value under the first read voltage will not affect the determination of the second valley value; on the contrary, it can improve the accuracy of the result. This is because if a memory cell can conduct under the first read voltage, and the second read voltage is greater than the first read voltage, then the memory cell will definitely conduct under the second read voltage. Therefore, those memory cells that conduct under the first read voltage are located to the left of the D1 interval corresponding to the second read voltage, and will not affect the number of memory cells in the D1, D2, and D3 intervals corresponding to the second read voltage, thus not affecting the determination of the second valley value.

[0176] Bit lines that are not subject to a read-deactivation voltage (e.g., bit lines coupled to memory cells that are not active, as indicated by a read value at the first read voltage) are charged to a preset voltage, and sensing nodes coupled to bit lines that are not subject to a read-deactivation voltage are also charged to a preset voltage. During sensing operation, the sensing nodes coupled to bit lines that are not subject to a read-deactivation voltage are controlled to discharge, thereby determining a second valley value using memory cells coupled to bit lines that are not subject to a read-deactivation voltage.

[0177] It should be noted that a read-inhibit voltage can be applied to a sensing node coupled to a bit line that is subjected to a read-inhibit voltage.

[0178] Then, the memory cells coupled to the selected word line are divided into multiple memory cell groups for sensing operations, and a second statistic is obtained for each memory cell group. This disclosure does not limit the grouping method. For example, the grouping method when performing the sensing operation under the second read voltage can be the same as the grouping method when performing the sensing operation under the first read voltage. The content of the sensing operation is the same as above and will not be repeated here.

[0179] Figure 13 This is a flowchart illustrating another method for determining a valley value provided in this embodiment of the disclosure. The following is in conjunction with... Figure 13 The embodiments shown will be described in detail. Figure 13 In the middle, steps one through nine are the same. Figure 12 Therefore, I will not elaborate further.

[0180] See Figure 13Step 10: Set the voltage of the selected word line WL (WL setup). For example, apply a second read voltage to the selected word line. The voltage setting for the selected word line can be performed by the line decoder / WL driver 93 in the external circuitry.

[0181] Step 11: Set the bit line voltage (knockout) based on the read value of the memory cell under the first read voltage. Specifically, if the read value of the memory cell indicates that it is turned on under the first read voltage, a read-disable voltage is applied to the bit line coupled to the memory cell. If the read value of the memory cell indicates that it is not turned on under the first read voltage, a preset voltage is applied to the bit line coupled to the memory cell.

[0182] The sensing node coupled to the bit line, which is not subjected to a read-disable voltage, is charged to a preset voltage. Here, the bit line and the sensing node can be charged synchronously.

[0183] Step 12: Control the sensing node to perform pre-discharge (sensing). Specifically, after charging the sensing node to a preset voltage, disconnect the charging circuit, connect the sensing node coupled to the bit line (which is not subject to a read-disable voltage), and the sensing node begins to discharge through the bit line. After a preset pre-discharge time, disconnect the sensing node and the bit line to stop the sensing node from discharging.

[0184] Step thirteen: The page buffer acquires and stores the read value (PB operation). Specifically, during the period when the sensing node stops discharging, the sensing circuit compares the voltage of the sensing node with the reference voltage to obtain the read value, which is then output to the bias latch DL. The bias latch stores the read value.

[0185] Step fourteen: Control the sensing node to perform main discharge (sensing). Specifically, the sensing node is connected to the bit line for the second time, and the sensing node continues to discharge based on the pre-discharge. After the preset main discharge duration, the sensing node and bit line are disconnected, causing the sensing node to stop discharging for the second time. The first discharge duration is equal to the sum of the main discharge duration and the pre-discharge duration.

[0186] Step 15: The page buffer acquires and stores the first value (PB operation). Specifically, during the period after the sensing node stops discharging for the second time, the sensing circuit compares the voltage of the sensing node with the reference voltage to obtain the first value, which is then output to the sensing latch DS. The sensing latch stores the first value.

[0187] Step sixteen: Control the sensing node to perform a second discharge (sensing). Specifically, connect the sensing node to the bit line for the third time, and the sensing node continues to perform a second discharge based on the pre-discharge. After the preset second discharge duration, disconnect the sensing node from the bit line, causing the sensing node to stop discharging for the third time.

[0188] Step seventeen: The page buffer obtains and stores the third value (PB operation). Specifically, during the period after the sensing node stops discharging for the third time, the sensing circuit compares the voltage of the sensing node with the reference voltage to obtain a second value, which is then output to the logic operation circuit. After obtaining the first value from the sensing latch DS, the logic operation circuit obtains the third value based on the first and second values ​​and outputs it to the second data latch D2. The second data latch D2 stores the third value under the second read voltage. The bias latch outputs the read value under the second read voltage to the cache latch DC, which stores the read value under the second read voltage.

[0189] Step 18: Recovery.

[0190] Similarly, if the pre-discharge duration of the memory cell group with the shortest first discharge duration is equal to the first discharge duration, and the main discharge duration is zero, then step fourteen is omitted in the operation flow of the memory cell group with the shortest first discharge duration. In step fifteen, the sensing circuit uses the read value as the first value and outputs it to the sensing latch.

[0191] In some embodiments, the peripheral circuitry is further configured to: correct the sensing duration of a read operation performed based on a second read voltage based on a plurality of second statistics of a plurality of memory cell groups. The specific operation method can be referred to the correction of the sensing duration of a read operation performed under a first read voltage, and will not be elaborated here.

[0192] In some embodiments, the peripheral circuitry is configured to determine multiple valleys in the threshold voltage distribution of the memory cell in a preset order; wherein the preset order is the sequence in which the peripheral circuitry applies multiple read voltages to the selected word line to determine the stored data in the memory cell. The advantage of this configuration is that during AVD operations, the peripheral circuitry can also execute the steps of applying read voltages in the AVD operation in the same order as in a conventional read operation, simplifying the control scheme for the peripheral circuitry, improving overall efficiency, and reducing redundant design.

[0193] The memory provided in this embodiment divides the selected word-coupled memory cells into multiple memory cell groups for sensing operations. The discharge durations of the multiple memory cell groups differ to correspondingly determine the number of memory cells in different threshold voltage ranges. Since the sensing operations performed on multiple memory cell groups can overlap, for example, sensing operations can be performed on multiple memory cell groups simultaneously. This allows the number of memory cells in multiple threshold voltage ranges to be determined within the same time period, thereby saving the operation time for determining valley values.

[0194] Furthermore, when performing sensing operations on the memory cell group, the sensing node is charged once and then discharged twice. The sensing node does not need to be recharged before the second discharge; instead, the second discharge is performed based on the first discharge. In other words, the starting voltage for the second discharge is determined based on the first discharge. This reduces the charging time, shortens the total AVD operation time, and simplifies the AVD operation process.

[0195] This disclosure also provides a method for operating a memory, the memory including a memory cell array and peripheral circuitry. The memory cell array includes multiple memory cells, word lines and bit lines are coupled to the multiple memory cells, and the peripheral circuitry is coupled to the word lines. The peripheral circuitry includes a page buffer, and the sensing node of the page buffer is coupled to the bit lines. Figure 14 This is a flowchart illustrating a memory operation method provided in an embodiment of the present disclosure, as shown below. Figure 14 As shown, the memory operation methods include:

[0196] S100: Apply the first read voltage to the selected word line;

[0197] S200: Charge the sensing node corresponding to the memory cell coupled to the selected word line;

[0198] S300: Divide the selected word line-coupled memory cell into multiple memory cell groups and perform sensing operations. Each memory cell group includes multiple memory cells. The sensing operations include: controlling multiple sensing nodes corresponding to the memory cell group to perform two discharges, wherein the starting voltage of the second discharge is determined based on the first discharge; and setting the discharge duration for different memory cell groups.

[0199] S400: Based on the discharge results of multiple sensing nodes corresponding to each storage cell group, a first statistical number for each storage cell group is obtained; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

[0200] In some embodiments, the operation method further includes: correcting the sensing duration in a read operation performed based on a first read voltage based on a plurality of first statistics of a plurality of memory cell groups.

[0201] In some embodiments, step S320, obtaining the first statistic for each memory cell group based on the discharge results of each discharge of the multiple sensing nodes corresponding to each memory cell group, includes: performing the following processing on the multiple sensing nodes corresponding to each memory cell group:

[0202] Based on the first discharge result of each sensing node, a first value is obtained, wherein the first value is used to indicate whether the threshold voltage of the memory cell is less than a first preset threshold voltage; based on the second discharge result of each sensing node, a second value is obtained, wherein the second value is used to indicate whether the threshold voltage of the memory cell is less than a second preset threshold voltage; logical operations are performed on the first value and the second value to obtain a third value, wherein the third value indicates whether the threshold voltage of the memory cell is within a preset threshold voltage range, the preset threshold voltage range being a range less than the second preset threshold voltage and greater than or equal to the first preset threshold voltage; based on the multiple third values ​​of multiple memory cells, a first statistic is obtained.

[0203] In some embodiments, the sensing node is charged to a preset voltage, and the first discharge includes a pre-discharge and a main discharge, with the pre-discharge duration being the same for different memory cell groups. Step S310: Controlling the multiple sensing nodes corresponding to the memory cell group to perform the first discharge of two discharges includes:

[0204] Multiple sensing nodes are controlled to perform pre-discharge starting from a preset voltage; after pre-discharge, multiple sensing nodes are controlled to perform main discharge, with the starting voltage of the main discharge being the termination voltage of the pre-discharge.

[0205] The operation method also includes: obtaining the read value of the storage cell at the first read voltage based on the pre-discharge result of the sensing node.

[0206] In some embodiments, the duration of the first discharge of one of the multiple memory cell groups is equal to the pre-discharge duration.

[0207] In some embodiments, the storage unit is used to store multi-bit data; the operation method further includes:

[0208] A second read voltage is applied to the selected word line; wherein the second read voltage and the first read voltage are used to determine the same bit data in the multi-bit data;

[0209] Based on the read value of the storage cell under the first read voltage, a read-inhibit voltage is applied to a portion of the bit lines;

[0210] Charge the sensing node coupled to the bit line that is not subjected to a read-blocking voltage;

[0211] The selected word line-coupled memory cell is divided into multiple memory cell groups for sensing operations, and the second statistical number of multiple memory cell groups is obtained;

[0212] The sensing duration in a read operation performed based on a second read voltage is corrected based on multiple second statistics from multiple memory cell groups.

[0213] The memory operation method provided in this disclosure divides the selected word-coupled memory cells into multiple memory cell groups for sensing operations. The discharge durations of the multiple memory cell groups differ to determine the number of memory cells in different threshold voltage ranges. Since the sensing operations performed on multiple memory cell groups can overlap, for example, sensing operations can be performed on multiple memory cell groups simultaneously. This allows the number of memory cells in multiple threshold voltage ranges to be determined within the same time period, thereby saving operation time for determining valley values. Furthermore, when performing sensing operations on memory cell groups, the sensing node is charged once and then discharged twice. The sensing node does not need to be recharged before the second discharge; instead, the second discharge continues based on the first discharge. In other words, the starting voltage of the second discharge is determined based on the first discharge, which reduces the charging time, shortens the total AVD operation time, and simplifies the AVD operation process.

[0214] The specific implementation methods of the methods in the above embodiments have been described in detail in the embodiments of the products corresponding to the methods, and will not be elaborated here.

[0215] This disclosure also provides a memory system, which includes a memory and a memory controller coupled to the memory and used to control the memory. The memory is any of the above-described memories and is used to implement the operation methods provided in this disclosure.

[0216] This disclosure also provides an electronic device, including any of the memory systems described above, for implementing the operation methods provided in this disclosure.

[0217] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: A storage cell array, comprising multiple storage cells; Word lines and bit lines are coupled to the plurality of memory cells; Peripheral circuitry, coupled to the word line, the peripheral circuitry including a page buffer, the sensing node of the page buffer being coupled to the bit line, the peripheral circuitry being configured as follows: Apply the first read voltage to the selected character line; Charge the sensing node corresponding to the memory cell coupled to the selected word line; The selected word line-coupled storage unit is divided into multiple storage unit groups to perform sensing operations, and the storage unit group includes multiple storage units; The sensing operation includes: controlling multiple sensing nodes corresponding to the storage cell group to perform two discharges, wherein the starting voltage of the second discharge is determined based on the first discharge; and the discharge duration is set differently for different storage cell groups. Based on the discharge results of each of the multiple sensing nodes corresponding to each of the storage cell groups, a first statistical number is obtained for each of the storage cell groups; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the first statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

2. The memory according to claim 1, characterized in that, The starting voltage of the second discharge is the ending voltage of the first discharge.

3. The memory according to claim 1, characterized in that, The peripheral circuit is also configured to: The sensing duration in a read operation performed based on the first read voltage is corrected based on multiple first statistics of the multiple groups of storage cells.

4. The memory according to claim 1, characterized in that, The first discharge duration is different for different memory cell groups, while the second discharge duration is the same.

5. The memory according to claim 4, characterized in that, The different memory cell groups are sorted from shortest to longest first discharge duration, wherein the first discharge duration of the latter in two adjacent memory cell groups is equal to the sum of the first discharge duration and the second discharge duration of the former.

6. The memory according to claim 4, characterized in that, The first discharge duration of the storage cell group includes one or more unit durations, and the second discharge duration includes one unit duration; The duration of the first discharge of the plurality of memory cell groups increases in increments of one unit duration.

7. The memory according to claim 1, characterized in that, The number of storage cells in each of the plurality of storage cell groups is the same.

8. The memory according to claim 1, characterized in that, The page buffer is configured as follows: Based on the first discharge result of the sensing node, a first value is obtained; wherein, the first value is used to indicate whether the threshold voltage of the storage cell is less than a first preset threshold voltage; Based on the second discharge result of the sensing node, a second value is obtained; wherein, the second value is used to indicate whether the threshold voltage of the memory cell is less than a second preset threshold voltage; A third value is obtained by performing logical operations on the first value and the second value; wherein, the third value indicates whether the threshold voltage of the memory cell is within the preset threshold voltage range, the preset threshold voltage range being the range that is less than the second preset threshold voltage and greater than or equal to the first preset threshold voltage; The peripheral circuitry further includes control logic coupled to the page buffer, the control logic being configured to obtain the first statistic based on the plurality of third values ​​of the plurality of memory cells.

9. The memory according to claim 8, characterized in that, The page buffer is configured as follows: The first voltage of the sensing node after the first discharge is compared with a reference voltage, and a first value is obtained based on the comparison result; wherein, if the first voltage is less than the reference voltage, the threshold voltage of the storage cell is less than the first preset threshold voltage; The second voltage of the sensing node after the second discharge is compared with the reference voltage, and a second value is obtained based on the comparison result; wherein, if the second voltage is less than the reference voltage, the threshold voltage of the storage cell is less than the second preset threshold voltage.

10. The memory according to claim 8, characterized in that, The page buffer includes: a sensing circuit, a sensing latch, a logic operation circuit, and a first data latch. The sensing circuit is coupled to the sensing node, the sensing latch is coupled to the sensing circuit, the logic operation circuit is coupled to the sensing circuit and the sensing latch, and the first data latch is coupled to the logic operation circuit. After the sensing node discharges for the first time, the sensing circuit is configured to obtain the first value; The sensing latch is configured to store the first value; After the sensing node discharges for the second time, the sensing circuit is configured to obtain the second value; The logic operation circuit is configured to: acquire the first value and the second value, and obtain the third value based on the first value and the second value; The first data latch is configured to store the third value.

11. The memory according to claim 1, characterized in that, The sensing node is charged to a preset voltage; the first discharge includes a pre-discharge and a main discharge, and the pre-discharge duration is the same for different memory cell groups. The page buffer is configured as follows: Control the sensing node to begin the pre-discharge from the preset voltage; Based on the pre-discharge results of the sensing node, the read value of the storage unit is obtained; The sensing node is controlled to perform the main discharge; wherein the starting voltage of the main discharge is the termination voltage of the pre-discharge.

12. The memory according to claim 11, characterized in that, The duration of the first discharge of one of the plurality of storage cell groups is equal to the duration of the pre-discharge.

13. The memory according to claim 11, characterized in that, The page buffer includes: a sensing circuit, a bias latch, and a cache latch. The sensing circuit is coupled to the sensing node, the bias latch is coupled to the sensing circuit, and the cache latch is coupled to the bias latch. After the sensing node is pre-discharged, the sensing circuit is configured to obtain the read value, and the bias latch is configured to store the read value. After the sensing node discharges for the second time, the bias latch is further configured to send the read value to the buffer latch; The cache latch is configured to store the read value.

14. The memory according to claim 1, characterized in that, The page buffer includes: a sensing control switch coupled between the sensing node and the bit line; The sensing control switch is configured to control the sensing node to be connected or disconnected from the bit line; wherein, when the sensing node is connected to the bit line, the sensing node discharges.

15. The memory according to claim 1, characterized in that, The storage unit is used to store multi-bit data; the peripheral circuit is further configured to: A second read voltage is applied to the selected word line; wherein the second read voltage and the first read voltage are used to determine the same bit data in the multi-bit data; Based on the read value of the memory cell under the first read voltage, a read-inhibit voltage is applied to a portion of the bit lines; Charge the sensing node coupled to the bit line that is not subjected to a read-inhibit voltage; The selected word line-coupled storage unit is divided into multiple storage unit groups and a sensing operation is performed to obtain a second statistical number for each storage unit group; The sensing duration in a read operation performed based on the second read voltage is corrected based on multiple second statistics of the multiple groups of storage cells.

16. A method for operating a memory, characterized in that, The memory includes a memory cell array, word lines, bit lines, and peripheral circuitry. The memory cell array includes multiple memory cells, the word lines and the bit lines are coupled to the multiple memory cells, the peripheral circuitry is coupled to the word lines, and the peripheral circuitry includes a page buffer. The sensing node of the page buffer is coupled to the bit lines. The operation method includes: Apply the first read voltage to the selected character line; Charge the sensing node corresponding to the memory cell coupled to the selected word line; The selected word line-coupled storage unit is divided into multiple storage unit groups to perform sensing operations. Each storage unit group includes multiple storage units. The sensing operation includes: controlling multiple sensing nodes corresponding to the storage unit group to perform two discharges, wherein the starting voltage of the second discharge is determined based on the first discharge; the discharge duration of different storage unit groups is set differently. Based on the discharge results of each of the multiple sensing nodes corresponding to each of the storage cell groups, a first statistical number is obtained for each of the storage cell groups; wherein, the discharge result of the sensing node is related to the threshold voltage of the storage cell, and the statistical number is used to indicate the number of storage cells in the storage cell group whose threshold voltage is within a preset threshold voltage range.

17. The method of operating the memory according to claim 16, characterized in that, The operation method further includes: The sensing duration in a read operation performed based on the first read voltage is corrected based on multiple first statistics of the multiple groups of storage cells.

18. The method of operating the memory according to claim 16, characterized in that, The step of obtaining a first statistical count for each of the multiple sensing nodes corresponding to each of the storage cell groups includes: performing the following processing on the multiple sensing nodes corresponding to each of the storage cell groups: Based on the first discharge result of each of the sensing nodes, a first value is obtained; wherein, the first value is used to indicate whether the threshold voltage of the storage cell is less than a first preset threshold voltage; A second value is obtained based on the second discharge result of each of the sensing nodes; wherein the second value is used to indicate whether the threshold voltage of the memory cell is less than a second preset threshold voltage; A third value is obtained by performing logical operations on the first value and the second value; wherein, the third value indicates whether the threshold voltage of the memory cell is within the preset threshold voltage range, the preset threshold voltage range being the range that is less than the second preset threshold voltage and greater than or equal to the first preset threshold voltage; The first statistic is obtained based on the third values ​​of the multiple storage units.

19. The method of operating the memory according to claim 16, characterized in that, The sensing node is charged to a preset voltage; the first discharge includes a pre-discharge and a main discharge, and the pre-discharge duration is the same for different memory cell groups. The first discharge of two discharges is performed on the multiple sensing nodes corresponding to the storage unit group, including: Control the plurality of sensing nodes to perform the pre-discharge starting from the preset voltage; After the pre-discharge, the plurality of sensing nodes are controlled to perform the main discharge, and the starting voltage of the main discharge is the ending voltage of the pre-discharge. The operation method further includes: obtaining the read value of the storage unit under the first read voltage based on the pre-discharge result of the sensing node.

20. The method of operating the memory according to claim 19, characterized in that, The duration of the first discharge of one of the plurality of storage cell groups is equal to the duration of the pre-discharge.

21. The method of operating the memory according to claim 16, characterized in that, The storage unit is used to store multi-bit data; the operation method further includes: A second read voltage is applied to the selected word line; wherein the second read voltage and the first read voltage are used to determine the same bit data in the multi-bit data; Based on the read value of the memory cell under the first read voltage, a read-inhibit voltage is applied to a portion of the bit lines; Charge the sensing node coupled to the bit line that is not subjected to a read-inhibit voltage; The selected word line-coupled storage unit is divided into multiple storage unit groups and a sensing operation is performed to obtain a second statistical number for each storage unit group; The sensing duration in a read operation performed based on the second read voltage is corrected based on multiple second statistics of the multiple groups of storage cells.

22. A memory system, characterized in that, The memory system includes: One or more memories as described in any one of claims 1 to 15; A memory controller is coupled to the memory and configured to control the memory.

23. An electronic device, characterized in that, Includes the memory system as described in claim 22.

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