Hybrid bonding packaging structure and manufacturing method thereof

Abstract

The invention provides a hybrid bonding packaging structure and a manufacturing method thereof, the manufacturing method of the hybrid bonding packaging structure comprises the following steps: a substrate wafer comprising a plurality of electrode areas arranged at intervals is provided, the electrode areas comprise a plurality of first electrodes, and the upper surfaces of the first electrodes are flush with the upper surfaces of the electrode areas; a sacrificial wafer is provided, a plurality of chip layers corresponding to the electrode areas in a one-to-one mode are fixed to the upper surface of the sacrificial wafer, each chip layer comprises second electrodes corresponding to the first electrodes in a one-to-one mode, and the second electrodes are flush with the upper surfaces of the chip layers; the sacrificial wafer is inversely arranged on the substrate wafer, and the first electrode and the second electrode are fixedly and electrically connected; removing the sacrifice wafer outside the fixed area of the chip layer, and forming a protective layer covering the chip layer and the exposed surface of the residual sacrifice wafer; and removing the residual sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer. According to the invention, the chip layer is fixed on the sacrificial wafer, and then the sacrificial wafer is bonded with the substrate wafer, so that the bonding precision and the product output efficiency are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a hybrid bonding packaging structure and its fabrication method. Background Technology

[0002] Chip-to-wafer (D2W) hybrid bonding technology is a commonly used packaging process that typically bonds individual chips (dies) to wafers (wafers) using hybrid bonding techniques. For example... Figure 1 The diagram shows a cross-sectional view of a D2W hybrid bonding package structure, including a semiconductor substrate 01, electrode region 011, first dielectric layer 013, chip layer 02, second electrode 021, second dielectric layer 022, and non-functional filler chip 03. This packaging process can achieve chip interconnects with a pitch of 10μm or less, providing excellent bonding pitch and scalability, allowing chips to be connected more tightly, thus achieving faster and shorter connections. However, each chip (i.e., chip layer 02) needs to be aligned with the wafer, resulting in a low yield per unit area (WPH) for this packaging process, and a large shift (shift) of approximately 200nm for the chip (i.e., chip layer 02). As the size of the I / O pads continues to shrink, the WPH will further decrease, while the relative shift of D2W increases. A large shift can cause conductivity problems between pads, affecting the product's lifespan.

[0003] Therefore, there is an urgent need to find a method for fabricating hybrid bonding packaging structures that can improve the bonding accuracy and product yield efficiency of hybrid bonding processes. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a hybrid bonding packaging structure and its manufacturing method, so as to solve the problems of poor bonding accuracy and low product output efficiency in the hybrid bonding process of the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a hybrid bonding packaging structure, comprising the following steps:

[0006] A substrate wafer is provided, the substrate wafer including a plurality of spaced electrode regions, the electrode regions including a plurality of first electrodes, the upper surface of the first electrodes being flush with the upper surface of the electrode regions;

[0007] A sacrificial wafer is provided, and a plurality of chip layers corresponding one-to-one with the electrode regions are fixed on the upper surface of the sacrificial wafer. The chip layers include a plurality of second electrodes, the first electrodes corresponding one-to-one with the inverted second electrodes, and the upper surface of the second electrodes is flush with the upper surface of the chip layers.

[0008] The sacrificial wafer with the chip layer fixed is inverted onto the substrate wafer, and the first electrode and the second electrode are fixedly electrically connected.

[0009] Remove the sacrificial wafer outside the area fixed by the chip layer, and form a protective layer covering the exposed surfaces of the chip layer and the remaining sacrificial wafer;

[0010] Remove the remaining sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer.

[0011] Optionally, the chip layer includes at least one chip.

[0012] Optionally, the method of fixing the chip layer to the upper surface of the sacrificial wafer includes fusion bonding.

[0013] Optionally, before fixing the chip layer to the upper surface of the sacrificial wafer, the method further includes a step of detecting and adjusting the offset of the chip layer.

[0014] Optionally, detecting and adjusting the offset of the chip layer includes the following steps:

[0015] Multiple predetermined regions are placed on the upper surface of the sacrificial wafer in the multiple chip layers, and the chip layers correspond one-to-one with the predetermined regions;

[0016] Alignment detection is performed between the chip layer and the preset region corresponding to the chip layer;

[0017] If the offset between the chip layer and its corresponding preset region is greater than the preset offset value, the position of the chip layer is adjusted, and the alignment between the chip layer and its corresponding preset region is checked again after the adjustment.

[0018] The subsequent steps will continue until the offset values ​​of all chip layers on the upper surface of the sacrificial wafer and their corresponding preset regions are detected to be within the preset offset value.

[0019] Optionally, the size of the electrode region is not smaller than the size of the chip layer.

[0020] Optionally, the electrode region is provided with a circuit structure corresponding to the chip in the chip layer.

[0021] Optionally, the method of fixing the first electrode and the second electrode electrically connected includes hybrid bonding.

[0022] Optionally, the method for removing the remaining sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer includes chemical mechanical polishing.

[0023] The present invention also provides a hybrid bonding package structure, which is fabricated using the above-described method for fabricating a hybrid bonding package structure.

[0024] As described above, the hybrid bonding packaging structure and its fabrication method of the present invention improve the manufacturing process by first fixing each chip constituting the chip layer onto the sacrificial wafer. The sacrificial wafer has the same size and shape as the substrate wafer, and the electrodes of each chip in the chip layer after the sacrificial wafer is inverted correspond one-to-one with the electrodes in the electrode area. Then, the sacrificial wafer is inverted onto the substrate wafer, and the electrodes of each chip in the chip layer correspond one-to-one with the electrodes in the electrode area. Then, the chip layer and the substrate wafer are hybrid bonded, which improves the product yield efficiency. By performing nanometer-level alignment detection and local micro-adjustment on the chip layer, the bonding offset distance is made no greater than 50nm, thereby improving the bonding accuracy and the reliability and yield of the packaging structure. This bonding method does not require reserving too much cutting area, which can reduce the distance between the electrode areas in the substrate wafer and reduce the blank area above the electrode areas. Therefore, there is no need to bond blank filling chips to ensure the physical structural stability of the packaging structure during the packaging process, thereby relatively reducing the size of the packaging structure and reducing the manufacturing cost, which has high industrial application value. Attached Figure Description

[0025] Figure 1 The diagram shows a cross-sectional view of the D2W hybrid bonding package structure.

[0026] Figure 2 The diagram shows a process flow chart of the method for fabricating the hybrid bonding encapsulation structure of the present invention.

[0027] Figure 3 The diagram shows a cross-sectional view of a substrate wafer used in the fabrication method of the hybrid bonding packaging structure of the present invention.

[0028] Figure 4 The diagram shows a cross-sectional view of the chip layer after it has been fixed onto the sacrificial wafer, illustrating the method for fabricating the hybrid bonding packaging structure of the present invention.

[0029] Figure 5 The diagram shows a cross-sectional structure of the chip layer bonded to the substrate wafer, illustrating the method for fabricating the hybrid bonding packaging structure of the present invention.

[0030] Figure 6 The diagram shows a cross-sectional view of the sacrificial wafer after removing the area fixed by the chip layer, which is part of the method for fabricating the hybrid bonding packaging structure of the present invention.

[0031] Figure 7The diagram shows a cross-sectional view of the method for fabricating the hybrid bonding packaging structure of the present invention after removing the sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer.

[0032] Figure 8 The diagram shows a cross-sectional view of the wafer after removing the sacrificial wafer and cutting it into individual packaging structures, which is a method for fabricating the hybrid bonding packaging structure of the present invention.

[0033] Explanation of icon numbers

[0034] 01 Semiconductor substrate

[0035] 011 Electrode Region

[0036] 012 First Electrode

[0037] 013 First Dielectric Layer

[0038] 02 Chip Layer

[0039] 021 Second Electrode

[0040] 022 Second dielectric layer

[0041] 03 Non-functional filler chip

[0042] 1. Substrate wafer

[0043] 1a Semiconductor layer

[0044] 11 Electrode Region

[0045] 12 First Electrode

[0046] 13 First dielectric layer

[0047] 2. Sacrificial wafer

[0048] 3. Chip layer

[0049] 31 Second Electrode

[0050] 32 Second dielectric layer

[0051] 4. Protective layer Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] Please see Figures 2 to 8It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] Example 1

[0055] This embodiment provides a method for fabricating a hybrid bonding packaging structure, such as... Figure 2 The diagram shown is a process flow chart of the fabrication method of the hybrid bonding packaging structure, including the following steps:

[0056] S1: A substrate wafer is provided, the substrate wafer including a plurality of spaced electrode regions, the electrode regions including a plurality of first electrodes, the upper surface of the first electrodes being flush with the upper surface of the electrode regions;

[0057] S2: A sacrificial wafer is provided, and a plurality of chip layers corresponding one-to-one with the electrode regions are fixed on the upper surface of the sacrificial wafer. The chip layers include a plurality of second electrodes, the first electrodes correspond one-to-one with the inverted second electrodes, and the upper surface of the second electrodes is flush with the upper surface of the chip layers.

[0058] S3: The sacrificial wafer with the chip layer fixed is placed upside down on the substrate wafer, and the first electrode and the second electrode are fixedly electrically connected;

[0059] S4: Remove the sacrificial wafer outside the area fixed by the chip layer, and form a protective layer covering the exposed surface of the chip layer and the remaining sacrificial wafer;

[0060] S5: Remove the remaining sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer.

[0061] Please see Figures 3 to 4 The following steps S1 and S2 are performed: a substrate wafer 1 is provided, the substrate wafer 1 includes a plurality of spaced electrode regions 11, the electrode regions 11 include a plurality of first electrodes 12, the upper surface of the first electrodes 12 is flush with the upper surface of the electrode regions 11; a sacrificial wafer 2 is provided, and a plurality of chip layers 3 corresponding one-to-one with the electrode regions 11 are fixed on the upper surface of the sacrificial wafer 2, the chip layers 3 include a plurality of second electrodes 31, the first electrodes 12 correspond one-to-one with the inverted second electrodes 31, and the upper surface of the second electrodes 31 is flush with the upper surface of the chip layers 3.

[0062] Specifically, such as Figure 3The diagram shown is a cross-sectional view of the substrate wafer 1. While ensuring the performance of the hybrid bonding packaging structure, the size and thickness of the substrate wafer 1 can be selected according to the actual situation, and are not limited here. The size and arrangement of the electrode region 11 can be selected according to the actual situation, and are not limited here.

[0063] Specifically, the substrate wafer 1 can be a wafer structure that has undergone multiple packaging processes, or a wafer structure that has undergone preliminary packaging. That is, each electrode region 11 in the substrate wafer 1 can be a preliminary package structure including multiple electronic components, or a single electronic component structure. Here, the electronic components can be active electronic components or passive electronic components.

[0064] Specifically, the first electrode 12 in the electrode region 11 is located in the first dielectric layer 13 on the upper surface of the substrate wafer 1. Each electrode in the first electrode 12 that needs to be bonded is exposed on the upper surface of the first dielectric layer 13, and the upper surface of each electrode in the first electrode 12 that needs to be bonded is flush with the upper surface of the first dielectric layer 13.

[0065] Specifically, the material of the first dielectric layer 13 located on the upper surface of the substrate wafer 1 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorinated glass, or other suitable dielectric materials.

[0066] Specifically, while ensuring the performance of the encapsulation structure in the electrode region 11, the number and thickness of the dielectric material in the first dielectric layer 13 can be selected according to the actual situation, and are not limited here; the number and cross-sectional size of the first electrodes 12 can be selected according to the actual situation, and are not limited here.

[0067] Specifically, the material of the first electrode 12 includes copper, aluminum, nickel, gold, silver, titanium, tantalum, tungsten, or other suitable conductive materials.

[0068] Specifically, such as Figure 4 The diagram shows a cross-sectional view of the chip layer 3 after it is fixed to the sacrificial wafer 2. The size and shape of the sacrificial wafer 2 are the same as those of the substrate wafer 1. The material of the sacrificial wafer 2 can be glass, silicon or other suitable materials. When the sacrificial wafer 2 is a silicon wafer, it is usually an undoped blank silicon wafer.

[0069] Specifically, the sacrificial wafer 2 is used to carry and fix the chip layer 3 that needs to be bonded to the electrode region 11. The arrangement of the chip layer 3 on the sacrificial wafer 2 corresponds one-to-one with the arrangement of the electrode region 11 on the substrate wafer 1. At the same time, the second electrode 31 that needs to be bonded in the chip layer 3 corresponds one-to-one with the first electrode 12 that needs to be bonded in the electrode region 11.

[0070] As an example, before fixing the chip layer 3 to the upper surface of the sacrificial wafer 2, the method further includes a step of detecting and adjusting the offset of the chip layer 3 to improve the subsequent bonding accuracy of the chip layer 3.

[0071] As an example, detecting and adjusting the offset of chip layer 3 includes the following steps:

[0072] Multiple preset regions (not shown) are placed on the upper surface of the sacrificial wafer 2 in multiple chip layers 3, and each chip layer 3 corresponds to one of the preset regions;

[0073] Alignment detection is performed between the chip layer 3 and the preset region corresponding to the chip layer 3;

[0074] If the offset between the chip layer 3 and its corresponding preset region is greater than the preset offset value, the position of the chip layer 3 is adjusted, and the alignment between the chip layer 3 and its corresponding preset region is checked again after the adjustment.

[0075] The subsequent steps will continue until the offset values ​​of all chip layers 3 on the upper surface of the sacrificial wafer 2 and their corresponding preset regions are detected to be within the preset offset values.

[0076] Specifically, after the sacrificial wafer 2 is inverted, the preset region corresponds one-to-one with the electrode region 11 in the substrate wafer 1.

[0077] Specifically, an alignment detection system (not shown) is used to detect the alignment between chip layer 3 and the preset region corresponding to chip layer 3, in order to determine the offset between chip layer 3 and the preset region corresponding to chip layer 3, and simultaneously determine the position of the chip layer 3 that is misaligned and the offset value between the misaligned chip layer 3 and the preset region corresponding to chip layer 3. In this embodiment, a nanometer-precision alignment detection system is used to detect the alignment between chip layer 3 and the preset region corresponding to chip layer 3.

[0078] Specifically, the nanometer-precision alignment detection system can be located on the machine that fixes the chip layer 3 to the sacrificial wafer 2, or it can be an alignment detection device located independently of the machine.

[0079] Specifically, the preset offset value is 50nm, meaning that the offset value between the chip layer 3 and the preset region corresponding to the chip layer 3 is no greater than 50nm.

[0080] Specifically, the position of the chip layer 3 is adjusted by a position fine-tuning mechanism when the offset value between the chip layer 3 and its corresponding preset region is greater than the preset offset value. When the offset (Shift) value of the chip layer 3 arranged on the sacrificial wafer 2 is greater than the preset offset value, the position fine-tuning mechanism performs local micro-adjustment on the chip layer 3 that has shifted, thereby ensuring that the offset distance of all chip layers 3 is no greater than 50nm.

[0081] Specifically, while ensuring process stability during the fabrication of the hybrid bonding packaging structure, the thickness of the sacrificial wafer 1 can be selected according to actual conditions, and is not limited here.

[0082] As an example, the chip layer 3 includes at least one chip; that is, the chip layer 3 can be a single chip, or a package structure that encapsulates multiple chips or chips and electronic devices. In this embodiment, the chip layer 3 contains only one chip corresponding to the electrode region 11.

[0083] Specifically, when the chip layer 3 includes multiple chips and electronic devices, the size and type of each electronic chip and electronic device in the chip layer 3 are selected according to actual functional needs, and are not restricted here.

[0084] As an example, the method for fixing the chip layer 3 to the upper surface of the sacrificial wafer 2 includes fusion bonding or other suitable methods. In this embodiment, fusion bonding (FB) is used to fix the chip layer 3 to a predetermined position on the upper surface of the sacrificial wafer 2.

[0085] Specifically, while ensuring the performance of the hybrid bonding packaging structure, the thickness and shape of the chip layer 3 can be selected according to the actual situation, and are not limited here.

[0086] As an example, the size of the electrode region 11 is not less than the size of the chip layer 3, that is, the cross-sectional size of each electrode region 11 in the substrate wafer 1 is greater than or equal to the cross-sectional size of the chip layer 3. Here, the cross-section refers to the cross section parallel to the upper and lower surfaces of the sacrificial wafer 2 or the substrate wafer 1.

[0087] As an example, the electrode region 11 is provided with a circuit structure corresponding to the chip layer 3, so that the devices in the chip layer 3 and the devices in the electrode region 11 work together to realize the functions required by the hybrid bonding packaging structure.

[0088] Specifically, the circuit structure in the electrode region 11 includes at least one of wiring layers, active devices, and passive devices. For example, the region where the electrode region 11 is located in the substrate wafer may contain only wiring layers, or it may contain a functional circuit composed of wiring layers and active devices, or it may contain a functional circuit structure composed of wiring layers and passive devices, or it may contain a functional circuit structure composed of active devices, passive devices, and wiring layers.

[0089] Specifically, the upper surface of the chip layer 3 is further provided with a second dielectric layer 32 for protecting the devices in the chip layer 3. The second electrode 31 is exposed on the upper surface of the second dielectric layer 32, and the upper surface of the second electrode 31 is flush with the upper surface of the second dielectric layer 32.

[0090] Specifically, the material of the second dielectric layer 32 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorinated glass, or other suitable dielectric materials. In this embodiment, the materials at the hybrid bonding interface between the first dielectric layer 13 and the second dielectric layer 32 are the same.

[0091] Specifically, while ensuring the performance of the chip layer 3, the thickness of the second dielectric layer 32 can be selected according to the actual situation, and is not limited here; the number of the second electrodes 31 can be selected according to the actual situation, and is not limited here.

[0092] Please see again Figures 5 to 8 The following steps are performed: Step S3, Step S4, and Step S5: The sacrificial wafer 2 with the chip layer 3 fixed is inverted onto the substrate wafer 1, and the first electrode 12 and the second electrode 31 are fixedly electrically connected; The sacrificial wafer 2 outside the area fixed by the chip layer 3 is removed, and a protective layer 4 is formed covering the exposed surfaces of the chip layer 3 and the remaining sacrificial wafer 2; The remaining sacrificial wafer 2 and the protective layer 4 covering the exposed surfaces of the sacrificial wafer 2 are removed.

[0093] As an example, such as Figure 5 The diagram shows a cross-sectional view of the chip layer 3 bonded to the substrate wafer 1. The method for fixing the first electrode 12 and the second electrode 31 electrically connects them includes hybrid bonding or other suitable methods. In this embodiment, a hybrid bonding process is used to bond the chip layer 3 to the electrode region 11 in the substrate wafer 1, while simultaneously fixing the first electrode 12 and the second electrode 32 electrically connects them.

[0094] Specifically, the material of the second electrode 32 includes copper, aluminum, nickel, gold, silver, titanium, tantalum, tungsten, or other suitable conductive materials. In this embodiment, the first electrode 12 exposed on the upper surface of the first dielectric layer 13 and the second electrode 31 exposed on the upper surface of the second dielectric layer 32 are made of the same material, so as to facilitate the bonding of the first electrode 12 and the second electrode 31 together using a hybrid bonding process.

[0095] As an example, such as Figure 6 The cross-sectional structure diagram after removing the sacrificial wafer 2 outside the fixed area of ​​the chip layer 3 is shown. Removing the sacrificial wafer 2 outside the fixed area of ​​the chip layer 3 includes the following steps: forming a patterned masking layer on the side of the sacrificial wafer 2 away from the chip layer 3; removing the sacrificial wafer 2 based on the patterned masking layer, and removing the masking layer.

[0096] Specifically, the masking layer can be a hard mask layer or a photoresist layer. When the masking layer is a hard mask layer, the process for forming the masking layer is the commonly used hard mask manufacturing process. When the masking layer is a photolithography layer, the process for forming the masking layer is the photoresist coating process. These will not be elaborated further here.

[0097] Specifically, the method for patterning the masking layer is the commonly used photolithography process, which will not be elaborated here.

[0098] Specifically, the method for removing the sacrificial wafer 2 based on the patterned masking layer includes dry etching, wet etching, or other suitable methods.

[0099] Specifically, when the masking layer is a commonly used hard mask layer, the method for removing the masking layer is a commonly used hard mask removal method; when the masking layer is a commonly used photoresist layer, the method for removing the masking layer is a commonly used photoresist layer removal method. These will not be elaborated further here.

[0100] Specifically, the method for forming the protective layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0101] Specifically, the material of the protective layer 4 includes silicon oxide, silicon nitride, epoxy resin, PI, PBO, BCB, phosphosilicate glass, fluorinated glass, or other suitable materials. In this embodiment, a TEOS layer covering the exposed surfaces of the substrate wafer 1, the remaining sacrificial wafer 2, and the chip layer 3 is formed using a chemical vapor deposition process. Simultaneously, by controlling the conditions under which the TEOS is formed, the TEOS layer is transformed into a silicon oxide layer; that is, the protective layer 4 is a silicon oxide layer.

[0102] Specifically, while ensuring the performance of the hybrid bonding packaging structure, the thickness of the protective layer 4 can be selected according to the actual situation, and is not limited here.

[0103] As an example, such as Figure 7 The diagram shown is a cross-sectional view of the sacrificial wafer 2 after removing the sacrificial wafer 2 and the protective layer 4 covering the exposed surface of the sacrificial wafer 2. Methods for removing the remaining sacrificial wafer 2 and the protective layer 4 covering the exposed surface of the sacrificial wafer 2 include chemical mechanical polishing or other suitable methods. In this embodiment, chemical mechanical polishing is used to simultaneously remove the remaining sacrificial wafer 2 and the protective layer 4 covering the exposed surface of the sacrificial wafer 2.

[0104] As an example, such as Figure 8 The diagram shows a cross-sectional view of the wafer after removing the sacrificial wafer 2 and cutting it into a single package structure. After removing the remaining sacrificial wafer 2 and the protective layer 4 covering the exposed surface of the sacrificial wafer 2, the method further includes cutting the substrate wafer 1 to form a single package structure.

[0105] Specifically, the method for cutting the substrate wafer 1 is mechanical cutting, laser cutting, or other suitable cutting methods.

[0106] Specifically, by selecting a sacrificial wafer 2 of the same size as the substrate wafer 1 as a carrier platform, and using a fused bonding process to fix the chip layer 3 corresponding one-to-one with the electrode region 11 to a preset position on the sacrificial wafer 2, the sacrificial wafer 2 is then flipped onto the substrate wafer 1, and the chip layer 3 and the electrode region 11 are mixed bonded, which improves the production efficiency of the mixed bonded product (i.e., the wafer output per hour WPH). By performing nanometer-level alignment detection and local micro-adjustment on the chip layer 3, the bonding offset distance is made no greater than 50nm, thereby improving the bonding accuracy and improving the reliability and yield of the packaging structure.

[0107] Specifically, the chip layer 3 is fixed on the sacrificial wafer 2, and the chip layer 3 is bonded to the electrode region 11 by bonding the sacrificial wafer 2 to the substrate wafer 1. This bonding method does not require reserving too much cutting area, which can reduce the distance between adjacent electrode regions 11 and reduce the blank area above the electrode region 11. It eliminates the need to fill the blank area above the electrode region 11 with a dummy die to ensure the physical structure stability of the packaging structure during the packaging process, thus reducing manufacturing costs.

[0108] The method for fabricating the hybrid bonding packaging structure in this embodiment improves the manufacturing process. First, each chip layer 3 is fixed at a preset position on the upper surface of the sacrificial wafer 2, which has the same size as the substrate wafer 1, so that the chip layer 3 corresponds one-to-one with the electrode region 11. Then, the sacrificial wafer 2 is inverted on the substrate wafer 1 for hybrid bonding, which improves the production efficiency of hybrid bonding products. Furthermore, by performing nanometer-level alignment detection and local micro-adjustment on the chip layer 3, the bonding offset distance is made no greater than 50nm, thereby improving the bonding accuracy and the reliability and yield of the packaging structure. At the same time, this bonding method does not require reserving too much cutting area, which can reduce the distance between the electrode regions 11 in the substrate wafer 1 and reduce the blank area above the electrode regions 11. Therefore, there is no need to bond blank filling chips to ensure the physical structural stability of the packaging structure during the packaging process, which reduces the manufacturing cost and relatively reduces the size of the packaging structure.

[0109] Example 2

[0110] This embodiment provides a hybrid bonding package structure, which is fabricated using the hybrid bonding package structure fabrication method described in Embodiment 1.

[0111] Specifically, the hybrid bonding package structure includes a semiconductor layer 1a, a chip layer 3, and a protective layer 4. The semiconductor layer 1a has an electrode region 11, which includes a plurality of first electrodes 12, the upper surfaces of which are flush with the upper surfaces of the electrode region 11. The chip layer 3 includes a plurality of second electrodes 31 that correspond one-to-one with and are fixedly electrically connected to the first electrodes 12, the lower surfaces of which are flush with the lower surfaces of the chip layer 3. The protective layer 4 covers the exposed sidewalls of the chip layer 3.

[0112] Specifically, the semiconductor layer 1a is obtained by cutting the substrate wafer as described in Example 1.

[0113] Specifically, the hybrid bonding packaging structure is fabricated using the hybrid bonding structure fabrication method described in Embodiment 1, thereby improving the bonding accuracy between the first electrode 12 and the second electrode 31 in the hybrid bonding packaging structure, and improving the packaging yield and the reliability of the packaging structure.

[0114] Specifically, the hybrid bonding packaging structure is fabricated using the hybrid bonding structure fabrication method described in Example 1, thereby reducing the volume of the packaging structure.

[0115] The hybrid bonding packaging structure of this embodiment is fabricated using the hybrid bonding packaging structure fabrication method described in Embodiment 1. By performing nanometer-level alignment detection and local micro-adjustment on the chip layer 3, the bonding accuracy between the first electrode 12 and the second electrode 31 in the hybrid bonding packaging structure is improved, thereby increasing the packaging yield and the reliability of the packaging structure, and reducing the volume of the packaging structure.

[0116] In summary, the hybrid bonding packaging structure and its fabrication method of the present invention, through improved manufacturing processes, first fixes each chip in the chip layer to a sacrificial wafer of the same size as the substrate wafer, and ensures that the electrodes of each chip in the inverted chip layer correspond one-to-one with the electrodes in the electrode region. Then, the sacrificial wafer is inverted on the substrate wafer for hybrid bonding, improving the production efficiency of hybrid bonding products. By performing nanometer-level alignment detection and local micro-adjustment on the chip layer, the bonding offset distance is kept to no more than 50nm, thereby improving bonding accuracy and simultaneously enhancing the reliability and yield of the packaging structure. This bonding method eliminates the need for reserving too much cutting area, reducing the distance between electrode regions in the substrate wafer and decreasing the blank area above the electrode regions. Consequently, it eliminates the need to bond blank filler chips to ensure the physical structural stability of the packaging structure during the packaging process, reducing manufacturing costs and relatively shrinking the size of the packaging structure. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a hybrid bonding encapsulation structure, characterized in that, Includes the following steps: A substrate wafer is provided, the substrate wafer including a plurality of spaced electrode regions, the electrode regions including a plurality of first electrodes, the upper surface of the first electrodes being flush with the upper surface of the electrode regions; A sacrificial wafer is provided, and a plurality of chip layers corresponding one-to-one with the electrode regions are fixed on the upper surface of the sacrificial wafer. The chip layers include a plurality of second electrodes, the first electrodes corresponding one-to-one with the inverted second electrodes, and the upper surface of the second electrodes is flush with the upper surface of the chip layers. The sacrificial wafer with the chip layer fixed is inverted onto the substrate wafer, and the first electrode and the second electrode are fixedly electrically connected. Remove the sacrificial wafer outside the area fixed by the chip layer, and form a protective layer covering the exposed surfaces of the chip layer and the remaining sacrificial wafer; Remove the remaining sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer.

2. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: The chip layer includes at least one chip.

3. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: Methods for attaching the chip layer to the upper surface of the sacrificial wafer include fusion bonding.

4. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: Before fixing the chip layer to the upper surface of the sacrificial wafer, the method further includes a step of detecting and adjusting the offset of the chip layer.

5. The method for fabricating the hybrid bonding encapsulation structure according to claim 4, characterized in that, Detecting and adjusting the offset of the chip layer includes the following steps: Multiple predetermined regions are placed on the upper surface of the sacrificial wafer in the multiple chip layers, and the chip layers correspond one-to-one with the predetermined regions; Alignment detection is performed between the chip layer and the preset region corresponding to the chip layer; If the offset between the chip layer and its corresponding preset region is greater than the preset offset value, the position of the chip layer is adjusted, and the alignment between the chip layer and its corresponding preset region is checked again after the adjustment. The subsequent steps will continue until the offset values ​​of all chip layers on the upper surface of the sacrificial wafer and their corresponding preset regions are detected to be within the preset offset value.

6. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: The size of the electrode region is not smaller than the size of the chip layer.

7. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: The electrode region contains circuit structures corresponding to the chips in the chip layer.

8. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: Methods for permanently connecting the first electrode and the second electrode include hybrid bonding.

9. The method for fabricating the hybrid bonding packaging structure according to claim 1, characterized in that: Methods for removing the remaining sacrificial wafer and the protective layer covering the exposed surface of the sacrificial wafer include chemical mechanical polishing.

10. A hybrid bonding packaging structure, characterized in that, The hybrid bonding package structure is fabricated using the method described in any one of claims 1 to 9.

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