Method of forming a semiconductor package structure
By using chemical mechanical polishing and etching solution treatment in the etching tank, the short circuit problem caused by the contact between the pads and the substrate in the silicon interposer was solved, resulting in better electrical performance.
Patent Information
- Application Number
- CN202511455321.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-13
- Publication Date
- 2026-03-03
- Estimated Expiration
- 2045-10-13
AI Technical Summary
In the manufacturing process of existing silicon interposers, the spacing between adjacent via interconnect structures is small, causing the pads to come into direct contact with the silicon substrate, creating a short circuit risk and affecting electrical performance.
The second surface of the semiconductor substrate is planarized using a chemical mechanical polishing process to form a first protective film. The semiconductor substrate is then placed vertically in an etching tank, and an etching solution is used to etch the semiconductor substrate to remove part of the thickness, thereby exposing the via interconnect structure. Pads are formed on the passivation layer to prevent the pads from directly contacting the substrate.
By uniform etching and preventing the formation of "foot-like defects," the passivation layer thickness is ensured to be uniform, short-circuit risks are avoided, and the electrical performance of the semiconductor packaging structure is improved.
Smart Images
Figure CN120933238B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of packaging technology, and in particular to a method for forming a semiconductor packaging structure. Background Technology
[0002] Silicon interposers, or silicon interposer substrates, are widely used in advanced packaging. A typical silicon interposer includes through-silicon vias (TSVs) within the interposer and a wiring layer on the front side of the interposer, which is electrically connected to the TSVs.
[0003] Existing silicon interposer fabrication processes generally include: providing a silicon substrate; forming via interconnect structures in the silicon substrate; then forming a wiring layer on the front side of the silicon substrate, the wiring layer being electrically connected to the end of the via interconnect structure near the front side; subsequently, performing a backside via reveal (BVR) process on the back side of the silicon substrate, so that the back side of the silicon substrate exposes the end of the via interconnect structure away from the front side of the silicon substrate; existing backside via reveal processes generally employ dry etching; next, forming a passivation layer on the back side of the silicon substrate covering the exposed via interconnect structure, the passivation layer exposing the end of the via interconnect structure away from the front side of the silicon substrate; and forming pads electrically connected to the via interconnect structure on the passivation layer.
[0004] However, when the spacing between adjacent via interconnect structures is small, the pads in the silicon interposer formed by the above method will directly contact the silicon substrate, which will bring short circuit risk and affect the electrical performance of the silicon interposer. Summary of the Invention
[0005] The purpose of this application is to provide a method for forming a semiconductor package structure, avoiding the generation of "foot-like" defects, preventing direct contact between the pads and the semiconductor substrate, thereby reducing the risk of short circuits and improving the electrical performance of the semiconductor package structure.
[0006] To achieve the above objectives, embodiments of this application provide a method for forming a semiconductor package structure, including:
[0007] A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, and having a plurality of discrete through-hole interconnect structures therein;
[0008] The second surface of the semiconductor substrate is planarized using a chemical mechanical polishing process until the end surface of the via interconnect structure away from the first surface of the semiconductor substrate is exposed.
[0009] A first protective film is formed on the first surface of the semiconductor substrate;
[0010] After the first protective film is formed, the semiconductor substrate is placed vertically in the etching tank. The first and second surfaces of the semiconductor substrate are perpendicular to the bottom surface of the etching tank. The etching solution in the etching tank covers the semiconductor substrate. The etching solution etches the semiconductor substrate material on the second surface, removing part of the thickness of the semiconductor substrate and exposing part of the height of the via interconnect structure.
[0011] Remove the semiconductor substrate from the etching trench;
[0012] A passivation layer is formed on the second surface of the semiconductor substrate, the passivation layer covering the exposed side of the via interconnect structure and exposing one end surface of the via interconnect structure away from the first surface of the semiconductor substrate;
[0013] Pads electrically connected to the via interconnect structure are formed on the passivation layer.
[0014] In some embodiments, placing the semiconductor substrate vertically in the etching tank includes: fixing the semiconductor substrate by clamping the edge of the semiconductor substrate with a jig; and placing the semiconductor substrate together with the jig in the etching tank.
[0015] In some embodiments, the clamps include at least two clamps that clamp the semiconductor substrate from two opposite edges of the semiconductor substrate.
[0016] In some embodiments, the clamp is connected to a drive device that drives the clamp to clamp or release the semiconductor substrate, and to place the clamp in and remove it from the etching groove.
[0017] In some embodiments, after the semiconductor substrate is placed vertically in the etching tank, during the etching process of the etching solution on the semiconductor substrate material of the second surface, the semiconductor substrate moves back and forth and / or left and right along a direction parallel to the bottom surface of the etching tank.
[0018] In some embodiments, the driving device drives the fixture to move back and forth and / or left and right in the etching tank along a direction parallel to the bottom surface of the etching tank, thereby causing the semiconductor substrate to move back and forth and / or left and right along a direction parallel to the bottom surface of the etching tank.
[0019] In some embodiments, the semiconductor substrate is made of silicon.
[0020] In some embodiments, the etching solution comprises a mixture of hydrogen fluoride and hydrogen peroxide.
[0021] In some embodiments, the etching solution includes a sodium hydroxide solution or an ammonium hydroxide solution.
[0022] In some embodiments, after planarizing the second surface of the semiconductor substrate using a chemical mechanical polishing process until the end surface of the via interconnect structure away from the first surface of the semiconductor substrate is exposed, and before the semiconductor substrate is placed vertically in an etching tank, the method further includes forming a second protective film on the exposed end surface of the via interconnect structure away from the first surface of the semiconductor substrate.
[0023] In some embodiments, the materials of the first protective film and the second protective film are dry films.
[0024] In some embodiments, the formation process of the first protective film includes: forming a first protective film covering the entire first surface of the semiconductor substrate by a film lamination process.
[0025] In some embodiments, the process of forming the second protective film includes: forming a second protective film covering the entire second surface of the semiconductor substrate after planarization by a lamination process; exposing and developing the second protective film to remove the second protective film on both sides of the via interconnect structure, and retaining the second protective film on one end surface of the via interconnect structure away from the first surface of the semiconductor substrate.
[0026] In some embodiments, after removing the semiconductor substrate from the etching tank, the method further includes: removing the first protective film and the second protective film.
[0027] In some embodiments, after removing the semiconductor substrate from the etching tank, the method further includes: cleaning the semiconductor substrate; and drying the cleaned semiconductor substrate.
[0028] In some embodiments, the semiconductor substrate is cleaned after the first protective film and the second protective film are removed.
[0029] In some embodiments, a wiring layer electrically connected to the via connection structure is further formed on the first surface of the semiconductor substrate; the first protective film covers the wiring layer.
[0030] In some embodiments, the wiring layer includes a dielectric layer located on a first surface of the semiconductor substrate and metal wiring located in the dielectric layer.
[0031] In some embodiments, the passivation layer formation process includes: forming a passivation layer on the second surface of the semiconductor substrate to cover the exposed via interconnect structure; and planarizing and removing a portion of the passivation layer using a chemical mechanical polishing process to expose one end surface of the via interconnect structure away from the first surface of the semiconductor substrate.
[0032] In some embodiments, the material of the passivation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, and silicon carbonitride.
[0033] In some embodiments, the via interconnect structure includes a metal layer and a diffusion-blocking layer covering the metal layer.
[0034] In some embodiments, the material of the metal layer is Cu, Al, W, Ag, Au, Pt, or Ni; and the material of the anti-diffusion barrier layer is one or more of Ti, TiN, Ta, and TaN.
[0035] In some embodiments, the process for forming the through-hole interconnect structure includes electroplating.
[0036] In some embodiments, the material of the pad includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN;
[0037] The process for forming the pads includes electroplating.
[0038] In some embodiments, the semiconductor package structure is used as an interposer.
[0039] The beneficial effects of this application are:
[0040] The method for forming a semiconductor package structure disclosed in this application provides a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other, and having a plurality of discrete through-hole interconnect structures in the semiconductor substrate; planarizing the second surface of the semiconductor substrate using a chemical mechanical polishing process until the end surface of the through-hole interconnect structure away from the first surface of the semiconductor substrate is exposed; forming a first protective film on the first surface of the semiconductor substrate; after forming the first protective film, vertically placing the semiconductor substrate in an etching tank, the first surface and the second surface of the semiconductor substrate being perpendicular to the bottom surface of the etching tank, the etching solution in the etching tank covering the semiconductor substrate, the etching solution etching the semiconductor substrate material on the second surface, removing a portion of the thickness of the semiconductor substrate, exposing a portion of the height of the through-hole interconnect structure; removing the semiconductor substrate from the etching tank; forming a passivation layer on the second surface of the semiconductor substrate, the passivation layer covering the exposed side of the through-hole interconnect structure and exposing the end surface of the through-hole interconnect structure away from the first surface of the semiconductor substrate; forming pads electrically connected to the through-hole interconnect structure on the passivation layer. In this application, when etching the second surface of a semiconductor substrate, the semiconductor substrate is placed vertically in an etching tank. The etching solution in the etching tank completely covers the semiconductor substrate, allowing the etching solution to provide comprehensive and uniform coverage of the second surface material. This ensures uniform etching of the semiconductor material in different areas of the second surface. Furthermore, because the semiconductor substrate is placed vertically, etching byproducts are moved downwards under gravity and do not adhere to the second surface. This results in better and more uniform etching of the semiconductor material on the second surface, particularly around the via interconnect structures. This ensures uniform and sufficient etching of the semiconductor material around the via interconnect structures, preventing the formation of semiconductor material residues around them. Figure 1 The "Sifooting" defect shown makes the second surface of the etched semiconductor substrate have a relatively flat surface, so a passivation layer of uniform thickness can be formed on the second surface. When pads that are electrically connected to the via interconnect structure are formed on the passivation layer, the pads will not have direct contact with the semiconductor substrate, avoiding the risk of short circuit and improving the electrical performance of the formed semiconductor package structure. Attached Figure Description
[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.
[0042] Figure 1 This is a schematic diagram of the structure when a "foot-shaped" defect is generated after etching the second surface of a semiconductor substrate.
[0043] Figure 2 This is a schematic diagram of the existing structure after a passivation layer and pads are formed on the second surface of a semiconductor substrate.
[0044] Figure 3 This is a flowchart illustrating a method for forming a semiconductor packaging structure provided in some embodiments of this application;
[0045] Figure 4 This is a schematic diagram of the structure after providing a semiconductor substrate in the method for forming a semiconductor packaging structure provided in some embodiments of this application;
[0046] Figure 5 This is a schematic diagram of the structure after planarizing the second surface of the semiconductor substrate in a method for forming a semiconductor packaging structure provided in some embodiments of this application;
[0047] Figure 6 This is a schematic diagram of the structure after forming a first protective film on a first surface of a semiconductor substrate and a second protective film on the surface of a via interconnect structure in some embodiments of this application.
[0048] Figure 7 This is a schematic diagram of the structure after etching the second surface of the semiconductor substrate in a method for forming a semiconductor packaging structure provided in some embodiments of this application;
[0049] Figure 8 This is a schematic diagram of the semiconductor substrate being vertically prevented from being etched in the etching tank in a method for forming a semiconductor package structure provided in some embodiments of this application;
[0050] Figure 9 This is a schematic diagram of the structure after the passivation layer is formed in the method for forming a semiconductor packaging structure provided in some embodiments of this application;
[0051] Figure 10This is a schematic diagram of the structure after the pads are formed in the method for forming a semiconductor package structure provided in some embodiments of this application. Detailed Implementation
[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0054] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.
[0055] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0056] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.
[0057] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.
[0058] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).
[0059] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.
[0060] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.
[0061] In existing silicon interposer manufacturing processes, refer to Figure 1 The backside via reveal (BVR) process for the second surface 12 of the semiconductor substrate 101 typically employs a dry etching process. However, due to the small spacing between adjacent via interconnects (TSVs) 102, the etching gas in the dry etching process is insufficient to completely etch the silicon (Si) material at the edges of the TSVs 102, resulting in uneven etching. This leads to residual silicon material around the TSVs 102, forming "Si footing" 21. The Si footing 21 causes unevenness on the second surface 12 of the etched semiconductor substrate 101. (See reference...) Figure 2When a passivation layer 107 is deposited on the second surface 12 of the etched semiconductor substrate 101, the thickness of the passivation layer 107 will be uneven. When a pad 108 electrically connected to the via interconnect structure 102 is formed on the passivation layer 107, the pad 108 will directly contact the "Si footing" 21. That is, the pad 108 will directly contact the semiconductor substrate 101 through the "Si footing" 21, which brings the risk of short circuit and affects the electrical performance of the formed interposer.
[0062] Therefore, embodiments of this application provide a method for forming a semiconductor packaging structure. Figure 3 This is a flowchart illustrating a method for forming a semiconductor package structure provided in some embodiments of this application. (Refer to...) Figure 3 The method for forming the semiconductor package structure includes the following steps:
[0063] Step S101: Provide a semiconductor substrate, the semiconductor substrate including opposing first and second surfaces, the semiconductor substrate having a plurality of discrete through-hole interconnect structures;
[0064] Step S102: The second surface of the semiconductor substrate is planarized using a chemical mechanical polishing process until the end surface of the via interconnect structure away from the first surface of the semiconductor substrate is exposed.
[0065] Step S103: A first protective film is formed on the first surface of the semiconductor substrate;
[0066] Step S104: After forming the first protective film, the semiconductor substrate is placed vertically in the etching tank. The first and second surfaces of the semiconductor substrate are perpendicular to the bottom surface of the etching tank. The etching solution in the etching tank covers the semiconductor substrate. The etching solution etches the semiconductor substrate material on the second surface, removing part of the thickness of the semiconductor substrate and exposing part of the height of the via interconnect structure.
[0067] Step S105: Remove the semiconductor substrate from the etching tank;
[0068] Step S106: A passivation layer is formed on the second surface of the semiconductor substrate. The passivation layer covers the exposed side of the via interconnect structure and exposes one end surface of the via interconnect structure away from the first surface of the semiconductor substrate.
[0069] Step S107: A pad electrically connected to the via interconnect structure is formed on the passivation layer.
[0070] The method for forming the semiconductor packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.
[0071] First, refer to Figure 3 In conjunction with references Figure 4 In step S101, a semiconductor substrate 101 is provided, the semiconductor substrate 101 including a first surface 11 and a second surface 12 opposite to each other, and the semiconductor substrate 101 having a plurality of discrete through-hole interconnect structures 102.
[0072] The semiconductor substrate 101 is made of a semiconductor material, which may be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC). In a specific example, the semiconductor substrate 101 is a silicon substrate.
[0073] The semiconductor substrate 101 includes a first surface 11 and a second surface 12 facing each other. The first surface 11 can be the front side of the semiconductor substrate 101, and the second surface 12 can be the back side of the semiconductor substrate 101. Figure 4 The attached figure shows the second surface 12 (or back side) of the semiconductor substrate 101 facing upwards.
[0074] A plurality of discrete via interconnect structures 102 are formed in the semiconductor substrate 101, and the process for forming the via interconnect structures 102 includes electroplating. In some embodiments, the process of forming the via interconnect structure 102 includes: forming a patterned mask layer on a first surface of the semiconductor substrate 101, the patterned mask layer having a plurality of openings exposing a portion of the front side of the semiconductor substrate 101; using the patterned mask layer as a mask, etching the semiconductor substrate 101 along the openings to form a plurality of trenches in the semiconductor substrate 101; and filling the trenches with a metal material to form the via interconnect structure 102.
[0075] In some embodiments, the via interconnect structure 102 includes a metal layer and a diffusion-blocking layer covering the metal layer. The diffusion-blocking layer prevents metal elements in the metal layer from diffusing outward. Specifically, the diffusion-blocking layer is located on the sidewalls and bottom surface of the trench, and the metal layer is located on the diffusion-blocking layer and fills the trench. The material of the metal layer is Cu, Al, W, Ag, Au, Pt, or Ni; the material of the diffusion-blocking layer is one or more of Ti, TiN, Ta, and TaN.
[0076] In some embodiments, continue to refer to Figure 4After forming the via interconnect structure 102, a wiring layer electrically connected to the via interconnect structure is formed on the first surface 11 of the semiconductor substrate 101. The wiring layer includes a dielectric layer 103 located on the first surface 11 of the semiconductor substrate 101 and metal wiring 104 located in the dielectric layer 103. In one example, the material of the dielectric layer 103 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material of the metal wiring 104 is one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.
[0077] Next, refer to Figure 3 In conjunction with references Figure 5 In step S102, a chemical mechanical polishing process is used to planarize the second surface 12 of the semiconductor substrate 101 until the end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101 is exposed.
[0078] The chemical mechanical polishing process uses a polishing slurry that includes abrasives, buffer solutions, polishing agents, and additives. In one example, the abrasive is one or more of alumina (Al2O3), silicon oxide (SiO2), and silicon nitride (Si3N4); the buffer solution is one or more of ammonia, phosphate, and carbonate; the polishing agent is one or more of cerium nitrate, aluminum nitrate, and nickel nitrate; and the additives include oxidants, dispersants, and surfactants.
[0079] Next, refer to Figure 3 In conjunction with references Figure 6 A first protective film 105 is formed on the first surface 11 of the semiconductor substrate 101.
[0080] The first protective film 105 is used to protect the structure formed on the first surface 11 of the semiconductor substrate 101 from being etched during subsequent etching processes. In some embodiments, the formation of the first protective film 105 only covers the first surface 11 of the semiconductor substrate 101. In other embodiments, the formation of the first protective film 105 may cover not only the first surface 11 of the semiconductor substrate 101, but also the side surface of the semiconductor substrate 101.
[0081] In some embodiments, when a wiring layer is formed on the first surface 11 of the semiconductor substrate 101, the first protective film 105 covers the wiring layer.
[0082] In some embodiments, after planarizing the second surface 12 of the semiconductor substrate 101 using a chemical mechanical polishing process until the end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101 is exposed, and before the semiconductor substrate 101 is vertically placed in the etching tank 14, the process further includes forming a second protective film 106 on the exposed end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101. The second protective film 106 protects the end of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101 from being etched during subsequent etching processes. The shape and size of the second protective film 106 are slightly larger than the shape and size of the end surface of the via interconnect structure 102, and the size of the second protective film 106 is 1.05 to 1.1 times the size of the end surface of the via interconnect structure 102, with an alignment accuracy of no more than 0.2 μm. During subsequent etching, the second protective film 106 affects the etching of the semiconductor material around the via interconnect structure 102, which helps to prevent the formation of "foot-shaped" defects in the semiconductor substrate 101 around the via interconnect structure 102.
[0083] In some embodiments, the materials of the first protective film 105 and the second protective film 106 are dry films. In one example, the dry film comprises a film-forming resin, a photopolymerizable monomer, a photoinitiator, a plasticizer, a tackifier, and a heat-resistant polymerization inhibitor. The photopolymerizable monomer is an epoxy resin or an acrylic resin. The photoinitiator is one or more of benzoin and its ethers, benzoin diethers, alkyl anthraquinones, and benzophenone / amines. The plasticizer is ethylene glycol diacetate. The tackifier is benzotriazole, benzimidazole, or indazole. The heat-resistant polymerization inhibitor is hydroquinone or p-methoxyphenol.
[0084] In some embodiments, the formation process of the first protective film 105 includes: forming a first protective film 105 covering the entire first surface 11 of the semiconductor substrate 101 by a film lamination process.
[0085] In some embodiments, the process of forming the second protective film 106 includes: forming a second protective film 106 covering the entire second surface 12 of the semiconductor substrate 101 after planarization by a film lamination process; exposing and developing the second protective film 106 to remove the second protective films 106 on both sides of the via interconnect structure 102, and retaining the second protective film 106 on one end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101.
[0086] Next, refer to Figure 3 In conjunction with references Figure 7 and Figure 8After forming the first protective film 105, the semiconductor substrate 101 is vertically placed in the etching tank 14 (reference). Figure 8 In the etching process, the first surface 11 and the second surface 12 of the semiconductor substrate 101 are perpendicular to the bottom surface of the etching tank 14. The etching solution 15 in the etching tank 14 covers the semiconductor substrate 101. The etching solution 15 etches the semiconductor substrate 101 material on the second surface 12, removing part of the thickness of the semiconductor substrate 101 and exposing part of the height of the through-hole interconnect structure 102.
[0087] In this application, when etching the second surface of the semiconductor substrate 101, the semiconductor substrate 101 is placed vertically in the etching tank 14 (see reference). Figure 8 In the etching process, the first surface 11 and the second surface 12 of the semiconductor substrate 101 are perpendicular to the bottom surface of the etching tank 14. The etching solution 15 in the etching tank 14 covers the semiconductor substrate 101. The etching solution 15 can cover the material of the second surface 12 of the semiconductor substrate 101 in an all-round and uniform manner, so as to uniformly etch the semiconductor material in different areas of the second surface 12. Since the semiconductor substrate 101 is placed vertically, the by-products generated by etching will move downward under the action of gravity and will not adhere to the second surface 12. This allows for better and more uniform etching of the semiconductor material on the second surface 12. In particular, the etching of the semiconductor material around the via interconnect structure 102 is also uniform and sufficient, so that no semiconductor material residue is generated around the via interconnect structure 102, thereby preventing the formation of such residues around the via interconnect structure 102. Figure 1 The "Si footing" 21 shown makes the second surface 12 of the etched semiconductor substrate 101 have a relatively flat surface, so that a passivation layer 107 of uniform thickness can be formed on the second surface 12 (see reference). Figure 9 When pads 108 that are electrically connected to via interconnect structure 102 are subsequently formed on passivation layer 107, pads 108 will not have direct contact with semiconductor substrate 101, avoiding the risk of short circuit and improving the electrical performance of the formed semiconductor package structure.
[0088] In some embodiments, when the semiconductor substrate 101 is made of silicon, the etching solution 15 may be a mixture of hydrogen fluoride and hydrogen peroxide. In another embodiment, the etching solution 15 may further comprise a sodium hydroxide solution or an ammonium hydroxide solution.
[0089] In some embodiments, continue to refer to Figure 8Placing the semiconductor substrate 101 vertically in the etching tank 14 includes: fixing the semiconductor substrate 101 by clamping its edge with a clamp 13; and placing the semiconductor substrate 101 together with the clamp 13 in the etching tank 14. The clamp 13 comprises at least two clamps, which clamp the semiconductor substrate 101 from two opposite edges, respectively, to better fix the semiconductor substrate 101 and to ensure that the clamps 13 do not affect the etching process. Figure 8 The number of clamps 13 described herein is two as an example. In other embodiments, the number of clamps 13 may be greater than two, such as three or four.
[0090] In some embodiments, the clamp 13 is connected to a drive device (not shown), which drives the clamp 13 to clamp or release the semiconductor substrate 101, and to place the clamp 13 in and remove it from the etching tank 14. It should be noted that the etching tank 14, the clamp 13, and the drive device can all be part of a wet etching apparatus.
[0091] In some embodiments, after the semiconductor substrate 101 is vertically placed in the etching tank 14, during the etching process of the etching solution 15 on the semiconductor substrate 101 material of the second surface 12, the semiconductor substrate 101 is moved back and forth and / or left and right along a direction parallel to the bottom surface of the etching tank 14. For example, in one example, during the etching process, the semiconductor substrate 101 is moved forward and / or back and forth along a direction parallel to the bottom surface of the etching tank 14; in another example, during the etching process, the semiconductor substrate 101 is moved to the left and / or forward and right along a direction parallel to the bottom surface of the etching tank 14; in another example, during the etching process, the semiconductor substrate 101 is moved forward along a direction parallel to the bottom surface of the etching tank 14, and can also move to the left and / or forward and right; in another example, during the etching process, the semiconductor substrate 101 is moved backward along a direction parallel to the bottom surface of the etching tank 14, and can also move to the left and / or forward and right. During the etching process, the semiconductor substrate 101 is moved, allowing the etching solution to better and more uniformly cover the second surface 12 of the semiconductor substrate 101. Etching byproducts can also be better moved from the second surface 12 to or diffuse to other locations, thus improving uniformity and better preventing the residue of semiconductor material around the via interconnect structure 102. This, in turn, better prevents the formation of [unspecified] around the via interconnect structure 102. Figure 1The "Si footing" 21 shown improves the flatness of the second surface 12 of the etched semiconductor substrate 101, further enhancing the passivation layer 107 subsequently formed on the second surface 12 (see reference). Figure 9 The uniformity of the passivation layer 107 thickness ensures that when the pads 108 for interconnecting the via structure 102 are subsequently formed on the passivation layer 107, the pads 108 are less likely to directly contact the semiconductor substrate 101, thus better avoiding the risk of short circuits and further improving the electrical performance of the formed semiconductor package structure. It should be noted that the forward and backward movements are along... Figure 8 The square and negative directions of the X-axis, the left and right movements are along the X-axis. Figure 8 The square on the Y-axis and the negative direction shift.
[0092] In some embodiments, the driving device drives the clamp 13 to move back and forth and / or left and right in the etching groove 14 along a direction parallel to the bottom surface of the etching groove 14, thereby causing the semiconductor substrate 101 to move back and forth and / or left and right along a direction parallel to the bottom surface of the etching groove 14.
[0093] Next, refer to Figure 3 In conjunction with references Figure 9 In step S105, the semiconductor substrate 101 is removed from the etching trench 14; and in step S106, a passivation layer 107 is formed on the second surface 12 of the semiconductor substrate 101. The passivation layer 107 covers the exposed side of the via interconnect structure 102 and exposes the end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101.
[0094] In some embodiments, after removing the semiconductor substrate 101 from the etching tank 14, the process further includes removing the first protective film 105 and the second protective film 106. In one example, the first protective film 105 and the second protective film 106 are removed by a film peeling process.
[0095] In some embodiments, after removing the semiconductor substrate 101 from the etching tank 14, the process further includes: cleaning the semiconductor substrate 101 to remove residual etching solution and etching byproducts; and drying the cleaned semiconductor substrate 101 to prevent residue of cleaning solution. In one example, cleaning the semiconductor substrate 101 is performed after removing the first protective film 105 and the second protective film 106.
[0096] In some embodiments, the passivation layer 107 is formed by: forming a passivation layer 107 covering the exposed via interconnect structure 102 on the second surface 12 of the semiconductor substrate 101; and planarizing and removing a portion of the passivation layer 107 using a chemical mechanical polishing process to expose one end surface of the via interconnect structure 102 away from the first surface 11 of the semiconductor substrate 101. In some embodiments, the material of the passivation layer 107 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.
[0097] Finally, refer to Figure 3 In conjunction with references Figure 10 A pad 108 electrically connected to the via interconnect structure 102 is formed on the passivation layer 107.
[0098] The material of the pad 108 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN;
[0099] The process of forming the pad 108 includes electroplating.
[0100] Thus, the semiconductor package structure of this application is formed. In some embodiments, the formed semiconductor package structure is used as an interposer.
[0101] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0102] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.
[0103] In summary, when etching the second surface of the semiconductor substrate, this application, by vertically placing the semiconductor substrate in the etching tank, ensures that the etching solution in the tank completely covers the semiconductor substrate. This allows for comprehensive and uniform coverage of the second surface material, enabling uniform etching of semiconductor materials in different areas of the second surface. Furthermore, because the semiconductor substrate is vertically placed, etching byproducts are carried downwards by gravity and do not adhere to the second surface. This results in better and more uniform etching of the semiconductor material on the second surface, particularly around the via interconnect structures, ensuring uniform and sufficient etching. This prevents the formation of semiconductor material residue around the via interconnect structures, thus preventing the formation of problems such as... Figure 1 The "Sifooting" defect shown makes the second surface of the etched semiconductor substrate have a relatively flat surface, so a passivation layer of uniform thickness can be formed on the second surface. When pads that are electrically connected to the via interconnect structure are formed on the passivation layer, the pads will not have direct contact with the semiconductor substrate, avoiding the risk of short circuit and improving the electrical performance of the formed semiconductor package structure.
[0104] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.
Claims
1. A method of forming a semiconductor package structure, comprising: The application relates to a semiconductor substrate manufacturing method. The method comprises the following steps: providing a semiconductor substrate comprising a first surface and a second surface, and a plurality of discrete through-hole interconnection structures in the semiconductor substrate; planarizing the second surface of the semiconductor substrate by a chemical mechanical polishing process until the end surface of the through-hole interconnection structure away from the first surface of the semiconductor substrate is exposed; forming a first protective film on the first surface of the semiconductor substrate; after forming the first protective film, vertically placing the semiconductor substrate in an etching tank, with the first surface and the second surface of the semiconductor substrate being perpendicular to the bottom surface of the etching tank, and the etching solution in the etching tank being higher than the semiconductor substrate, so that the semiconductor substrate material on the second surface is etched by the etching solution, and part of the thickness of the semiconductor substrate is removed to expose part of the height of the through-hole interconnection structure; removing the semiconductor substrate from the etching tank; forming a passivation layer on the second surface of the semiconductor substrate, which covers the exposed side surface of the through-hole interconnection structure and exposes the end surface of the through-hole interconnection structure away from the first surface of the semiconductor substrate; 2. The method of claim 1, wherein forming a pad on the passivation layer and electrically connected with the through-hole interconnection structure.
3. The method of claim 2, wherein Vertically placing the semiconductor substrate in the etching tank comprises the following steps: fixing the semiconductor substrate by clamping the edges of the semiconductor substrate by a clamp; and placing the semiconductor substrate and the clamp in the etching tank.
4. The method of claim 2, wherein The clamp comprises at least two, and clamps the semiconductor substrate from the opposite edges of the semiconductor substrate.
5. The method of claim 4, wherein The clamp is connected with a driving device, and the driving device drives the clamp to clamp or release the semiconductor substrate, and drives the clamp to be placed in and removed from the etching tank.
6. The method of claim 5, wherein After vertically placing the semiconductor substrate in the etching tank, during the etching process of the semiconductor substrate material on the second surface by the etching solution, the semiconductor substrate moves forward and backward and / or moves left and right along the direction parallel to the bottom surface of the etching tank.
7. The method of claim 5, wherein The driving device drives the clamp to move forward and backward and / or move left and right along the direction parallel to the bottom surface of the etching tank in the etching tank, so that the semiconductor substrate moves forward and backward and / or moves left and right along the direction parallel to the bottom surface of the etching tank.
8. The method of claim 7, wherein The material of the semiconductor substrate comprises silicon.
9. The method of claim 7, wherein The etching solution comprises a mixture of hydrogen fluoride and hydrogen peroxide.
10. The method of claim 1, wherein The etching solution comprises a sodium hydroxide solution or an ammonium hydroxide solution.
11. The method of claim 10, wherein After planarizing the second surface of the semiconductor substrate by the chemical mechanical polishing process until the end surface of the through-hole interconnection structure away from the first surface of the semiconductor substrate is exposed, and before vertically placing the semiconductor substrate in the etching tank, the method further comprises the following step: forming a second protective film on the end surface of the through-hole interconnection structure away from the first surface of the semiconductor substrate.
12. The method of claim 11, wherein The materials of the first protective film and the second protective film are dry films. The forming process of the first protective film comprises the following step: forming the first protective film covering the whole first surface of the semiconductor substrate by a film pasting process.
13. The method of claim 11, wherein The forming process of the second protective film includes: forming a second protective film covering the whole second surface of the semiconductor substrate after chemical mechanical polishing process by a film pasting process; exposing and developing the second protective film to remove the second protective film on both sides of the via interconnection structure, and to keep the second protective film on the end surface of the via interconnection structure away from the first surface of the semiconductor substrate.
14. The method of claim 10, wherein After the semiconductor substrate is removed from the etching tank, the method further includes: removing the first protective film and the second protective film.
15. The method of claim 14, wherein After the semiconductor substrate is removed from the etching tank, the method further includes: cleaning the semiconductor substrate; and drying the cleaned semiconductor substrate.
16. The method of claim 15, wherein The cleaning of the semiconductor substrate is performed after the first protective film and the second protective film are removed.
17. The method of claim 1, wherein The first surface of the semiconductor substrate further forms a wiring layer electrically connected with the via interconnection structure; and the first protective film covers the wiring layer.
18. The method of claim 17, wherein The wiring layer includes a dielectric layer on the first surface of the semiconductor substrate and a metal wiring in the dielectric layer.
19. The method of claim 1, wherein The forming process of the passivation layer includes: forming a passivation layer covering the exposed via interconnection structure on the second surface of the semiconductor substrate; and removing part of the passivation layer by chemical mechanical polishing process to expose the end surface of the via interconnection structure away from the first surface of the semiconductor substrate.
20. The method of claim 19, wherein The material of the passivation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon carbonitride.
21. The method of claim 1, wherein The via interconnection structure includes a metal layer and a diffusion barrier layer covering the metal layer.
22. The method of claim 21, wherein The material of the metal layer is Cu, Al, W, Ag, Au, Pt or Ni; and the material of the diffusion barrier layer is one or more of Ti, TiN, Ta and TaN.
23. The method of claim 21, wherein The process of forming the via interconnection structure includes electroplating.
24. The method of forming a semiconductor package structure of claim 1, wherein, The material of the pad includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC and WN. The process of forming the pad includes electroplating.
25. The method of claim 1, wherein The semiconductor package structure is used as an interposer.
Citation Information
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