Method for forming conductive channel

Abstract

The invention provides a forming method of a conductive channel, and relates to the technical field of semiconductors, and the method comprises the steps: forming an insulating lamination layer on a conductive layer; forming a groove / through hole in the insulating laminated layer; and filling a conductive material in the groove / through hole for forming a conductive channel in contact with the conductive layer, performing wet etching on the plurality of insulating layers in the insulating laminated layer in the process of forming the groove / through hole, or neutralizing polar charges at the interface of the plurality of insulating layers in the insulating laminated layer in the process of forming the insulating laminated layer, and dry etching is carried out on the insulating laminated layer in the process of forming the groove / through hole. Because a local electric field cannot be formed in a specific region by wet etching, the generation of an electric arc is avoided; and the polar charges are neutralized firstly and then the dry etching is carried out, so that the generation of electric arcs can be obviously reduced and even avoided, the stability in the etching process is improved, and the reliability and the performance of the conductive channel are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a conductive channel. Background Technology

[0002] In the field of semiconductor manufacturing technology, filling structures such as trenches and vias with conductive materials to form interconnect structures is a key part of achieving electrical connections between different components within a chip. As semiconductor technology continues to advance, chip sizes are shrinking, and the aspect ratio of interconnect structures is increasing, placing higher demands on manufacturing processes.

[0003] To achieve high aspect ratio interconnect structures, multiple and relatively thick insulating layers are typically deposited. However, during dry etching of the insulating layers, charge easily accumulates between the layers. This charge accumulation can lead to arcing during subsequent dry etching. Especially when etching to the dielectric layer interface, the arcing alters the environment within the process cavity, forming divergent tower-shaped defects. These defects severely impact device performance and reliability. Summary of the Invention

[0004] In view of the above problems, there is a need to propose an improved method for forming conductive channels.

[0005] The method for forming a conductive channel according to this application includes:

[0006] An insulating layer is formed on the conductive layer;

[0007] A first trench / first via is formed in the insulating stack; and

[0008] The first trench / first through-hole is filled with conductive material to form a conductive channel that contacts the conductive layer.

[0009] During the formation of the first trench / first via, multiple insulating layers in the insulating stack are wet-etched.

[0010] Alternatively, during the formation of the insulating stack, the polar charges at the interfaces of the multiple insulating layers in the insulating stack are neutralized, and the insulating stack is dry-etched during the formation of the first trench / first via.

[0011] Optionally, in the step of forming the insulating stack, the following steps are repeated:

[0012] Deposit an insulating layer;

[0013] The density and polarity of the freely moving charge at the interface of one of the insulating layers are detected.

[0014] Based on the test results, the data system provides feedback, and an opposite polarity charge is injected to make the interface electrically neutral.

[0015] Optionally, the step of forming the first trench / first through hole includes:

[0016] A chemical difference is created between the insulating stack located in the open region and the non-open region of the first trench / first via to change the selectivity of wet etching of the insulating stack located in the open region and the non-open region.

[0017] Optionally, it further includes: forming a second photolithographic mask on the insulating stack to cover the non-opening region, while the opening region is exposed.

[0018] The step of forming the chemical property difference includes: implanting ions into the opening region using a high-energy ion implantation process to form a modified portion in the insulating stack.

[0019] Optionally, in the step of implanting ions into the opening region using a high-energy ion implantation process, the ions are implanted near the upper surface of the lowest insulating layer in the insulating stack.

[0020] Optionally, after the modified portion is removed by wet etching, the bottom layer of the insulating stack is dry etched to allow the first trench / first via to penetrate the insulating stack.

[0021] Optionally, the surface of the second photomask is hardened using the high-energy ion implantation process.

[0022] Optionally, before forming the first trench / first through hole, the forming method further includes:

[0023] Aluminum is deposited on the insulating stack to form a second barrier layer; and

[0024] A second photolithographic mask is formed on the second barrier layer, the second photolithographic mask exposing the opening region of the first trench / first via.

[0025] The second barrier layer serves as a hard mask for the insulating stack in the dry etching process.

[0026] Optionally, before forming the second photolithographic mask, the forming method further includes: oxidizing the upper surface of the second barrier layer to form aluminum oxide.

[0027] Optionally, the second barrier layer is formed using a thermal aluminum deposition process to oxidize the upper surface of the second barrier layer.

[0028] The process temperature of the hot aluminum deposition process is also used to anneal the insulating laminate.

[0029] One of the above technical solutions has the following unexpected technical effect:

[0030] In the formation of the first trench / via, a wet etching process is employed. Because wet etching uses liquid chemical reagents, it can uniformly etch the entire surface without creating localized electric fields in specific areas, thus avoiding arcing. Alternatively, during the formation of the insulating stack, the polar charges at the interfaces between adjacent insulating layers are neutralized first. This significantly reduces or even eliminates arcing during the subsequent dry etching process for forming the first trench / via. These two methods not only improve the stability of the etching process but also reduce the formation of divergent tower-shaped defects, thereby enhancing the reliability and performance of the interconnect structure.

[0031] High-energy ion implantation is used to implant ions into the opening region to form modified parts in the insulating stack. This greatly increases the selectivity of the modified parts to the unmodified insulating stack. Therefore, wet etching can be used instead of dry etching to etch part of the insulating stack.

[0032] While modifying the insulating stack using high-energy ion implantation, high-energy ions are also implanted into the photomask above the insulating stack, causing the surface of the photomask to harden and even form a hard outer shell of carbon layer, further increasing its ability to resist etch ions (plasma) in subsequent dry etching processes. This eliminates the need to increase the thickness of the photomask due to the increase in aspect ratio, thereby saving costs.

[0033] By depositing aluminum on an insulating stack to form a second barrier layer, and then forming a photomask on the second barrier layer, the second barrier layer and the photomask together form a composite mask, which can further enhance the etch resistance of the mask and ensure that there will be no mask damage or displacement during the etching process, thereby ensuring the accuracy and consistency of the etching.

[0034] A second barrier layer is formed using a hot-aluminum deposition process, which oxidizes the upper surface of the second barrier layer to form a dense aluminum oxide film, further enhancing the mask's etch resistance. Furthermore, the process temperature of the hot-aluminum deposition process can also be used to anneal the insulating stack, thereby eliminating internal stress in the insulating stack and making it flatter. This flattened insulating stack not only helps improve the uniformity and consistency of subsequent processes but also reduces thin film defects caused by internal stress, further enhancing the reliability and performance of the interconnect structure.

[0035] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit this application. Attached Figure Description

[0036] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0037] Figure 1 This shows a schematic diagram of the structure after the first barrier layer, dielectric layer and mask layer are formed on the conductive layer in the first embodiment of this application;

[0038] Figure 2 A schematic diagram showing the generation of polar charges at the interface when the first insulating layer in the insulating stack is formed in the first embodiment of this application is shown;

[0039] Figure 3 This diagram illustrates the neutralization of polar charges at the interface of the first insulating layer in the first embodiment of this application.

[0040] Figure 4 This shows a schematic diagram of the structure after the insulating laminate is formed in the first embodiment of this application;

[0041] Figure 5 This illustration shows a schematic diagram of the modification of the upper surface of the insulating laminate in the first embodiment of this application;

[0042] Figure 6 This shows a schematic diagram of the structure after forming the second photolithographic mask in the first embodiment of this application;

[0043] Figure 7 This shows a schematic diagram of the structure after etching the upper insulating layer of the insulating stack in the first embodiment of this application;

[0044] Figure 8 This shows a schematic diagram of the structure after etching the intermediate insulating layer of the insulating stack in the first embodiment of this application;

[0045] Figure 9 This shows a schematic diagram of the structure after etching the lower insulating layer and dielectric layer of the insulating stack in the first embodiment of this application;

[0046] Figure 10 This shows a schematic diagram of the structure after etching the first barrier layer in the first embodiment of this application;

[0047] Figure 11 This shows a schematic diagram of the structure after the inner liner is formed in the first embodiment of this application;

[0048] Figure 12 This shows a schematic diagram of the structure after the conductive channel is formed in the first embodiment of this application;

[0049] Figure 13 This shows a schematic diagram of the structure after the second barrier layer is formed on the insulating stack in the second embodiment of this application;

[0050] Figure 14 This shows a schematic diagram of the structure after forming a second photolithographic mask on the second barrier layer in the second embodiment of this application;

[0051] Figure 15 This shows a schematic diagram of the structure after etching the upper insulating layer of the insulating stack in the second embodiment of this application;

[0052] Figure 16 This shows a schematic diagram of the structure after etching the intermediate insulating layer of the insulating stack in the second embodiment of this application;

[0053] Figure 17 This shows a schematic diagram of the structure after etching the first barrier layer in the second embodiment of this application;

[0054] Figure 18 This invention provides a schematic diagram of the structure after the inner liner layer is formed in the second embodiment of this application.

[0055] Figure 19 This shows a schematic diagram of the structure after forming a second photolithographic mask on the insulating stack in the third embodiment of this application;

[0056] Figure 20 This illustration shows a schematic diagram of high-energy ion implantation of an insulating stack located in an opening region in a third embodiment of this application;

[0057] Figure 21 This shows a schematic diagram of the structure after the modified portion is formed in the insulating stack located in the opening region according to the third embodiment of this application;

[0058] Figure 22 This shows a schematic diagram of the structure of the modified part after wet etching in the third embodiment of this application;

[0059] Figure 23 This shows a schematic diagram of the structure after etching the lower insulating layer and dielectric layer of the insulating stack in the third embodiment of this application;

[0060] Figure 24 This shows a schematic diagram of the structure after etching the first barrier layer in the third embodiment of this application;

[0061] Figure 25 A schematic diagram of the structure after the inner liner layer is formed in the third embodiment of this application is shown.

[0062] Explanation of reference numerals in the attached figures: 10-First photolithographic mask; 20-Second photolithographic mask; 21-Carbon layer; 101-First barrier layer; 102-Dielectric layer; 103-Mask layer; 103a-Opening; 104-First insulating layer; 105-Second insulating layer; 106-Third insulating layer; 106a-Unmodified layer; 106b-Modified layer; 107-Second barrier layer; 108-Modified part; 110-Conductive layer; 121a-First trench; 121b-First via; 122-Second via; 130-Conductive channel; 131-Inner liner layer; 132-Conductive material; q-Polar charge; S1-Opening region; S2-Unopening region. Detailed Implementation

[0063] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0064] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0065] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] This application may be presented in various forms, some of which will be described below.

[0067] In related technologies, the required aspect ratio for trench vias has reached approximately 13 or even higher. When employing related process technologies, two main challenges arise: firstly, positive photomasks may not be sufficient to block the light, as process dimensions limit the mask thickness. While negative photomasks can be used, they require redesigning the mask, increasing process costs and slowing development. Secondly, filling Cu with trench vias with large aspect ratios presents significant challenges; therefore, the quality of the trench vias is crucial.

[0068] Currently, before forming vias, multiple insulating layers are deposited sequentially above the conductive layer. However, each insulating layer itself has internal stress, and there is also interaction stress between them. In addition, the contact interface between adjacent insulating layers is prone to charge accumulation, which leads to the formation of electric arcs when the subsequent dry etching reaches the interface. This changes the environment within the process cavity, resulting in divergent tower-shaped defects. Furthermore, these charges are more likely to generate electric arcs under the promotion of thin film stress, thus forming more tower-shaped defects. Tower-shaped defects are caused by the combination of plasma and interlayer charges during dry etching, resulting in lateral etching, i.e., the etching extends to the sides.

[0069] In view of the above problems, there is a need to propose an improved method for forming conductive channels. Figures 1 to 12 The following shows cross-sectional views of the method for forming conductive channels in the first embodiment of this application at some stages. Figures 1 to 12 This processing method is explained in detail.

[0070] like Figure 1 As shown, along the thickness direction of the conductive layer 110, a first barrier layer 101, a dielectric layer 102, and a mask layer 103 are sequentially formed on the conductive layer 110 using a deposition process, for example. Then, a first photolithographic mask 10 is formed on the mask layer 103. Dry etching is then performed on the mask layer 103 through the first photolithographic mask 10 to form an opening 103a in the mask layer 103. The dry etching stops near the surface of the dielectric layer 102, thereby exposing a portion of the dielectric layer 102 to the opening 103a. Afterward, the first photolithographic mask 10 is removed, for example, using an ashing process. The etching selectivity of the dielectric layer 102 differs from that of the first barrier layer 101 and the mask layer 103.

[0071] In this embodiment, the conductive layer 110 is made of metals such as copper, silver, and tungsten, or polycrystalline silicon. The first barrier layer 101 is made of nitrogen-doped silicon carbide (NDC) and has a thickness of 600 angstroms. The first barrier layer 101 prevents metal elements in the conductive layer 110 from diffusing into the dielectric layer 102. The dielectric layer 102 is made of tetraethy lorthosilicate (TEOS) and has a thickness of 6000 angstroms. The mask layer 103 is made of silicon nitride and has a thickness of 2000 angstroms. However, this embodiment is not limited to these specific examples, and those skilled in the art can adjust the materials and thicknesses of the conductive layer 110, the first barrier layer 101, the dielectric layer 102, and the mask layer 103 as needed.

[0072] Furthermore, a first insulating layer 104 is formed on the mask layer 103, such as... Figure 2 As shown.

[0073] In this step, for example, a deposition process is used to form a first insulating layer 104 covering the mask layer 103, and the first insulating layer 104 fills the opening 103a, covering the exposed dielectric layer 102. During the deposition process, the upper surface (interface) of the first insulating layer 104 is prone to charge accumulation. In this embodiment, the accumulation of negative charge is used as an example for explanation.

[0074] Furthermore, the free-moving charge density and polarity at the interface of the first insulating layer 104 are detected, and based on the detection results, a charge of opposite polarity is injected to make the interface electrically neutral, such as... Figure 3 As shown.

[0075] In this step, for example, an advanced process control (APC) system based on big data is used to feed back to the next process. If the free charge on the surface of the first insulating layer 104 is negatively charged, then according to the charge density, the same amount of positive charge is injected to remove the free charge on the surface of the first insulating layer 104.

[0076] Furthermore, a second insulating layer 105 and a third insulating layer 106 are sequentially deposited on the first insulating layer 104, thereby forming an insulating laminate structure composed of the first insulating layer 104 to the third insulating layer 106, such as... Figure 4 As shown.

[0077] In this step, after each layer of insulating layer is deposited, the free-moving charge density and polarity at the interface of the insulating layer must be repeatedly detected, and based on the detection results, the data system provides feedback to inject a charge of the opposite polarity to make the interface electrically neutral.

[0078] In this embodiment, the material of the first insulating layer 104 to the third insulating layer 106 is TEOS, wherein the thickness of the first insulating layer 104 and the second insulating layer 105 is 13,000 angstroms, and the thickness of the third insulating layer 106 is 8,000 angstroms. However, the embodiments of this application are not limited thereto, and those skilled in the art can make other settings for the number of insulating layers, the material, and the thickness of each insulating layer as needed.

[0079] Furthermore, the surface of the third insulating layer 106 is modified, such as... Figure 5 As shown.

[0080] In this step, for example, high-energy ion implantation is performed on the entire wafer to modify the surface of the third insulating layer 106, forming a modified layer 106b. The portion without implanted ions is the unmodified layer 106a, for example, nitrogen ions are implanted to form silicon oxynitride. The etching selectivity of the modified layer 106b compared to the first insulating layer 104 and the second insulating layer 105 is relatively large. In subsequent etching steps, the third insulating layer 106 can act as a hard mask for the first insulating layer 104 and the second insulating layer 105, thus eliminating the need for a thicker negative photoresist mask, thereby saving costs and reducing development time. In addition, high-energy ion implantation can also weaken or even eliminate the internal stress of the material film during deposition.

[0081] Furthermore, a second photomask 20 is formed on the third insulating layer 106, such as... Figure 6 As shown. The pattern opening of the second photolithography mask 20 corresponds to the opening 103a in the mask layer 103, and its lateral dimension is larger than that of the opening 103a.

[0082] Further, the third insulating layer 106 is dry-etched using the second photolithography mask 20 to form the openings of the first trench 121a / first via 121b in the third insulating layer 106, such as... Figure 7 As shown. In this embodiment, the first trench 121a will be used as an example for the subsequent description. After etching is completed, the second photomask 20 is removed, for example, by an ashing process.

[0083] Furthermore, the second insulating layer 105 is dry etched, such as... Figure 8 As shown. Since the etching selectivity of the modified layer 106b in the third insulating layer 106 is relatively large compared with that of the second insulating layer 105, the third insulating layer 106 can be used as a hard mask for the second insulating layer 105 in this step.

[0084] Further, the first insulating layer 104 and the dielectric layer 102 are subjected to dry etching, such as... Figure 9As shown. In this step, the etching of the first trench 121a stops at the surface of the mask layer 103, and the dielectric layer 102 is further etched through the opening 103a to form the second via 122. In this step, the third insulating layer 106 continues to serve as a hard mask for the first insulating layer 104.

[0085] Furthermore, the first barrier layer 101 is etched through using an over-etching process, such as... Figure 10 As shown.

[0086] In this step, the dielectric layer 102 serves as a hard mask for the first barrier layer 101, ensuring that the etched dimensions of the first barrier layer 101 are consistent with those of the second via 122. Simultaneously, the mask layer 103 is also etched to form the first trench 121a, and the dielectric layer 102 serves as an etch stop layer for the mask layer 103.

[0087] After the etching step is completed, the first trench 121a communicates with the second via 122, exposing the conductive layer 110. In this embodiment, a plurality of second vias 122 are spaced apart along the Z-axis, the first trench 121a extends along the Z-axis, and the first trench 121a communicates with at least two second vias 122.

[0088] In this embodiment, the lateral dimension (width) of the second through hole 122 is, for example, 3240 angstroms. The total depth-to-width ratio of the first trench 121a after connecting with the second through hole 122 is the ratio of the total thickness of the first barrier layer 101 to the third insulating layer 106 to the lateral dimension of the second through hole 122, which can reach approximately 13. However, the embodiments of this application are not limited to this, and those skilled in the art can make other settings for the lateral dimension of the second through hole 122 as needed.

[0089] Furthermore, an inner liner 131 is formed on the surface of the third insulating layer 106 and the inner surface of the first trench 121a and the second through hole 122, such as Figure 11 As shown.

[0090] In this step, for example, a physical vapor deposition (PVD) process is used to form the liner 131. The material of the liner 131 is, for example, tantalum (Ta) and tantalum nitride (TaN), which is used to prevent metal elements in the subsequently formed conductive channels from diffusing to the outside of the first trench 121a and the second via 122.

[0091] Furthermore, conductive material 132 is filled inside the first trench 121a and the second through hole 122 to form a conductive channel 130, such as... Figure 12 As shown.

[0092] In this step, for example, an electrochemical plating (ECP) process is used to fill the interior of the first trench 121a and the second through-hole 122 with conductive material 132. Then, a chemical mechanical polishing (CMP) process is used to remove excess inner liner 131 and conductive material 132 from the surface of the third insulating layer 106, and the third insulating layer 106 is thinned. The conductive material 132 is, for example, copper, and the thickness of the third insulating layer 106 after thinning is 5000 angstroms.

[0093] Figures 13 to 18 The following shows cross-sectional views of the method for forming conductive channels in the second embodiment of this application at some stages. Figures 13 to 18 This processing method will be explained in further detail.

[0094] In this embodiment, the method of forming the first barrier layer 101, dielectric layer 102, mask layer 103, and insulating stack on the conductive layer 110 is largely the same as in the first embodiment. The steps are described in detail here and can be referred to [reference needed]. Figures 1 to 4 And related descriptions.

[0095] After forming the insulating stack, aluminum is further deposited on the insulating stack to form a second barrier layer 107, such as... Figure 13 As shown.

[0096] In this step, for example, a thermal aluminum deposition process is used to form the second barrier layer 107, with a process temperature of, for example, 300°C to 400°C. The aluminum on the surface of the second barrier layer 107 is oxidized at high temperature to form a dense alumina film, making the second barrier layer 107 a composite barrier layer formed of aluminum and alumina. Since the etching selectivity of the second barrier layer 107 and the insulating stack is relatively large, in subsequent etching steps, the second barrier layer 107 can serve as a hard mask for the insulating stack, while the dense alumina film can further enhance the etch resistance of the mask.

[0097] In this embodiment, the process temperature of the hot aluminum deposition process is also used to anneal the insulating stack, thereby eliminating the internal stress in the first insulating layer 104 to the third insulating layer 106, making the insulating stack flatter. This flattened insulating stack not only helps to improve the uniformity and consistency of subsequent processes, but also reduces thin film defects caused by internal stress, further improving the reliability and performance of the interconnect structure.

[0098] Further, a second photomask 20 is formed on the second barrier layer 107, and dry etching is performed on the second barrier layer 107 through the second photomask 20 to transfer the pattern on the second photomask 20 into the second barrier layer 107, such as... Figure 14 As shown.

[0099] Furthermore, using the second barrier layer 107 and the second photolithographic mask 20 as a composite hard mask, dry etching is performed on the third insulating layer 106 to form the opening of the first trench 121a in the third insulating layer 106, as shown below. Figure 15 As shown. After etching is completed, the second photomask 20 is removed, for example, by an ashing process.

[0100] Furthermore, the second insulating layer 105 is dry etched, such as... Figure 16 As shown. In this step, the second barrier layer 107 continues to serve as a hard mask for the second insulating layer 105.

[0101] Furthermore, the first insulating layer 104 and the dielectric layer 102 are dry etched, and the first barrier layer 101 is etched through using an over-etching process, such as... Figure 17 As shown. This step can be referred to. Figures 8 to 10 The relevant descriptions will not be repeated here.

[0102] Furthermore, an inner liner 131 is formed on the surface of the second barrier layer 107 and on the inner surface of the first trench 121a and the second through hole 122, such as Figure 18 As shown. This step can be referred to. Figure 11 The relevant descriptions will not be repeated here.

[0103] Furthermore, conductive material 132 is filled inside the first trench 121a and the second through hole 122 to form a structure as shown in the figure. Figure 12 The conductive channel 130 is shown.

[0104] Figures 19 to 25 The following shows cross-sectional views of the method for forming conductive channels in the third embodiment of this application at some stages. Figures 19 to 25 This processing method will be explained in further detail.

[0105] In this embodiment, the method of forming the first barrier layer 101, the dielectric layer 102, and the mask layer 103 on the conductive layer 110 is largely the same as in the first embodiment. The steps are described in detail here and can be referred to [reference needed]. Figure 1 And related descriptions.

[0106] After etching the mask layer 103 to form the opening 103a and removing the first photolithographic mask 10, a first insulating layer 104, a second insulating layer 105, and a third insulating layer 106 are sequentially deposited on the mask layer 103 to form an insulating stack structure, such as... Figure 19 As shown. In this embodiment, the polar charge q between the interfaces of adjacent insulating layers was not neutralized during the formation of the insulating stack.

[0107] Furthermore, a second photomask 20 is formed on the insulating stack, such as... Figure 19As shown. The second photolithography mask 20 exposes the opening region S1 of the first trench 121a, while covering the non-opening region S2.

[0108] Furthermore, a chemical difference is formed between the insulating stacks in the open region S1 and the non-open region S2 located in the first trench 121a, so as to change the selectivity of wet etching of the insulating stacks 104 to 106 located in the open region S1 and the non-open region S2.

[0109] In some specific embodiments, high-energy ion implantation is used to implant ions into the opening region S1 and the surface of the second photolithographic mask 20, such as... Figure 20 As shown.

[0110] In this step, ions are implanted near the upper surface of the lowest insulating layer in the insulating stack. Specifically, in the opening region S1, the implanted ions pass through the third insulating layer 106 to reach the second insulating layer 105, and stop near the interface between the first insulating layer 104 and the second insulating layer 105, thereby forming a modified portion 108 in the insulating stack, such as... Figure 21 As shown. For example, by injecting ions from groups 3 to 5 of the periodic table, such as nitrogen, silicon oxynitride is generated.

[0111] In this embodiment, the high-energy ion implantation process can also harden the surface of the second photomask 20. This hardens the surface of the second photomask 20, even forming a hard outer shell such as a carbon layer 21, further increasing its resistance to etch ions (plasma) in subsequent dry etching processes. This eliminates the need to increase the thickness of the photomask due to the increased aspect ratio, thus saving costs. Furthermore, high-energy ion implantation can also reduce or even eliminate the internal stress of the material film during deposition.

[0112] Furthermore, the modified part 108 is removed using a wet etching process, such as... Figure 22 As shown. In this step, since the implanted ions stop near the interface between the first insulating layer 104 and the second insulating layer 105, each interface in the insulating stack does not need to be dry-etched, which can reduce or even eliminate the influence of charge q at each adjacent interface.

[0113] Further, the first insulating layer 104 and the dielectric layer 102 are subjected to dry etching, such as... Figure 23 As shown. In this step, the etching of the first trench 121a stops at the surface of the mask layer 103, thus penetrating the insulating stack. The dielectric layer 102 is further etched through the opening 103a to form the second via 122. In this step, the second photolithographic mask 20, whose surface has been hardened, can continue to serve as a hard mask for the first insulating layer 104.

[0114] Furthermore, the first barrier layer 101 is etched through using an over-etching process, such as... Figure 24 As shown. The first trench 121a communicates with the second via 122, exposing the conductive layer 110. The second photomask 20 is removed after etching is complete.

[0115] Furthermore, an inner liner 131 is formed on the surface of the insulating laminate and on the inner surface of the first trench 121a and the second through hole 122, such as Figure 25 As shown. This step can be referred to. Figure 11 The relevant descriptions will not be repeated here.

[0116] Furthermore, conductive material 132 is filled inside the first trench 121a and the second through hole 122 to form a structure as shown in the figure. Figure 12 The conductive channel 130 is shown.

[0117] One of the above technical solutions has the following unexpected technical effect:

[0118] In the formation of the first trench / via, a wet etching process is employed. Because wet etching uses liquid chemical reagents, it can uniformly etch the entire surface without creating localized electric fields in specific areas, thus avoiding arcing. Alternatively, during the formation of the insulating stack, the polar charges at the interfaces between adjacent insulating layers are neutralized first. This significantly reduces or even eliminates arcing during the subsequent dry etching process for forming the first trench / via. These two methods not only improve the stability of the etching process but also reduce the formation of divergent tower-shaped defects, thereby enhancing the reliability and performance of the interconnect structure.

[0119] High-energy ion implantation is used to implant ions into the opening region to form modified parts in the insulating stack. This greatly increases the selectivity of the modified parts to the unmodified insulating stack. Therefore, wet etching can be used instead of dry etching to etch part of the insulating stack.

[0120] While modifying the insulating stack using high-energy ion implantation, high-energy ions are also implanted into the photomask above the insulating stack, causing the surface of the photomask to harden and even form a hard outer shell of carbon layer, further increasing its ability to resist etch ions (plasma) in subsequent dry etching processes. This eliminates the need to increase the thickness of the photomask due to the increase in aspect ratio, thereby saving costs.

[0121] By depositing aluminum on an insulating stack to form a second barrier layer, and then forming a photomask on the second barrier layer, the second barrier layer and the photomask together form a composite mask, which can further enhance the etch resistance of the mask and ensure that there will be no mask damage or displacement during the etching process, thereby ensuring the accuracy and consistency of the etching.

[0122] A second barrier layer is formed using a hot-aluminum deposition process, which oxidizes the upper surface of the second barrier layer to form a dense aluminum oxide film, further enhancing the mask's etch resistance. Furthermore, the process temperature of the hot-aluminum deposition process can also be used to anneal the insulating stack, thereby eliminating internal stress in the insulating stack and making it flatter. This flattened insulating stack not only helps improve the uniformity and consistency of subsequent processes but also reduces thin film defects caused by internal stress, further enhancing the reliability and performance of the interconnect structure.

[0123] As described above, these embodiments of the present application do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The scope of protection of this application should be determined by the scope defined by the claims of the present application and their equivalents.

Claims

1. A method for forming a conductive channel, characterized in that, include: An insulating layer is formed on the conductive layer; A first trench / first through-hole is formed in the insulating stack; as well as The first trench / first through-hole is filled with conductive material to form a conductive channel that contacts the conductive layer. During the formation of the first trench / first via, multiple insulating layers in the insulating stack are wet-etched. Alternatively, during the formation of the insulating stack, the polar charges at the interfaces of the multiple insulating layers in the insulating stack are neutralized, and the insulating stack is dry-etched during the formation of the first trench / first via.

2. The forming method according to claim 1, characterized in that, In the step of forming the insulating stack, the following steps are repeated: Deposit an insulating layer; The density and polarity of the freely moving charge at the interface of one of the insulating layers are detected. Based on the test results, the data system provides feedback, and an opposite polarity charge is injected to make the interface electrically neutral.

3. The forming method according to claim 1, characterized in that, The steps for forming the first trench / first through hole include: A chemical difference is created between the insulating stack located in the open region and the non-open region of the first trench / first via to change the selectivity of wet etching of the insulating stack located in the open region and the non-open region.

4. The forming method according to claim 3, characterized in that, Also includes: A second photolithographic mask is formed on the insulating stack to cover the non-opening region, while the opening region is exposed. The step of forming the chemical property difference includes: implanting ions into the opening region using a high-energy ion implantation process to form a modified portion in the insulating stack.

5. The forming method according to claim 4, characterized in that, In the step of implanting ions into the opening region using a high-energy ion implantation process, the ions are implanted near the upper surface of the lowest insulating layer in the insulating stack.

6. The forming method according to claim 5, characterized in that, After the modified portion is removed by wet etching, the bottom layer of the insulating stack is dry etched to allow the first trench / first via to penetrate the insulating stack.

7. The forming method according to claim 4, characterized in that, The surface of the second photomask is hardened using the high-energy ion implantation process described above.

8. The forming method according to claim 1, characterized in that, Before forming the first trench / first through hole, the forming method further includes: Aluminum is deposited on the insulating stack to form a second barrier layer; and A second photolithographic mask is formed on the second barrier layer, the second photolithographic mask exposing the opening region of the first trench / first via. The second barrier layer serves as a hard mask for the insulating stack in the dry etching process.

9. The forming method according to claim 8, characterized in that, Before forming the second photolithographic mask, the forming method further includes: oxidizing the upper surface of the second barrier layer to form aluminum oxide.

10. The forming method according to claim 9, characterized in that, The second barrier layer is formed using a thermal aluminum deposition process to oxidize the upper surface of the second barrier layer. The process temperature of the hot aluminum deposition process is also used to anneal the insulating laminate.

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