Semiconductor structure and manufacturing method thereof
By fabricating vias on a beveled substrate and growing epitaxial layers inside and outside the vias, the problem of high dislocation density in III-V compound semiconductor films was solved, resulting in improved crystal quality and enhanced device performance.
Patent Information
- Application Number
- CN202410584935.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-11
- Publication Date
- 2025-11-11
AI Technical Summary
In existing technologies, III-V compound semiconductor films have high dislocation densities, which leads to device performance degradation and failure.
By using a beveled substrate and a mask layer, through-holes penetrating the mask layer are fabricated on the beveled substrate, and epitaxial layers are grown inside and outside the through-holes. This causes dislocations in the epitaxial layers to deviate from the through-hole extension direction and terminate at the through-hole sidewalls, thereby reducing the dislocation density.
It effectively reduces the dislocation density of semiconductor structures, improves crystal quality, and enhances the performance of semiconductor devices.
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of science and technology, III-V compound semiconductors, with gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP) as typical representatives, have gradually become a research hotspot. They are suitable for manufacturing high-speed, high-frequency, high-power, and light-emitting electronic devices, and therefore have broad application prospects.
[0003] There are still many problems to be solved in the epitaxial growth of III-V compounds on substrates, such as lattice mismatch between materials, polar / nonpolar effects, and large differences in thermal expansion coefficients, which can easily cause dislocations in heteroepitaxial growth. The dislocations are mainly line dislocations in the
[0001] crystal orientation. When the thickness of the III-V compound semiconductor film reaches the critical value, cracks are prone to occur, causing device performance degradation and failure. Summary of the Invention
[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same, in order to solve the technical problem of a large number of dislocations in semiconductor film layers in the prior art.
[0005] According to one aspect of this application, an embodiment of this application provides a semiconductor structure. The semiconductor structure includes: a beveled substrate; a mask layer located on one side of the beveled substrate, the mask layer including a through-hole extending through the mask layer; and an epitaxial layer, at least a portion of the epitaxial layer being located within the through-hole.
[0006] According to another aspect of this application, one embodiment of this application provides a method for fabricating a semiconductor structure. The method includes: providing a beveled substrate; fabricating a mask layer on one side of the beveled substrate; etching the mask layer to form a through-hole penetrating the mask layer; and fabricating an epitaxial layer through the through-hole.
[0007] This application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a beveled substrate and a mask layer located on one side of the beveled substrate. The mask layer includes a via that penetrates the mask layer. At least a portion of the epitaxial layer is located within the via. The epitaxial layer is grown on the beveled substrate exposed by the via. Some dislocations in the epitaxial layer deviate from the extension direction of the via and terminate at the sidewall of the via, thereby reducing the dislocation density of the semiconductor structure, improving crystal quality, and enhancing the characteristics of the semiconductor device. Attached Figure Description
[0008] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application.
[0009] Figure 2 As shown Figure 1 A schematic diagram of a three-dimensional structure of a beveled substrate and a mask layer;
[0010] Figure 3 As shown Figure 1 A schematic diagram of a three-dimensional structure of another type of obliquely shaped substrate and mask layer;
[0011] Figure 4 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0012] Figure 5 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0013] Figure 6 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0014] Figure 7 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0015] Figure 8 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0016] Figure 9 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0017] Figure 10 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0018] Figure 11 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0019] Figure 12 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0020] Figure 13 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0021] Figure 14 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0022] Figures 15 to 19 This is a schematic diagram of an intermediate structure for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation
[0023] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0024] To reduce the dislocation density of semiconductor structures, this application provides the following technical solution:
[0025] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, the semiconductor structure includes: a beveled substrate 10; a mask layer 20 located on one side of the beveled substrate 10, the mask layer 20 including a through-hole 201 penetrating the mask layer; and an epitaxial layer 30, at least a portion of the epitaxial layer 30 being located within the through-hole 201.
[0026] Specifically, such as Figure 1 As shown, the mask layer 20 is located on one side of the beveled substrate 10, and the via 201 penetrates the mask layer 20. The epitaxial layer 30 is epitaxially grown from the beveled substrate 10 exposed by the via 201. Since the substrate is a material with a bevel, some dislocations in the epitaxial layer, such as dislocation A, deviate from the extension direction of the via and terminate at the sidewall of the via, thereby reducing the dislocation density of the semiconductor structure. For example, the beveled substrate is single-crystal silicon, and its surface is a (111) crystal plane with a bevel. The normal direction of the (111) crystal plane deviates from the extension direction of the via. Penetrating dislocations generally extend along the c-axis direction, that is, dislocation A extends along the normal direction of the (111) crystal plane. Therefore, as the epitaxial layer grows in the via, dislocation A gradually deviates from the extension direction of the via and terminates at the sidewall of the via, thereby reducing the dislocation density of the semiconductor structure.
[0027] It should be noted that the extension direction of the via refers to the line connecting the center points of all cross sections of the via in a direction parallel to the plane of the beveled substrate.
[0028] Optionally, Figure 2 As shown Figure 1 A schematic diagram of a three-dimensional structure of a beveled substrate and a mask layer, as shown in the figure. Figure 2 As shown, the projection shape of the through hole 201 on the beveled substrate 10 is strip-shaped; Figure 3 As shown Figure 1 Another schematic diagram of the three-dimensional structure of the obliquely shaped substrate and mask layer, as shown below. Figure 3 As shown, the projection shape of the through hole 201 on the beveled substrate 10 is square; alternatively, the projection shape of the through hole on the beveled substrate is circular, hexagonal or other shapes, and those skilled in the art can set the through hole shape according to actual needs.
[0029] In one embodiment, such as Figure 1As shown, the beveled substrate 10 includes a first exposed surface 101 exposed by a via 201. The first exposed surface 101 has a bevel angle α, which ranges from 0.1° to 20°. Specifically, appropriately increasing the bevel angle α can increase the angle at which dislocation A deviates from the via extension direction, increasing the likelihood that the dislocation terminates at the via sidewall, thereby further reducing the dislocation density of the semiconductor structure. Optionally, the bevel angle α is not greater than 20°. However, an excessively large bevel angle α (e.g., a bevel angle α greater than 30°) will cause a change in the crystal plane of the first exposed surface, resulting in a decrease in the epitaxial rate.
[0030] Optionally, the bevel angle α ranges from 0.2° to 8°. Specifically, due to the physical properties of the substrate and semiconductor material, a small bevel angle α can further improve the dislocation density. Optionally, the bevel angle α is 0.2°, 0.8°, 1°, 2°, 4°, or 8°, and those skilled in the art can select a suitable bevel angle value according to actual needs. For example, when the beveled substrate is sapphire, the bevel angle is 0.2°; when the beveled substrate is GaN or SiC, the bevel angle is 4°.
[0031] In one embodiment, when the beveled substrate 10 is monocrystalline silicon, monocrystalline germanium, or monocrystalline silicon-germanium, the first exposed surface 101 has a beveled angle α that deviates from the (111) crystal plane; or, when the beveled substrate 10 is monocrystalline silicon carbide or sapphire, the first exposed surface 101 has a beveled angle α that deviates from the (0001) crystal plane. Specifically, the (111) crystal plane of monocrystalline silicon, monocrystalline germanium, and monocrystalline silicon-germanium, as well as the (0001) crystal plane of monocrystalline silicon carbide and sapphire, are more conducive to the subsequent epitaxial growth of the epitaxial layer 30.
[0032] It should be noted that, for example, when the beveled substrate 10 is a single crystal silicon, a single crystal germanium, or a single crystal silicon-germanium, the first exposed surface 101 has a beveled angle α that deviates from the (111) crystal plane. The plane where the first exposed surface 101 is located is the plane where the beveled substrate 10 is located. The angle difference between the plane where the beveled substrate 10 is located and the (111) crystal plane is α.
[0033] In one embodiment, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the beveled substrate 10 is made of single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium. The beveled substrate 10 includes a second exposed surface 102 exposed by a via 201, and the crystal plane of the second exposed surface 102 is a (111) crystal plane. Specifically, the surface of the beveled substrate 10 is etched with alkaline solution to form a groove, and the bottom of the groove is the second exposed surface 102 with a (111) crystal plane. The (111) crystal plane is beneficial for the subsequent epitaxial growth of the epitaxial layer 30.
[0034] Optionally, such as Figure 4As shown, the plane containing the second exposed surface 102 is not parallel to the plane containing the beveled substrate 10. Specifically, the beveled substrate 10 is a single-crystal silicon, a single-crystal germanium, or a single-crystal silicon-germanium mixture. The plane containing the beveled substrate 10 has a bevel angle α that deviates from the (111) crystal plane. The crystal plane of the second exposed surface 102 is the (111) crystal plane. Therefore, the angle between the plane containing the beveled substrate 10 and the second exposed surface 102 is the bevel angle α. In other words, the plane containing the second exposed surface 102 is not parallel to the plane containing the beveled substrate 10.
[0035] In one embodiment, the cross-sectional shape of the through hole 201 in the direction perpendicular to the plane of the beveled substrate 10 is any one of a rectangle, trapezoid, parallelogram, and irregular pentagon.
[0036] Optionally, such as Figure 1 As shown, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the via 201 is rectangular, which can be formed by dry etching, with the etching direction perpendicular to the plane of the mask layer 20; as Figure 4 As shown, in the direction perpendicular to the plane containing the beveled substrate 10, the cross-sectional shape of the through-hole 201 is an irregular pentagon. This can be achieved by... Figure 1 An alkaline etching step is added to the through hole 201 shown, resulting in an irregular pentagonal cross-sectional shape.
[0037] Optionally, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5 As shown, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the through-hole 201 is trapezoidal; specifically, the cross-sectional shape of the through-hole 201 is an isosceles trapezoid; optionally, the cross-sectional shape of the through-hole 201 is a right trapezoid (not shown); optionally, due to process errors, the cross-sectional shape of the through-hole 201 is a common trapezoid with different lower base angles (not shown). Optionally, Figure 6 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 6 As shown, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the through hole 201 is an irregular pentagon. This can be achieved by... Figure 5 The through-hole 201 shown is further etched with an alkaline solution, resulting in an irregular pentagonal cross-sectional shape.
[0038] Optionally, Figure 7 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 7 As shown, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the via 201 is a parallelogram, which can be formed by dry etching, with the etching direction not perpendicular to the plane of the mask layer 20. Optionally, Figure 8 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 8 As shown, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the through hole 201 is an irregular pentagon. This can be achieved by... Figure 7 The through-hole 201 shown is further etched with an alkaline solution, resulting in an irregular pentagonal cross-sectional shape.
[0039] In one embodiment, such as Figure 1 As shown, the extension direction of the through hole 201 is perpendicular to the plane of the beveled substrate 10. Specifically, in the direction perpendicular to the plane of the beveled substrate 10, the cross-sectional shape of the through hole 201 is rectangular.
[0040] In one embodiment, such as Figure 8 As shown, the extension direction B1 of the through-hole 201 and the crystal orientation B2 of the beveled substrate 10 are located on different sides of the vertical axis z, and the vertical axis z is perpendicular to the plane where the beveled substrate 10 is located. Specifically, as Figure 8 As shown, dislocations extending along the crystal orientation B2 of the beveled substrate 10 are more likely to terminate at the sidewalls of the via, thus reducing the dislocation density of the semiconductor structure. If the via's extension direction is on the same side of the vertical axis as the crystal orientation of the beveled substrate, i.e., the dislocation extends along the via's extension direction, the probability of the dislocation terminating at the via's sidewall decreases, and the crystal quality of the semiconductor structure is not as good. Figure 8 The crystal quality of the semiconductor structure shown.
[0041] In one embodiment, such as Figure 1 As shown, the epitaxial layer 30 includes a first epitaxial layer 31 and a second epitaxial layer 32. The first epitaxial layer 31 is located within the via 201, and the second epitaxial layer 32 is located on the side of the mask layer 20 away from the beveled substrate 10. Specifically, the first epitaxial layer 31 is first formed on the via 201, and then the first epitaxial layer 31 is laterally epitaxially grown and healed on the side of the mask layer 20 away from the beveled substrate 10 to form the second epitaxial layer 32. In fact, the dislocation reduction is further achieved during the laterally growing process of the first epitaxial layer 31.
[0042] In one embodiment, Figure 9 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 9 As shown, from the angled substrate 10 towards the mask layer 20, the second epitaxial layer 32 includes an N-type semiconductor layer 302, an active layer 303, and a P-type semiconductor layer 304 stacked sequentially. Specifically, the N-type semiconductor layer 302, the active layer 303, and the P-type semiconductor layer 304 fabricated on the mask layer 20 have a low dislocation density, improving the crystal quality of the semiconductor structure and thus increasing the luminous efficiency of the final fabricated light-emitting device.
[0043] Optionally, taking the second epitaxial layer 32 as an example where the material is GaN-based, the N-type semiconductor layer 302 is N-type GaN, the active layer 303 is a multi-quantum-well layer composed of GaN and GaN-based ternary or quaternary compounds, and the P-type semiconductor layer 304 is P-type GaN. Optionally, such as... Figure 9 As shown, the first epitaxial layer 31 includes a buffer layer 301, which is used to heal the epitaxial layer into a flat surface, facilitating the subsequent fabrication of a flat semiconductor film. Optionally, the first epitaxial layer 31 includes a nucleation layer and a buffer layer. Optionally, Figure 9 The electrode structure is not shown; this semiconductor structure may be an intermediate structure for fabricating light-emitting devices.
[0044] In one embodiment, Figure 10 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 10 As shown, from the angled substrate 10 to the mask layer 20, the second epitaxial layer 32 includes a channel layer 306 and a barrier layer 307 stacked sequentially. Specifically, the channel layer 306 and barrier layer 307 fabricated on the mask layer 20 have a low dislocation density, improving the crystal quality of the semiconductor structure and thus increasing the power efficiency of the final fabricated power device.
[0045] Optionally, taking the second epitaxial layer 32 as an example where the second epitaxial layer 32 is a GaN-based material, the channel layer 306 is GaN, and the barrier layer 307 is AlGaN. Optionally, such as... Figure 10 As shown, the first epitaxial layer 31 includes a buffer layer 301, which is used to heal the epitaxial layer into a flat surface, which is beneficial for subsequent fabrication of a flat semiconductor film layer; optionally, the first epitaxial layer 31 includes a nucleation layer and a buffer layer.
[0046] In one embodiment, Figure 11 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 11 As shown, the via 201 of the mask layer 20 extends into the interior of the beveled substrate 10, and a groove is formed on the surface of the beveled substrate 10, with the bottom of the groove being a crystal plane with a beveled angle. During epitaxy, the epitaxial layer 30 first fills the groove of the beveled substrate 10, and then fills the via 201 located in the mask layer 20. Optionally, as shown... Figure 11 As shown, the through-hole 201 and the sidewall of the groove in the mask layer 20 are both perpendicular to the plane of the beveled substrate 10.
[0047] Optionally, Figure 12 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 12 As shown, when the beveled corner substrate 10 is single-crystal silicon, single-crystal germanium or single-crystal silicon-germanium, the groove formed on the surface of the beveled corner substrate 10 is further treated with alkaline solution to form a second exposed surface 102 with (111) crystal plane.
[0048] Optionally, Figure 13 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 13 As shown, the extension direction of the via 201 of the mask layer 20 is not perpendicular to the plane of the beveled substrate 10, and the penetration direction of the groove on the surface of the beveled substrate 10 is perpendicular to the plane of the beveled substrate 10. In other words, the extension direction of the via 201 of the mask layer 20 and the penetration direction of the groove on the surface of the beveled substrate 10 are not the same.
[0049] It should be noted that, as Figure 13 As shown, when the beveled corner substrate 10 is a single crystal silicon, single crystal germanium or single crystal silicon germanium, the groove formed on the surface of the beveled corner substrate 10 is further treated with alkaline solution, and a second exposed surface with a (111) crystal plane is formed at the bottom of the groove.
[0050] Optionally, Figure 14 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 14 As shown, the upward extension direction B3 of the through hole 201 and the downward penetration direction B4 of the groove on the surface of the beveled substrate 10 are located on the same side of the vertical axis z. Dislocations can be terminated by the sidewall of the through hole 201, which has a good dislocation reduction effect.
[0051] It should be noted that, as Figure 14 As shown, when the beveled corner substrate 10 is a single crystal silicon, single crystal germanium or single crystal silicon germanium, the groove formed on the surface of the beveled corner substrate 10 is further treated with alkaline solution, and a second exposed surface with a (111) crystal plane is formed at the bottom of the groove.
[0052] One embodiment of this application also provides a method for fabricating a semiconductor structure. Figures 15 to 18 This is a schematic diagram of an intermediate structure for fabricating a semiconductor structure according to an embodiment of this application, such as... Figures 15 to 18 As shown, the manufacturing method includes:
[0053] Step S1, as follows Figure 15 As shown, a beveled substrate 10 is provided. Optionally, the beveled substrate is any one of single-crystal silicon, single-crystal germanium, single-crystal silicon-germanium, single-crystal silicon carbide, and sapphire. Specifically, the beveled substrate 10 can be commercially available, or it can be a substrate with a specific crystal plane, which is then beveled to obtain a beveled angle α, the range of which is 0.1° to 20°; further, the range of which is 0.2° to 8°.
[0054] Step S2, as follows Figure 16 As shown, a mask layer 20 is fabricated on one side of the beveled substrate 10. Optionally, the material of the mask layer 20 is SiO2 or SiN. Optionally, a patterned photoresist layer 202 is fabricated above the mask layer 20.
[0055] Step S3, as follows Figure 17 As shown, using a patterned photoresist layer 202 as a mask, the mask layer 20 is etched to form a via 201 penetrating the mask layer 20. Optionally, as... Figure 18 As shown, the photoresist layer 202 is removed.
[0056] Step S4, as follows Figure 1 As shown, an epitaxial layer 30 is fabricated from the via 201. Specifically, during epitaxy, dislocation A gradually deviates from the extension direction of the via and terminates at the sidewall of the via, thereby reducing the dislocation density of the semiconductor structure and resulting in a higher quality semiconductor crystal.
[0057] Optionally, such as Figure 1 As shown, within the via 201, the first epitaxial layer 31 is first epitaxially extended. When it reaches the height of the upper surface of the mask layer 20, the first epitaxial layer 31 is laterally epitaxially extended and healed to form the second epitaxial layer 32, and finally the upper surface of the semiconductor structure is a flat structure.
[0058] In one embodiment, such as Figure 19 As shown, the beveled substrate 10 is made of single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium. Before fabricating the epitaxial layer 30, the fabrication method further includes: wet etching the beveled substrate 10 within the via 201 using an alkaline solution to form a second exposed surface 102 exposed by the via 201. The crystal plane of the second exposed surface 102 is a (111) crystal plane. Specifically, for example, due to the anisotropy of single-crystal silicon, the etching rate of single-crystal silicon varies in different crystal orientations in an alkaline solution. When single-crystal silicon is etched using KOH solution, anisotropic V-shaped etching occurs, resulting in a (111) crystal plane. The (111) crystal plane is more conducive to the epitaxial growth of epitaxial structure layers (e.g., epitaxial structure layers of III-V group compound materials).
[0059] This application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a beveled substrate and a mask layer located on one side of the beveled substrate. The mask layer includes a via that penetrates the mask layer. At least a portion of the epitaxial layer is located within the via. The epitaxial layer is grown on the beveled substrate exposed by the via. Some dislocations in the epitaxial layer deviate from the extension direction of the via and terminate at the sidewall of the via, thereby reducing the dislocation density of the semiconductor structure, improving crystal quality, and enhancing the characteristics of the semiconductor device.
[0060] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.
Claims
1. A semiconductor structure, characterized in that, include: Beveled substrate; A mask layer located on one side of the beveled substrate, the mask layer including a through-hole penetrating the mask layer; An epitaxial layer, at least a portion of which is located within the via.
2. The semiconductor structure according to claim 1, characterized in that, The beveled substrate includes a first exposed surface exposed by the via, the first exposed surface having a bevel angle ranging from 0.1° to 20°.
3. The semiconductor structure according to claim 2, characterized in that, When the beveled substrate is monocrystalline silicon, monocrystalline germanium, or monocrystalline silicon-germanium, the first exposed surface has the beveled angle deviating from the (111) crystal plane; or, When the beveled substrate is a single-crystal silicon carbide or sapphire, the first exposed surface has the beveled angle that deviates from the (0001) crystal plane.
4. The semiconductor structure according to claim 1, characterized in that, The beveled substrate is a single-crystal silicon, a single-crystal germanium, or a single-crystal silicon-germanium substrate, and the beveled substrate includes a second exposed surface exposed by the via, the crystal plane of the second exposed surface being the (111) crystal plane.
5. The semiconductor structure according to claim 4, characterized in that, The plane containing the second exposed surface is not parallel to the plane containing the beveled substrate.
6. The semiconductor structure according to claim 1, characterized in that, The extension direction of the through hole is perpendicular to the plane of the beveled substrate.
7. The semiconductor structure according to claim 1, characterized in that, The extension direction of the through hole is located on a different side of the vertical axis from the crystal orientation of the beveled substrate, and the vertical axis is perpendicular to the plane where the beveled substrate is located.
8. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer is located within the via, and the second epitaxial layer is located on the side of the mask layer away from the beveled substrate.
9. The semiconductor structure according to claim 8, characterized in that, From the direction of the beveled substrate toward the mask layer, the second epitaxial layer includes: an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked sequentially.
10. The semiconductor structure according to claim 8, characterized in that, From the direction of the beveled substrate toward the mask layer, the second epitaxial layer includes a channel layer and a barrier layer stacked sequentially.
11. A method for fabricating a semiconductor structure, characterized in that, include: Provide beveled substrates; A mask layer is fabricated on one side of the beveled substrate; The mask layer is etched to form a through-hole penetrating the mask layer; An epitaxial layer is fabricated from the aforementioned through-hole.
12. The manufacturing method according to claim 11, characterized in that, The beveled substrate is monocrystalline silicon, monocrystalline germanium, or monocrystalline silicon-germanium. Before fabricating the epitaxial layer, the fabrication method further includes: Within the via, an alkaline solution is used to wet-etch the beveled substrate to form a second exposed surface exposed by the via, the crystal plane of the second exposed surface being the (111) crystal plane.