Semiconductor structure and forming method thereof

Abstract

The semiconductor structure includes: an interposer including: a substrate; a redistribution structure (RDS) on the substrate; a passivation film on the RDS, where the passivation film includes a first etch stop layer (ESL) on the RDS and a first dielectric layer on the first ESL; a via embedded in the passivation film, where the via is electrically coupled to the conductive feature of the RDS; a bonding film on the passivation film, in which the bonding film includes a second ESL on the passivation film and a second dielectric layer on the second ESL; and a bonding pad and a first dummy bonding pad embedded in the bonding film, in which the bonding pad is electrically coupled to the via and the first dummy bonding pad is electrically isolated; and a die attached to the interposer with a die connector of the die bonded to the bond pad. The embodiment of the invention also relates to a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. To a large extent, this improvement in integration density stems from the iterative reduction in the size of the smallest components, which allows more components to be integrated into a given area.

[0003] With the growing demand for miniaturized electronic devices, there is a need for packaging technologies for smaller and more innovative semiconductor dies. An example of such packaging systems is the PoP (PoS) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is Chip-on-Wafer-on-Semiconductor (CoWoS) technology. In some embodiments, to form a CoWoS structure, multiple semiconductor chips are attached to a wafer, and a dicing process is then performed to separate the wafer into multiple interposers, each with one or more semiconductor chips attached. The interposer with attached semiconductor chips is called a Chip-on-Wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form the CoWoS structure. Another example is System-on-Chip (SoIC) technology, a three-dimensional (3D) chip-to-chip stacking technology that integrates active and passive chips into a single SoC system. SoIC platforms utilize front-end technologies and sophisticated methods from silicon wafer fabs to 3D stacked chips. So, the IC platform allows for the integration of known good dies (KGD) with different chip sizes, functions, and wafer node technologies. The resulting structure enables ultra-high density vertical stacking to achieve high performance, low power consumption, and low resistance inductance-capacitance (RLC). These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and small footprint. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, including:

[0005] An interposer layer, comprising: a substrate; a redistribution structure (RDS) located on a first side of the substrate; a passivation film located on the redistribution structure, wherein the passivation film includes a first etch stop layer (ESL) located on the redistribution structure and a first dielectric layer located on the first etch stop layer; a via embedded in the passivation film, wherein the via is electrically coupled to a conductive component of the redistribution structure; a bonding film located on the passivation film, wherein the bonding film includes a second etch stop layer located on the passivation film and a second dielectric layer located on the second etch stop layer; and bonding pads and a first pseudo bonding pad embedded in the bonding film, wherein the bonding pad is electrically coupled to the via, and the first pseudo bonding pad is electrically isolated; and

[0006] The semiconductor structure also includes a die attached to the interposer, wherein die connectors of the die are bonded to the bonding pads. Another embodiment of this disclosure provides a semiconductor structure including:

[0007] An interposer layer comprising: a substrate; a redistribution structure (RDS) located above a first side of the substrate; a passivation film located above the redistribution structure, wherein the passivation film includes a first etch stop layer (ESL) located above the redistribution structure and a first dielectric layer located above the first etch stop layer; a via extending through the passivation film and electrically coupled to the topmost conductive component of the redistribution structure; a bonding film located above the passivation film, wherein the bonding film includes a second etch stop layer located above the passivation film and a second dielectric layer located above the second etch stop layer; a bonding pad extending through the bonding film and electrically coupled to the via; and a first dummy bonding pad embedded in the bonding film;

[0008] The semiconductor structure also includes a first die and a molding material, the first die being attached to a first side of the interposer, wherein a first die connector of the first die is bonded to the bonding pad; the molding material is located above the first side of the interposer and around the first die.

[0009] Another embodiment of this disclosure provides a method for forming a semiconductor structure, the method comprising:

[0010] Forming an interposer layer includes: forming a redistribution structure (RDS) over a substrate; forming a passivation film on the redistribution structure by sequentially forming a first etch stop layer (ESL) and a first dielectric layer on the redistribution structure; forming a via extending through the passivation film and electrically coupled to the topmost conductive component of the redistribution structure; forming a bonding film on the passivation film by sequentially forming a second etch stop layer and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film.

[0011] The method further includes: attaching a die connector to the bonding pad; and forming a molding material around the die on the interlayer. Attached Figure Description

[0012] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0013] Figures 1 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E Various views of the semiconductor structure at various manufacturing stages according to embodiments are shown.

[0014] Figure 7A and Figure 7B Various views of a semiconductor structure according to another embodiment are shown.

[0015] Figure 8 A cross-sectional view of a semiconductor structure according to yet another embodiment is shown.

[0016] Figure 9 A flowchart of a method for forming a semiconductor structure in some embodiments is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Throughout the description, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials and by the same or similar methods.

[0018] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. In the discussion herein, figures with the same numbers but different letters (e.g., Figure 7A and Figure 7B The diagram shows various views of the same semiconductor structure at the same stage of manufacturing.

[0019] In some embodiments, the passivation film used as the interposer comprises only an ESL layer and a dielectric layer, which simplifies the film design and reduces manufacturing costs and processing time. Due to the reduced thickness of the passivation film, the vias formed within it have shorter lengths and larger bottom surfaces, which advantageously reduces the resistance of the vias. Furthermore, since there is only one interface between the ESL and dielectric layers within the passivation film, the risk of delamination of the passivation film from the vias is reduced.

[0020] Figures 1 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E Various views (e.g., cross-sectional views, top views) of a semiconductor structure 300 at various manufacturing stages according to an embodiment are shown. The semiconductor structure 300 may be, for example, a SOIC device. In the illustrated embodiment, the semiconductor structure 300 includes an interposer 100 and a die 200 attached to the interposer 100. Figures 1 to 5 The manufacturing process steps for forming the intermediate layer 100 are shown. Figures 6A to 6EVarious views of the semiconductor structure 300 are shown after the die 200 is attached to the interposer 100.

[0021] Figure 1 A cross-sectional view of an interposer 100 in an early stage of manufacturing is shown. The interposer 100 may be a portion of a wafer, which will later be diced to form multiple interposers 100 (e.g., multiple individual interposers 200) to which a die is attached.

[0022] Figure 1 The intermediate layer 100 includes a substrate 110, a through-hole 101, a redistribution structure (RDS) 104 formed on the upper surface of the substrate 110, and conductive pads 121 (e.g., copper pads) formed on the lower surface of the substrate 100. A passivation layer may be formed on the lower surface of the substrate 110 to cover at least a portion of the conductive pads 121. An external connector 123 (see [link to documentation]) is then formed on the conductive pads 121. Figure 6A ), to provide electrical connections to other devices.

[0023] The substrate 110 may be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, the substrate 110 may optionally be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnect functions.

[0024] In some embodiments, substrate 110 may include electronic components, such as resistors, capacitors, etc. These electronic components may be active, passive, or a combination thereof. In other embodiments, substrate 110 does not contain active or passive electronic components and includes only wires and / or vias to provide electrical connections. These and other variations are intended to be included entirely within the scope of this disclosure.

[0025] Through-hole 101 extends from the upper surface of substrate 110 to the lower surface of substrate 110 and provides electrical connection between conductive pad 121 and conductive components of RDS 104. Through-hole 101 can be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloys, doped polysilicon, combinations thereof, etc. A barrier layer can be formed between through-hole 101 and substrate 110. The barrier layer can include suitable materials such as titanium nitride, but other materials such as tantalum nitride, titanium, etc., can also be optionally used.

[0026] RDS104 is formed on the upper surface of substrate 110. RDS104 may include one or more dielectric layers 105 (e.g., silicon oxide) and conductive components 103 (e.g., wires, vias) formed in one or more dielectric layers. Figure 1In the example, RDS104 is shown as having a dielectric layer 105 and conductive components 103 (e.g., conductive pads, wires) formed in the dielectric layer 105. It should be understood that multiple dielectric layers 105 and multiple layers of conductive components may be formed in RDS104.

[0027] In some embodiments, one or more dielectric layers 105 are formed of materials such as nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. One or more dielectric layers 105 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or combinations thereof.

[0028] In some embodiments, the conductive component 103 of the RDS104 includes wires and / or vias formed of a suitable conductive material (such as copper, titanium, tungsten, aluminum, etc.). In some embodiments, the conductive component 103 is formed of an alloy, such as an aluminum-copper alloy, a titanium-aluminum-copper alloy, etc. The RDS104 can be formed by the following steps: for example, forming a dielectric layer 105, forming an opening in the dielectric layer 105 to expose the underlying conductive component, forming a seed layer above the dielectric layer 105 and in the opening, forming a patterned photoresist with a designed pattern above the seed layer, plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and above the seed layer, and removing the photoresist and portions of the seed layer on which no conductive material is formed. The above process can be repeated until a target number of dielectric layers 105 and conductive components 103 are formed.

[0029] Next, in Figure 2 In this embodiment, a passivation film 108 (also referred to as a passivation structure) is formed on RDS104. In the illustrated embodiment, the passivation film 108 includes an etch stop layer (ESL) 107 and a dielectric layer 109 located on the ESL 107.

[0030] In some embodiments, ESL 107 is formed of a suitable material, such as silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), silicon carbonitride (e.g., SiCN), silicon oxynitride (SiON), etc., and can be formed by a suitable formation method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc. In some embodiments, ESL 107 serves to protect the underlying structure and provide control points for subsequent etching processes. The thickness T1 of ESL 107 can be between about 300 angstroms and about 5000 angstroms, such as between 1000 angstroms and 5000 angstroms or between 3000 angstroms and about 5000 angstroms. In some embodiments, the thickness T1 of ESL 107 is greater than the typical thickness of ESL in a passivation film without an interposer layer in the structure of this disclosure, which can be about 700 angstroms or less. As will be discussed in more detail below, the increased thickness T1 of ESL 107 reliably protects the underlying conductive parts (e.g., the topmost conductive part 103 of RDS 104) from the effects of subsequent etching processes and provides a control point for stopping subsequent etching processes.

[0031] The dielectric layer 109 is formed on ESL 107 using a suitable material such as silicon oxide (e.g., SiO), but other suitable materials may also be used. Suitable formation methods (such as PVD, CVD, PECVD) can be performed to form the dielectric layer 109. In the illustrated embodiment, the thickness T1 of ESL 107 is not less than one-seventh of the thickness T2 of dielectric layer 109 and not greater than the thickness T2 (e.g., T2 / 7 ≤ T1 ≤ T2). For example, the thickness T1 can be between about 12.5% ​​and about 50% of the thickness T of passivation film 108 (e.g., T = T1 + T2). As an example, the thickness T of passivation film 108 can be between about 0.1 μm and about 3 μm. The lower boundary of thickness T (e.g., 0.1 μm) ensures sufficient electrical isolation between the subsequently formed pseudo-bonding pad 117B and the underlying conductive component 103, and the upper boundary of thickness T (e.g., 3 μm) ensures low resistance for the subsequently formed via 115. More details are discussed below.

[0032] The disclosed thickness range T1 (e.g., T2 / 7 ≤ T1 ≤ T2) ensures that the passivation film 108 functions as designed and provides sufficient protection for the underlying structure (e.g., conductive component 103). Note that in the illustrated embodiment, the passivation film 108 comprises only a single layer of ESL 107 and a single layer of dielectric layer 109, while a typical passivation film for an interposer may comprise multiple ESLs and multiple dielectric layers interleaved with each other. In some embodiments, in the subsequent etching process that forms the via opening (for forming via 115), the ESL 107 (e.g., a carbon- or nitride-containing material) is used to control the stopping point of the etching process. For example, when the etching process reaches ESL 107, carbon or nitrogen can be detected using an optical emission spectrometer (OES) and a signal can be issued that the etching process should end soon, and in response, the etching process can be controlled / adjusted accordingly to stop at the correct time. If the thickness T1 is too small (e.g., less than T2 / 7), etching through ESL107 may occur before OES can reliably detect carbon or nitrogen, thus not providing sufficient buffer time to stop the etching process and not providing adequate protection for the underlying structure. Conversely, if the thickness T1 is too large (e.g., greater than T2), etching through ESL 107 may take too long, thus increasing processing time and cost.

[0033] Next, in Figure 3 In this process, a via 115 is formed in the passivation film 108. In some embodiments, the via 115 is formed of a suitable conductive material, such as copper, aluminum-copper alloy, titanium-aluminum-copper alloy, etc. To form the via 115, a via opening is formed to extend through the passivation film 108 to expose the underlying conductive component 103 (e.g., the topmost conductive pattern of RDS 104), and then a conductive material is formed in the via opening. Next, a planarization process (such as chemical mechanical planarization (CMP)) is performed to remove excess portions of the conductive material from the upper surface of the passivation film 108 and to achieve a coplanar upper surface between the passivation film 108 and the remaining portion of the conductive material. The remaining portion of the conductive material in the via opening forms the via 115.

[0034] The via opening can be formed by an etching process comprising two etching steps. For example, as a first etching step, a first plasma etching process can be performed using a first gas source to etch through the dielectric layer 109 and expose ESL 107. Next, as a second etching step, a second plasma etching process can be performed using a second gas source to etch through ESL 107. The first gas source may include, for example, C4F6, to selectively etch the dielectric layer 109. The second gas source may include, for example, CF4, CHF3, and O2, to selectively etch ESL 107. As discussed above, when the etching process reaches ESL 107, OES can be used to detect carbon or nitrogen elements and accordingly control / adjust the etching process to stop at the correct time to avoid damage to the underlying conductive component 103.

[0035] Advantages are achieved through the structure of the passivation film 108. For example, the passivation film 108 comprises only one ESL 107 and one dielectric layer 109, thus having only one interface between the ESL 107 and the dielectric layer 109. As a result, the via 115 extends through only one interface within the passivation film 108 (e.g., between the ESL 107 and the dielectric layer 109). In some embodiments, the more interfaces of the passivation film 108 the via 115 must extend through, the higher the risk of delamination of the passivation film 108. Since the disclosed passivation film 108 has only one interface, the risk of delamination of the passivation film 108 is significantly reduced. Furthermore, due to the fewer layers in the passivation film 108, its thickness T is reduced. Therefore, the height H of the via 115 is reduced. In some embodiments, the height H of the via 115 is between about 0.1 μm and about 3 μm, which can be 75% or more smaller than the height of a via formed in a passivation film having multiple ESLs and multiple dielectric layers. Because via 115 typically has tapered sidewalls (due to the characteristics of the etching process used to form the via opening), a shorter via 115 has a larger bottom surface area for contacting the underlying conductive component 103. The larger bottom surface area and shorter height of via 115 advantageously reduce the resistance of via 115.

[0036] Next, in Figure 4 In this embodiment, a bonding film 112 is formed on the passivation film 108. In the illustrated embodiment, the bonding film 112 includes an ESL 111 and a dielectric layer 113. The ESL 111 and the dielectric layer 113 may be the same as or similar to the ESL 107 and dielectric layer 109 of the passivation film 108, respectively, and may be formed using the same materials and the same formation method, therefore details will not be repeated.

[0037] Next, in Figure 5In this process, bonding pads 117 (e.g., 117A and 117B) are formed in the bonding film 112. In some embodiments, the bonding pads 117 are formed of a suitable conductive material, such as copper, aluminum-copper alloy, titanium-aluminum-copper alloy, etc. To form the bonding pad 117A, a pad opening is formed to extend through the bonding film 112 to expose the underlying via 115. A conductive material is then formed in the pad opening, and a planarization process such as CMP is subsequently performed to remove excess conductive material from the upper surface of the bonding film 112 and to achieve a coplanar upper surface between the bonding film 112 and the remaining conductive material. The remaining conductive material in the pad opening forms the bonding pad 117A.

[0038] It is worth noting that, in Figure 5 In this embodiment, dummy bonding pads 117B are also formed in the bonding film 112. In the illustrated embodiment, dummy bonding pads 117B are electrically isolated. In some embodiments, dummy bonding pads 117B are formed in the bonding film 112 to achieve a substantially uniform metal density in the bonding film 12, thereby avoiding or reducing surface irregularities (e.g., depressions) of the bonding film 112 during planarization processes (e.g., CMP). Except for the electrical isolation of dummy bonding pads 117B (e.g., not electrically coupled to via 115), dummy bonding pads 117B can be formed simultaneously with bonding pads 117A using the same processing steps. Dummy bonding pads 117B may or may not have the same shape as bonding pads 117A, details of which are discussed below.

[0039] After forming the bonding pad 117 Figure 5 The structure shown illustrates the interposer layer 100 of this disclosure. The interposer layer 100 is used to form... Figure 6A The semiconductor structure 300.

[0040] Next, in Figure 6A In this process, die 200 is attached (e.g., bonded) to interposer 100. Next, molding material 205 is formed around die 200 on interposer 100. In some embodiments, multiple semiconductor structures 300 are formed on the same wafer, and a dicing process can then be performed along the dicing region shown by dashed line 220 to form individual (e.g., separate) semiconductor structures 300.

[0041] Figure 6A A die 200 in the semiconductor structure 300 is shown as a non-limiting example. It should be understood that any suitable number of dies can be attached to the interposer 100. For example, multiple dies can be arranged laterally and / or vertically relative to each other to form a 3D stacked die in the semiconductor structure 300.

[0042] In some embodiments, die 200 includes a substrate 210, electronic components (e.g., transistors, resistors, capacitors, diodes, etc.) formed in / on the substrate 210, and interconnect structures above the substrate 210 connecting the electronic components to form functional circuitry of die 200. Die 200 also includes conductive posts 201A (also referred to as die connectors 201A), which provide electrical connections to circuitry of die 200. Furthermore, die 200 may include pseudo-conductive posts 201B (also referred to as pseudo-die connectors 201B) for bonding to pseudo-bonding pads 117B of interposer 100. In some embodiments, pseudo-conductive posts 201B are electrically isolated. Conductive posts 201A and pseudo-conductive posts 201B may be collectively referred to as conductive post 201 (or die connector 201).

[0043] The substrate 210 of die 200 can be a doped or undoped semiconductor substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0044] The electronic components of die 200 include a wide variety of active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors), etc. The electronic components of die 200 can be formed within or on the substrate 210 of die 200 using any suitable method. The interconnect structure of die 200 includes one or more metallization layers (e.g., copper layers) formed in one or more dielectric layers and is used to connect the various electronic components to form functional circuits.

[0045] One or more passivation layers can be formed over the interconnect structure of die 200 to provide a degree of protection for the structure of die 200. The passivation layers can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, etc. The passivation layers can be formed using processes such as chemical vapor deposition (CVD), but any suitable process can be used.

[0046] Conductive pads (not shown) may be formed over the passivation layer and may extend through the passivation layer to make electrical contact with the interconnect structure of the die 200. The conductive pads may include aluminum, but other materials such as copper may be used optionally.

[0047] Die connectors 201 of die 200 are formed on conductive pads to provide conductive areas for electrical connections to the circuitry of die 200. Die connectors 201 may be copper pillars, contact bumps such as microbumps, etc., and may comprise materials such as copper, tin, silver, or other suitable materials. A dielectric layer 203, such as an oxide layer (e.g., SiO), may be formed around die connectors 201.

[0048] In some embodiments, die connector 201 of die 200 is bonded to a corresponding bonding pad 117 of interposer 100 via a direct bonding process without the use of adhesive materials (e.g., solder materials), such as through direct metal-to-metal bonding and direct dielectric-to-dielectric bonding. The direct bonding process may include cleaning the surfaces of die 200 and interposer 100, aligning die connector 201 with the corresponding bonding pad 117, and pressing die connector 201 and bonding pad 117 together. Heat treatment may be performed to facilitate directional bonding. The resulting bonding between die 200 and interposer 100 includes dielectric-to-dielectric bonding (e.g., dielectric layer 203 to dielectric layer 113) and metal-to-metal bonding (e.g., die connector 201 to bonding pad 117).

[0049] Next, a molding material 205 is formed around the die 200 on the interposer 100. As an example, the molding material 205 may include an epoxy resin, an organic polymer, a polymer with or without silica-based fillers or glass fillers, or other materials. In some embodiments, the molding material 205 includes a liquid molding compound (LMC), which is a gel-like liquid when applied. The molding material 205 may also comprise a liquid or a solid when applied. Optionally, the molding material 205 may include other insulating and / or encapsulating materials. In some embodiments, a wafer-level molding process is used to apply the molding material 205. The molding material 205 may be molded using, for example, compression molding, transfer molding, molded underfill (MUF), or other methods.

[0050] Next, in some embodiments, a curing process is used to cure the molding material 205. The curing process may include heating the molding material 205 to a predetermined temperature and maintaining it for a predetermined time using an annealing process or other heating process. The curing process may also include ultraviolet (UV) exposure, infrared (IR) energy exposure, combinations thereof, or combinations thereof with heating processes. Optionally, other methods may be used to cure the molding material 205. In some embodiments, a curing process is not included.

[0051] After the molding material 205 is formed, a planarization process such as CMP can be performed to achieve a flat upper surface of the molding material 205. In the illustrated embodiment, the molding material 205 extends further from the interposer 100 than the die 200, thus covering the upper surface of the die 200. For example, due to cutting, the sidewalls of the molding material 205 are aligned with the corresponding sidewalls of the interposer 100 along the same vertical line.

[0052] like Figure 6A As shown, an external connector 123 (also referred to as a conductive bump) is formed on the conductive pad 121. The external connector 123 can be any suitable type of external contact, such as microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel plating, electroless palladium plating (ENEPI G) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb, combinations thereof, etc. The external connector 123 can be formed on the conductive pad 121 prior to the dicing process. For example, after forming the molding material 205, the wafer including the semiconductor structure 300 is flipped over, and the side of the wafer with the molding material 205 is attached to the dicing strip. Next, the external connector 123 is formed on the conductive pad 121 using a suitable forming method. A dicing process is then performed to separate the wafer into individual semiconductor structures 300.

[0053] Figure 6B It shows along Figure 6A Example cross-sectional view of semiconductor structure 300 with cross-section AA in the figure. Figure 6A Corresponding to along Figure 6B A cross-sectional view of the cross section BB in the diagram.

[0054] Figure 6B The sidewalls of dielectric layer 113 are shown (completely overlapping with the sidewalls of interposer layer 100). Figure 6B The sidewall of the core 200, which is not visible in the cross-section AA, is shown in dashed lines. Figure 6B The diagram also shows a cross-section of bonding pads 117 (e.g., 117A and 117B), which have the same shape as the top view of bonding pads 117.

[0055] exist Figure 6B In the example, bonding pad 117A and pseudo bonding pad 117B have the same shape (e.g., circular). Figure 6BThe diagram shows two rows of bonding pads 117, each row comprising two bonding pads 117A and one pseudo bonding pad 117B (e.g., labeled 117B1 in the top row and 117B2 in the bottom row). In some embodiments, all die connectors 201 of the die 200 (e.g., 201A and 201B) have the same shape (e.g., in a cross-sectional or top view) that matches the shape of the bonding pads 117A. Because in Figure 6B The center bonding pad 117A and the pseudo bonding pad 117B have the same shape, therefore in Figure 6B In the example, die connectors 201A and 201B, bonding pad 117A, and pseudo bonding pad 117B all have the same shape. Note that... Figure 6B (as well as Figure 6C , Figure 6D and Figure 6E The number, shape, size, and location of the bonding pads 117 (e.g., 117A, 117B1, 117B2) shown in the diagram are non-limiting examples. Other numbers, shapes, sizes, and locations of the bonding pads 117 are also possible and are fully intended to be included within the scope of this disclosure.

[0056] Figure 6C It shows along Figure 6A Another example cross-sectional view of the semiconductor structure 300 with cross-section AA in the figure. Figure 6C In the example, pseudo-bonding pad 117B1 has a first shape (e.g., pentagon), pseudo-bonding pad 117B2 has a second shape (e.g., hexagon), and bonding pad 117A has a third shape (e.g., circle), wherein the first shape, the second shape, and the third shape are different shapes. Figure 6C A cross-section of the dummy die connector 201B coupled to the dummy bonding pads 117B (e.g., 117B1 and 117B2) is also shown in dashed lines. Figure 6C As shown, the dummy die connector 201B and the bonding pad 117A have the same shape (e.g., circular). When aligned and bonded together, in a top view (or a plan view projecting the die connector 201 and the bonding pad 117A onto the same plane), each dummy die connector 201B is positioned within the boundary (e.g., sidewall) of the corresponding dummy bonding pad 117B (e.g., 117B1 or 117B2). Specifically, in Figure 6C In this configuration, the center of each pseudo die connector 201B coincides with (e.g., overlaps) the center of the corresponding pseudo bonding pad 117B, and the sidewall of each pseudo die connector 201B is spaced apart from (e.g., does not contact) the sidewall of the corresponding pseudo bonding pad 117B. Figure 6CThe cross-section of the die connector 201A coupled to the bonding pad 117A is not shown because the sidewall of each die connector 201A overlaps (e.g., completely overlaps) with the sidewall of the corresponding bonding pad 117A.

[0057] Allowing the dummy bonding pads 117B to have different shapes and sizes can offer advantages. For example, dummy bonding pads 117B with different shapes can serve as reference points for pick-and-place tools equipped with computer vision technology to identify the orientation / position of the bonding pads 117, allowing the die 200 (and die connector 201) to be oriented in the correct direction for bonding with the bonding pads 117 via the pick-and-place tools. Different shapes of the dummy bonding pads 117B can also help human operators reduce errors during testing or troubleshooting, especially when the die 200 has a symmetrical shape and the position of the die connector 201 remains the same even if the die 200 is rotated, for example, by 90 degrees or 180 degrees. Furthermore, by not restricting the size and shape of the pseudo bonding pad 117B to match the size and shape of the pseudo die connector 201B, the designer of the interposer 100 has greater freedom in choosing the size and shape of the pseudo bonding pad 117B, making it easier to achieve a substantially uniform metal density on the surface of the interposer 100, which in turn helps to reduce or avoid surface unevenness (e.g., depressions).

[0058] Figure 6D It shows along Figure 6A Another example cross-sectional view of the semiconductor structure 300 with cross-section AA in the figure. Figure 6D and Figure 6C Similar, but with some differences. For example, in a top view (or plan view), the circular shape of the dummy die connector 201B is inscribed within the shape (e.g., hexagonal or pentagonal) of the dummy bonding pad 117B. In other words, the center of the circle coincides with (e.g., overlaps with) the center of the hexagon (or pentagon), and the circle contacts each side of the hexagon (or pentagon) at a single point without crossing it.

[0059] Figure 6E It shows along Figure 6A Another example cross-sectional view of the semiconductor structure 300 with cross-section AA in the figure. Figure 6EIn this design, dummy bonding pads 117B (e.g., 117B1 and 117B2) have a first shape (e.g., cross-shaped), and bonding pads 117A have a second shape (e.g., circular). The center of each dummy die connector 201B coincides with (e.g., overlaps with) the center of the corresponding dummy bonding pad 117B. It is noteworthy that although dummy bonding pads 117B1 and 117B2 have the same shape, there is rotation between their shapes. For example, the two axes L1 and L2 of the cross shape of dummy bonding pad 117B2 are respectively aligned with... Figure 6E The vertical and horizontal directions of the pseudo-bond pad 117B1 are aligned, and therefore aligned with the row and column directions of the array of bonding pads 117A. The two axes L1 and L2 of the cross-shaped pseudo-bond pad 117B1 rotate relative to the two axes L1 and L2 of the pseudo-bond pad 117B2, and therefore are not aligned with the row and column directions of the array of bonding pads 117A. Therefore, the angle between the cross-shaped axis L1 (or L2) of the pseudo-bond pad 117B1 and the row (or column) direction of the array of bonding pads 117B1 can be used to distinguish pseudo-bond pads 117B1 and 117B2, and the positions of pseudo-bond pads 117B1 and 117B2 can be used as reference points for a pick-and-place tool equipped with computer vision technology to properly rotate the die 200 for bonding.

[0060] Figure 7A A cross-sectional view of a semiconductor structure 300A in another embodiment is shown. Semiconductor structure 300A is similar to semiconductor structure 300, but each pseudo-bonding pad 117B of semiconductor structure 300A includes discrete portions of conductive material, rather than a single continuous volume of conductive material. Furthermore, in Figure 7A In the example, die 200 does not have a dummy die connector 201B that is bonded to the dummy bonding pad 117B. Instead, the upper surface of the dummy bonding pad 117B is in contact with the dielectric layer 203 of die 200.

[0061] Figure 7B It shows along Figure 7A A cross-sectional view of semiconductor structure 300A is shown in section AA. For simplicity, only a portion of semiconductor structure 300A, including pseudo-bonding pads 117B1 and 117B2, is shown. Figure 7B In the example, the pseudo-bond pad 117B1 (or 117B2) is similar to Figure 6CThe pseudo-bonding pads 117B1 (or 117B2) are formed by removing segments of conductive material and replacing them with the material of the bonding film 112, and the remaining segments of the pseudo-bonding pads 117B1 (or 117B2) form discrete portions of the pseudo-bonding pads 117B1 (or 117B2). Note that the outer boundaries of the discrete portions of the pseudo-bonding pads 117B1 and 117B2 still have pentagonal and hexagonal shapes, respectively. Pad openings with discrete opening portions can be formed in the bonding film 112, and the discrete portions of each pad opening can be filled with conductive material. Figure 7A and Figure 7B The pseudo-bonding pads 117B (e.g., 117B1 and 117B2).

[0062] In semiconductor structure 300A, the die 200 does not need to form a dummy die connector 201B, thus simplifying production and saving costs. In addition, the portion of dielectric layer 113 disposed between discrete portions of the dummy bonding pad 117B can form a direct dielectric-to-dielectric bond with dielectric layer 203 of die 200, thus improving the bonding strength between die 200 and interposer 100.

[0063] Figure 8 A cross-sectional view of a semiconductor structure 300B in yet another embodiment is shown. Semiconductor structure 300B is similar to semiconductor structure 300, but has more vertically stacked dies. For example, a first die 200A is bonded to an interposer 100, and a second die 200B is bonded to the upper surface of the first die 200A.

[0064] The first die 200A is similar to die 200, but an additional die connector 201 is formed on the upper surface of the first die 200A away from the interposer 100. Furthermore, a substrate via (TSV) 207 is formed in the first die 200A to electrically couple the die connector 201 on the upper and lower surfaces of the first die 200A. In the illustrated embodiment, a dummy die connector 201B is formed on the lower surface of the first die 200A for bonding to a dummy bonding pad 117B of the interposer 100, and the dummy die connector 201B is not formed on the upper surface of the first die 200A.

[0065] The second die 200B is similar to die 200, but does not form a pseudo-die connector 201B. The die connector 201 of the second die 200B is engaged with the corresponding die connector 201 at the upper surface of the first die 200A. Molding material 205 seals the first die 200A and the second die 200B.

[0066] The embodiments offer advantages. For example, the disclosed passivation film 108 for the interposer 100 comprises only an ESL layer 107 and a dielectric layer 109, which simplifies the film design and reduces manufacturing costs and processing time. Furthermore, due to the reduced thickness of the passivation film 108, the vias 115 formed in the passivation film 108 have shorter lengths and larger bottom surfaces, which reduces the resistance of the vias 115. Additionally, the disclosed passivation film 108 has only one interface between the ESL and dielectric layers within the passivation film 108, which further reduces the risk of delamination of the passivation film 108 from the vias 115. Since the interposer 100 is used to form the semiconductor structure 300 (or 300A, 300B), the passivation film 108 undergoes subsequent high-temperature processes, such as bonding processes for the die 200 and molding processes for forming the molding material 205. High-temperature processing and a mismatch in the coefficient of thermal expansion (CTE) between the molding material 205 and the interposer 100 can induce high stress in the passivation film 108, potentially leading to delamination of the passivation film 108. Delamination of the passivation film 108 can cause device failure in the semiconductor device 300 (or 300A, 300B). The disclosed structure for the passivation film 108 reduces the risk of delamination, thereby decreasing device failure in the semiconductor structure 300 (or 300A, 300B) and improving production yield.

[0067] Figure 9 A flowchart of a method 1000 for forming a semiconductor structure in some embodiments is shown. It should be understood that... Figure 9 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 9 The steps shown.

[0068] refer to Figure 9 At frame 1010, an interposer is formed, comprising: forming a redistribution structure (RDS) over a substrate; forming a passivation film on the RDS by sequentially forming a first etch stop layer (ESL) and a first dielectric layer on the RDS; forming a via extending through the passivation film and electrically coupled to the topmost conductive component of the RDS; forming a bonding film on the passivation film by sequentially forming a second ESL and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film. At frame 1020, a die connector of the die is bonded to the bonding pad. At frame 1030, a molding material is formed around the die on the interposer.

[0069] According to an embodiment, the semiconductor structure includes: an interposer, wherein the interposer includes: a substrate; a redistribution structure (RDS) located on a first side of the substrate; a passivation film located on the RDS, wherein the passivation film includes a first etch stop layer (ESL) located on the RDS and a first dielectric layer located on the first ESL; a via embedded in the passivation film, wherein the via is electrically coupled to a conductive component of the RDS; a bonding film located on the passivation film, wherein the bonding film includes a second ESL located on the passivation film and a second dielectric layer located on the second ESL; and bonding pads and a first dummy bonding pad embedded in the bonding film, wherein the bonding pad is electrically coupled to the via, and the first dummy bonding pad is electrically isolated. The semiconductor structure also includes a die attached to the interposer, wherein die connectors of the die are bonded to the bonding pads. In an embodiment, the thickness of the passivation film is equal to the sum of the thickness of the first ESL and the thickness of the first dielectric layer. In an embodiment, the thickness of the bonding film is equal to the sum of the thickness of the second ESL and the thickness of the second dielectric layer. In an embodiment, the first ESL and the second ESL are made of the same material, wherein the first dielectric layer and the second dielectric layer are made of the same material. In an embodiment, the first ESL and the second ESL are silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, and wherein the first dielectric layer and the second dielectric layer are silicon oxide. In an embodiment, a first dummy die connector of the die is bonded to a first dummy bonding pad, wherein the first dummy die connector is electrically isolated. In an embodiment, in a top view, the bonding pad and the first dummy bonding pad have different shapes. In an embodiment, the interposer further includes a second dummy bonding pad embedded in the bonding film, wherein in a top view, each of the bonding pad, the first dummy bonding pad, and the second dummy bonding pad has a different shape. In an embodiment, a second dummy die connector of the die is bonded to a second dummy bonding pad, wherein in a top view, the first dummy die connector, the second dummy die connector, and the die connector have the same shape as the bonding pad. In an embodiment, the upper surface of the via is flush with the upper surface of the passivation film away from the substrate, and the lower surface of the via is flush with the lower surface of the passivation film facing the substrate. In one embodiment, the upper surface of the bonding pad is flush with the upper surface of the bonding film away from the substrate, and the lower surface of the bonding pad is flush with the lower surface of the bonding film facing the substrate.

[0070] According to an embodiment, the semiconductor structure includes an interposer comprising: a substrate; a redistribution structure (RDS) located above a first side of the substrate; a passivation film located above the RDS, wherein the passivation film includes a first etch stop layer (ESL) located above the RDS and a first dielectric layer located above the first ESL; a via extending through the passivation film and electrically coupled to a topmost conductive component of the RDS; a bonding film located above the passivation film, wherein the bonding film includes a second ESL located above the passivation film and a second dielectric layer located above the second ESL; a bonding pad extending through the bonding film and electrically coupled to the via; and a first dummy bonding pad embedded in the bonding film. The semiconductor structure further includes: a first die attached to a first side of the interposer, wherein a first die connector of the first die is bonded to the bonding pad; and a molding material located above the first side of the interposer and around the first die. In an embodiment, the sum of a first thickness of the first ESL and a second thickness of the first dielectric layer is the same as a third thickness of the passivation film. In an embodiment, the first dummy die connector of the first die is bonded to the first dummy bonding pad. In an embodiment, in a top view, the bonding pad and the first dummy bonding pad have different shapes, wherein the interposer layer further includes a second dummy bonding pad embedded in the bonding film, wherein in a top view, the first dummy bonding pad and the second dummy bonding pad have different shapes, wherein a second dummy die connector of the first die is bonded to the second dummy bonding pad. In an embodiment, the first die connector and the first dummy die connector are located on a first side of the first die, wherein the first die also includes a second die connector located on a second opposite side of the first die, and includes a substrate via (TSV) electrically coupling the first die connector and the second die connector, wherein the semiconductor structure also includes a second die attached to the second opposite side of the first die, wherein a third die connector of the second die is bonded to the second die connector of the first die.

[0071] According to an embodiment, a method of forming a semiconductor structure includes: forming an interposer, including: forming a redistribution structure (RDS) over a substrate; forming a passivation film on the RDS by sequentially forming a first etch stop layer (ESL) and a first dielectric layer on the RDS; forming a via extending through the passivation film and electrically coupled to a topmost conductive component of the RDS; forming a bonding film on the passivation film by sequentially forming a second ESL and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film. The method further includes: bonding a die connector of a die to the bonding pad; and forming a molding material around the die on the interposer. In an embodiment, the method further includes bonding a dummy die connector of the die to the first dummy bonding pad. In an embodiment, in a top view, the bonding pad and the first dummy bonding pad are formed with different shapes. In one embodiment, forming the interposer layer further includes forming a second pseudo-bonding pad in the bonding film, wherein, in a top view, the first pseudo-bonding pad and the second pseudo-bonding pad are formed to have different shapes.

[0072] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: Intermediary layer, wherein the intermediary layer includes: Substrate; A redistribution structure (RDS) is located on a first side of the substrate; A passivation film is located on the redistribution structure, wherein the passivation film includes a first etch stop layer (ESL) located on the redistribution structure and a first dielectric layer located on the first etch stop layer; A via is embedded in the passivation film, wherein the via is electrically coupled to a conductive component of the redistribution structure; A bonding film is located on the passivation film, wherein the bonding film includes a second etch stop layer located on the passivation film and a second dielectric layer located on the second etch stop layer; and A bonding pad and a first dummy bonding pad are embedded in the bonding film, wherein the bonding pad is electrically coupled to the via, and the first dummy bonding pad is electrically isolated; and A die is attached to the interposer layer, wherein the die connector of the die is engaged with the bonding pad.

2. The semiconductor structure according to claim 1, wherein, The thickness of the passivation film is equal to the sum of the thickness of the first etch stop layer and the thickness of the first dielectric layer.

3. The semiconductor structure according to claim 2, wherein, The thickness of the bonding film is equal to the sum of the thickness of the second etch stop layer and the thickness of the second dielectric layer.

4. The semiconductor structure according to claim 2, wherein, The first etch stop layer and the second etch stop layer are made of the same material, and the first dielectric layer and the second dielectric layer are made of the same material.

5. The semiconductor structure according to claim 4, wherein, The first etch stop layer and the second etch stop layer are silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride, and wherein the first dielectric layer and the second dielectric layer are silicon oxide.

6. The semiconductor structure according to claim 2, wherein, The first pseudo die connector of the die is bonded to the first pseudo bonding pad, wherein the first pseudo die connector is electrically isolated.

7. The semiconductor structure according to claim 6, wherein, In the top view, the bonding pad and the first pseudo bonding pad have different shapes.

8. The semiconductor structure according to claim 7, wherein, The interposer layer further includes a second pseudo-bonding pad embedded in the bonding film, wherein, in the top view, each of the bonding pad, the first pseudo-bonding pad, and the second pseudo-bonding pad has a different shape.

9. A semiconductor structure, comprising: The intermediary layer includes: Substrate; A redistribution structure (RDS) is located above the first side of the substrate; A passivation film is located above the redistribution structure, wherein the passivation film includes a first etch stop layer (ESL) located above the redistribution structure and a first dielectric layer located above the first etch stop layer; A via extends through the passivation film and is electrically coupled to the topmost conductive component of the redistribution structure; A bonding film is located above the passivation film, wherein the bonding film includes a second etch stop layer located above the passivation film and a second dielectric layer located above the second etch stop layer; The bonding pads extend through the bonding film and are electrically coupled to the vias; and The first pseudo-bonding pad is embedded in the bonding film; A first die is attached to a first side of the interposer layer, wherein a first die connector of the first die is engaged with the bonding pad; and Molded material is located above the first side of the intermediate layer and around the first die.

10. A method for forming a semiconductor structure, the method comprising: The intermediary layer is formed, including: A redistribution structure (RDS) is formed above the substrate; A passivation film is formed on the redistribution structure by sequentially forming a first etch stop layer (ESL) and a first dielectric layer on the redistribution structure. A via is formed, the via extending through the passivation film and electrically coupled to the topmost conductive component of the redistribution structure; A bonding film is formed on the passivation film by sequentially forming a second etch stop layer and a second dielectric layer on the passivation film. Forming bonding pads that extend through the bonding film and are electrically coupled to the vias; and A first pseudo-bonding pad is formed in the bonding film; The die connector is bonded to the bonding pad; and A molding material is formed around the core on the intermediate layer.

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