Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductors, and aims to reduce the capacitance value of a parasitic capacitor between two adjacent conductive structures, reduce capacitive coupling between the two adjacent conductive structures and improve the reliability of the semiconductor structure. Signal delay of the conductive structures caused by parasitic capacitance between two adjacent conductive structures is avoided, and the performance of the semiconductor structure is improved. The semiconductor structure comprises a plurality of conductive structures, a plurality of dielectric parts and a first insulating layer which are arranged at intervals. And each medium part is positioned on one side of one conductive structure. The first insulating layer is located on the sides, away from the conductive structure, of the multiple dielectric parts and located in the area between every two adjacent dielectric parts. And air gap structures are formed between the two adjacent conductive structures and between the two adjacent dielectric parts located on one side of the two adjacent conductive structures. The semiconductor structure can be applied to a memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its preparation method, a memory system, and an electronic device. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, and the memory density for planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture comprises a memory array layer and a peripheral device layer that facilitates the operation of the memory array layer.

[0004] It should be noted that the information disclosed in the background section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] On one hand, a semiconductor structure is provided, including a plurality of conductive structures, a plurality of dielectric portions, and a first insulating layer spaced apart. Each of the dielectric portions is located on one side of one of the conductive structures. The first insulating layer is located on the side of the plurality of dielectric portions away from the conductive structures and is located in the region between two adjacent dielectric portions. An air gap structure is formed between two adjacent conductive structures and between two adjacent dielectric portions located on one side of two adjacent conductive structures, and the first insulating layer defines the boundary of the air gap structure near the end of the first insulating layer.

[0006] The semiconductor structure provided by the above embodiments of this disclosure, by providing multiple dielectric portions within the semiconductor structure and positioning each dielectric portion on one side of a conductive structure, can increase the size of the air gap structure between two adjacent conductive structures along a first direction (i.e., the direction from one conductive structure to another among two adjacent conductive structures located on opposite sides of an air gap structure). This ensures that the air gap structure reduces the capacitance value of the parasitic capacitance between two adjacent conductive structures, thereby reducing the capacitance value of the parasitic capacitance between two adjacent conductive structures, reducing the capacitive coupling between two adjacent conductive structures, avoiding signal delay in the conductive structure caused by the parasitic capacitance between two adjacent conductive structures, and improving the performance of the semiconductor structure.

[0007] In some embodiments, the air gap structure includes a first portion located between two adjacent dielectric portions and a second portion located between two adjacent conductive structures. The average dimension of the first portion along a first direction is smaller than the average dimension of the second portion along the first direction, where the first direction is the direction from one conductive structure to the other among two adjacent conductive structures located on opposite sides of an air gap structure.

[0008] In some embodiments, the size of the first portion of the air gap structure gradually decreases along the first direction from one end of the dielectric portion near the conductive structure to the end of the dielectric portion away from the conductive structure.

[0009] In some embodiments, the second portion of the air gap structure has the same dimension everywhere along the first direction.

[0010] In some embodiments, the first insulating layer contacts the dielectric portion between two adjacent dielectric portions along the first direction. The first direction is the direction from one conductive structure to the other among two adjacent conductive structures located on opposite sides of one air gap structure.

[0011] In some embodiments, between two adjacent conductive structures, along the first direction, the first insulating layer contacts a portion of the sidewall of the conductive structure near the dielectric portion.

[0012] In some embodiments, between two adjacent conductive structures, along the first direction, the first insulating layer does not contact the sidewall of the conductive structure.

[0013] In some embodiments, along the first direction, a second portion of the air gap structure near one end of the first insulating layer contacts the sidewall of the conductive structure.

[0014] In some embodiments, the size of the dielectric portion along the second direction is 5 nm to 20 nm, and the second direction is perpendicular to the plane where the first insulating layer is located.

[0015] In some embodiments, the highest point of the air gap structure at the end away from the conductive structure is further away from the conductive structure than the side surface of the dielectric portion that is further away from the conductive structure.

[0016] In some embodiments, the material of the dielectric portion is different from the material of the first insulating layer.

[0017] In some embodiments, the material of the dielectric portion is the same as the material of the first insulating layer.

[0018] In some embodiments, the material of the dielectric portion includes one or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0019] In some embodiments, the semiconductor structure includes a plurality of memory cells arranged in an array, each memory cell including a first transistor, the first transistor including a gate, a source, a drain and a channel, the source, the channel and the drain being arranged sequentially, and the gate being located on at least one side of the channel.

[0020] The conductive structure is the gate, and the two gates of two adjacent first transistors are at least partially opposite to each other, with the air gap structure located between the portions of the two gates that are opposite to each other.

[0021] In some embodiments, the semiconductor structure includes a plurality of first transistors arranged in an array, each first transistor including a gate and a semiconductor pillar, the semiconductor pillar including a source, a channel and a drain disposed thereon, the gate being located on at least one side of the channel.

[0022] The conductive structure is the semiconductor pillar, with the two semiconductor pillars of two adjacent first transistors arranged opposite each other, and the air gap structure located between the two semiconductor pillars.

[0023] In some embodiments, the semiconductor structure includes a plurality of bit lines. The conductive structure is the bit line.

[0024] In some embodiments, the semiconductor structure includes peripheral circuitry.

[0025] On the other hand, a method for fabricating a semiconductor structure is provided, comprising:

[0026] Multiple conductive structures are formed at intervals.

[0027] Multiple dielectric portions are formed, each of which is located on one side of one of the conductive structures.

[0028] A first insulating layer is formed, which covers the plurality of dielectric portions and is located in the region between two adjacent dielectric portions.

[0029] An air gap structure is formed between two adjacent conductive structures and between two adjacent dielectric portions located on one side of the two adjacent conductive structures, and the first insulating layer defines the boundary of the air gap structure near the end of the first insulating layer.

[0030] In some embodiments, forming a plurality of medium portions includes:

[0031] A sacrificial layer is formed between two adjacent conductive structures.

[0032] A dielectric portion is formed on one side of each of the conductive structures using a region-selective deposition process.

[0033] Remove the sacrificial layer.

[0034] In some embodiments, the sacrificial layer is made of titanium nitride.

[0035] In another aspect, a storage system is provided, including the semiconductor structure and controller described above. The controller is electrically connected to the semiconductor structure.

[0036] In another aspect, an electronic device is provided, including a processor and a storage system as described above. The processor is coupled to the storage system.

[0037] It is understood that the beneficial effects that the semiconductor structure preparation method, storage system and electronic device provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure in the above text, and will not be repeated here. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a structural diagram of an electronic device provided according to some embodiments;

[0040] Figure 2 This is a structural diagram of a storage system provided according to some embodiments;

[0041] Figure 3A This is a structural diagram of a memory provided according to some embodiments;

[0042] Figure 3B This is a structural diagram of a storage array layer within a memory according to some embodiments;

[0043] Figure 4 This is a structural diagram of a semiconductor structure provided according to some embodiments;

[0044] Figure 5 This is another structural diagram of a semiconductor structure provided according to some embodiments;

[0045] Figure 6This is yet another structural diagram of a semiconductor structure provided according to some embodiments;

[0046] Figure 7 This is yet another structural diagram of a semiconductor structure provided according to some embodiments;

[0047] Figure 8 This is yet another structural diagram of a semiconductor structure provided according to some embodiments;

[0048] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0049] Figure 10 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S1 in the flowchart of the semiconductor structure fabrication method;

[0050] Figure 11 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S2 in the flowchart of the semiconductor structure fabrication method;

[0051] Figure 12 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S21 in the flowchart of the semiconductor structure fabrication method;

[0052] Figure 13 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S22 in the flowchart of the semiconductor structure fabrication method;

[0053] Figure 14 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S23 in the flowchart of the semiconductor structure fabrication method;

[0054] Figure 15 for Figure 9 A structural diagram of a semiconductor structure corresponding to step S3 in the flowchart of the semiconductor structure fabrication method;

[0055] Figure 16 for Figure 9 Another structural diagram of the semiconductor structure corresponding to step S3 in the flowchart of the semiconductor structure fabrication method. Detailed Implementation

[0056] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0057] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0058] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0059] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0060] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0061] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0062] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0063] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] It should be noted that, for example, BL / 2 in the accompanying drawings of this disclosure indicates that the component can be either BL or 2, and other similar reference numerals in the drawings also follow the above description.

[0066] like Figure 1 As shown, this application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic device 1000.

[0067] In some embodiments, please continue reading Figure 1 The aforementioned electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0068] For example, the processor 200 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0069] The storage system 100 described above will be described in detail below.

[0070] like Figure 2 As shown, Figure 2 This is a structural diagram of a storage system 100 provided according to some embodiments. The storage system 100 may include a semiconductor structure D and a controller 20. The semiconductor structure D and the controller 20 are electrically connected.

[0071] For example, the storage system 100 described above can be integrated into a memory card. Memory cards include, for example, any of the following: PC card (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0072] The aforementioned storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0073] The aforementioned storage system 100 can also be integrated into a solid state drive (SSD).

[0074] For example, the controller 20 in the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0075] The controller 20 can also be configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0076] For example, controller 20 may be configured to manage data stored in memory 10 and communicate with external devices (e.g., a host).

[0077] The controller 20 can also be configured to control the operation of the memory 10, such as read, erase and program operations.

[0078] Controller 20 can also be configured to manage various functions related to data stored or to be stored in memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0079] The controller 20 can also be configured to process error correction codes for data read from or written to the memory 10.

[0080] Of course, controller 20 can also perform any other suitable function, such as formatting memory 10; or controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0081] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0082] The semiconductor structure D described above will be explained in detail below.

[0083] In some embodiments, such as Figure 3A As shown, Figure 3A This is a structural diagram of a memory 10 provided according to some embodiments. The semiconductor structure D can be the memory 10.

[0084] Alternatively, the semiconductor structure D can also be part of the memory 10. That is, the memory 10 may include the semiconductor structure D.

[0085] For example, please continue reading Figure 3A The memory 10 may include a memory array layer 11 and a peripheral device layer 12. The peripheral device layer 12 is coupled to the memory array layer 11. The peripheral device layer 12 may be configured to control and sense the memory array layer 11.

[0086] The memory array layer 11 and the peripheral device layer 12 can be fabricated separately (and in some embodiments, the memory array layer 11 and the peripheral device layer 12 can be fabricated in parallel), such that the thermal budget for fabricating one of the memory array layer 11 and the peripheral device layer 12 does not limit the process for fabricating the other of the memory array layer 11 and the peripheral device layer 12.

[0087] Based on this, the separately fabricated memory array layer 11 and peripheral device layer 12 can be bonded to form memory 10. That is, the memory array layer 11 and peripheral device layer 12 can form a large number of interconnect structures (e.g., bonding contacts) through bonding interface 13 to enable direct, short-distance (e.g., micrometer-level) electrical connections between the memory array layer 11 and peripheral device layer 12, rather than long-distance (e.g., millimeter- or centimeter-level) electrical connections on a circuit board (e.g., printed circuit board, PCB). This helps reduce the power consumption of memory 10 and achieve high-speed I / O throughput. Data transfer between memory array layer 11 and peripheral device layer 12 can be performed through the interconnect structures (e.g., bonding contacts) of bonding interface 13.

[0088] The following uses memory 10, which includes a semiconductor structure D, as an example to illustrate some embodiments of this disclosure.

[0089] In some embodiments, please continue reading Figure 3A and combined Figure 3B , Figure 3B This is a structural diagram of a memory array layer 11 within a memory 10 according to some embodiments. When the memory 10 includes a semiconductor structure D, the memory array layer 11 within the memory 10 may include the semiconductor structure D, and / or, the peripheral device layer 12 within the memory 10 may include the semiconductor structure D.

[0090] For example, one of the memory array layer 11 and the peripheral device layer 12 within the memory 10 may include a semiconductor structure D. For instance, the memory array layer 11 within the memory 10 may include a semiconductor structure D. As another example, the peripheral device layer 12 within the memory 10 may include a semiconductor structure D.

[0091] Alternatively, both the memory array layer 11 and the peripheral device layer 12 within the memory 10 may include a semiconductor structure D.

[0092] In some embodiments, please continue reading Figure 3A and Figure 3B The memory array layer 11 within the memory 10 includes a semiconductor structure D, which may include multiple memory cells MC arranged in an array.

[0093] It should be noted that, Figure 3A and Figure 3BThe illustrated embodiment uses the above-mentioned "array-arranged multiple memory cells MC" as an example, specifically a Dynamic Random Access Memory (DRAM) cell array. However, the type of "array-arranged multiple memory cells MC" in this disclosure is not limited to this. "Array-arranged multiple memory cells MC" can include any suitable type of memory cell array that uses transistors as switching and selection devices. For example, "array-arranged multiple memory cells MC" can include PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin-transfer torque (STT) memory cell arrays, etc.

[0094] Please continue reading. Figure 3B The "multiple memory cells MC arranged in an array" includes an array of dynamic random access memory (DRAM) cells, each memory cell MC may include a capacitor C for storing one bit of data as a positive or negative charge and one or more first transistors T1 for controlling (e.g., switching and selecting) access to it.

[0095] For example, the first transistor T1 can be a vertical transistor. For instance, the first transistor T1 can be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0096] In some embodiments, please continue reading Figure 3B The first transistor T1 may include a gate G, a source s, a drain d, and a channel TC. The source s, channel TC, and drain d of the first transistor T1 may be arranged sequentially, and the gate G is located on at least one side of the channel TC. The two gates G of two adjacent first transistors T1 are at least partially opposite to each other.

[0097] It is understood that the gate G of the first transistor T1 and the word line WL within the memory array layer 11 can be a continuous conductive structure. That is, the gate G of the first transistor T1 can be considered as part forming the word line WL, or the word line WL can be considered as an extension of the gate G of the first transistor T1 to couple to the peripheral device layer 12. The first transistor T1 can be turned on or off by applying a voltage to the word line WL.

[0098] The gate G of the first transistor T1 is made of a conductive material.

[0099] For example, the material of the gate G of the first transistor T1 may include polysilicon, metal, metal compound, or silicide. For instance, the material of the gate G of the first transistor T1 may include doped polysilicon (i.e., gate polysilicon), tungsten (W), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0100] The gate G of the first transistor T1 may include multiple conductive layers. For example, the gate G of the first transistor T1 may include a titanium nitride (TiN) layer and a tungsten (W) layer stacked together.

[0101] In other embodiments, such as Figure 4 As shown, Figure 4 This is a structural diagram of a semiconductor structure D according to some embodiments. The first transistor T1 in the memory cell MC within the semiconductor structure D may also include a gate G and a semiconductor pillar T11. The semiconductor pillar T11 includes a source, a channel, and a drain arranged sequentially, with the gate G located on at least one side of the channel. The two semiconductor pillars T11 of two adjacent first transistors T1 are arranged opposite to each other.

[0102] The semiconductor pillar T11 of the first transistor T1 includes a conductive material.

[0103] In some embodiments, please continue reading Figure 3A and Figure 3B The memory array layer 11 within the memory 10 includes a semiconductor structure D, which may also include multiple bit lines BL. The source s or drain d of the first transistor T1 is connected to the bit line BL. When the first transistor T1 is turned on, the bit line BL can perform read or write operations on the first transistor T1.

[0104] In some embodiments, please continue reading Figure 3A The peripheral device layer 12 within the memory 10 includes a semiconductor structure D, which may also include peripheral circuitry WD.

[0105] For example, the peripheral circuitry WD can be any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory array layer 11. For instance, the peripheral circuitry WD may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0106] For example, the peripheral circuitry WD can use complementary metal-oxide-semiconductor (CMOS) technology. For instance, it can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0107] In some embodiments, such as Figure 5 As shown, Figure 5 This is a structural diagram of a semiconductor structure D according to some embodiments. The semiconductor structure D includes a plurality of conductive structures 2. The plurality of conductive structures 2 are arranged at intervals.

[0108] It should be noted that, Figure 5 The number of conductive structures 2 within the semiconductor structure D shown is merely illustrative. The number of conductive structures 2 can be set according to actual needs, and no specific limitations are imposed on the embodiments of this disclosure.

[0109] For example, the conductive structure 2 may include materials such as metal, monocrystalline silicon, or doped polycrystalline silicon.

[0110] For example, please continue reading Figure 3A and Figure 5 The semiconductor structure D includes multiple memory cells MC arranged in an array. Figure 5 In the illustrated embodiment, the conductive structure 2 can be the gate G of the first transistor T1 within the memory cell MC.

[0111] Please continue reading. Figure 4 and Figure 5 The semiconductor structure D includes multiple memory cells MC arranged in an array. Figure 5 The conductive structure 2 in the illustrated embodiment can also be the semiconductor pillar T11 of the first transistor T1 in the memory cell MC.

[0112] Based on the semiconductor structure D, which includes multiple bit lines BL, Figure 5 The conductive structure 2 in the illustrated embodiment can also be a bit line BL.

[0113] Based on the semiconductor structure D, including the peripheral circuit WD, Figure 5 The conductive structure 2 in the illustrated embodiment can also be a transistor within the peripheral circuit WD.

[0114] It should be noted that, although this combination Figure 3A , Figure 3B and Figure 4The types of conductive structures 2 within the semiconductor structure D in this application have been described; however, the above description is exemplary and not exhaustive, and therefore not limited to the disclosed embodiments. The conductive structure 2 within the semiconductor structure D can also be other structures comprising conductive materials and having conductive properties.

[0115] In some embodiments, please continue reading Figure 5 The semiconductor structure D also includes an air gap structure 3. The air gap structure 3 is located between two adjacent conductive structures 2.

[0116] Understandably, please continue reading. Figure 3A and Figure 5 The semiconductor structure D includes multiple memory cells MC arranged in an array, and Figure 5 In the embodiment shown, when the conductive structure 2 is the gate G of the first transistor T1 in the memory cell MC, the air gap structure 3 can be located between the portions of the two gates G of two adjacent first transistors T1 that are disposed opposite to each other.

[0117] Please continue reading. Figure 4 and Figure 5 The semiconductor structure D includes multiple memory cells MC arranged in an array, and Figure 5 In the embodiment shown, when the conductive structure 2 is the semiconductor pillar T11 of the first transistor T1 in the memory cell MC, the air gap structure 3 can be located between the two semiconductor pillars T11 of two adjacent first transistors T1.

[0118] Based on the semiconductor structure D, which includes multiple bit lines BL, and Figure 5 In the embodiment shown, when the conductive structure 2 is a bit line BL, the air gap structure 3 can be located between two adjacent bit lines BL.

[0119] Based on the semiconductor structure D, including the peripheral circuit WD, and Figure 5 When the conductive structure 2 in the illustrated embodiment is a transistor within the peripheral circuit WD, the air gap structure 3 can be located between two adjacent transistors within the peripheral circuit WD.

[0120] By forming an air gap structure 3 between two adjacent conductive structures 2, the gas in the air gap structure 3 has a low dielectric constant, which can reduce the capacitance value of the parasitic capacitance between the two adjacent conductive structures 2, thereby reducing the probability of signal delay caused by the parasitic capacitance in the conductive structure 2. This is beneficial to improving the performance of the semiconductor structure D and increasing the yield of the semiconductor structure D.

[0121] For example, the gas within the air gap structure 3 may include argon, nitrogen, helium, or dry air.

[0122] In some embodiments, please continue reading Figure 5The semiconductor structure D also includes a first insulating layer 4. The first insulating layer 4 is located on one side of the plurality of conductive structures 2 and the air gap structure 3 between two adjacent conductive structures 2. The first insulating layer 4 can define the boundary of the end 3c of the air gap structure 3 located between two adjacent conductive structures 2 near the first insulating layer 4.

[0123] For example, the first insulating layer 4 can be formed by a chemical vapor deposition (CVD) process.

[0124] Chemical vapor deposition (CVD) is a process in which one or more compounds or elemental gases containing elements constituting the first insulating layer 4 are introduced into a reaction chamber containing a semiconductor structure D. The reactants undergo a chemical reaction under gaseous conditions, and the first insulating layer 4 is deposited on one side of the surface of multiple conductive structures 2 and the gap between two adjacent conductive structures 2 within the semiconductor structure D by means of the spatial gas-phase chemical reaction.

[0125] Please continue reading. Figure 5 The first insulating layer 4 includes a first sub-part 41 and a second sub-part 42. During the formation of the first insulating layer 4 by a chemical vapor deposition (CVD) process, a portion of the reactive material used to form the first insulating layer 4 may enter the gap between two adjacent conductive structures 2, forming the first sub-part 41 of the first insulating layer 4. That is, the first sub-part 41 of the first insulating layer 4 extends between the two adjacent conductive structures 2. The first sub-part 41 of the first insulating layer 4 and the two adjacent conductive structures 2 simultaneously intersect at least one straight line (e.g., straight line TT) parallel to the first direction X (i.e., the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of a gap structure 3).

[0126] Another portion of the reactive material used to form the first insulating layer 4 accumulates on one side of the surface between the plurality of conductive structures 2 and the gap between two adjacent conductive structures 2, forming a second sub-part 42 of the first insulating layer 4. That is, the second sub-part 42 is located on one side of the air gap structure 3 and the plurality of conductive structures 2. The second sub-part 42 can prevent subsequent reactive material from continuing to enter the gap between two adjacent conductive structures 2, thereby forming an air gap structure 3 between two adjacent conductive structures 2 and defining the boundary of the air gap structure 3 near the end 3c of the first insulating layer 4.

[0127] Since the first sub-part 41 of the first insulating layer 4 is located in the gap between two adjacent conductive structures 2, the first sub-part 41 of the first insulating layer 4 will occupy part of the space in the gap between the two adjacent conductive structures 2. This causes the size L1 of the air gap structure 3 located in the gap between the two adjacent conductive structures 2 to decrease along the first direction X (i.e., in the direction from one conductive structure 2 to the other in the two adjacent conductive structures 2 located on opposite sides of one air gap structure 3). This can easily affect the effect of the air gap structure 3 on reducing the capacitance value of the parasitic capacitance between the two adjacent conductive structures 2, resulting in a larger capacitance value of the parasitic capacitance between the two adjacent conductive structures 2 and stronger capacitive coupling between the two adjacent conductive structures 2. This may cause signal delay of the conductive structure 2 and further lead to a decrease in the performance of the semiconductor structure D.

[0128] Based on this, in some embodiments, such as Figure 6 and Figure 7 As shown, Figure 6 and Figure 7 All are structural diagrams of a semiconductor structure D provided according to some embodiments. The semiconductor structure D also includes a plurality of dielectric portions 5, each dielectric portion 5 being located on one side of a conductive structure 2. A first insulating layer 4 is located on the side of the plurality of dielectric portions 5 away from the conductive structure 2, and is located in the region between two adjacent dielectric portions 5.

[0129] An air gap structure 3 is formed between two adjacent conductive structures 2 and between two adjacent dielectric portions 5 located on one side of the two adjacent conductive structures 2. The first insulating layer 4 defines the boundary of the air gap structure 3 at one end 3c near the first insulating layer 4.

[0130] For example, please continue reading Figure 6 The first insulating layer 4 includes a first sub-part 41 and a second sub-part 42. The first sub-part 41 includes a first portion 411 and a second portion 412. During the formation of the first insulating layer 4 by chemical vapor deposition (CVD), a portion of the reactive material used to form the first insulating layer 4 may enter the gap between two adjacent dielectric portions 5, forming the first portion 411 within the first sub-part 41 of the first insulating layer 4. That is, the first sub-part 41 (specifically, the first portion 411 within the first sub-part 41) of the first insulating layer 4 extends between the two adjacent dielectric portions 5. The first sub-part 41 (specifically, the first portion 411 within the first sub-part 41) of the first insulating layer 4 and the two adjacent dielectric portions 5 simultaneously intersect at least one straight line (e.g., straight line TT) parallel to the first direction X (i.e., the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0131] The portion of the reactive material used to form the first insulating layer 4 may also pass through the gap between two adjacent dielectric portions 5 and enter the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4, forming a second portion 412 within the first sub-part 41 of the first insulating layer 4. That is, the first sub-part 41 of the first insulating layer 4 (specifically, the second portion 412 within the first sub-part 41) extends to the space between the two adjacent conductive structures 2. The first sub-part 41 of the first insulating layer 4 (specifically, the second portion 412 within the first sub-part 41) and the two adjacent conductive structures 2 simultaneously intersect at least one straight line (e.g., straight line NN) parallel to the first direction X (i.e., the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0132] The portion of the reactive material used to form the first insulating layer 4 accumulates on one side of the surface between the plurality of dielectric portions 5 and the gap between two adjacent dielectric portions 5, forming a second sub-portion 42 of the first insulating layer 4. That is, the second sub-portion 42 is located on one side of the air gap structure 3 and the plurality of dielectric portions 5. The second sub-portion 42 can prevent subsequent reactive material from continuing to enter the gap between two adjacent dielectric portions 5, thereby forming an air gap structure 3 between two adjacent dielectric portions 5 and between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4, and defining the boundary of the air gap structure 3 near the end 3c of the first insulating layer 4.

[0133] Alternatively, please continue reading Figure 7 The first insulating layer 4 includes a first sub-part 41 and a second sub-part 42. The first sub-part 41 includes a first portion 411. During the formation of the first insulating layer 4 by chemical vapor deposition (CVD), a portion of the reactive material used to form the first insulating layer 4 may enter the gap between two adjacent dielectric portions 5, forming the first portion 411 within the first sub-part 41 of the first insulating layer 4. That is, the first sub-part 41 (specifically, the first portion 411 within the first sub-part 41) of the first insulating layer 4 extends between the two adjacent dielectric portions 5. The first sub-part 41 (specifically, the first portion 411 within the first sub-part 41) of the first insulating layer 4 and the two adjacent dielectric portions 5 simultaneously intersect at least one straight line (e.g., straight line TT) parallel to the first direction X (i.e., the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0134] The reactant used to form the first insulating layer 4 does not enter the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4. That is, the first sub-part 41 of the first insulating layer 4 does not extend between the two adjacent conductive structures 2. The first sub-part 41 of the first insulating layer 4 and the two adjacent conductive structures 2 do not simultaneously intersect any straight line (e.g., straight line NN) parallel to the first direction X (i.e., the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0135] Another portion of the reactive material used to form the first insulating layer 4 accumulates on one side of the surface between the plurality of dielectric portions 5 and the gap between two adjacent dielectric portions 5, forming a second sub-part 42 of the first insulating layer 4. That is, the second sub-part 42 is located on one side of the air gap structure 3 and the plurality of dielectric portions 5. The second sub-part 42 can prevent subsequent reactive material from continuing to enter the gap between two adjacent dielectric portions 5, thereby forming an air gap structure 3 between two adjacent dielectric portions 5 and between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4, and defining the boundary of the air gap structure 3 near the end 3c of the first insulating layer 4.

[0136] In summary, by providing multiple dielectric portions 5 within the semiconductor structure D, each dielectric portion 5 being located on one side of a conductive structure 2, and by positioning the multiple dielectric portions 5 between the multiple conductive structures 2 and the first insulating layer 4, when the first insulating layer 4 is formed, most or all of the reactive material used to form the first sub-part 41 of the first insulating layer 4 enters the gap between two adjacent dielectric portions 5, and the first portion 411 within the first sub-part 41 used to form the first insulating layer 4.

[0137] A small amount of reactant material used to form the first sub-section 41 of the first insulating layer 4 may pass through the gap between two adjacent dielectric sections 5 and enter the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric sections 5 away from the first insulating layer 4, to form the second sub-section 412 within the first sub-section 41 of the first insulating layer 4.

[0138] Alternatively, the reactant used to form the first sub-section 41 of the first insulating layer 4 may not enter the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric sections 5 away from the first insulating layer 4, that is, the first sub-section 41 of the first insulating layer 4 only includes the first portion 411 located in the gap between the two adjacent dielectric sections 5.

[0139] The first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) can occupy a small amount or not occupy part of the space in the gap between two adjacent conductive structures 2, thereby increasing the size L1 of the air gap structure 3 formed between two adjacent conductive structures 2 along the first direction X (i.e., in the two adjacent conductive structures 2 located on opposite sides of one air gap structure 3, along the direction from one conductive structure 2 to the other conductive structure 2). This ensures that the air gap structure 3 reduces the capacitance value of the parasitic capacitance between two adjacent conductive structures 2, thereby reducing the capacitance value of the parasitic capacitance between two adjacent conductive structures 2, reducing the capacitive coupling between two adjacent conductive structures 2, avoiding signal delay of the conductive structure 2 due to the parasitic capacitance between two adjacent conductive structures 2, and improving the performance of the semiconductor structure D.

[0140] In some embodiments, please continue reading Figure 6 and Figure 7 The dielectric portion 5 has a dimension L2 of 5 nm to 20 nm along the second direction Z. The second direction Z is perpendicular to the plane containing the first insulating layer 4.

[0141] It is understandable that, when forming the first insulating layer 4, the larger the dimension L2 of the dielectric portion 5 along the second direction Z, the longer the path of the reactant material used to form the first sub-part 41 of the first insulating layer 4 passes through the gap between two adjacent dielectric portions 5 and enters the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4. This makes it more difficult for the reactant material used to form the first sub-part 41 of the first insulating layer 4 to enter the gap between the two adjacent conductive structures 2. This allows the first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) to occupy a small amount or not at all the space within the gap between the two adjacent conductive structures 2. This increases the size L1 of the air gap structure 3 formed between two adjacent conductive structures 2 along the first direction X (i.e., along the direction from one conductive structure 2 to the other in two adjacent conductive structures 2 located on opposite sides of one air gap structure 3). This ensures that the air gap structure 3 reduces the capacitance value of the parasitic capacitance between the two adjacent conductive structures 2, thereby reducing the capacitance value of the parasitic capacitance between the two adjacent conductive structures 2, reducing the capacitive coupling between the two adjacent conductive structures 2, avoiding signal delay of the conductive structure 2 caused by the parasitic capacitance between the two adjacent conductive structures 2, and improving the performance of the semiconductor structure D.

[0142] For example, the dimension L2 of the dielectric portion 5 along the second direction Z can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm, etc.

[0143] In some embodiments, please continue reading Figure 6 and Figure 7 The air gap structure 3 in the semiconductor structure D includes a first portion 3a located between two adjacent dielectric portions 5 and a second portion 3b located between two adjacent conductive structures 2.

[0144] Since the semiconductor structure D has multiple dielectric portions 5, each dielectric portion 5 is located on one side of a conductive structure 2, and the multiple dielectric portions 5 are located between the multiple conductive structures 2 and the first insulating layer 4, when the first insulating layer 4 is formed, most or all of the reactant material used to form the first sub-part 41 of the first insulating layer 4 enters the gap between two adjacent dielectric portions 5, and a small amount or no reactant material used to form the first sub-part 41 of the first insulating layer 4 passes through the gap between two adjacent dielectric portions 5 and enters the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4.

[0145] Therefore, the first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) occupies a relatively large amount of space in the gap between two adjacent dielectric parts 5, and the average size of the first part 3a located between two adjacent dielectric parts 5 in the air gap structure 3 along the first direction X (i.e., in the two adjacent conductive structures 2 located on opposite sides of an air gap structure 3, along the direction from one conductive structure 2 to the other conductive structure 2) is relatively small.

[0146] The first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) occupies relatively little space in the gap between two adjacent conductive structures 2, or does not occupy any space in the gap between two adjacent conductive structures 2. The average size of the second part 3b located between two adjacent conductive structures 2 in the air gap structure 3 along the first direction X (i.e., in the direction from one conductive structure 2 to the other among two adjacent conductive structures 2 located on opposite sides of one air gap structure 3) is relatively large.

[0147] That is, the average size of the first part 3a located between two adjacent dielectric parts 5 within the air gap structure 3 along the first direction X (i.e., along the direction from one conductive structure 2 to another conductive structure 2 in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3) is smaller than the average size of the second part 3b located between two adjacent conductive structures 2 within the air gap structure 3 along the first direction X (i.e., along the direction from one conductive structure 2 to another conductive structure 2 in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0148] For example, please continue reading Figure 6 and Figure 7Along the direction from the end 5a of the dielectric portion 5 near the conductive structure 2 to the end 5b of the dielectric portion 5 away from the conductive structure 2, the space occupied by the first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) in the gap between two adjacent dielectric portions 5 gradually increases.

[0149] In other words, along the direction from the end 5a of the dielectric portion 5 near the conductive structure 2 to the end 5b of the dielectric portion 5 away from the conductive structure 2, the size L1 of the first portion 3a located between two adjacent dielectric portions 5 in the air gap structure 3 gradually decreases along the first direction X (i.e., in the direction from one conductive structure 2 to the other conductive structure 2 among two adjacent conductive structures 2 located on opposite sides of one air gap structure 3).

[0150] For example, please continue reading Figure 7 When the first insulating layer 4 is formed, if the reactant used to form the first sub-part 41 of the first insulating layer 4 does not pass through the gap between the two adjacent dielectric parts 5 and enters the gap between the two adjacent conductive structures 2 located on the side of the two adjacent dielectric parts 5 away from the first insulating layer 4, the first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) does not occupy the space in the gap between the two adjacent conductive structures 2, and the size L1 of the second part 3b located between the two adjacent conductive structures 2 in the air gap structure 3 along the first direction X (i.e., in the two adjacent conductive structures 2 located on opposite sides of an air gap structure 3, along the direction from one conductive structure 2 to the other conductive structure 2) can be equal everywhere.

[0151] In some embodiments, please continue reading Figure 6 and Figure 7 When forming the first insulating layer 4, when a portion of the reactant used to form the first insulating layer 4 enters the gap between two adjacent dielectric sections 5 and forms the first portion 411 within the first sub-section 41 of the first insulating layer 4, the first insulating layer 4 (i.e., the first portion 411 within the first sub-section 41 of the first insulating layer 4) can contact the dielectric section 5 between the two adjacent dielectric sections 5 along the first direction X (i.e., along the direction from one conductive structure 2 to the other conductive structure 2 in two adjacent conductive structures 2 located on opposite sides of an air gap structure 3).

[0152] In some embodiments, please continue reading Figure 6When forming the first insulating layer 4, when a portion of the reactant used to form the first insulating layer 4 passes through the gap between two adjacent dielectric portions 5 and enters the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric portions 5 away from the first insulating layer 4, forming the second portion 412 within the first sub-part 41 of the first insulating layer 4, between the two adjacent conductive structures 2, along the first direction X (i.e., in the two adjacent conductive structures 2 located on opposite sides of a gap structure 3, along the direction from one conductive structure 2 to another), the first insulating layer 4 (i.e., the second portion 412 within the first sub-part 41 of the first insulating layer 4) can contact the sidewall of the conductive structure 2 near the dielectric portion 5.

[0153] In other embodiments, please continue to refer to Figure 7 When the first insulating layer 4 is formed, if the reactant used to form the first insulating layer 4 does not enter the gap between the two adjacent conductive structures 2 located on the side away from the first insulating layer 4 of the two adjacent dielectric portions 5, that is, when the first sub-part 41 of the first insulating layer 4 does not include the second part 412 located between the two adjacent conductive structures 2, the first insulating layer 4 does not contact the sidewall of the conductive structure 2 between the two adjacent conductive structures 2 along the first direction X (that is, in the two adjacent conductive structures 2 located on opposite sides of a gap structure 3, along the direction from one conductive structure 2 to the other conductive structure 2).

[0154] It is understandable that, since the reactant used to form the first insulating layer 4 does not enter the gap between the two adjacent conductive structures 2 located on the side of the two adjacent dielectric parts 5 away from the first insulating layer 4, the reactant used to form the first insulating layer 4 will not occupy part of the space in the gap between the two adjacent conductive structures 2. Only the second part 3b of the air gap structure 3 is provided in the gap between the two adjacent conductive structures 2. Along the first direction X (that is, in the two adjacent conductive structures 2 located on opposite sides of one air gap structure 3, along the direction from one conductive structure 2 to the other), the end of the second part 3b of the air gap structure 3 near the first insulating layer 4 is in contact with the sidewall of the conductive structure 2.

[0155] In some embodiments, please continue reading Figure 6 and Figure 7 The highest point 3aa of the air gap structure 3 in the semiconductor structure D, which is away from the conductive structure 2, is away from the conductive structure 2, while the surface 5b of the dielectric part 5, which is away from the conductive structure 2, is away from the conductive structure 2.

[0156] In some embodiments, please continue reading Figure 6 and Figure 7 The material of the dielectric portion 5 within the semiconductor structure D can be different from the material of the first insulating layer 4.

[0157] For example, the material of the dielectric portion 5 may include one or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0158] The material of the first insulating layer 4 may include one or more of the materials that are different from those of the dielectric part 5, such as silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0159] In other embodiments, such as Figure 8 As shown, Figure 8 This is a structural diagram of a semiconductor structure D according to some embodiments. The material of the dielectric portion 5 within the semiconductor structure D can be the same as the material of the first insulating layer 4.

[0160] For example, the material of the dielectric portion 5 and the material of the first insulating layer 4 may both include one or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide and fluorine-doped silicon oxide, and the material of the dielectric portion 5 and the material of the first insulating layer 4 are the same.

[0161] The preparation method of the above semiconductor structure D is described in detail below.

[0162] In some embodiments, such as Figure 9 As shown, Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor structure D according to some embodiments. It should be noted that... Figure 9 The method for fabricating the semiconductor structure D shown is not exclusive and can also be used in... Figure 9 Other steps are performed before, after, or between any step in the fabrication method of the semiconductor structure D shown.

[0163] The method for preparing semiconductor structure D includes the following steps S1 to S3.

[0164] S1: As Figure 10 As shown, Figure 10 for Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structural diagram of semiconductor structure D corresponding to step S1. Multiple conductive structures 2 are formed at intervals.

[0165] For example, please continue reading Figure 10 and combined Figure 9 Step S1 in the above method for preparing semiconductor structure D, which involves forming a plurality of spaced conductive structures 2, can specifically be:

[0166] Multiple trenches (i.e. gaps J between two adjacent conductive structures 2) are formed on the wafer by photolithography, wet etching and / or dry etching processes to obtain conductive structures 2 located on opposite sides of the trenches (i.e. gaps J between two adjacent conductive structures 2).

[0167] In some examples, multiple trenches (i.e. gaps J between two adjacent conductive structures 2) are formed on the wafer by photolithography, wet etching and / or dry etching processes. While obtaining conductive structures 2 located on opposite sides of the trenches (i.e. gaps J between two adjacent conductive structures 2), a substrate 1 located on one side of the multiple conductive structures 2 can also be obtained.

[0168] It is understood that the multiple conductive structures 2 formed by the above process are made of the same material as the substrate 1 and are an integral structure.

[0169] Alternatively, step S1 in the above method for preparing semiconductor structure D, which involves forming a plurality of spaced conductive structures 2, can specifically be:

[0170] A conductive film layer is formed on one side of the substrate 1, and then the conductive film layer is patterned to form a plurality of conductive structures 2 spaced apart.

[0171] It is understandable that the materials of the multiple conductive structures 2 and the substrate 1 formed by the above process can be different.

[0172] For example, substrate 1 can be a semiconductor substrate. For example, it can be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate.

[0173] Alternatively, substrate 1 can also be an insulating substrate, such as a silicon-on-insulator (SOI) substrate.

[0174] Alternatively, substrate 1 can also be a conductive substrate, such as a metal substrate.

[0175] S2: As Figure 11 As shown, Figure 11 for Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structure of semiconductor structure D corresponding to step S2. Multiple dielectric portions 5 are formed, each dielectric portion 5 located on one side of a conductive structure 2.

[0176] For example, please continue reading Figure 9 Step S2 in the above method for preparing semiconductor structure D may include steps S21 to S23.

[0177] S21: As Figure 12 As shown, Figure 12 for Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structural diagram of semiconductor structure D corresponding to step S21. A sacrificial layer 6 is formed between two adjacent conductive structures 2.

[0178] For example, the material of the sacrificial layer 6 may include titanium nitride.

[0179] S22: As Figure 13 As shown, Figure 13 for Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structure of semiconductor structure D corresponding to step S22. A dielectric portion 5 is formed on one side of each conductive structure 2 using a region-selective deposition process.

[0180] For example, the above-mentioned "region-selective deposition process" can be the area-selective atomic layer deposition (ASALD) process.

[0181] Atomic Layer Deposition (ALD) is a deposition process used to grow thin films in atomic-layer units. In ALD, gas-phase reactions are suppressed by sequentially injecting reactants, and film is deposited on the target surface through a self-limiting adsorption process. The total thickness of the film deposited using ALD can be adjusted by the number of deposition cycles; therefore, ALD has the advantage of easily adjusting film thickness in atomic-layer units.

[0182] Area Selective Atomic Layer Deposition (ASALD) is a thin film growth process that selectively grows on a selected surface (e.g., one side of conductive structure 2) using atomic layer deposition (ALD) technology.

[0183] For example, in the Area Selective Atomic Layer Deposition (ASALD) process, an inhibitor can be used to selectively deposit the material used to form the dielectric portion 5 onto one side of the conductive structure 2.

[0184] For example, the material of the dielectric portion 5 may include one or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0185] For example, the material of the dielectric part 5 may include one of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0186] For example, the material of the dielectric part 5 may include two or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

[0187] S23: As Figure 14 As shown, Figure 14 for Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structural diagram of semiconductor structure D corresponding to step S23. The sacrificial layer 6 is removed.

[0188] For example, the sacrificial layer 6 located between two adjacent conductive structures 2 can be removed by a wet etching process.

[0189] It should be noted that, Figure 9 , Figure 12 , Figure 13 and Figure 14 The illustration only takes step S2 of the method for preparing semiconductor structure D, which includes steps S21 to S23, as an example, in which multiple dielectric portions 5 are formed through steps S21 to S23, and each dielectric portion 5 is located on one side of a conductive structure 2. However, the method for forming multiple dielectric portions 5 in step S2 of the method for preparing semiconductor structure D in this application includes, but is not limited to, this. For example, in step S22 above, a dielectric portion 5 is formed on one side of each conductive structure 2 by a region selective deposition process. Alternatively, a film layer including the material for forming the dielectric portion 5 can be formed on one side of the gap between multiple conductive structures 2 and two adjacent conductive structures 2, and then the film layer is patterned to form multiple dielectric portions 5, with each dielectric portion 5 located on one side of a conductive structure 2.

[0190] S3: As Figure 15 and Figure 16 As shown, Figure 15 and Figure 16 All Figure 9 The flowchart of the method for fabricating semiconductor structure D shows the structure of semiconductor structure D corresponding to step S3. A first insulating layer 4 is formed, which covers multiple dielectric portions 5 and is located in the region between two adjacent dielectric portions 5.

[0191] An air gap structure 3 is formed between two adjacent conductive structures 2 and between two adjacent dielectric portions 5 located on one side of the two adjacent conductive structures 2. The first insulating layer 4 defines the boundary of the air gap structure 3 at one end 3c near the first insulating layer 4.

[0192] By forming a plurality of dielectric portions 5 within a semiconductor structure D, each dielectric portion 5 being located on one side of a conductive structure 2, and the plurality of dielectric portions 5 being located between the plurality of conductive structures 2 and the first insulating layer 4, when the first insulating layer 4 is formed, most or all of the reactive material used to form the first sub-portion 41 of the first insulating layer 4 enters the gap between two adjacent dielectric portions 5.

[0193] A small amount of the reactant material used to form the first sub-section 41 of the first insulating layer 4 may pass through the gap between two adjacent dielectric sections 5 and enter the gap between two adjacent conductive structures 2 located on the side of the two adjacent dielectric sections 5 away from the first insulating layer 4. Alternatively, the reactant material used to form the first sub-section 41 of the first insulating layer 4 may not enter the gap between the two adjacent conductive structures 2 located on the side of the two adjacent dielectric sections 5 away from the first insulating layer 4.

[0194] The first insulating layer 4 (i.e., the first sub-part 41 of the first insulating layer 4) can occupy a small amount or not occupy part of the space in the gap between two adjacent conductive structures 2, thereby increasing the size L1 of the air gap structure 3 formed between two adjacent conductive structures 2 along the first direction X (i.e., in the two adjacent conductive structures 2 located on opposite sides of one air gap structure 3, along the direction from one conductive structure 2 to the other conductive structure 2). This ensures that the air gap structure 3 reduces the capacitance value of the parasitic capacitance between two adjacent conductive structures 2, thereby reducing the capacitance value of the parasitic capacitance between two adjacent conductive structures 2, reducing the capacitive coupling between two adjacent conductive structures 2, avoiding signal delay of the conductive structure 2 due to the parasitic capacitance between two adjacent conductive structures 2, and improving the performance of the semiconductor structure D.

[0195] It should be noted that, Figure 15 Taking the example that the materials of the dielectric part 5 and the first insulating layer 4 are different, for example, Figure 9 The flowchart of the method for preparing semiconductor structure D is illustrated with a structural diagram of semiconductor structure D corresponding to step S3. Figure 16 Taking the example where the material of the dielectric layer 5 and the material of the first insulating layer 4 are the same, for Figure 9 The flowchart of the method for preparing semiconductor structure D is illustrated with a structural diagram of semiconductor structure D corresponding to step S3.

[0196] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple conductive structures spaced apart; Multiple dielectric portions, each of which is located on one side of one of the conductive structures; A first insulating layer is located on the side of the plurality of dielectric portions away from the conductive structure, and in the region between two adjacent dielectric portions; An air gap structure is formed between two adjacent conductive structures and between two adjacent dielectric portions located on one side of the two adjacent conductive structures, and the first insulating layer defines the boundary of the air gap structure near the end of the first insulating layer.

2. The semiconductor structure according to claim 1, characterized in that, The air gap structure includes a first portion located between two adjacent dielectric portions and a second portion located between two adjacent conductive structures. The average size of the first portion along a first direction is smaller than the average size of the second portion along the first direction. The first direction is the direction from one conductive structure to the other among two adjacent conductive structures located on opposite sides of one air gap structure.

3. The semiconductor structure according to claim 2, characterized in that, Along the direction from the end of the dielectric portion near the conductive structure to the end of the dielectric portion away from the conductive structure, the size of the first portion of the air gap structure gradually decreases along the first direction.

4. The semiconductor structure according to claim 2, characterized in that, The second part of the air gap structure has the same dimension everywhere along the first direction.

5. The semiconductor structure according to claim 1, characterized in that, Between two adjacent dielectric portions, along the first direction, the first insulating layer contacts the dielectric portion; the first direction is the direction from one conductive structure to the other in two adjacent conductive structures located on opposite sides of one air gap structure.

6. The semiconductor structure according to claim 5, characterized in that, Between two adjacent conductive structures, along the first direction, the first insulating layer contacts a portion of the sidewall of the conductive structure near the dielectric portion.

7. The semiconductor structure according to claim 5, characterized in that, Between two adjacent conductive structures, along the first direction, the first insulating layer does not contact the sidewall of the conductive structure.

8. The semiconductor structure according to claim 5, characterized in that, Along the first direction, the second portion of the air gap structure is in contact with the sidewall of the conductive structure at one end near the first insulating layer.

9. The semiconductor structure according to claim 1, characterized in that, The dielectric portion has a dimension of 5 nm to 20 nm along the second direction; the second direction is perpendicular to the plane containing the first insulating layer.

10. The semiconductor structure according to claim 1, characterized in that, The highest point of the air gap structure at the end furthest from the conductive structure is further away from the conductive structure than the surface of the dielectric portion on the side furthest from the conductive structure.

11. The semiconductor structure according to claim 1, characterized in that, The material of the dielectric portion is different from the material of the first insulating layer.

12. The semiconductor structure according to claim 1, characterized in that, The material of the dielectric portion is the same as the material of the first insulating layer.

13. The semiconductor structure according to any one of claims 1 to 12, characterized in that, The material of the dielectric part includes one or more of silicon oxide, silicon dioxide, carbon-doped silicon oxide, and fluorine-doped silicon oxide.

14. The semiconductor structure according to any one of claims 1 to 12, characterized in that, The semiconductor structure includes a plurality of memory cells arranged in an array. Each memory cell includes a first transistor, which includes a gate, a source, a drain, and a channel. The source, the channel, and the drain are arranged sequentially, and the gate is located on at least one side of the channel. The conductive structure is the gate, and the two gates of two adjacent first transistors are at least partially opposite to each other, with the air gap structure located between the portions of the two gates that are opposite to each other.

15. The semiconductor structure according to any one of claims 1 to 12, characterized in that, The semiconductor structure includes a plurality of first transistors arranged in an array, each first transistor including a gate and a semiconductor pillar, the semiconductor pillar including a source, a channel and a drain disposed thereon, the gate being located on at least one side of the channel; The conductive structure is the semiconductor pillar, with the two semiconductor pillars of two adjacent first transistors arranged opposite each other, and the air gap structure located between the two semiconductor pillars.

16. The semiconductor structure according to any one of claims 1 to 12, characterized in that, The semiconductor structure includes multiple bit lines; The conductive structure is the bit line.

17. The semiconductor structure according to any one of claims 1 to 12, characterized in that, The semiconductor structure includes peripheral circuitry.

18. A method for fabricating a semiconductor structure, characterized in that, include: Multiple conductive structures are formed at intervals; Multiple dielectric portions are formed, each of the dielectric portions being located on one side of one of the conductive structures; A first insulating layer is formed, which covers the plurality of dielectric portions and is located in the region between two adjacent dielectric portions; An air gap structure is formed between two adjacent conductive structures and between two adjacent dielectric portions located on one side of the two adjacent conductive structures, and the first insulating layer defines the boundary of the air gap structure near the end of the first insulating layer.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, The formation of multiple dielectric sections includes: A sacrificial layer is formed between two adjacent conductive structures; A dielectric portion is formed on one side of each of the conductive structures by a region-selective deposition process. Remove the sacrificial layer.

20. The method for preparing a semiconductor structure according to claim 19, characterized in that, The sacrificial layer is made of titanium nitride.

21. A storage system, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 17; The controller is electrically connected to the semiconductor structure.

22. An electronic device, characterized in that, include: The processor, and the storage system as claimed in claim 21, wherein the processor is coupled to the storage system.

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