Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a first semiconductor structure and a second semiconductor structure which are stacked in a first direction. The first semiconductor structure comprises a first bonding layer and a first conductive structure located in the first bonding layer; the second semiconductor structure comprises a second bonding layer and a second conductive structure located in the second bonding layer; one end of the first conductive structure is in bonding connection with one end of the second conductive structure; the semiconductor device further comprises a first MIM structure located in the first bonding layer, and the first MIM structure is connected with the other end of the first conductive structure. And / or a second MIM structure located in the second bonding layer, the second MIM structure being connected with the other end of the second conductive structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As integrated circuits increasingly demand big data processing capabilities, Moore's Law is nearing its limit, and miniaturizing semiconductor devices is becoming increasingly difficult. 3D integration technology has become an effective solution to continue improving PPAC (performance, power, area, cost) in the post-Moore era. Summary of the Invention

[0003] This disclosure provides a semiconductor device and a method for manufacturing the same; wherein the semiconductor device includes: a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure includes: a first bonding layer and a first conductive structure located in the first bonding layer; the second semiconductor structure includes: a second bonding layer and a second conductive structure located in the second bonding layer; one end of the first conductive structure is bonded to one end of the second conductive structure; wherein the semiconductor device further includes: a first MIM structure located in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or, a second MIM structure located in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

[0004] In some embodiments, the first bonding layer includes one or more of the first MIM structures; the second bonding layer includes one or more of the second MIM structures.

[0005] In some embodiments, both the first MIM structure and the second MIM structure include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer.

[0006] In some embodiments, the semiconductor device further includes: a first interconnect layer located on one side of the first bonding layer opposite to the second bonding layer along the first direction, away from the second bonding layer; and a first interconnect structure located in the first interconnect layer; a second interconnect layer located on one side of the second bonding layer opposite to the first direction, away from the first bonding layer; and a second interconnect structure located in the second interconnect layer.

[0007] In some embodiments, when the semiconductor device includes only the first MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; and the second conductive structure is directly connected to the second interconnect structure.

[0008] In some embodiments, when the semiconductor device includes only the second MIM structure, the first electrode layer of the second MIM structure is connected to the second interconnect structure; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure; and the first conductive structure is directly connected to the first interconnect structure.

[0009] In some embodiments, when the semiconductor device includes the first MIM structure and the second MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; the first electrode layer of the second MIM structure is connected to the second interconnect structure; and the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure.

[0010] In some embodiments, the semiconductor device further includes: a third conductive structure penetrating the first bonding layer, and a fourth conductive structure penetrating the second bonding layer, wherein the third conductive structure is bonded to the fourth conductive structure; wherein the third conductive structure is electrically isolated from the first conductive structure, and the fourth conductive structure is electrically isolated from the second conductive structure.

[0011] In some embodiments, the semiconductor device further includes: a third interconnect structure located in the first interconnect layer, the third interconnect structure being electrically isolated from the first interconnect structure; and a fourth interconnect structure located in the second interconnect layer, the fourth interconnect structure being electrically isolated from the second interconnect structure; wherein the third conductive structure is connected to the third interconnect structure, and the fourth conductive structure is connected to the fourth interconnect structure.

[0012] In some embodiments, the semiconductor device further includes: peripheral circuitry located on one side of the first interconnect layer along the first direction, away from the first bonding layer; and a memory cell array located on one side of the second interconnect layer along the first direction, away from the second bonding layer.

[0013] In some embodiments, the semiconductor device further includes: a fifth conductive structure located in the first bonding layer and connected to the first conductive structure; and a sixth conductive structure located in the second bonding layer and connected to the second conductive structure.

[0014] This disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure; the first semiconductor structure comprising: a first bonding layer and a first conductive structure located in the first bonding layer; forming a second semiconductor structure; the second semiconductor structure comprising: a second bonding layer and a second conductive structure located in the second bonding layer; stacking the first semiconductor structure and the second semiconductor structure along a first direction such that one end of the first conductive structure is bonded to one end of the second conductive structure; wherein the method further comprises: forming a first MIM structure in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or forming a second MIM structure in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

[0015] In some embodiments, the method includes: forming a first interconnect layer; forming a first interconnect structure in the first interconnect layer; forming a first sub-bonding layer on one side of the first interconnect layer along the first direction; forming a first groove in the first sub-bonding layer, the first groove exposing the first interconnect structure; forming a first conductive layer in the first groove and on a portion of the surface of the first sub-bonding layer; forming a dielectric layer on the surface of the first conductive layer; and forming a second electrode layer on the surface of the dielectric layer to form a first MIM structure.

[0016] In some embodiments, the method further includes: forming a second sub-bonding layer on the first sub-bonding layer; forming a second groove penetrating the second sub-bonding layer in the second sub-bonding layer, the second groove exposing one end of the first MIM structure; forming a first conductive structure in the second groove; the first conductive structure being connected to one end of the first MIM structure; wherein the first sub-bonding layer and the second sub-bonding layer constitute the first bonding layer.

[0017] In some embodiments, the method further includes: forming a third groove in the first bonding layer; the third groove being spaced apart from the second groove; forming a third conductive structure in the third groove; and the third conductive structure being electrically isolated from the first conductive structure.

[0018] In some embodiments, the method further includes: forming a fourth groove in the first bonding layer; the fourth groove communicating with the second groove; forming a fifth conductive structure in the fourth groove; and the fifth conductive structure being connected to the first conductive structure.

[0019] In some embodiments, forming the second semiconductor structure includes: forming a second interconnect layer; forming a second interconnect structure in the second interconnect layer; forming a third sub-bonding layer on one side of the second interconnect layer along the first direction; forming a fifth groove in the third sub-bonding layer, the fifth groove exposing the second interconnect structure; forming a first conductive layer in the fifth groove and on a portion of the surface of the third sub-bonding layer; forming a dielectric layer on the surface of the first conductive layer; and forming a second electrode layer on the surface of the dielectric layer to form a second MIM structure.

[0020] In some embodiments, the method further includes: forming a fourth sub-bonding layer on the third sub-bonding layer; forming a sixth groove in the fourth sub-bonding layer, the sixth groove exposing the second MIM structure located on a portion of the surface of the third sub-bonding layer; forming a second conductive structure in the sixth groove; the second conductive structure being connected to the second MIM structure; wherein the third sub-bonding layer and the fourth sub-bonding layer constitute the second bonding layer.

[0021] In some embodiments, the method further includes: forming a seventh groove in the second bonding layer; the seventh groove being spaced apart from the sixth groove; forming a fourth conductive structure in the seventh groove; and the fourth conductive structure being electrically isolated from the second conductive structure.

[0022] In some embodiments, the method further includes: forming an eighth groove in the second bonding layer; the eighth groove communicating with the fifth groove; forming a sixth conductive structure in the eighth groove; and the sixth conductive structure being connected to the second conductive structure.

[0023] In this embodiment, by adding a first MIM structure to the first bonding layer, the utilization rate of the first bonding layer is improved, and / or by adding a second MIM structure to the second bonding layer, the utilization rate of the second bonding layer is improved, without requiring additional space occupied by the first semiconductor structure, the second semiconductor structure device region, or the substrate region. Furthermore, designing the MIM structure in the bonding layer, compared to designing it in the substrate, other dielectric layers, or passivation layers, reduces the space occupied by other device structures and metal interconnect structures, and reduces electrical interference or bridging risks between the MIM structure and other devices and metal interconnect structures, thereby increasing the utilization rate of the semiconductor device. Additionally, the first and second MIM structures can be connected using the conductive structures in their respective bonding layers, eliminating the need for additional design and addition of MIM structure lead wires, saving the process steps of "forming contact holes for the positive and negative terminals of the capacitor and connecting the capacitor to the circuit," without increasing the process difficulty. Moreover, the first and second MIM structures can resist voltage fluctuations, thus preventing the semiconductor device from being affected by voltage signal instability and improving the reliability of the semiconductor device. Attached Figure Description

[0024] Figure 1 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ; Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ; Figure 3 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 3 ; Figure 4 A schematic diagram of the manufacturing process of a semiconductor device provided in an embodiment of this disclosure; Figure 5 This is a cross-sectional schematic diagram of a first functional layer provided in an embodiment of the present disclosure; Figure 6 This is a schematic cross-sectional view of the formation of a first sub-bonding layer according to an embodiment of the present disclosure; Figure 7 This is a cross-sectional schematic diagram of the formation of a first groove according to an embodiment of the present disclosure; Figure 8 This is a cross-sectional schematic diagram of the formation of a first conductive material layer according to an embodiment of the present disclosure; Figure 9 This is a schematic cross-sectional view of the formation of an insulating material layer according to an embodiment of the present disclosure; Figure 10 This is a cross-sectional schematic diagram of the formation of a first electrode layer according to an embodiment of the present disclosure; Figure 11This is a schematic cross-sectional view of the formation of a second sub-bonding layer according to an embodiment of the present disclosure; Figure 12 This is a cross-sectional schematic diagram of the planarization process of the second sub-bonding layer provided in an embodiment of the present disclosure; Figure 13 This is a cross-sectional schematic diagram of the formation of a third groove according to an embodiment of the present disclosure; Figure 14 This is a cross-sectional schematic diagram of the formation of the second groove provided in an embodiment of the present disclosure; Figure 15 This is a cross-sectional schematic diagram of the formation of a first conductive structure according to an embodiment of the present disclosure; Figure 16 This is a cross-sectional schematic diagram of the formation of the fourth groove provided in an embodiment of the present disclosure; Figure 17 This is a cross-sectional schematic diagram of the formation of a fifth conductive structure according to an embodiment of the present disclosure; Figure 18 This is a schematic diagram of the bonding between a first semiconductor structure and a second semiconductor structure provided in an embodiment of the present disclosure.

[0025] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0030] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0033] It should be understood that the bonding process for wafers places extremely high demands on the flatness of the wafer surface. For example, in the bonding process between the first and second wafers, a bonding layer is typically formed on the side where the two wafers meet, followed by planarization using chemical mechanical polishing (CMP) to meet the surface flatness requirements of the bonding technology. Subsequent processes form bonding contacts and conductive structures within the bonding layer, achieving electrical connection between the two wafers through the connection of these contacts and conductive structures. However, due to the limited area occupied by the bonding contacts and conductive structures, the utilization rate of the bonding layer is relatively low.

[0034] Based on this, in order to solve one or more of the above problems, this disclosure provides a semiconductor device, which includes: a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure includes: a first bonding layer and a first conductive structure located in the first bonding layer; the second semiconductor structure includes: a second bonding layer and a second conductive structure located in the second bonding layer; one end of the first conductive structure is bonded to one end of the second conductive structure; wherein, the semiconductor device further includes: a first MIM structure located in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or, a second MIM structure located in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

[0035] Thus, by adding a first MIM structure to the first bonding layer, the utilization rate of the first bonding layer is improved, and / or by adding a second MIM structure to the second bonding layer, the utilization rate of the second bonding layer is improved, without requiring additional space in the device regions of the first semiconductor structure, the second semiconductor structure, or the substrate region. Furthermore, designing the MIM structure in the bonding layer, compared to designing it in the substrate, other dielectric layers, or passivation layers, reduces the space occupied by other device structures and metal interconnect structures, and reduces electrical interference or bridging risks between the MIM structure and other devices or metal interconnect structures, thereby increasing the utilization rate of the semiconductor device. Additionally, the first and second MIM structures can be connected using the conductive structures in their respective bonding layers, eliminating the need for additional design and addition of lead wires for the MIM structure, saving the process steps of "forming contact holes for the positive and negative terminals of the capacitor and connecting the capacitor to the circuit," without increasing the process complexity. Moreover, the first and second MIM structures can resist voltage fluctuations, thus preventing the semiconductor device from being affected by voltage signal instability and improving its reliability.

[0036] To make the above-described objects, features, and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Before introducing the semiconductor device illustrated in the drawings, various directions that may be used in the following description are defined. The stacking direction of the semiconductor structure is defined as a first direction (i.e., the Z-axis direction), and intersecting second directions (i.e., the X-axis direction) and third directions (i.e., the Y-axis direction) are defined in a plane perpendicular to the first direction. In some embodiments, the first direction, the second direction, and the third direction may be mutually perpendicular, i.e., the X-axis direction, the Y-axis direction, and the Z-axis direction are mutually perpendicular.

[0037] refer to Figure 1 , Figure 1 This is a schematic cross-sectional structure diagram of a semiconductor device provided as an example of this disclosure. Figure 1 The diagram shows cross-sectional schematics of semiconductor devices in three different scenarios on the XZ plane, as shown in Figures (a), (b), and (c). Figure 1 In Figure (a), a first MIM structure 110 is provided in the first bonding layer, and a second MIM structure is not provided in the second bonding layer. Figure 1 In Figure (b), the first bonding layer does not have a first MIM structure, while the second bonding layer has a second MIM structure 210. Figure 1 In Figure (c), a first MIM structure 110 is provided in the first bonding layer, and a second MIM structure 210 is provided in the second bonding layer.

[0038] like Figure 1 As shown, a semiconductor device may include a first semiconductor structure 100 and a second semiconductor structure 200, which are stacked along the Z-axis. The first semiconductor structure 100 and the second semiconductor structure 200 can be connected to each other perpendicularly using bonding techniques. This reduces the planar dimensions of the semiconductor device and improves integration density. Here, bonding techniques include, for example, hybrid bonding (also known as "metal / dielectric hybrid bonding"), a direct bonding technique that forms bonds between surfaces without the use of intermediate layers such as solder or adhesive, and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding.

[0039] The first semiconductor structure 100 may include a first functional layer 102, which may contain peripheral circuits and / or a memory cell array. The peripheral circuits may include multiple CMOS transistors and related control circuits, such as control logic, sensing amplifier circuits, row decoders, column decoders, data input / output buffers, drivers, and read / write circuits. When the control logic receives read / write operation commands and address data, under the control of the control logic, the row decoder or column decoder can apply the corresponding voltage generated by the driver to the corresponding bit line or word line based on the decoded address to achieve data reading or writing, and interact with external devices through the data input / output buffers. The memory cell array may include multiple memory cells, such as NAND memory cells, PCM memory cells, and DRAM memory cells. For ease of understanding, the following embodiments use the example of peripheral circuits in the first functional layer 102 for illustrative purposes.

[0040] In other embodiments, the first functional layer 102 may not have peripheral circuits, but instead may have other circuits or devices. This disclosure does not limit this. It should be understood that the description of peripheral circuits in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise specified, in various embodiments of this disclosure, peripheral circuits may be replaced with other circuits or devices.

[0041] The first semiconductor structure 100 may further include a first interconnect layer 104, which is located on one side of the first functional layer 102 along the Z-axis. The first interconnect layer 104 has multiple interconnect structures, which are electrically isolated from each other, such as a first interconnect structure 112 and a third interconnect structure 114, etc., with the first interconnect structure 112 and the third interconnect structure 114 being electrically isolated from each other. The interconnect structures in the first interconnect layer 104 may include lateral wires and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first interconnect layer 104 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Here, the peripheral circuitry in the first functional layer 102 can be connected to the interconnect structures in the first interconnect layer 104 in any suitable manner.

[0042] The first semiconductor structure 100 may further include a first bonding layer 106, which is located on the side of the first interconnect layer 104 away from the first functional layer 102 along the Z-axis. The first bonding layer 106 has multiple conductive structures disposed therein, which are electrically isolated from each other; such as a first conductive structure 108, a third conductive structure 116, etc., where the first conductive structure 108 and the third conductive structure 116 are electrically isolated from each other. The conductive structures in the first bonding layer 106 may extend along the Z-axis for transmitting electrical signals. These conductive structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Here, the interconnect structures in the first interconnect layer 104 may be connected to the conductive structures in the first bonding layer 106 in any suitable manner.

[0043] In some embodiments, such as Figure 1 As shown in Figures (a), (b), and (c), the third conductive structure 116 penetrates the first bonding layer 106 along the Z-axis. At the opposite ends of the third conductive structure 116 along the Z-axis, one end is connected to the third interconnect structure 114, and the other end can be connected to structures in other layers (such as the fourth conductive structure 216).

[0044] In some embodiments, such as Figure 1 As shown in Figures (a) and (c), a first MIM structure 110 is further provided in the first bonding layer 106. One end of the first MIM structure 110 can be connected to one end of the first conductive structure 108 along the Z-axis, and the other end of the first MIM structure 110 can be connected to the first interconnect structure 112. In other words, the first MIM structure 110 is located between the first conductive structure 108 and the first interconnect structure 112. Here, one end of the first conductive structure 108 along the Z-axis is connected to the first MIM structure, and the other end along the Z-axis can be connected to structures in other layers (such as the second conductive structure 208).

[0045] In some embodiments, the first bonding layer 106 may include one or more first MIM structures 110 to improve the compatibility of the first semiconductor structure.

[0046] In some embodiments, such as Figure 1 As shown in Figure (b), the first MIM structure 110 is not provided in the first bonding layer 106. In this case, the first conductive structure 108 can penetrate the first bonding layer 106 along the Z-axis direction. The two ends of the first conductive structure 108 along the Z-axis direction can be connected to the structures in other layers. For example, one end of the two ends of the first conductive structure 108 along the Z-axis direction is connected to the second conductive structure 208, and the other end is connected to the first interconnect structure 112.

[0047] In some embodiments, the first MIM structure 110 is a capacitor structure. Here, the first MIM structure 110 may include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the first MIM structure 110; the dielectric layer can be used as the dielectric of the first MIM structure 110; and the second electrode layer can be used as the upper electrode of the first MIM structure 110. Exemplarily, the constituent materials of both the first electrode layer and the second electrode layer include, but are not limited to, titanium nitride. The constituent materials of the dielectric layer include high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are typically significantly higher than this value. In some specific examples, the constituent materials of the dielectric layer may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.

[0048] In some embodiments, the first MIM structure 110 may take on a variety of different shapes, such as a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL), which are not limited in this disclosure.

[0049] In some specific embodiments, reference is made to Figure 1 In Figure (a), when the semiconductor device includes only the first MIM structure 110, the first electrode layer of the first MIM structure 110 is connected to the first interconnect structure 112; the second electrode layer of the first MIM structure 110 is connected to the other end of the first conductive structure 108. At this time, the second conductive structure 208 is directly connected to the second interconnect structure 212.

[0050] Based on this, in the embodiments of this disclosure, the peripheral circuit can be coupled to external devices through the first interconnect structure 112, the first MIM structure 110, and the first conductive structure 108; or it can be coupled to external devices through the third interconnect structure 114 and the third conductive structure 116.

[0051] The second semiconductor structure 200 may include a second functional layer 202, which may contain peripheral circuits and / or memory cell arrays. The peripheral circuits and memory cell arrays have already been described and will not be repeated here. For ease of understanding, the following embodiments use a memory cell array in the second functional layer 202 as an example for illustrative purposes.

[0052] In other embodiments, the second functional layer 202 may not include a memory cell array, but instead may include other circuits or devices, which is not limited in this disclosure. It should be understood that the description of the memory cell array in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise specified, the memory cell array may be replaced by other circuits or devices in various embodiments of this disclosure.

[0053] The second semiconductor structure 200 may further include a second interconnect layer 204, which is located on one side of the second functional layer 202 along the Z-axis. The second interconnect layer 204 contains multiple interconnect structures, which are electrically isolated from each other, such as a second interconnect structure 212 and a fourth interconnect structure 214, with the second interconnect structure 212 and the fourth interconnect structure 214 being electrically isolated from each other. The interconnect structures in the second interconnect layer 204 may include lateral wires and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the second interconnect layer 204 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Here, the memory cell array in the second functional layer 202 can be connected to the interconnect structures in the second interconnect layer 204 in any suitable manner.

[0054] The second semiconductor structure 200 may further include a second bonding layer 206, which is located on the side of the second interconnect layer 204 away from the second functional layer 202 along the Z-axis. The second bonding layer 206 has multiple conductive structures disposed therein, which are electrically isolated from each other; such as a second conductive structure 208, a fourth conductive structure 216, etc., where the second conductive structure 208 and the fourth conductive structure 216 are electrically isolated from each other. The conductive structures in the second bonding layer 206 may extend along the Z-axis for transmitting electrical signals. These conductive structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Here, the interconnect structures in the second interconnect layer 204 may be connected to the conductive structures in the second bonding layer 206 in any suitable manner.

[0055] In some embodiments, such as Figure 1 As shown in Figures (a), (b), and (c), the fourth conductive structure 216 penetrates the second bonding layer 206 along the Z-axis. At one end of the fourth conductive structure 216 along the Z-axis, it is connected to the fourth interconnect structure 214, and the other end can be connected to structures in other layers (such as the third conductive structure 116).

[0056] In some embodiments, such as Figure 1As shown in Figure (a), the second MIM structure 210 is not provided in the second bonding layer 206. At this time, the second conductive structure 208 can penetrate the second bonding layer 206 along the Z-axis direction. The two ends of the second conductive structure 208 along the Z-axis direction can be connected to the structures in other layers. For example, one end of the two ends of the second conductive structure 208 along the Z-axis direction is connected to the first conductive structure 108, and the other end is connected to the second interconnect structure 212.

[0057] In some embodiments, such as Figure 1 As shown in Figures (b) and (c), a second MIM structure 210 is further provided in the second bonding layer 206. One end of the second MIM structure 210 can be connected to one end of the second conductive structure 208 along the Z-axis, and the other end of the second MIM structure 210 can be connected to the second interconnect structure 212. In other words, the second MIM structure 210 is located between the second conductive structure 208 and the second interconnect structure 212. The second conductive structure 208 is connected to the second MIM structure along the Z-axis, and the other end along the Z-axis can be connected to structures in other layers (such as the first conductive structure 108).

[0058] In some embodiments, the second bonding layer 206 may include one or more second MIM structures 210 to improve the compatibility of the second semiconductor structure.

[0059] In some embodiments, the second MIM structure 210 is a capacitor structure. Here, the second MIM structure 210 may include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the second MIM structure 210; the dielectric layer can be used as the dielectric of the second MIM structure 210; and the second electrode layer can be used as the upper electrode of the second MIM structure 210. Exemplarily, the constituent materials of both the first electrode layer and the second electrode layer include, but are not limited to, titanium nitride. The constituent materials of the dielectric layer include high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are typically significantly higher than this value. In some specific examples, the constituent materials of the dielectric layer may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.

[0060] In some embodiments, the second MIM structure 210 may take on a variety of different shapes, such as a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL), which are not limited in this disclosure.

[0061] In some specific embodiments, reference is made to Figure 1In Figure (b), when the semiconductor device includes only the second MIM structure 210, the first electrode layer of the second MIM structure 210 is connected to the second interconnect structure 212; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure 208; at this time, the first conductive structure 108 is directly connected to the first interconnect structure 112.

[0062] In some specific embodiments, reference is made to Figure 1 In Figure (c), when the semiconductor device includes a first MIM structure 110 and a second MIM structure 210, the first electrode layer of the first MIM structure 110 is connected to the first interconnect structure 112; the second electrode layer of the first MIM structure 110 is connected to the other end of the first conductive structure 108; the first electrode layer of the second MIM structure 210 is connected to the second interconnect structure 212; and the second electrode layer of the second MIM structure 210 is connected to the other end of the second conductive structure 208.

[0063] Based on this, in this embodiment of the disclosure, the memory cell array can be coupled to external devices through the second interconnect structure 212, the second MIM structure 210, and the second conductive structure 208; or it can be coupled to external devices through the fourth interconnect structure 214 and the fourth conductive structure 216.

[0064] It should be noted that after the first semiconductor structure 100 and the second semiconductor structure 200 are stacked and bonded, the first conductive structure 108 is bonded to the second conductive structure 208, and the third conductive structure 116 is bonded to the fourth conductive structure 216. The third conductive structure 116 is connected to the third interconnect structure 114, and the fourth conductive structure 216 is connected to the fourth interconnect structure 214.

[0065] In other words, the peripheral circuit can be connected to the memory cell array through the connection of the third interconnect structure 114, the third conductive structure 116, the fourth conductive structure 216, and the fourth interconnect structure 214; it can also be connected to the memory cell array through the connection of the first interconnect structure 112, the first MIM structure 110, the first conductive structure 108, the second conductive structure 208, and the second interconnect structure 212; it can also be connected to the memory cell array through the connection of the first interconnect structure 112, the first conductive structure 108, the second conductive structure 208, the second MIM structure 210, and the second interconnect structure 212; and it can also be connected to the memory cell array through the connection of the first interconnect structure 112, the first MIM structure 110, the first conductive structure 108, the second conductive structure 208, the second MIM structure 210, and the second interconnect structure 212.

[0066] In some embodiments, the first semiconductor structure 100 can be a wafer, and the second semiconductor structure 200 can be a wafer, i.e. Figure 1 The semiconductor device shown is a wafer-to-wafer bonding stack (W2W).

[0067] In the above embodiments, the connection paths of the third interconnect structure, the third conductive structure, the fourth conductive structure, and the fourth interconnect structure are not connected to the first MIM structure and / or the second MIM structure. In other embodiments, refer to Figure 2 This connection path can also be connected to the first MIM structure and / or the second MIM structure.

[0068] In some embodiments, reference Figure 2 , Figure 2 This is a schematic diagram of another semiconductor device cross-sectional structure provided as an example of this disclosure. Figure 2 The diagram shows cross-sectional schematics of semiconductor devices in three different scenarios on the XZ plane, as shown in Figures (a), (b), and (c). Figure 2 In Figure (a), a first MIM structure 310 is provided in the first bonding layer, and a second MIM structure is not provided in the second bonding layer. Figure 2 In Figure (b), the first bonding layer does not have a first MIM structure, while the second bonding layer has a second MIM structure 410. Figure 2 In Figure (c), a first MIM structure 310 is provided in the first bonding layer, and a second MIM structure 410 is provided in the second bonding layer.

[0069] refer to Figure 2 The semiconductor device may include a first semiconductor structure 300 and a second semiconductor structure 400, which are stacked along the Z-axis. The first semiconductor structure 300 and the second semiconductor structure 400 can be perpendicularly stacked and connected to each other using the bonding technology described above. This reduces the planar dimensions of the semiconductor device and improves integration density.

[0070] The first semiconductor structure 300 may include a first functional layer 302, which may contain peripheral circuits and / or a memory cell array. For ease of understanding, the following embodiments use the example of a first functional layer 302 containing peripheral circuits for illustrative purposes.

[0071] The first semiconductor structure 300 may further include a first interconnect layer 304, which is located on one side of the first functional layer 302 along the Z-axis. The first interconnect layer 304 has multiple interconnect structures, which are electrically isolated from each other, such as a first interconnect structure 312 and a third interconnect structure 314, etc., with the first interconnect structure 312 and the third interconnect structure 314 being electrically isolated from each other. The interconnect structures in the first interconnect layer 304 may include lateral wires and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first interconnect layer 304 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Here, the peripheral circuitry in the first functional layer 302 can be connected to the interconnect structures in the first interconnect layer 304 in any suitable manner.

[0072] The first semiconductor structure 300 may further include a first bonding layer 306, which is located on the side of the first interconnect layer 304 away from the first functional layer 302 along the Z-axis. The first bonding layer 306 has multiple conductive structures, such as a first conductive structure 308 and a fifth conductive structure 316, where the first conductive structure 308 and the fifth conductive structure 316 are connected. The conductive structures in the first bonding layer 306 may extend along the Z-axis for transmitting electrical signals. These conductive structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Here, the interconnect structures in the first interconnect layer 304 may be connected to the conductive structures in the first bonding layer 306 in any suitable manner.

[0073] In some embodiments, such as Figure 2 As shown in Figures (a), (b), and (c), the fifth conductive structure 316 penetrates the first bonding layer 306 along the Z-axis direction; one end of the fifth conductive structure 316 along the Z-axis direction is connected to the third interconnect structure 314, and the other end can be connected to structures in other layers (such as the sixth conductive structure 416); one end of the fifth conductive structure 316 along the X-axis / Y-axis direction is connected to the first conductive structure 308.

[0074] In some embodiments, such as Figure 2As shown in Figures (a) and (c), a first MIM structure 310 is further provided in the first bonding layer 306. One end of the first MIM structure 310 can be connected to one end of the first conductive structure 308 along the Z-axis, and the other end of the first MIM structure 310 can be connected to the first interconnect structure 312. In other words, the first MIM structure 310 is located between the first conductive structure 308 and the first interconnect structure 312. The first conductive structure 308 is connected to the first MIM structure along the Z-axis, and the other end along the Z-axis can be connected to structures in other layers (such as the second conductive structure 408). In this embodiment, the first MIM structure 310 can be connected to the fifth conductive structure 316.

[0075] In some embodiments, the first bonding layer 306 may include one or more first MIM structures 310.

[0076] In some embodiments, such as Figure 2 As shown in Figure (b), the first MIM structure 310 is not provided in the first bonding layer 306. In this case, one end of the first conductive structure 308 along the Z-axis is connected to the second conductive structure 408, and the other end can be coupled to other interconnect structures (not shown in the figure). One end of the first conductive structure 308 along the X-axis / Y-axis is connected to the fifth conductive structure 316.

[0077] In some embodiments, the first MIM structure 310 includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the first MIM structure 310; the dielectric layer can be used as the dielectric of the first MIM structure 310; and the second electrode layer can be used as the upper electrode of the first MIM structure 310.

[0078] In some specific embodiments, reference is made to Figure 2 In Figure (a), when the semiconductor device includes only the first MIM structure 310, the first electrode layer of the first MIM structure 310 is connected to the first interconnect structure 312; the second electrode layer of the first MIM structure 310 is connected to the other end of the first conductive structure 308. At this time, the second conductive structure 408 is connected to the sixth conductive structure 416. Based on this, in this embodiment of the present disclosure, the peripheral circuit can be coupled to an external device through the first MIM structure 310.

[0079] The second semiconductor structure 400 may include a second functional layer 402, which may contain peripheral circuits and / or a memory cell array. The peripheral circuits and memory cell array have been described previously and will not be repeated here. For ease of understanding, the following embodiments use a memory cell array in the second functional layer 402 as an example for illustrative purposes.

[0080] The second semiconductor structure 400 may further include a second interconnect layer 404, which is located on one side of the second functional layer 402 along the Z-axis. The second interconnect layer 404 contains multiple interconnect structures, which are electrically isolated from each other, such as a second interconnect structure 412 and a fourth interconnect structure 414, with the second interconnect structure 412 and the fourth interconnect structure 414 being electrically isolated from each other. The interconnect structures in the second interconnect layer 404 may include lateral wires and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the second interconnect layer 404 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Here, the memory cell array in the second functional layer 402 can be connected to the interconnect structures in the second interconnect layer 404 in any suitable manner.

[0081] The second semiconductor structure 400 may further include a second bonding layer 406, which is located on the side of the second interconnect layer 404 away from the second functional layer 402 along the Z-axis. The second bonding layer 406 has multiple conductive structures, such as a second conductive structure 408 and a sixth conductive structure 416, where the second conductive structure 408 and the sixth conductive structure 416 are connected. The conductive structures in the second bonding layer 406 can extend along the Z-axis for transmitting electrical signals. These conductive structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The interconnect structures in the second interconnect layer 404 can be connected to the conductive structures in the second bonding layer 406 in any suitable manner.

[0082] In some embodiments, such as Figure 2 As shown in Figures (a), (b), and (c), the sixth conductive structure 416 penetrates the second bonding layer 406 along the Z-axis. At one end of the sixth conductive structure 416 along the Z-axis, it is connected to the fourth interconnect structure 414, and the other end can be connected to structures in other layers (such as the fifth conductive structure 316). At one end of the sixth conductive structure 416 along the X-axis / Y-axis, it is connected to the second conductive structure 408.

[0083] In some embodiments, such as Figure 2 As shown in Figure (a), the second MIM structure 410 is not provided in the second bonding layer 406. At this time, one end of the second conductive structure 408 is connected to the first conductive structure 308, and the other end is connected to the sixth conductive structure 416.

[0084] In some embodiments, such as Figure 2 As shown in Figures (b) and (c), a second MIM structure 410 is further provided in the second bonding layer 406. One end of the second MIM structure 410 can be connected to one end of the second conductive structure 408 along the Z-axis, and the other end of the second MIM structure 410 can be connected to the second interconnect structure 412. In other words, the second MIM structure 410 is located between the second conductive structure 408 and the second interconnect structure 412. The second conductive structure 408 is connected to the second MIM structure along the Z-axis, and the other end along the Z-axis can be connected to structures in other layers (such as the first conductive structure 308).

[0085] In some embodiments, the second bonding layer 406 may include one or more second MIM structures 410.

[0086] In some embodiments, the second MIM structure 410 includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the second MIM structure 410; the dielectric layer can be used as the dielectric of the second MIM structure 410; and the second electrode layer can be used as the upper electrode of the second MIM structure 410.

[0087] In some specific embodiments, reference is made to Figure 2 In Figure (b), when the semiconductor device includes only the second MIM structure 410, the first electrode layer of the second MIM structure 410 is connected to the second interconnect structure 412; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure 408; at this time, the first conductive structure 308 is directly connected to the fifth conductive structure 316.

[0088] In some specific embodiments, reference is made to Figure 2 In Figure (c), when the semiconductor device includes a first MIM structure 310 and a second MIM structure 410, the first electrode layer of the first MIM structure 310 is connected to the first interconnect structure 312; the second electrode layer of the first MIM structure 310 is connected to the other end of the first conductive structure 308; the first electrode layer of the second MIM structure 410 is connected to the second interconnect structure 412; and the second electrode layer of the second MIM structure 410 is connected to the other end of the second conductive structure 408. Here, the first conductive structure 308 is also connected to the fifth conductive structure 316, and the second conductive structure 408 is connected to the sixth conductive structure 416. Based on this, in this embodiment of the present disclosure, the memory cell array can be coupled to an external device through the second MIM structure 410.

[0089] It should be noted that after the first semiconductor structure 300 and the second semiconductor structure 400 are stacked and bonded, the first conductive structure 308 is bonded to the second conductive structure 408, and the fifth conductive structure 316 is bonded to the sixth conductive structure 416. The fifth conductive structure 316 is connected to the third interconnect structure 314, and the sixth conductive structure is connected to the fourth interconnect structure 414. In this way, the peripheral circuit can be connected to the memory cell array through multiple connection methods.

[0090] In some embodiments, the first semiconductor structure 300 can be a wafer, and the second semiconductor structure 400 can be a wafer, i.e. Figure 2 The semiconductor device shown is a wafer-to-wafer bonding stack (W2W).

[0091] It should be noted that, Figure 1 In the semiconductor device shown, the peripheral circuit can be connected to the memory cell array through a MIM structure or without a MIM structure, thus improving the connection flexibility of the peripheral circuit. Figure 2 In the semiconductor device shown, the peripheral circuitry is connected to the memory cell array via a MIM structure. The MIM structure acts as a resistor against voltage fluctuations, thus preventing the semiconductor device from being affected by voltage signal instability and improving its reliability. Furthermore, the first and / or second MIM structures can be led out using the first and second conductive structures, eliminating the need for additional design and lead wires, and reducing process complexity. Moreover, adding MIM structures within the bonding layer increases the utilization rate of the bonding layer and the overall utilization rate of the semiconductor device. Compared to designing the MIM structure in the substrate device region, other dielectric layers, or passivation layers, it reduces the space occupied by the MIM structure on other device structures and metal interconnect structures, and reduces electrical interference or bridging risks between the MIM capacitor structure and other devices and metal interconnect structures. In addition, because the wiring density of the first and second conductive structures at the bonding interface is lower than that in the substrate device region, other dielectric layers, or passivation layers, and the bonding layer has a higher layer height than other dielectric layers or passivation layers, a larger charge storage capacity can be designed for the MIM structure at the same level, making the MIM structure more effective at resisting voltage fluctuations.

[0092] In some embodiments, reference Figure 3 , Figure 3 This is a schematic cross-sectional view of another semiconductor device provided by way of example in this disclosure. The semiconductor device may include a first semiconductor structure 600 and a plurality of second semiconductor structures 602; the plurality of second semiconductor structures 602 are separated from each other by an isolation structure 604. The isolation structure 604 may be any suitable material, such as an air gap.

[0093] In some specific embodiments, the first semiconductor structure 600 can be a wafer, and the second semiconductor structure 602 can be a chip, i.e. Figure 3 The semiconductor device shown is a bonded stack of a wafer and multiple chips (C2W).

[0094] refer to Figure 3 , Figure 3 The diagram shows cross-sectional schematics of semiconductor devices in three different scenarios on the XZ plane, as shown in Figures (a), (b), and (c). Figure 3 In Figure (a), a first MIM structure 606 is provided in the first bonding layer, and a second MIM structure is not provided in the second bonding layer. Figure 3 In Figure (b), the first bonding layer does not have a first MIM structure, while the second bonding layer has a second MIM structure 608. Figure 3 In Figure (c), a first MIM structure 606 is provided in the first bonding layer, and a second MIM structure 608 is provided in the second bonding layer.

[0095] Based on the above-described semiconductor device, this disclosure also provides a method for manufacturing a semiconductor device. Figure 4 This is a schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of this disclosure; as shown Figure 4 As shown, the manufacturing method includes the following steps: Step S501: Form a first semiconductor structure; the first semiconductor structure includes: a first bonding layer, and a first conductive structure located in the first bonding layer.

[0096] Step S502: Form a second semiconductor structure; the second semiconductor structure includes: a second bonding layer, and a second conductive structure located in the second bonding layer.

[0097] Step S503: Stack the first semiconductor structure and the second semiconductor structure along the first direction so that one end of the first conductive structure is bonded to one end of the second conductive structure.

[0098] Step S504: The method further includes: forming a first MIM structure in a first bonding layer, wherein the first MIM structure is connected to the other end of a first conductive structure; and / or forming a second MIM structure in a second bonding layer, wherein the second MIM structure is connected to the other end of a second conductive structure.

[0099] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs. Figures 5 to 18 This is a schematic diagram of the manufacturing process of a semiconductor device provided in the embodiments of this disclosure. The following is in conjunction with... Figures 4 to 18 A method for manufacturing a semiconductor device according to embodiments of this disclosure will be described.

[0100] In some embodiments, reference Figure 5 The method includes providing a first functional layer 701, in which peripheral circuitry or a memory cell array is configured. The peripheral circuitry may include multiple CMOS transistors and related control circuitry, such as control logic, sensing amplifier circuitry, row decoders, column decoders, data input / output buffers, drivers, and read / write circuits. When the control logic receives read / write operation commands and address data, under the control of the control logic, the row decoder or column decoder can apply the corresponding voltage generated by the driver to the corresponding bit line or word line based on the decoded address to achieve data reading or writing, and interact with external devices through the data input / output buffers. The memory cell array may include multiple memory cells, such as NAND memory cells, PCM memory cells, and DRAM memory cells. Methods for forming peripheral circuitry or memory cell arrays are relatively mature and will not be elaborated here.

[0101] In other embodiments, the first functional layer may not include peripheral circuits, but instead may include other circuits or devices; this disclosure does not limit this. It should be understood that the descriptions of peripheral circuits in the following embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Unless otherwise specified, in various embodiments of this disclosure, peripheral circuits may be replaced with other circuits or devices.

[0102] In some embodiments, reference Figure 5The method further includes forming a first interconnect layer 702 on one side of the first functional layer 701 along the Z-axis. Multiple interconnect structures, such as a first interconnect structure 703 and a third interconnect structure 704, are formed in the first interconnect layer 702, and the first interconnect structure 703 and the third interconnect structure 704 are electrically isolated from each other. The interconnect structures in the first interconnect layer 702 may include lateral conductors and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first interconnect layer 702 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The methods for forming the first interconnect layer 702 include, but are not limited to, deposition processes, including chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) processes.

[0103] In some embodiments, reference Figure 6 The method further includes forming a first sub-bonding layer 705 on one side of the first interconnect layer along the Z-axis direction. The material of the first sub-bonding layer 705 includes, but is not limited to, silicon oxide. Methods for forming the first sub-bonding layer 705 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0104] In some embodiments, reference Figure 7 The method further includes forming a first groove 706 in the first sub-bonding layer 705, the first groove 706 exposing the first interconnect structure 703. The method for forming the first groove 706 includes, but is not limited to, etching.

[0105] In some embodiments, reference Figure 8The method further includes: forming a first conductive material layer 7071 in the first groove 706 and on the surface of the first sub-bonding layer 705; forming a dielectric material layer 7072 on the surface of the first conductive material layer; and forming a second electrode material layer 7073 on the surface of the dielectric material layer 7072. The constituent materials of the first electrode material layer and the second electrode material layer are, but are not limited to, titanium nitride. The constituent materials of the dielectric material layer include high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some examples, the constituent materials of the dielectric material layer may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The methods for forming the first conductive material layer 7071, the dielectric material layer 7072, and the second electrode material layer 7073 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD processes, etc.

[0106] In some embodiments, reference Figure 9 The method further includes forming an insulating material layer 708 on the surface of the second electrode material layer 7073. The constituent materials of the insulating material layer 708 include, but are not limited to, silicon oxide. Methods for forming the insulating material layer 708 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0107] In some embodiments, reference Figure 10 The method further includes: removing a portion of the first conductive material layer 7071 to form a first electrode layer 7074, removing a portion of the dielectric material layer 7072 to form a dielectric layer 7075, and removing a portion of the second electrode material layer 7073 to form a second electrode layer 7076. Here, the first electrode layer 7074, the dielectric layer 7075, and the second electrode layer 7076 constitute a first MIM structure. The first electrode layer can be used as the lower electrode of the first MIM structure; the dielectric layer can be used as the dielectric of the first MIM structure; and the second electrode layer can be used as the upper electrode of the first MIM structure.

[0108] Continue to refer to Figure 10 The method further includes removing a portion of the insulating material layer 708 to form an insulating layer 709. The insulating layer 709 covers the surface of the first MIM structure 707 and serves to isolate and protect the first MIM structure. Here, the removal process includes, but is not limited to, etching.

[0109] In some embodiments, reference Figure 11The method further includes: forming a second sub-bonding layer 710 on the first sub-bonding layer 705, wherein the second sub-bonding layer 710 covers the exposed first sub-bonding layer 705 and the covering insulating layer 709. The material of the second sub-bonding layer 710 can be the same as the material of the first sub-bonding layer 705, such as silicon oxide. Methods for forming the second sub-bonding layer 710 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0110] In some embodiments, reference Figure 12 The method further includes: planarizing the surface of the second sub-bonding layer 710; here, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP). (See reference...) Figure 12 The planarized second sub-bonding layer 710 and the first sub-bonding layer 705 together form the first bonding layer 711.

[0111] In some embodiments, reference Figure 13 The method further includes forming a third groove 712 in the first bonding layer 711. The third groove 712 is located on one side of the first MIM structure 707 along the X-axis and / or Y-axis direction. The third groove 712 penetrates the first bonding layer 711 along the Z-axis direction. The method for forming the third groove 712 includes, but is not limited to, etching.

[0112] In some embodiments, reference Figure 14 The method further includes forming a second groove 713 in the second sub-bonding layer 710, the second groove 713 penetrating the second sub-bonding layer 710 and the insulating layer 709 along the Z-axis direction and exposing one end of the first MIM structure 707; exemplaryly, the second groove 713 exposes the second electrode layer of the first MIM structure 707. The method for forming the second groove 713 includes, but is not limited to, etching. Here, the third groove 712 is isolated from the second groove 713. It should be noted that the formation order of the second groove 713 and the third groove 712 can be selected according to actual needs, and this disclosure does not limit it.

[0113] In some embodiments, reference Figure 15The method further includes: forming a first conductive structure 714 in the second groove 713; the first conductive structure 714 is connected to one end of the first MIM structure 707, and the other end of the first MIM structure 707 is connected to the first interconnect structure 703. Specifically, the first conductive structure 714 is connected to the second electrode layer of the first MIM structure 707. The first electrode layer of the first MIM structure 707 is connected to the first interconnect structure 703. The constituent materials of the first conductive structure 714 include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The methods for forming the first conductive structure 714 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD processes, etc.

[0114] Continue to refer to Figure 15 The method further includes forming a third conductive structure 715 in a third groove 712. The third conductive structure 715 penetrates the first bonding layer 711 along the Z-axis direction, and one end of the third conductive structure 715 is connected to a third interconnect structure 704. Here, the third conductive structure 715 is electrically isolated from the first conductive structure 714. The constituent materials of the third conductive structure 715 include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The methods for forming the third conductive structure 715 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD processes, etc. Here, the first conductive structure 714 and the third conductive structure 715 can be formed in the same process to save process steps and manufacturing time. They can also be formed in different process processes to improve process reliability. In addition, if they are formed in different process processes, their manufacturing order can be selected according to actual conditions. In this way, a first semiconductor structure 700 is formed.

[0115] In other embodiments, reference is made to Figure 16 The method further includes: forming a fourth groove 716 in the first bonding layer 711; the fourth groove 716 is connected to the second groove 713; the method for forming the fourth groove 716 includes, but is not limited to, etching.

[0116] In some embodiments, reference Figure 17 The method further includes: forming a fifth conductive structure 717 in the fourth groove 716; the fifth conductive structure 717 being connected to the first conductive structure 714. Here, the first conductive structure 714 and the fifth conductive structure 717 can be formed in the same process to save process steps and manufacturing time.

[0117] In some embodiments, the method further includes providing a second functional layer, wherein a peripheral circuit or a memory cell array is disposed in the second functional layer. Methods for forming peripheral circuits or memory cell arrays are well-established and will not be elaborated upon here.

[0118] In other embodiments, the second functional layer may not include a memory cell array, but instead may include other circuits or devices; this disclosure does not limit this. It should be understood that the descriptions of the memory cell array in the following embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Unless otherwise specifically emphasized, the memory cell array in various embodiments of this disclosure may be replaced by other circuits or devices.

[0119] In some embodiments, the method further includes forming a second interconnect layer on one side of the second functional layer along the Z-axis. Multiple interconnect structures, such as a second interconnect structure, a fourth interconnect structure, etc., are formed in the second interconnect layer, and the second interconnect structure and the fourth interconnect structure are electrically isolated from each other. The interconnect structures in the second interconnect layer may include lateral conductors and vias. The interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in the first interconnect layer 702 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0120] Methods for forming the second interconnect layer include, but are not limited to, deposition processes, such as CVD, LPCVD, PECVD, PVD, and ALD processes.

[0121] In some embodiments, the method further includes forming a third sub-bonding layer on one side of the first interconnect layer along the Z-axis. The material of the third sub-bonding layer includes, but is not limited to, silicon oxide. Methods for forming the third sub-bonding layer include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0122] In some embodiments, the method further includes forming a fifth groove in a third sub-bonding layer, the fifth groove exposing a second interconnect structure. Methods for forming the fifth groove include, but are not limited to, etching.

[0123] In some embodiments, the method further includes: forming a first conductive material layer in the fifth groove and on the surface of the third sub-bonding layer; forming a dielectric material layer on the surface of the first conductive material layer; and forming a second electrode material layer on the surface of the dielectric material layer. The constituent materials of both the first and second electrode material layers include, but are not limited to, titanium nitride. The constituent material of the dielectric material layer includes a high-k dielectric constant (High-K) material, which generally refers to a material with a dielectric constant higher than 3.9, and is typically significantly higher than this value. In some specific examples, the constituent material of the dielectric material layer may include, but is not limited to, alumina (Al₂O₃), zirconium oxide (ZrO), hafnium oxide (HfO₂), etc. The methods for forming the first conductive material layer, the dielectric material layer, and the second electrode material layer include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD processes, etc.

[0124] In some embodiments, the method further includes forming an insulating material layer on the surface of the second electrode material layer. The insulating material layer may be composed of, but is not limited to, silicon oxide. Methods for forming the insulating material layer may include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0125] In some embodiments, the method further includes: removing a portion of a first conductive material layer to form a first electrode layer, removing a portion of a dielectric material layer to form a dielectric layer, and removing a portion of a second electrode material layer to form a second electrode layer, wherein the first electrode layer, the dielectric layer, and the second electrode layer constitute a second MIM structure. The first electrode layer can be used as the lower electrode of the second MIM structure; the dielectric layer can be used as the dielectric of the second MIM structure; and the second electrode layer can be used as the upper electrode of the second MIM structure. The method further includes: removing a portion of an insulating material layer to form an insulating layer. The insulating layer covers the surface of the second MIM structure to isolate and protect the second MIM structure. Here, the removal process includes, but is not limited to, etching.

[0126] In some embodiments, the method further includes: forming a fourth sub-bonded layer on the third sub-bonded layer, the fourth sub-bonded layer covering the exposed third sub-bonded layer and a covering insulating layer. The material of the fourth sub-bonded layer can be the same as the material of the third sub-bonded layer, such as silicon oxide. Methods for forming the fourth sub-bonded layer include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD processes, etc.

[0127] In some embodiments, the method further includes: planarizing the surface of the fourth sub-bonding layer; here, the planarization process includes, but is not limited to, CMP. Here, the planarized fourth sub-bonding layer and the third sub-bonding layer constitute a second bonding layer.

[0128] In some embodiments, the method further includes forming a seventh groove in the second bonding layer. The seventh groove is located on one side of the second MIM structure along the X-axis and / or Y-axis direction. The seventh groove extends through the second bonding layer along the Z-axis direction. The method for forming the seventh groove includes, but is not limited to, etching.

[0129] In some embodiments, the method further includes: forming a sixth groove in the fourth sub-bonding layer, the sixth groove penetrating the fourth sub-bonding layer and the insulating layer along the Z-axis direction and exposing one end of the second MIM structure; exemplaryly, the sixth groove exposes the second electrode layer of the second MIM structure. The method for forming the sixth groove includes, but is not limited to, etching. Here, the sixth groove and the seventh groove are isolated from each other. It should be noted that the formation order of the sixth and seventh grooves can be selected according to actual needs, and this disclosure does not limit it.

[0130] In some embodiments, the method further includes: forming a second conductive structure in a sixth groove; connecting the second conductive structure to one end of a second MIM structure; specifically, connecting the second conductive structure to a second electrode layer of the second MIM structure. The constituent materials of the second conductive structure include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. Methods for forming the second conductive structure include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0131] The method further includes forming a fourth conductive structure in the seventh groove. Here, the fourth conductive structure is electrically isolated from the second conductive structure. The constituent materials of the fourth conductive structure include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. Methods for forming the fourth conductive structure include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes. Thus, a second semiconductor structure is formed.

[0132] In other embodiments, the method further includes: forming an eighth groove in the second bonding layer; the eighth groove communicating with the sixth groove; and forming a sixth conductive structure in the eighth groove; the sixth conductive structure being connected to the second conductive structure. The process for forming the eighth groove includes, but is not limited to, etching, and the method for forming the sixth conductive structure includes, but is not limited to, CVD, LPCVD, PECVD, PVD, and ALD processes.

[0133] In some embodiments, reference Figure 18 The method further includes: bonding a first semiconductor structure 700 and a second semiconductor structure 800 along the Z-axis direction, so that one end of the first conductive structure is bonded to one end of the second conductive structure, and the third conductive structure is connected to the fourth conductive structure. It should be noted that... Figure 18The semiconductor device shown in the figure has a first MIM structure 707 in the first semiconductor structure 700 and a second MIM structure 718 in the second semiconductor structure 800. In other embodiments of the semiconductor device, the first MIM structure may be provided only in the first semiconductor structure or the second MIM structure may be provided only in the second semiconductor structure, and this disclosure does not limit this.

[0134] in addition, Figure 18 The semiconductor device shown includes a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure, wherein the first and third conductive structures are electrically isolated from each other, and the second and fourth conductive structures are electrically isolated from each other. In other embodiments, the semiconductor device includes a first conductive structure, a second conductive structure, a fifth conductive structure, and a sixth conductive structure, wherein the first conductive structure is connected to the fifth conductive structure, and the second conductive structure is connected to the sixth conductive structure. This disclosure does not impose any limitations on this.

[0135] It should be noted that terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0136] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first semiconductor structure and a second semiconductor structure stacked along a first direction; The first semiconductor structure includes: a first bonding layer and a first conductive structure located in the first bonding layer; the second semiconductor structure includes: a second bonding layer and a second conductive structure located in the second bonding layer; one end of the first conductive structure is bonded to one end of the second conductive structure. The semiconductor device further includes: a first MIM structure located in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or, a second MIM structure located in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

2. The semiconductor device according to claim 1, characterized in that, The first bonding layer includes one or more of the first MIM structures; The second bonding layer includes one or more of the second MIM structures.

3. The semiconductor device according to claim 1, characterized in that, Both the first MIM structure and the second MIM structure include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: A first interconnect layer located on the side of the first bonding layer away from the second bonding layer on opposite sides along the first direction, and a first interconnect structure located in the first interconnect layer; A second interconnect layer located on the side of the second bonding layer away from the first bonding layer on opposite sides along the first direction, and a second interconnect structure located in the second interconnect layer.

5. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes only the first MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; and the second conductive structure is directly connected to the second interconnect structure.

6. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes only the second MIM structure, the first electrode layer of the second MIM structure is connected to the second interconnect structure; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure; and the first conductive structure is directly connected to the first interconnect structure.

7. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes the first MIM structure and the second MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; the first electrode layer of the second MIM structure is connected to the second interconnect structure; and the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure.

8. The semiconductor device according to any one of claims 4 to 7, characterized in that, The semiconductor device further includes: A third conductive structure penetrating the first bonding layer and a fourth conductive structure penetrating the second bonding layer, wherein the third conductive structure and the fourth conductive structure are bonded together; wherein the third conductive structure is electrically isolated from the first conductive structure, and the fourth conductive structure is electrically isolated from the second conductive structure.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: a third interconnect structure located in the first interconnect layer, the third interconnect structure being electrically isolated from the first interconnect structure; and a fourth interconnect structure located in the second interconnect layer, the fourth interconnect structure being electrically isolated from the second interconnect structure. The third conductive structure is connected to the third interconnect structure, and the fourth conductive structure is connected to the fourth interconnect structure.

10. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: peripheral circuitry located on one side of the first interconnect layer along the first direction, away from the first bonding layer; and a memory cell array located on one side of the second interconnect layer along the first direction, away from the second bonding layer.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes: A fifth conductive structure located in the first bonding layer, the fifth conductive structure being connected to the first conductive structure; and a sixth conductive structure located in the second bonding layer, the sixth conductive structure being connected to the second conductive structure.

12. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first semiconductor structure is formed; the first semiconductor structure includes: a first bonding layer, and a first conductive structure located in the first bonding layer; A second semiconductor structure is formed; the second semiconductor structure includes: a second bonding layer, and a second conductive structure located in the second bonding layer; The first semiconductor structure and the second semiconductor structure are stacked along a first direction so that one end of the first conductive structure is bonded to one end of the second conductive structure. The method further includes: forming a first MIM structure in the first bonding layer, wherein the first MIM structure is connected to the other end of the first conductive structure; and / or forming a second MIM structure in the second bonding layer, wherein the second MIM structure is connected to the other end of the second conductive structure.

13. The manufacturing method according to claim 12, characterized in that, The formation of the first semiconductor structure includes: A first interconnect layer is formed, and a first interconnect structure is formed in the first interconnect layer; A first sub-bonding layer is formed on one side of the first interconnect layer along the first direction; A first groove is formed in the first sub-bonding layer, the first groove exposing the first interconnect structure; A first conductive layer is formed in the first groove and on a portion of the surface of the first sub-bonding layer, a dielectric layer is formed on the surface of the first conductive layer, and a second electrode layer is formed on the surface of the dielectric layer to form a first MIM structure.

14. The manufacturing method according to claim 13, characterized in that, The method further includes: A second sub-bonding layer is formed on the first sub-bonding layer; A second groove is formed in the second sub-bonding layer, penetrating the second sub-bonding layer, and the second groove exposes one end of the first MIM structure; A first conductive structure is formed in the second groove; the first conductive structure is connected to one end of the first MIM structure. The first sub-bonding layer and the second sub-bonding layer constitute the first bonding layer.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: A third groove is formed in the first bonding layer; the third groove is spaced apart from the second groove. A third conductive structure is formed in the third groove; the third conductive structure is electrically isolated from the first conductive structure.

16. The manufacturing method according to claim 14, characterized in that, The method further includes: A fourth groove is formed in the first bonding layer; the fourth groove is connected to the second groove. A fifth conductive structure is formed in the fourth groove; the fifth conductive structure is connected to the first conductive structure.

17. The manufacturing method according to claim 12, characterized in that, The formation of the second semiconductor structure includes: A second interconnect layer is formed, and a second interconnect structure is formed in the second interconnect layer; A third sub-bonding layer is formed on one side of the second interconnect layer along the first direction; A fifth groove is formed in the third sub-bonding layer, the fifth groove exposing the second interconnect structure; A first conductive layer is formed in the fifth groove and on a portion of the surface of the third sub-bonding layer. A dielectric layer is formed on the surface of the first conductive layer, and a second electrode layer is formed on the surface of the dielectric layer to form a second MIM structure.

18. The manufacturing method according to claim 17, characterized in that, The method further includes: A fourth sub-bonding layer is formed on the third sub-bonding layer; A sixth groove is formed in the fourth sub-bonding layer, the sixth groove exposing the second MIM structure located on a portion of the surface of the third sub-bonding layer; A second conductive structure is formed in the sixth groove; the second conductive structure is connected to the second MIM structure. The third sub-bond synthesis and the fourth sub-bonding layer constitute the second bonding layer.

19. The manufacturing method according to claim 18, characterized in that, The method further includes: A seventh groove is formed in the second bonding layer; the seventh groove is spaced apart from the sixth groove. A fourth conductive structure is formed in the seventh groove; the fourth conductive structure is electrically isolated from the second conductive structure.

20. The manufacturing method according to claim 19, characterized in that, The method further includes: An eighth groove is formed in the second bonding layer; the eighth groove communicates with the fifth groove. A sixth conductive structure is formed in the eighth groove; the sixth conductive structure is connected to the second conductive structure.

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