Data processing method and device, electronic equipment, storage medium and program product

Abstract

The present disclosure provides a data processing method and device, electronic equipment, storage medium and program product, which are applied to the technical field of communication. The method comprises the following steps: determining the elements of each row of a storage matrix based on the row position and shift value of a non-zero basis matrix in each column of a check matrix; determining a check sub-result corresponding to an input codeword based on the position of a non-zero term of a check sub-matrix and the input codeword; determining a first check result corresponding to the input codeword based on the check sub-result of all check sub-matrices corresponding to the check matrix; and in response to the first check result representing that the input codeword does not pass the check, determining whether to decode the input codeword based on the first check result and a first flip threshold. In this way, when performing the check, the check sub-result is obtained in a manner of parallel computing a plurality of check sub-matrices or each row of the storage matrix, and then the check result is obtained, which can accelerate the check speed and improve the decoding efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a data processing method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] Bit-flipping (BF) decoding algorithms, as a low-complexity hard-decision iterative method, have attracted much attention due to their hardware friendliness. The core idea is to calculate the error location using a parity check equation and flip unreliable bits iteratively to gradually eliminate decoding errors. However, classic bit-flipping algorithms often rely on the parity check result obtained after each iteration based on the parity check matrix, using the maximum number of non-zero parity check elements in the result as the bit-flipping threshold. This calculation process often consumes a significant amount of time, affecting the decoding speed. Summary of the Invention

[0003] This disclosure provides a data processing method, apparatus, electronic device, storage medium, and program product to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this disclosure, a data processing method is provided, comprising:

[0005] Based on the row positions and shift values ​​of the non-zero basis matrices in each column of the parity-check matrix, the elements of each row of the storage matrix are determined; wherein, the rows of the storage matrix correspond one-to-one with the columns of the parity-check matrix, and each non-zero basis matrix in the parity-check matrix corresponds to two elements in the storage matrix; the odd-numbered elements in each row of the storage matrix represent the row positions of the corresponding non-zero basis matrix in the parity-check matrix; and the even-numbered elements represent the shift values ​​of the corresponding non-zero basis matrix.

[0006] Based on the row position and shift value represented by the elements in any row of the storage matrix, determine the position of the non-zero item in the corresponding parity submatrix of the parity matrix;

[0007] Based on the positions of the non-zero items in the check matrix and the input codeword, the check result corresponding to the input codeword is determined; in the check result, the position of the non-zero element is related to the position of the non-zero item in the check matrix; the value of the non-zero element in the check result is related to the value of the corresponding element in the input codeword.

[0008] Based on the check results of all check sub-matrices corresponding to the check matrix, determine the first check result corresponding to the input codeword;

[0009] In response to the first verification result indicating that the input codeword has failed the verification, it is determined whether to decode the input codeword based on the first verification result and the first flip threshold.

[0010] In the above scheme, after determining the elements of each row of the storage matrix, the method further includes:

[0011] The storage matrix is ​​determined based on the elements of each row of the storage matrix, and the storage matrix is ​​stored in the storage space.

[0012] The method in the above scheme further includes:

[0013] Receive input codewords;

[0014] The storage matrix is ​​obtained from the storage space.

[0015] In the above scheme, obtaining the storage matrix from the storage space includes:

[0016] Obtain the first alternative storage matrix from the storage space;

[0017] Based on the first candidate storage matrix and the input codeword, determine the verification weight value corresponding to the first candidate storage matrix;

[0018] In response to the verification weight value being within a first preset range, a second candidate storage matrix in the storage space is determined as the storage matrix; wherein the sparsity of the second candidate storage matrix is ​​greater than the sparsity of the first candidate storage matrix;

[0019] Alternatively, in response to the verification weight value being within a second preset range, the first candidate storage matrix is ​​determined to be the storage matrix;

[0020] Alternatively, in response to the verification weight value being within a third preset range, a third candidate storage matrix is ​​determined as the storage matrix; wherein the sparsity of the third candidate storage matrix is ​​less than the sparsity of the first candidate storage matrix.

[0021] In the above scheme, the verification matrix is ​​composed of multiple non-zero basis matrices, or is composed of multiple non-zero basis matrices and a zero basis matrix; all elements in the zero basis matrix are 0; the non-zero basis matrix includes the identity matrix and the matrix obtained by shifting the identity matrix based on the shift value;

[0022] Each check submatrix includes one column of the base matrix from the check matrix.

[0023] In the above scheme, determining the elements of each row of the storage matrix based on the row positions and shift values ​​of the non-zero basis matrices in each column of the parity-check matrix includes:

[0024] Based on any parity submatrix in the parity check matrix, determine the elements of the corresponding row in the storage matrix, specifically including:

[0025] Based on the position identifier of each non-zero basis matrix in the parity submatrix, the odd-numbered elements of the corresponding row of the storage matrix are determined;

[0026] Based on the shift value of each non-zero basis matrix in the parity submatrix, the even-numbered elements of the corresponding row of the storage matrix are determined.

[0027] In the above scheme, determining the check result corresponding to the input codeword based on the position of the non-zero item in the check matrix and the input codeword includes:

[0028] Multiple check sub-matrices and check sub-results corresponding to the input codewords are determined in parallel, specifically including performing the following operations on each check sub-matrice:

[0029] The elements corresponding to the positions of the non-zero items in the input codeword are determined, and the check result is formed according to their order in the input codeword.

[0030] In the above scheme, determining the check result corresponding to the input codeword based on the position of the non-zero item in the check matrix and the input codeword includes:

[0031] Determine the elements in the input codeword that correspond to the positions of the non-zero items, and construct the elements at the corresponding positions in the check result according to their order in the input codeword;

[0032] Determine that all other elements in the checksum result are 0.

[0033] In the above scheme, determining the first check result corresponding to the input codeword based on the check sub-results of all check sub-matrices corresponding to the check matrix includes:

[0034] For each verification sub-result obtained, the verification sub-result is added to the first temporary verification result, and the first temporary verification result is updated based on the result of the addition.

[0035] The first temporary verification result obtained is determined to be the first verification result corresponding to the input codeword;

[0036] The initial value of the first temporary verification result is a vector with all elements being 0.

[0037] The method in the above scheme further includes:

[0038] In response to the first verification result indicating that the input codeword passes the verification, the input codeword is output.

[0039] The method in the above scheme further includes:

[0040] The first verification weight value is determined based on the first verification result;

[0041] Determine the standard verification weight value based on the verification matrix;

[0042] The first flip threshold is determined based on the maximum column weight of the check matrix, the current number of calculations, the first check weight value, the standard check weight value, the maximum column weight offset, the iteration decay factor, and the check weight value sensitivity coefficient.

[0043] In the above scheme, determining the first flip threshold based on the maximum column weight of the parity check matrix, the current number of calculations, the first parity check weight value, the standard parity check weight value, the maximum column weight offset, the iteration decay factor, and the parity check weight value sensitivity coefficient includes:

[0044] The decay value is determined based on the iterative decay factor and the current number of calculations;

[0045] The flip adjustment coefficient is determined based on the first check weight value, the standard check weight value, and the check weight value sensitivity coefficient.

[0046] The first flip threshold is determined based on the maximum column weight, maximum column weight offset, attenuation value, and flip adjustment coefficient of the parity matrix.

[0047] In the above scheme, determining whether to decode the input codeword based on the first verification result and the first flip threshold includes:

[0048] The first verification weight value is determined based on the first verification result;

[0049] In response to the first verification weight value being greater than or equal to the first flip threshold, the input codeword is flipped and decoded to obtain the first decoded codeword;

[0050] Alternatively, in response to the first verification weight value being less than the first flip threshold, the input codeword is determined to be the first decoded codeword.

[0051] The method in the above scheme further includes:

[0052] Based on the positions of the non-zero items in the check submatrix and the first decoded codeword, determine the first temporary check result corresponding to the first decoded codeword;

[0053] Based on the first verification result and the first temporary verification result, the second verification result is determined;

[0054] In response to the second verification result indicating that the first decoded codeword has passed the verification, the first decoded codeword is output.

[0055] Alternatively, in response to the second verification result indicating that the first decoded codeword has failed verification, a second verification weight value is determined based on the second verification result; and based on the second verification weight value and the second flip threshold, it is determined whether to decode the first decoded codeword.

[0056] In the above scheme, determining the first temporary check result corresponding to the first decoded codeword based on the position of the non-zero item in the check submatrix and the first decoded codeword includes:

[0057] For each check result obtained based on the position of the non-zero item in the check matrix and the first decoded codeword, the check result is added to the second temporary check result, and the second temporary check result is updated based on the result of the addition.

[0058] The final obtained second temporary verification result is determined to be the first temporary verification result corresponding to the first decoded codeword;

[0059] The initial value of the second temporary verification result is a vector with all elements being 0.

[0060] The method in the above scheme further includes:

[0061] Compare the first check weight value and the second check weight value;

[0062] If the absolute value of the difference between the second check weight value and the first check weight value is greater than the change threshold, the storage matrix is ​​replaced and the input codeword is re-checked.

[0063] According to a second aspect of this disclosure, a data processing apparatus is provided, the apparatus comprising:

[0064] The storage matrix determination unit is used to determine the elements of each row of the storage matrix based on the row position and shift value of the non-zero base matrix in each column of the parity check matrix. The rows of the storage matrix correspond one-to-one with the columns of the parity check matrix, and each non-zero base matrix in the parity check matrix corresponds to two elements in the storage matrix. The odd-numbered elements in each row of the storage matrix represent the row position of the corresponding non-zero base matrix in the parity check matrix, and the even-numbered elements represent the shift value of the corresponding non-zero base matrix.

[0065] The non-zero term determination unit is used to determine the position of the non-zero term in the corresponding parity submatrix of the parity check matrix based on the row position and shift value represented by the elements in any row of the storage matrix.

[0066] The verification unit is used to determine the verification result corresponding to the input codeword based on the position of the non-zero item in the verification sub-matrix and the input codeword; in the verification sub-result, the position of the non-zero element is related to the position of the non-zero item in the verification sub-matrix; the value of the non-zero element in the verification sub-result is related to the value of the corresponding element in the input codeword; and the first verification result corresponding to the input codeword is determined based on the verification results of all verification sub-matrixes corresponding to the verification matrix.

[0067] The decoding unit is configured to determine whether to decode the input codeword based on the first verification result and the first flip threshold in response to the first verification result indicating that the input codeword has failed the verification.

[0068] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0069] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods of this disclosure.

[0070] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.

[0071] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the methods described in this disclosure.

[0072] The data processing method disclosed herein determines the elements of each row of a storage matrix based on the row positions and shift values ​​of the non-zero basis matrices in each column of the parity check matrix. The rows of the storage matrix correspond one-to-one with the columns of the parity check matrix, and each non-zero basis matrix in the parity check matrix corresponds to two elements in the storage matrix. Odd-numbered elements in each row of the storage matrix represent the row positions of the corresponding non-zero basis matrices in the parity check matrix; even-numbered elements represent the shift values ​​of the corresponding non-zero basis matrices. Based on the row positions and shift values ​​represented by the elements in any row of the storage matrix, the positions of the non-zero terms in the corresponding parity check submatrix of the parity check matrix are determined. Based on the positions of the non-zero terms in the parity check submatrix and the input codeword, the parity check result corresponding to the input codeword is determined. In the parity check result, the positions of the non-zero elements are related to the positions of the non-zero terms in the parity check submatrix; the values ​​of the non-zero elements in the parity check result are related to the values ​​of the corresponding elements in the input codeword. Based on the parity check results of all parity check submatrices corresponding to the parity check matrix, a first parity check result corresponding to the input codeword is determined. In response to the first parity check result indicating that the input codeword has failed the check, a determination is made, based on the first parity check result and a first flip threshold, whether to decode the input codeword. In this way, by using two elements in the storage matrix to represent a non-zero basis matrix in the check matrix, only the storage matrix is ​​stored during storage, reducing storage space and speeding up matrix retrieval during check. During check, multiple check sub-matrices are computed in parallel or each row of the storage matrix is ​​stored to obtain the check sub-result, thereby obtaining the check result, which can speed up the check and improve decoding efficiency.

[0073] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0074] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0075] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0076] Figure 1 This diagram illustrates the relationship between the number of erroneous bits in a codeword and the SW value.

[0077] Figure 2 A schematic diagram of a first optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0078] Figure 3 A schematic diagram of a second optional flow of the data processing method provided in an embodiment of this disclosure is shown;

[0079] Figure 4 An optional schematic diagram of the storage matrix provided in an embodiment of this disclosure is shown;

[0080] Figure 5 A schematic diagram of a third optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0081] Figure 6 A data flow diagram of the data processing method provided in an embodiment of this disclosure is shown;

[0082] Figure 7 A schematic diagram of a fourth optional flow of the data processing method provided in this disclosure embodiment is shown;

[0083] Figure 8 This diagram illustrates a first performance comparison between the method described in this embodiment and the method described in related technologies;

[0084] Figure 9 This diagram illustrates a second performance comparison between the method described in the embodiments of this disclosure and the methods described in related technologies;

[0085] Figure 10 A schematic diagram of an optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown;

[0086] Figure 11 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0087] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0088] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0089] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0090] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0091] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0092] With the rapid development of wireless communication, storage systems, and IoT technologies, the demand for highly reliable data transmission is becoming increasingly urgent. Low-Density Parity-Check (LDPC) codes, due to their excellent performance approaching the Shannon limit, have become a core error correction coding scheme in fields such as 5G, satellite communication, and solid-state storage. However, the design of efficient decoding algorithms for LDPC codes has always faced the challenge of balancing complexity and performance. While the traditional Belief Propagation (BP) algorithm boasts excellent performance, its high computational complexity and floating-point operation requirements limit its application in scenarios with stringent low-power or real-time requirements. Against this backdrop, Bit-Flipping (BF) decoding algorithms, as a low-complexity hard-decision iterative method, have attracted considerable attention due to their hardware friendliness. Their core idea is to calculate the error location through the check equation and flip unreliable bits during iteration, gradually eliminating decoding errors. However, classic bit-flipping algorithms often rely on the maximum number of non-zero parities calculated after each iteration as the bit-flipping threshold. This calculation and comparison process often takes a lot of time. In addition, in the middle stage of iterative decoding, the maximum value calculated in each round often jumps back and forth between two fixed numbers. This makes the number of errors corrected in each iteration in the middle stage of decoding very small, resulting in slower performance.

[0093] To address the aforementioned issues, academia and industry have proposed improvement schemes in recent years, such as Weighted Bit-Flipping (WBF) and Reliability-Based Flipping (RBF) algorithms, which improve performance by introducing soft information weights or dynamically adjusting the flipping rules. However, these improvements often come at the cost of complexity, either relying on prior knowledge of specific channel models or introducing specific functions, limiting their versatility and hindering their hardware implementation. Furthermore, Gradient Descent Bit-Flipping (GDBF) decoding methods and their variants have also been proposed. These methods have lower computational complexity but inevitably lead to performance degradation. Therefore, a high-performance bit-flipping decoding method that is easy to implement in hardware is urgently needed.

[0094] In the decoding process of LDPC codes, if the valid codeword is a binary vector The necessary and sufficient condition for its validity is that the codeword satisfies the linear constraint relationship of the check equation H, that is, all check equations are valid (mathematically manifested as...). When codeword c is transmitted through the channel and is interfered with by noise, the vector y=c+e (where e is an error vector, such as a noise vector) obtained at the receiving end will lead to... If the error is not equal to 0, then at least one non-zero checksum exists in the parity check equation. The Syndrome Weight (SW) value represents the number of times the parity check equation no longer holds true. The core task of the decoder is to use an iterative algorithm to dynamically correct erroneous bits in the received sequence and gradually approach the condition that the error is not met. Valid codewords with orthogonal constraints.

[0095] In view of the problems existing in the related technologies, the present disclosure provides a data processing method to at least solve some or all of the above-mentioned technical problems.

[0096] Figure 1 A schematic diagram showing the relationship between the number of error bits in a codeword and the SW value is presented.

[0097] For a specific parity check H, the number of errors in the received codeword often has a certain mathematical relationship with its SW value, such as... Figure 1 As shown, the SW value increases with the increase of the number of erroneous bits in the codeword. Therefore, this embodiment of the present disclosure proposes that the initial error in the received codeword can be predicted by the SW value.

[0098] Specifically, during the decoding process, utilize To determine whether decoding was successful, the initial SW value is used to estimate errors in the initial codewords. Codewords with a high number of initial errors are discarded, and codewords with SW values ​​within the BF decoding range are fed into the BF decoder. Furthermore, the SW value is used to select the parity check matrix, choosing the best match from multiple pre-configured parity check matrices targeting different error ranges for subsequent decoding operations. Codeword selection using SW values ​​saves unnecessary iteration delays and reduces power consumption. Simultaneously, by continuously monitoring SW changes, the decoder intelligently assesses the current channel quality and dynamically switches the parity check matrix to match the environment, avoiding the limitations of static matrices.

[0099] Figure 2 A schematic diagram of a first alternative flow of the data processing method provided in this disclosure embodiment is shown, and the steps will be described accordingly.

[0100] Step S201: Based on the row positions and shift values ​​of the non-zero base matrices in each column of the parity matrix, determine the elements of each row of the storage matrix.

[0101] In some embodiments, the parity check matrix consists of at least one non-zero basis matrix and at least one zero basis matrix; wherein the non-zero basis matrix includes an identity matrix, or a shifted identity matrix; and all elements of the zero matrix are 0. The non-zero basis matrix and the zero basis matrix have the same dimension, and in this embodiment of the disclosure, the basis matrix includes either a non-zero basis matrix or a zero basis matrix.

[0102] In some embodiments, the parity check matrix is ​​divided into multiple parity check submatrices, and the number of columns of each parity check submatric is the same as the number of columns of the non-zero basis matrix, that is, each parity check submatric is composed of a basis matrix.

[0103] In some embodiments, the carrier implementing the data processing method (hereinafter referred to as the carrier) can represent a check submatrix in the check matrix using a row vector; the row vectors corresponding to all check submatrixes constitute the storage matrix. That is, a row element in the storage matrix corresponds to a check submatrix in the check matrix.

[0104] In some embodiments, the number of zero-based matrices in each column of the parity check matrix is ​​the same. When representing the parity check matrix based on the storage matrix, the zero-based matrix may not be reflected in the storage matrix in order to save storage space. In the storage matrix, a non-zero-based matrix in the parity check matrix is ​​represented by the adjacent odd and even elements in each row (such as the first and second elements, or the third and fourth elements), thus transforming the non-zero-based matrix from i×i elements to 2 elements; n is the number of rows or columns of the non-zero-based matrix.

[0105] In some embodiments, in the storage matrix, odd-numbered elements in each row represent the row position of the corresponding non-zero basis matrix in the parity check matrix; even-numbered elements represent the shift value of the corresponding non-zero basis matrix. For example, the first element in any row of the storage matrix represents the position of the first non-zero basis matrix in the corresponding parity check matrix, and the second element represents the shift value of the non-zero basis matrix relative to the identity matrix.

[0106] The carrier can be computer programs, electronic circuits, databases, mobile applications, electronic devices, cloud computing platforms, distributed systems, artificial intelligence frameworks, mathematical models, automation tools, and microcontrollers, etc., which are software or hardware capable of implementing algorithms and methods.

[0107] Step S202: Based on the row position and shift value represented by the elements in any row of the storage matrix, determine the position of the non-zero item in the corresponding parity submatrix of the parity check matrix.

[0108] In some embodiments, the carrier can determine the position of the non-zero item in the check submatrix based on the row position and shift value represented by the element in each row of the storage matrix; specifically, since the check submatrix is ​​a submatrix composed of a column of zero-based matrices and non-zero-based matrices, the position of the non-zero item in the check submatrix can be determined based on the position and shift value of the non-zero-based matrix in the check submatrix.

[0109] Step S203: Based on the positions of the non-zero items in the check sub-matrix and the input codeword, determine the check sub-result corresponding to the input codeword.

[0110] In some embodiments, the present disclosure uses multiple check sub-matrices to check the input codeword in parallel to obtain a check result; during the check process, the input codeword corresponding to the position of the non-zero item in the check sub-matrice is retained as the check result corresponding to the check sub-matrice.

[0111] In the checksum result, the position of the non-zero element is related to the position of the non-zero item in the checksum matrix; the value of the non-zero element in the checksum result is related to the value of the corresponding element in the input codeword.

[0112] Step S204: Based on the check results of all check sub-matrices corresponding to the check matrix, determine the first check result corresponding to the input codeword.

[0113] In some embodiments, each time the carrier obtains a check result of a check submatrix, it adds the check result to a first temporary check result and updates the result of the addition as a new first temporary check result; thus, after updating the first temporary check result based on all check submatrixes, the final first temporary check result is determined as the first check result.

[0114] In this way, during verification, the input codeword is verified in parallel based on all parity sub-matrices, and the temporary verification results are dynamically updated during the verification process. The final temporary verification result is used as the final result of the current round of verification, which can greatly shorten the time required for the verification process. In the prior art, verification is performed directly based on the parity matrix and the input codeword, that is, the input codeword is multiplied by the entire parity matrix. However, in this proposal, the parity matrix is ​​split into multiple parity sub-matrices. During calculation, it is not based on the product of a vector and the parity sub-matrices, but retains the positions of the non-zero elements in the input codeword that correspond to the parity sub-matrices, reducing the use of computing resources and the computation time.

[0115] Step S205: In response to the first verification result indicating that the input codeword has failed the verification, determine whether to decode the input codeword based on the first verification result and the first flip threshold.

[0116] In some embodiments, the number of non-zero elements in the first verification result represents the number of verification equations that failed. If all elements in the first verification result are 0, it means that the input codeword has passed the verification and can be directly output without decoding. If at least one element in the first verification result is not 0, it means that the input codeword has failed the verification and needs to be decoded and verified again before it can be output.

[0117] If the input codeword fails the verification, the carrier determines whether to decode the input codeword based on the first verification result and the first flip threshold.

[0118] Thus, the data processing method provided in this embodiment of the present disclosure uses two elements in the storage matrix to represent a non-zero basis matrix in the check matrix. During storage, only the storage matrix is ​​stored, reducing storage space and speeding up matrix acquisition during check. During check, multiple check sub-matrices or each row of the storage matrix are computed in parallel to obtain the check sub-results, thereby obtaining the check result. This can speed up the check and improve decoding efficiency.

[0119] Figure 3 A second alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0120] Step S301: Determine the storage matrix corresponding to each check matrix and store the storage matrix.

[0121] In some embodiments, the carrier determines the storage matrix corresponding to each parity check matrix, specifically including performing the following operations on each parity check matrix:

[0122] Based on the row positions and shift values ​​of the non-zero basis matrices included in the c-th parity submatrix of the parity check matrix, the element in the c-th row of the storage matrix is ​​determined. The parity check matrix consists of m×n basis matrices; specifically, each row of the parity check matrix includes n basis matrices, and each column includes m basis matrices; the dimension of each basis matrix is ​​i×i.

[0123] Assuming that the c-th parity submatrix in the parity check matrix includes the d-th basis matrix which is a non-zero basis matrix, then in the c-th row of the storage matrix corresponding to the parity submatrix, the element corresponding to the d-th basis matrix (usually the 2d-1 or 2d-3 element) is d or d-1, and the offset of the d-th basis matrix is ​​also included.

[0124] For example, take the parity check matrix H as an example:

[0125]

[0126] Where 0 represents the identity matrix, -1 represents the zero-based matrix, 1 represents the identity matrix with a shift of 1, 2 represents the identity matrix with a shift of 2, and 3 represents the identity matrix with a shift of 3. The parity check matrix corresponds to 6 parity check submatrices, namely... , , , , as well as .

[0127] In related technologies, when storing the parity check matrix, the stored parity check matrix is ​​(m×i)×(n×i) dimensional, and the elements in the parity check matrix are 0 or 1. The calculation is based on the (m×i)×(n×i) dimensional parity check matrix and the input codeword. Therefore, it will occupy more storage space and increase the amount of calculation during the verification.

[0128] Figure 4 An optional schematic diagram of the storage matrix provided in an embodiment of this disclosure is shown.

[0129] In the storage matrix, each row corresponds to a parity submatrix of the parity matrix. In each row, odd-numbered elements correspond to the position of the base matrix in the parity submatrix, and even-numbered elements correspond to the shift value of the base matrix.

[0130] The QC-LDPC code stored in the storage space (such as the parity check matrix module) is a structured LDPC code. Its parity check matrix exhibits a quasi-cyclic structure, meaning that each row or column of the parity check matrix is ​​composed of a cyclically shifted basis matrix (a non-zero basis matrix or a zero basis matrix) of the same size, generated through basis matrix expansion. This type of matrix combines the randomness of random LDPC codes with the regularity of cyclic structures, preserving excellent error correction performance while significantly reducing encoding and decoding complexity. This storage mode stores the matrix according to its actual columns. The first row of the storage matrix stores the first column of the parity check matrix's basis matrix, the second row stores the second column, and so on, with the last row storing the last column. Since the parity check matrix of a QC-LDPC code can usually be represented by its basis matrix, when the row position and shift value information of a column are obtained, the row and column positions of each element 1 in the corresponding actual parity check matrix can be derived. This storage method avoids the space waste caused by global storage by storing the effective elements in the matrix.

[0131] Furthermore, using 0 as the index, assuming y is the actual row position of element 1 in the parity check matrix, x is the actual column position of element 1 in the parity check matrix, a is its row position in the base matrix, b is its column position in the base matrix, the dimension of the base matrix is ​​i×i, and the shift factor of the non-zero base matrix is ​​f, then the actual row position interval of element 1 in the parity check matrix is ​​from a×i to (a+1)×i-1 rows; the actual column position interval is from b×i to (b+1)×i-1 columns. For each cyclic submatrix of this column, the column position of element 1 in the actual matrix of the 0th row of the submatrix is:

[0132] x = b × i + f

[0133] The column positions of the other row 1 elements in the base matrix can also be obtained from the above rules.

[0134] Assume that a row of data stored in the storage matrix (corresponding to a column of the parity-check matrix H) has a data width of X bits. The data structure is as follows: [X-1:K] represents the row index of the first non-zero item in this column, and [K-1:P] represents the shift value corresponding to the first non-zero item in this column. A set of data has a bit width of [X-1:P]. The data structure and bit width of other cyclic submatrices stored in this row are the same as described above. Here, n is the number of columns in the base matrix corresponding to the QC-LDPC parity-check matrix.

[0135] In some embodiments, a verification submatrix is ​​used. For example, if the first basis matrix is ​​the identity matrix, then the first two elements of the first row in the corresponding storage matrix are [0,0]. The first 0 indicates the position of the basis matrix in the parity submatrix, and the second element indicates the shift value of the basis matrix relative to the identity matrix. Furthermore, the third and fourth elements of the first row in the storage matrix are [2,1]. Here, 2 indicates that the non-zero basis matrix is ​​the third basis matrix in the parity submatrix, and 1 indicates that the shift value of the non-zero basis matrix relative to the identity matrix is ​​1. Thus, the elements of the first row of the storage matrix are [0,0,2,1,3,1]. That is, only 6 elements in the first row of the storage matrix can represent 4i×i elements, greatly saving storage space.

[0136] Further, all elements of the storage matrix are obtained:

[0137]

[0138] In some embodiments, the carrier may determine the storage matrix corresponding to the parity check matrix with different sparsities based on the sparsity of the parity check matrix, and store the storage matrix in the storage space.

[0139] In step S302, in response to receiving the input codeword, the storage matrix is ​​obtained from the storage space.

[0140] In some embodiments, the carrier receives an input codeword, obtains a storage matrix from the storage space, and verifies the input codeword.

[0141] In specific implementation, the carrier can obtain a first candidate storage matrix from the storage space; based on the first candidate storage matrix and the input codeword, determine the verification weight value corresponding to the first candidate storage matrix; in response to the verification weight value being within a first preset range, determine a second candidate storage matrix in the storage space as the storage matrix; wherein the sparsity of the second candidate storage matrix is ​​greater than the sparsity of the first candidate storage matrix; or, in response to the verification weight value being within a second preset range, determine the first candidate storage matrix as the storage matrix; or, in response to the verification weight value being within a third preset range, determine the third candidate storage matrix as the storage matrix; wherein the sparsity of the third candidate storage matrix is ​​less than the sparsity of the first candidate storage matrix.

[0142] The carrier can select a more suitable storage matrix based on the verification weight value. If the current verification weight value is low, a verification matrix with lower sparsity can be selected to reduce the amount of computation in the subsequent verification process. If the current verification weight value is high, a verification matrix with higher sparsity can be selected to improve the accuracy of the subsequent verification and decoding processes.

[0143] Step S303: Based on the row position and shift value represented by the elements in any row of the storage matrix, determine the position of the non-zero item in the corresponding parity submatrix of the parity check matrix.

[0144] Step S304: Based on the positions of the non-zero items in the check sub-matrix and the input codeword, determine the check sub-result corresponding to the input codeword.

[0145] Step S305: Based on the check sub-results of all check sub-matrices corresponding to the check matrix, determine the first check result corresponding to the input codeword.

[0146] Step S306: In response to the first verification result indicating that the input codeword has failed the verification, determine whether to decode the input codeword based on the first verification result and the first flip threshold.

[0147] The specific steps of steps S303 to S306 are the same as those of steps S202 to S205, and will not be repeated here.

[0148] Thus, the data processing method provided in this embodiment of the present disclosure uses two elements in the storage matrix to represent a non-zero basis matrix in the check matrix. During storage, only the storage matrix is ​​stored, reducing storage space and speeding up matrix acquisition during check. During check, multiple check sub-matrices or each row of the storage matrix are computed in parallel to obtain the check sub-results, thereby obtaining the check result. This can speed up the check and improve decoding efficiency.

[0149] Figure 5A schematic diagram of a third optional flow of the data processing method provided in this disclosure embodiment is shown. Figure 6 A schematic diagram of the data flow of the data processing method provided in an embodiment of this disclosure is shown.

[0150] Step S501: Based on the row position and shift value represented by the elements in any row of the storage matrix, determine the position of the non-zero item in the corresponding parity submatrix of the parity check matrix.

[0151] In some embodiments, the carrier determines the position of the non-zero item in the corresponding parity submatrix in the parity check matrix based on the row position and shift value represented by the element in any row of the storage matrix.

[0152] In specific implementation, since the check matrix is ​​composed of a base matrix, in each check submatrix, at most one element in each row has a value of 1, and the values ​​of the remaining elements are all 0. Therefore, the carrier can determine the position of the non-zero item in the check submatrix based on the element in any row of the storage matrix.

[0153] Step S502: Based on the positions of the non-zero items in the check matrix and the input codeword, determine the check result corresponding to the input codeword.

[0154] In some embodiments, such as Figure 6 As shown, the carrier performs a checksum calculation on the input codeword (i.e., the initial codeword) based on the checksum matrix to obtain a checksum result. The checksum calculation may include multiplying the input codeword by the transpose of the checksum matrix, resulting in a column vector where each column represents a checksum result. Specifically, the carrier determines the elements in the input codeword corresponding to the positions of the non-zero terms, and constructs the corresponding elements in the checksum result according to their order in the input codeword; other elements in the checksum result are determined to be 0. In the checksum result, the position of the non-zero element is related to the position of the non-zero term in the checksum matrix; the value of the non-zero element in the checksum result is related to the value of the corresponding element in the input codeword.

[0155] Step S503: Based on the check results of all check sub-matrices corresponding to the check matrix, determine the first check result corresponding to the input codeword.

[0156] In some embodiments, each time the carrier acquires a verification result, it adds the verification result to the first temporary verification result and updates the first temporary verification result based on the result of the addition; the first temporary verification result is determined to be the first verification result corresponding to the input codeword; wherein the initial value of the first temporary verification result is a vector with all elements being 0.

[0157] In practice, the carrier sequentially reads the selected storage matrix row by row, reads the corresponding row position and shift value of the storage matrix, calculates in parallel the actual positions of all non-zero items in the check submatrix corresponding to each row of the storage matrix, and performs partial comparison with the corresponding input codeword. The calculation yields the checksum result, which is then modulo-2 added to the first temporary checksum result to update the first temporary checksum result in real time. Once the input code and each row of the storage matrix have been calculated, the complete first checksum result can be obtained. This method avoids the need for complete calculations. The resulting consumption of computing resources is suitable for hardware pipelining implementation.

[0158] Step S504: In response to the first verification result indicating that the input codeword has failed verification, the first flip threshold is determined.

[0159] In some embodiments, such as Figure 6 As shown, the carrier can determine whether the input codeword passes the verification based on the number of non-zero elements in the verification result (i.e., the number of verification weight values); if the number of non-zero elements is 0, it means that the input codeword passes the verification and can be directly output; if the number of non-zero elements is not 0, it means that the input codeword fails the verification and needs to be decoded.

[0160] In some embodiments, the carrier determines a first flip threshold, including: determining a first verification weight value based on a first verification result; determining a standard verification weight value based on a verification matrix; and determining the first flip threshold based on the maximum column weight of the verification matrix, the current number of calculations, the first verification weight value, the standard verification weight value, the maximum column weight offset, the iteration decay factor, and the verification weight value sensitivity coefficient.

[0161] In specific implementation, the carrier determines the attenuation value based on the iterative attenuation factor and the current number of calculations; determines the flip adjustment coefficient based on the first check weight value, the standard check weight value, and the check weight value sensitivity coefficient; and determines the first flip threshold based on the maximum column weight, the maximum column weight offset, the attenuation value, and the flip adjustment coefficient of the check matrix. The flip threshold is used to determine whether to flip the input codeword to achieve decoding of the input codeword; that is, the flip threshold is used to determine whether to perform BF flip decoding on the input codeword.

[0162] The iteration decay factor is related to the current number of verifications, and the number of calculations refers to the number of verifications that have been performed so far (or the current verification number). The maximum column weight offset is a set value. In scenarios with high verification weight values ​​or in the early stages of verification, the maximum column weight offset is 0, and the flip threshold is mainly affected by the iteration decay factor. At this time, the iteration decay factor is relatively large, and the sensitivity coefficient of the verification weight value is relatively small. In scenarios with low verification weight values ​​or in the later stages of verification, the maximum column weight offset is -1, and the flip threshold is affected by the sensitivity coefficient of the verification weight value. When the verification weight value changes abruptly (suddenly becomes high or suddenly becomes low), the verification matrix is ​​switched and the flip threshold is recalculated.

[0163] Specifically, the carrier determines the corresponding flip threshold based on the current number of flips (or decoding times, verification times). The flip threshold is determined based on the verification weight value (SW value) of the verification result obtained after each decoding and verification, and the number of flips. The flip threshold is calculated once for each flip or verification. When the SW value is high and it is the initial iteration, the flip threshold is lowered to accelerate the flipping process. When the SW value is low and it is the later iteration of the set iteration, the flip threshold is raised to prevent false flips. When the SW value changes abruptly, i.e., suddenly increases or decreases, the verification matrix is ​​switched, and the flip threshold is reset. In each round of iteration, the threshold function is set to T = col_weight – α – β × (Iteration_loop%g) + γ × log(SW / SW_norm).

[0164] Where `col_weight` is the maximum column weight of the selected parity-check matrix, and `g` is the cyclic update value of the flip threshold (`g` is less than `col_weight`). The current iteration count is represented as `Iteration_loop`. `SW` is the SW value corresponding to the previous iteration, and `SW_norm` is the standard SW value of the currently used parity-check matrix. `α`, `β`, and `γ` are the maximum column weight offset, the iteration decay factor, and the SW value sensitivity coefficient, respectively. When the decoding scenario involves high SW values ​​and early iterations, `α` defaults to 0, and the flip threshold is dominated by `β`, in which case `β` is larger and `γ` is smaller. When the decoding scenario involves low SW values ​​and later iterations, `α` defaults to -1, and the flip threshold is dominated by `γ`, in which case `γ` is larger and `β` is smaller. When the SW value changes abruptly and the iteration count is in the middle stage, the matrix is ​​switched and the corresponding threshold function is reset.

[0165] Furthermore, the carrier can determine the maximum column weight offset value based on the range corresponding to the SW value; if the SW value is within the fourth threshold range, the maximum column weight offset is determined to be 0; if the SW value is within the fifth threshold range, the maximum column weight offset is determined to be -1. The fourth threshold range is greater than the fifth threshold range, and both the fourth and fifth threshold ranges can be set according to actual needs.

[0166] Step S505: Based on the first flip threshold and the first verification weight value, determine whether to perform flip decoding.

[0167] In some embodiments, such as Figure 6 As shown, the carrier determines a first weight verification value based on the first verification result. In response to the first verification weight value being greater than or equal to the first flip threshold, the input codeword is flipped and decoded to obtain a first decoded codeword, and step S506 is executed; or, in response to the verification weight value being less than the first flip threshold, the input codeword is determined to be the first decoded codeword, and the first decoded codeword is output.

[0168] Step S506: The input codeword is flipped and decoded to obtain the first decoded codeword.

[0169] In some embodiments, such as Figure 6 As shown, the carrier can determine the codewords that fail the verification in the input codeword based on the position of the non-zero element in the first verification result, and flip the codewords that fail the verification in the input codeword (i.e., bit flip), while keeping the other codewords in the input codeword unchanged, to obtain the first decoded codeword.

[0170] Step S507: Verify the first decoded codeword based on the storage matrix to determine the second verification result.

[0171] In some embodiments, the carrier determines a first temporary verification result corresponding to the first decoded codeword based on the position of the non-zero item in the verification submatrix and the first decoded codeword; and determines a second verification result based on the first verification result and the first temporary verification result.

[0172] In specific implementation, each time the carrier obtains a check result based on the position of the non-zero item in the check sub-matrix and the first decoded codeword, the check result is added to the second temporary check result, and the second temporary check result is updated based on the result of the addition; the final second temporary check result is determined to be the first temporary check result corresponding to the input codeword; wherein, the initial value of the second temporary check result is a vector with all elements being 0.

[0173] In some embodiments, in response to the second verification result indicating that the first decoded codeword has passed the verification, the first decoded codeword is output; if the second verification result indicates that the first decoded codeword has not passed the verification, steps S505 to S507 are repeated until the verification result indicates that the decoded codeword has passed the verification, and the decoded codeword that has passed the verification is output.

[0174] In some embodiments, the method for determining the second flip threshold is the same as step S504: determining a second verification weight value based on the second verification result; determining a standard verification weight value based on the verification matrix; and determining the second flip threshold based on the maximum column weight of the verification matrix, the current number of calculations, the second verification weight value, the standard verification weight value, the maximum column weight offset, the iteration decay factor, and the verification weight value sensitivity coefficient. Specifically, the maximum column weight offset may differ from that used when calculating the first flip threshold; the iteration decay factor and the verification weight value sensitivity coefficient may differ from those used when calculating the first flip threshold; the current number of calculations is the number of calculations used to calculate the first flip threshold plus one; and the second verification weight value is determined based on the second verification result.

[0175] In some optional embodiments, after the carrier completes each verification and obtains the verification result, it determines the verification weight value based on the verification result and compares the current verification weight value with the previously obtained verification weight value. If the absolute value of the difference between the second verification weight value and the first verification weight value is greater than the change threshold, the storage matrix is ​​replaced and the input codeword is re-verified.

[0176] Thus, the data processing method provided in this disclosure uses two elements in the storage matrix to represent a non-zero basis matrix in the check matrix. During storage, only the storage matrix is ​​stored, reducing storage space and accelerating matrix acquisition during check. During check, multiple check sub-matrices or each row of the storage matrix are computed in parallel to obtain the check sub-results, thereby accelerating the check speed and facilitating hardware pipeline implementation. During decoding, determining whether to perform flip decoding based on the SW value avoids unnecessary iterations when codeword errors exceed the error correction limit of the BF decoder. Determining the flip threshold based on the number of iterations and the SW value improves the decoding performance of the BF decoder and facilitates hardware implementation.

[0177] Figure 7 A fourth optional flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0178] Step S701: Initialize the BF decoder.

[0179] In some embodiments, the carrier is configured with several pre-stored parity check matrices and the maximum column weight of the corresponding parity check matrices; a SW threshold is set for each parity check matrix; the maximum number of iterations for decoding, the flip threshold loop value, and the flip threshold function are set, and the parity check matrix is ​​a QC-LDPC code.

[0180] Step S702: Verify the input codeword.

[0181] In some embodiments, the carrier sequentially reads the storage matrix row by row, reads the corresponding row and shift factor of the storage matrix, calculates in parallel the actual positions of all non-zero items in the column of QC-Size (the dimension of the base matrix), and performs partial comparison with the corresponding input codeword. The calculation is performed, and after obtaining the result, a modulo-2 addition operation is performed with the temporary verification result at the corresponding position to update the verification result. The temporary verification result is initialized to 0. After reading all rows of the storage matrix (one round), the complete result is obtained. That is, the verification result, at which point the corresponding SW value is calculated.

[0182] Step S703: Determine the check matrix based on the SW value.

[0183] In some embodiments, the carrier can select the best-matching parity check matrix from a pre-configured set of multiple parity check matrices for different error ranges for subsequent decoding operations. When the SW value is within a set first threshold range, a parity check matrix with a higher code rate and simpler structure is selected, sacrificing some error correction capability to obtain more information transmission bits, thus gaining speed and power consumption advantages. When the SW value exceeds the set first threshold range but meets the second threshold range, a set standard matrix is ​​selected. When the SW value exceeds the second threshold range and falls into the third threshold range, a matrix with a lower code rate and more parity bits is selected, reducing the number of information bits transmitted to improve decoding accuracy. Codeword filtering based on the SW value saves unnecessary iteration delay and reduces power consumption. After determining the parity check matrix, step S702 is repeated. After executing step S702, the calculation process in step S704 is executed. If the final obtained SW value is within the set SW threshold, it enters the BF decoder; otherwise, the parity check matrix is ​​re-determined.

[0184] Step S704: Determine the verification result.

[0185] In some embodiments, the module still reads the selected parity-check matrix row by row sequentially and calculates the number of non-zero parities corresponding to QC-Size information bits in parallel. Then, the number of non-zero parities corresponding to QC-Size information bits is compared with a flip threshold. If this number of non-zero parities is greater than or equal to the flip threshold in this iteration, the information bits are flipped. Simultaneously, the flipped decoded codeword is partially compared with the corresponding parity-check matrix. The calculation and the temporary verification result are used to perform a modulo-2 addition operation to update the verification result in real time.

[0186] Step S705: Determine whether to continue decoding based on the verification weight value.

[0187] In some embodiments, after all information bits have been flipped, the carrier calculates the corresponding SW value. When SW is 0, it indicates that the verification has passed. When the result is not 0, the next round of iteration continues according to the new number of check bits, and the result of the current verification equation is set as the result of the temporary verification equation for the next round of iteration. At the same time, the flipping threshold of the next round of iteration is changed according to the threshold function. Steps S704 to S705 are repeated until the verification passes or the set maximum number of iterations is reached.

[0188] Thus, the entire iterative process utilizes part of The calculation is used to update the results of the temporary verification equation in real time, avoiding the need for complete calculations. The computation increases resource consumption and latency. However, parallel computation of QC-Size information bits improves decoding efficiency and facilitates hardware pipelining. Furthermore, after the information bits are flipped according to the threshold, the corresponding check equation results can be updated synchronously, further improving decoding efficiency.

[0189] Figure 8 A schematic diagram showing a first performance comparison between the method described in the embodiments of this disclosure and the method described in related technologies is illustrated.

[0190] Figure 8 The horizontal axis represents the residual bit error rate (RBER), and the vertical axis represents the forward frame error rate (FER).

[0191] like Figure 8 As shown, taking a code rate of 0.872 as an example, the method described in this embodiment of the present disclosure is used for testing. Under the same residual bit error rate, the method provided in this embodiment of the present disclosure has a lower forward frame error rate, which is a significant improvement compared to the prior art. This shows that the method described in this embodiment of the present disclosure can significantly improve the error correction performance of the BF decoder.

[0192] Figure 9 A second performance comparison diagram is shown between the method described in the embodiments of this disclosure and the method described in related technologies.

[0193] like Figure 9 The comparison of the average number of decoding iterations also shows that the decoding method described in this embodiment effectively reduces the number of iterative decodings, which indicates that the method described in this embodiment can effectively reduce decoding latency.

[0194] Figure 10 A schematic diagram of an optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown, and the details will be described in terms of each part.

[0195] like Figure 10As shown, the data processing device includes a storage matrix determination unit, a non-zero item determination unit, a verification unit, and a decoding unit.

[0196] The storage matrix determination unit is used to determine the elements of each row of the storage matrix based on the row position and shift value of the non-zero base matrix in each column of the parity check matrix; wherein, the rows of the storage matrix correspond one-to-one with the columns of the parity check matrix, and each non-zero base matrix in the parity check matrix corresponds to two elements in the storage matrix; the odd-numbered elements in each row of the storage matrix represent the row position of the corresponding non-zero base matrix in the parity check matrix; and the even-numbered elements represent the shift value of the corresponding non-zero base matrix.

[0197] The non-zero term determination unit is used to determine the position of the non-zero term in the corresponding parity submatrix in the parity matrix based on the row position and shift value represented by the elements in any row of the storage matrix.

[0198] The verification unit is used to determine the verification result corresponding to the input codeword based on the position of the non-zero item in the verification sub-matrix and the input codeword; in the verification sub-result, the position of the non-zero element is related to the position of the non-zero item in the verification sub-matrix; the value of the non-zero element in the verification sub-result is related to the value of the corresponding element in the input codeword; and based on the verification results of all verification sub-matrixes corresponding to the verification matrix, the first verification result corresponding to the input codeword is determined.

[0199] The decoding unit is configured to, in response to a first verification result indicating that the input codeword has failed verification, determine whether to decode the input codeword based on the first verification result and a first flip threshold.

[0200] The storage matrix determining unit, after determining the elements of each row of the storage matrix, is further configured to determine the storage matrix based on the elements of each row of the storage matrix and store the storage matrix in the storage space.

[0201] The storage matrix determination unit is also used to receive input codewords and obtain the storage matrix from the storage space.

[0202] The storage matrix determination unit is specifically configured to: obtain a first candidate storage matrix from the storage space; determine a verification weight value corresponding to the first candidate storage matrix based on the first candidate storage matrix and the input codeword; and determine a second candidate storage matrix in the storage space as the storage matrix if the verification weight value is within a first preset range, wherein the sparsity of the second candidate storage matrix is ​​greater than that of the first candidate storage matrix; or, determine the first candidate storage matrix as the storage matrix if the verification weight value is within a second preset range; or, determine the third candidate storage matrix as the storage matrix if the verification weight value is within a third preset range, wherein the sparsity of the third candidate storage matrix is ​​less than that of the first candidate storage matrix.

[0203] In some embodiments, the parity check matrix is ​​constructed based on multiple non-zero basis matrices, or based on multiple non-zero basis matrices and a zero basis matrix; all elements in the zero basis matrix are 0; the non-zero basis matrix includes an identity matrix and a matrix obtained by shifting the identity matrix based on shift values;

[0204] Each check submatrix includes one column of the base matrix from the check matrix.

[0205] The storage matrix determination unit is specifically used to determine the elements of the corresponding row of the storage matrix based on any parity submatrix in the parity matrix, specifically including:

[0206] Based on the position identifier of each non-zero basis matrix in the parity submatrix, the odd-numbered elements of the corresponding row of the storage matrix are determined;

[0207] Based on the shift value of each non-zero basis matrix in the parity submatrix, the even-numbered elements of the corresponding row of the storage matrix are determined.

[0208] The verification unit is specifically used to determine multiple verification sub-matrices and the verification results corresponding to the input codewords in parallel, specifically including performing the following operations on each verification sub-matrice:

[0209] The elements corresponding to the positions of the non-zero items in the input codeword are determined, and the check result is formed according to their order in the input codeword.

[0210] The verification unit is specifically used to determine the element in the input codeword that corresponds to the position of the non-zero item, and to form the element at the corresponding position in the verification sub-result according to its order in the input codeword;

[0211] Determine that all other elements in the checksum result are 0.

[0212] The verification unit is specifically used to add the verification sub-result to the first temporary verification result for each verification sub-result obtained, and update the first temporary verification result based on the result of the addition.

[0213] The first temporary verification result obtained is determined to be the first verification result corresponding to the input codeword;

[0214] The initial value of the first temporary verification result is a vector with all elements being 0.

[0215] The decoding unit is further configured to output the input codeword in response to the first verification result indicating that the input codeword has passed the verification.

[0216] The decoding unit is also used to determine a first verification weight value based on the first verification result;

[0217] Determine the standard verification weight value based on the verification matrix;

[0218] The first flip threshold is determined based on the maximum column weight of the check matrix, the current number of calculations, the first check weight value, the standard check weight value, the maximum column weight offset, the iteration decay factor, and the check weight value sensitivity coefficient.

[0219] The decoding unit is specifically used to determine the attenuation value based on the iterative attenuation factor and the current number of calculations;

[0220] The flip adjustment coefficient is determined based on the first check weight value, the standard check weight value, and the check weight value sensitivity coefficient.

[0221] The first flip threshold is determined based on the maximum column weight, maximum column weight offset, attenuation value, and flip adjustment coefficient of the parity matrix.

[0222] The decoding unit is specifically used to determine the first verification weight value based on the first verification result;

[0223] In response to the first verification weight value being greater than or equal to the first flip threshold, the input codeword is flipped and decoded to obtain the first decoded codeword;

[0224] Alternatively, in response to the verification weight value being less than the first flip threshold, the input codeword is determined to be the first decoded codeword.

[0225] The decoding unit is specifically used to determine the first temporary check result corresponding to the first decoded codeword based on the position of the non-zero item in the check submatrix and the first decoded codeword.

[0226] Based on the first verification result and the first temporary verification result, the second verification result is determined;

[0227] In response to the second verification result indicating that the first decoded codeword has passed the verification, the first decoded codeword is output.

[0228] Alternatively, in response to the second verification result indicating that the first decoded codeword has failed verification, a second verification weight value is determined based on the second verification result; and based on the second verification weight value and the second flip threshold, it is determined whether to decode the first decoded codeword.

[0229] The decoding unit is specifically used to obtain a check result based on the position of the non-zero item in the check sub-matrix and the first decoded codeword, then add the check result to the second temporary check result, and update the second temporary check result based on the result of the addition;

[0230] The final obtained second temporary verification result is determined to be the first temporary verification result corresponding to the input codeword;

[0231] The initial value of the second temporary verification result is a vector with all elements being 0.

[0232] The decoding unit is specifically used to compare the first check weight value and the second check weight value.

[0233] If the absolute value of the difference between the second check weight value and the first check weight value is greater than the change threshold, the storage matrix is ​​replaced and the input codeword is re-checked.

[0234] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0235] Figure 11 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0236] like Figure 11 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0237] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0238] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0239] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0240] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0241] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0242] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0243] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0244] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0245] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0246] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0247] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, The method includes: Based on the row positions and shift values ​​of the non-zero basis matrices in each column of the parity-check matrix, the elements of each row of the storage matrix are determined. The rows of the storage matrix correspond one-to-one with the columns of the parity-check matrix, and each non-zero basis matrix in the parity-check matrix corresponds to two elements in the storage matrix. Odd-numbered elements in each row of the storage matrix represent the row position of the corresponding non-zero basis matrix in the parity-check matrix; even-numbered elements represent the shift value of the corresponding non-zero basis matrix. The non-zero basis matrices include the identity matrix and the matrix obtained by shifting the identity matrix based on the shift value. Based on the row position and shift value represented by the elements in any row of the storage matrix, determine the position of the non-zero item in the corresponding parity submatrix of the parity matrix; Based on the positions of the non-zero items in the check matrix and the input codeword, the check result corresponding to the input codeword is determined; in the check result, the position of the non-zero element is related to the position of the non-zero item in the check matrix; the value of the non-zero element in the check result is related to the value of the corresponding element in the input codeword. Based on the check results of all check sub-matrices corresponding to the check matrix, determine the first check result corresponding to the input codeword; The first verification weight value is determined based on the first verification result; the standard verification weight value is determined based on the verification matrix; the first flip threshold is determined based on the maximum column weight of the verification matrix, the current number of calculations, the first verification weight value, the standard verification weight value, the maximum column weight offset, the iteration decay factor, and the sensitivity coefficient of the verification weight value. In response to the first verification result indicating that the input codeword has failed verification, a determination is made, based on the first verification result and the first flip threshold, whether to decode the input codeword, specifically including: In response to the first verification weight value being greater than or equal to the first flip threshold, the input codeword is flipped and decoded to obtain the first decoded codeword; Alternatively, in response to the first verification weight value being less than the first flip threshold, the input codeword is determined to be the first decoded codeword.

2. The method according to claim 1, characterized in that, After determining the elements of each row of the storage matrix, the method further includes: The storage matrix is ​​determined based on the elements of each row of the storage matrix, and the storage matrix is ​​stored in the storage space.

3. The method according to claim 2, characterized in that, The method further includes: Receive input codewords; The storage matrix is ​​obtained from the storage space.

4. The method according to claim 3, characterized in that, The step of obtaining the storage matrix from the storage space includes: Obtain the first alternative storage matrix from the storage space; Based on the first candidate storage matrix and the input codeword, determine the verification weight value corresponding to the first candidate storage matrix; In response to the verification weight value being within a first preset range, a second candidate storage matrix in the storage space is determined as the storage matrix; wherein the sparsity of the second candidate storage matrix is ​​greater than the sparsity of the first candidate storage matrix; Alternatively, in response to the verification weight value being within a second preset range, the first candidate storage matrix is ​​determined to be the storage matrix; Alternatively, in response to the verification weight value being within a third preset range, a third candidate storage matrix is ​​determined as the storage matrix; wherein the sparsity of the third candidate storage matrix is ​​less than the sparsity of the first candidate storage matrix.

5. The method according to claim 1, characterized in that, The verification matrix is ​​constructed based on multiple non-zero basis matrices, or based on multiple non-zero basis matrices and a zero basis matrix; all elements in the zero basis matrix are 0. Each check submatrix includes one column of the base matrix from the check matrix.

6. The method according to claim 5, characterized in that, The process of determining the elements of each row of the storage matrix based on the row positions and shift values ​​of the non-zero basis matrices in each column of the parity-check matrix includes: Based on any parity submatrix in the parity check matrix, determine the elements of the corresponding row in the storage matrix, specifically including: Based on the position identifier of each non-zero basis matrix in the parity submatrix, the odd-numbered elements of the corresponding row of the storage matrix are determined; Based on the shift value of each non-zero basis matrix in the parity submatrix, the even-numbered elements of the corresponding row of the storage matrix are determined.

7. The method according to claim 1, characterized in that, The process of determining the check result corresponding to the input codeword based on the positions of the non-zero items in the check matrix and the input codeword includes: Multiple check sub-matrices and check sub-results corresponding to the input codewords are determined in parallel, specifically including performing the following operations on each check sub-matrice: The elements corresponding to the positions of the non-zero items in the input codeword are determined, and the check result is formed according to their order in the input codeword.

8. The method according to claim 1, characterized in that, The process of determining the check result corresponding to the input codeword based on the positions of the non-zero items in the check matrix and the input codeword includes: Determine the elements in the input codeword that correspond to the positions of the non-zero items, and construct the elements at the corresponding positions in the check result according to their order in the input codeword; Determine that all other elements in the checksum result are 0.

9. The method according to claim 7 or 8, characterized in that, The determination of the first verification result corresponding to the input codeword based on the verification results of all verification sub-matrices corresponding to the verification matrix includes: For each verification sub-result obtained, the verification sub-result is added to the first temporary verification result, and the first temporary verification result is updated based on the result of the addition. The first temporary verification result obtained is determined to be the first verification result corresponding to the input codeword; The initial value of the first temporary verification result is a vector with all elements being 0.

10. The method according to claim 1, characterized in that, The method further includes: In response to the first verification result indicating that the input codeword passes the verification, the input codeword is output.

11. The method according to claim 1, characterized in that, The determination of the first flip threshold based on the maximum column weight of the verification matrix, the current number of calculations, the first verification weight value, the standard verification weight value, the maximum column weight offset, the iteration decay factor, and the sensitivity coefficient of the verification weight value includes: The decay value is determined based on the iterative decay factor and the current number of calculations; The flip adjustment coefficient is determined based on the first check weight value, the standard check weight value, and the check weight value sensitivity coefficient. The first flip threshold is determined based on the maximum column weight, maximum column weight offset, attenuation value, and flip adjustment coefficient of the parity matrix.

12. The method according to claim 1, characterized in that, The method further includes: Based on the positions of the non-zero items in the check submatrix and the first decoded codeword, determine the first temporary check result corresponding to the first decoded codeword; Based on the first verification result and the first temporary verification result, the second verification result is determined; In response to the second verification result indicating that the first decoded codeword has passed the verification, the first decoded codeword is output. Alternatively, in response to the second verification result indicating that the first decoded codeword has failed verification, a second verification weight value is determined based on the second verification result; and based on the second verification weight value and the second flip threshold, it is determined whether to decode the first decoded codeword.

13. The method according to claim 12, characterized in that, The determination of the first temporary check result corresponding to the first decoded codeword based on the position of the non-zero item in the check submatrix and the first decoded codeword includes: For each check result obtained based on the position of the non-zero item in the check matrix and the first decoded codeword, the check result is added to the second temporary check result, and the second temporary check result is updated based on the result of the addition. The final obtained second temporary verification result is determined to be the first temporary verification result corresponding to the first decoded codeword; The initial value of the second temporary verification result is a vector with all elements being 0.

14. The method according to claim 12, characterized in that, The method further includes: Compare the first check weight value and the second check weight value; If the absolute value of the difference between the second check weight value and the first check weight value is greater than the change threshold, the storage matrix is ​​replaced and the input codeword is re-checked.

15. A data processing apparatus, characterized in that, The device includes: The storage matrix determination unit is used to determine the elements of each row of the storage matrix based on the row position and shift value of the non-zero basis matrix in each column of the parity check matrix. The rows of the storage matrix correspond one-to-one with the columns of the parity check matrix, and each non-zero basis matrix in the parity check matrix corresponds to two elements in the storage matrix. Odd-numbered elements in each row of the storage matrix represent the row position of the corresponding non-zero basis matrix in the parity check matrix; even-numbered elements represent the shift value of the corresponding non-zero basis matrix. The non-zero basis matrix includes the identity matrix and the matrix obtained by shifting the identity matrix based on the shift value. The non-zero term determination unit is used to determine the position of the non-zero term in the corresponding parity submatrix of the parity check matrix based on the row position and shift value represented by the elements in any row of the storage matrix. The verification unit is used to determine the verification result corresponding to the input codeword based on the position of the non-zero item in the verification sub-matrix and the input codeword; in the verification sub-result, the position of the non-zero element is related to the position of the non-zero item in the verification sub-matrix; the value of the non-zero element in the verification sub-result is related to the value of the corresponding element in the input codeword; and the first verification result corresponding to the input codeword is determined based on the verification results of all verification sub-matrixes corresponding to the verification matrix. The decoding unit is configured to: determine a first check weight value based on a first check result; determine a standard check weight value based on a check matrix; determine a first flip threshold based on the maximum column weight of the check matrix, the current number of calculations, the first check weight value, the standard check weight value, the maximum column weight offset, the iteration decay factor, and the check weight value sensitivity coefficient; and, in response to the first check result indicating that the input codeword has failed the check, determine whether to decode the input codeword based on the first check result and the first flip threshold. Specifically, in response to the first check weight value being greater than or equal to the first flip threshold, the unit performs flip decoding on the input codeword to obtain a first decoded codeword; or, in response to the first check weight value being less than the first flip threshold, determines the input codeword as the first decoded codeword.

16. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-14.

17. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-14.

18. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-14.

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