Uci e-based data transmission method, storage medium and artificial intelligence chip

Abstract

The application provides a data transmission method based on UCIe, a storage medium and an artificial intelligence chip. The data transmission method comprises the following steps: communicating through a first core particle and a second core particle; receiving a bypass receiving data signal and a bypass receiving clock signal from a sending module of the first core particle through a receiving module of the second core particle; transmitting the bypass receiving data signal and the bypass receiving clock signal to a serial-parallel conversion module of the second core particle through the receiving module; counting the bypass receiving clock signal through the serial-parallel conversion module to obtain a bypass receiving frame count value, and sampling the bypass receiving data signal according to the bypass receiving frame count value; determining a bypass spur removal count value according to a bypass spur removal counter start signal through the serial-parallel conversion module; and resetting the bypass receiving frame count value through the serial-parallel conversion module when the bypass spur removal count value is equal to a bypass spur removal counter threshold value. The application can ensure good data transmission quality between core particles.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a UCIe-based data transmission method, a computer-readable storage medium, and an artificial intelligence chip. Background Technology

[0002] During communication between chips, since the bypass received data and bypass received clock are in one-to-one correspondence, the type of bypass data packet needs to be determined based on the data packet type code (opcode), and the serial-to-parallel conversion also needs to be completed based on the counting of the bypass received clock signal. However, if a clock glitch occurs on the receiving link, the receiver will experience data mis-sampling, which may lead to errors in data packet type code determination and serial-to-parallel conversion, ultimately resulting in bypass data packet parsing errors. Summary of the Invention

[0003] This invention relates to a UCIe-based data transmission method, a computer-readable storage medium, and an artificial intelligence chip, which can effectively ensure the reliability and correctness of data transmission in die-to-die sideband (or auxiliary channel) data transmission.

[0004] According to an embodiment of the present invention, the UCIe-based data transmission method of the present invention includes the following steps: communicating with a second chip via a first chip; receiving a bypass reception data signal and a bypass reception clock signal from the transmitting module of the first chip via a receiving module of the second chip; transmitting the bypass reception data signal and the bypass reception clock signal to a serial-to-parallel conversion module of the second chip via the receiving module; counting the bypass reception clock signal via the serial-to-parallel conversion module to obtain a bypass reception frame count value, and sampling the bypass reception data signal according to the bypass reception frame count value; determining the bypass glitch clearing count value via the serial-to-parallel conversion module according to a bypass glitch clearing counter start signal; and resetting the bypass reception frame count value via the serial-to-parallel conversion module when the bypass glitch clearing count value is equal to the bypass glitch clearing counter threshold value.

[0005] In the data transmission method according to an embodiment of the present invention, the data transmission method further includes the following steps: generating a bypass reception valid indication signal by means of the serial-to-parallel conversion module according to the clock domain of the bypass reception clock signal; and synchronizing the bypass reception valid indication signal to the clock domain of the bypass normally open clock signal by means of the serial-to-parallel conversion module to generate the bypass glitch clearing counter start signal.

[0006] In the data transmission method according to an embodiment of the present invention, the step of counting the bypass glitch clearing count value includes: when the bypass received frame count value is greater than or equal to the clearing counter start threshold value, the bypass glitch clearing count value is started through the serial-to-parallel conversion module.

[0007] In the data transmission method according to an embodiment of the present invention, the bypass glitch clearing counter threshold value is equal to the number of bits of bypass data packets plus the number of idle intervals between bypass data packets, minus the clearing counter start threshold value, minus the synchronization count, and minus the safety margin value.

[0008] In the data transmission method according to an embodiment of the present invention, the step of counting the bypass glitch clearing count value includes: starting to count the bypass glitch clearing count value through the serial-to-parallel conversion module at the rising edge of the bypass receiving valid indication signal.

[0009] In the data transmission method according to an embodiment of the present invention, the step of resetting the bypass received frame count value includes: when the bypass glitch clearing count value is equal to the bypass glitch clearing counter threshold value, the bypass glitch clearing count value is reset to zero by the serial-to-parallel conversion module, and an asynchronous clearing signal for the bypass received frame counter is generated; and the bypass received frame count value is asynchronously reset by the asynchronous clearing signal for the bypass received frame counter using the serial-to-parallel conversion module.

[0010] In the data transmission method according to an embodiment of the present invention, the step of resetting the bypass received frame count value includes: when the serial-to-parallel conversion module determines that the length of the bypass received data packet of the bypass received data signal is a first length according to the bypass data packet type code, the serial-to-parallel conversion module resets the bypass received frame count value to the first reset value.

[0011] In the data transmission method according to an embodiment of the present invention, the step of resetting the bypass received frame count value further includes: when the serial-to-parallel conversion module determines that the length of the bypass data packet of the bypass received data signal is not a first length, the serial-to-parallel conversion module determines whether the bypass glitch clearing count value is greater than or equal to a first length threshold value and less than a second length threshold value, so as to reset the bypass received frame count value to a second reset value, wherein the second length threshold value is greater than the first length threshold value.

[0012] In the data transmission method according to an embodiment of the present invention, the step of resetting the bypass received frame count value further includes: when the bypass glitch clearing count value is greater than or equal to the first length threshold value and less than the second length threshold value, resetting the bypass received frame count value to the second reset value through the serial-to-parallel conversion module; and when the bypass glitch clearing count value is less than the first length threshold value, or greater than or equal to the second length threshold value, resetting the bypass received frame count value to the third reset value through the serial-to-parallel conversion module.

[0013] In the data transmission method according to an embodiment of the present invention, the bypass receive frame count value is reset during the idle interval between two bypass data packets.

[0014] In the data transmission method according to an embodiment of the present invention, the bypass receive frame count value is reset during the idle interval between bypass data packets of a bypass data packet.

[0015] According to an embodiment of the present invention, the computer-readable storage medium is used to store a computer program. The computer program is executed by a processor to implement the steps of the UCIe-based data transmission method.

[0016] According to an embodiment of the present invention, the artificial intelligence chip of the present invention includes a first chip and a second chip. The second chip is coupled to the first chip and is used to communicate with the first chip. A receiving module of the second chip receives a bypass reception data signal and a bypass reception clock signal from a transmitting module of the first chip, and the receiving module transmits the bypass reception data signal and the bypass reception clock signal to a serial-to-parallel conversion module of the second chip. The serial-to-parallel conversion module counts the bypass reception clock signal to obtain a bypass reception frame count value, samples the bypass reception data signal according to the bypass reception frame count value, and determines the bypass glitch clearing count value according to a bypass glitch clearing counter start signal. When the bypass glitch clearing count value is equal to the bypass glitch clearing counter threshold value, the bypass reception frame count value is reset by the serial-to-parallel conversion module.

[0017] Based on the above, the UCIe-based data transmission method, computer-readable storage medium, and artificial intelligence chip of the present invention can accurately sample bypass data packets during bypass communication, thereby effectively ensuring the data transmission quality of bypass between chips.

[0018] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of the present invention;

[0021] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present invention;

[0022] Figure 4 This is a flowchart illustrating the reset bypass receive frame count value according to an embodiment of the present invention;

[0023] Figure 5 This is a data timing diagram of multiple signals according to an embodiment of the present invention;

[0024] Figure 6 This is a data timing diagram of multiple signals according to another embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.

[0026] Explanation of icon numbers

[0027] 100: Data transmission system;

[0028] 110: First chip;

[0029] 111: First physical layer architecture;

[0030] 121: Second physical layer architecture;

[0031] 112: Encoding module;

[0032] 113: Parallel-to-serial conversion module;

[0033] 114: Sending module;

[0034] 120: Second core;

[0035] 122: Receiver module;

[0036] 123: Serial-to-parallel conversion module;

[0037] 124: Decoding module;

[0038] 201: Encoded signal;

[0039] 202: Serial data signal;

[0040] 203: First bypass receives data signal;

[0041] RSD: Second bypass data reception signal;

[0042] 204: First sampled data signal;

[0043] SD: Second sampled data signal;

[0044] RSC: Bypass receive clock signal;

[0045] SC: Bypass Receive Frame Count;

[0046] SCA: Bypass normally open clock signal;

[0047] SCC: Bypass glitch removal count;

[0048] SFC: Bypass Receive Frame Counter Asynchronous Clear Signal;

[0049] 700: Artificial intelligence chip. Detailed Implementation

[0050] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0051] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention. (See reference) Figure 1 The data transmission system 100 includes a first chiplet 110 and a second chiplet 120. The first chiplet 110 and the second chiplet 120 are used to implement inter-chiplet communication based on the Universal Chiplet Interconnect Express (UCIe) protocol. The first chiplet 110 can be coupled to the second chiplet 120, for example, via multiple bump lanes.

[0052] In this embodiment, bypass communication can be established between the first chip 110 and the second chip 120, wherein the bypass is independent of the main data channel between the first chip 110 and the second chip 120. In this embodiment, the bypass can be composed of a clock channel (i.e., a clock signal line) and a data channel (i.e., a data signal line). In this embodiment, the first chip 110 and the second chip 120 can transmit information through sideband messages to, for example, implement link initialization and link training between the first chip 110 and the second chip 120.

[0053] In this embodiment, the bypass is used to transmit control signals or management information and to ensure efficient collaboration between the cores. For example, the first core 110 and the second core 120 can transmit control commands through the bypass to help coordinate the operation of the main data channel. The first core 110 and the second core 120 can also transmit core status information, such as error detection or performance monitoring, through the bypass.

[0054] In one embodiment of the present invention, the data transmission system 100 may be implemented in an electronic device, and the electronic device includes a storage unit and a processor. The storage unit is used to store a computer program. The processor is coupled to the storage unit and is used to execute the computer program stored in the storage unit to cause the electronic device to perform the UCIe-based data transmission method as described in the embodiments of the present invention.

[0055] Processors may include, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar processing devices, or combinations thereof.

[0056] Storage units may include, for example, random access memory (RAM), non-volatile memory, hard disk drive (HDD), or solid state drive (SSD). Random access memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile memory may include, for example, flash memory or read-only memory (ROM).

[0057] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of the present invention. (Reference) Figure 2 , Figure 1 The first core 110 may have the following characteristics: Figure 2 The circuit configuration of the first physical layer architecture 111 shown, and the second chip 120 may have, as Figure 2The circuit configuration of the second physical layer architecture 121 is shown. In this embodiment, the first physical layer architecture 111 of the first chip 110 includes an encoding module 112, a parallel-to-serial conversion module 113, and a transmitting module 114. The second physical layer architecture 121 of the second chip 120 includes a receiving module 122, a serial-to-parallel conversion module 123, and a decoding module 124. In this embodiment, the parallel-to-serial conversion module 113 is coupled to the encoding module 112 and the transmitting module 114. The serial-to-parallel conversion module 123 is coupled to the receiving module 122 and the decoding module 124. The transmitting module 114 is coupled to the receiving module 122.

[0058] In this embodiment, the encoding module 112 can receive the RDI (Raw Die-to-Die Interface) bypass configuration signal and the RDI bypass configuration valid signal, and generate the corresponding encoded signal 201. The encoding module 112 can encode the sideband packet to generate the encoded signal 201, and transmit the encoded signal 201 to the parallel-to-serial conversion module 113. The parallel-to-serial conversion module 113 performs parallel-to-serial conversion on the encoded signal 201 and outputs a serial data signal 202 to the transmitting module 114. The transmitting module 114 can transmit the serial data signal 202 to the receiving module 122. The receiving module 122 can use the serial data signal 202 as a first bypass received data signal 203 and transmit the first bypass received data signal 203 to the serial-to-parallel conversion module 123. Furthermore, the receiving module 122 can also receive the accompanying clock signal from the transmitting module 114 as a bypass received clock signal.

[0059] In this embodiment, the serial-to-parallel conversion module 123 performs serial-to-parallel conversion on the first bypass received data signal 203, and samples the first bypass received data signal 203, which has been converted into a parallel data signal, according to the bypass received clock signal to generate a first sampled data signal 204. The serial-to-parallel conversion module 123 outputs the first sampled data signal 204 to the decoding module 124. The decoding module 124 decodes the first sampled data signal 204, performs related parsing operations on the bypass data packets, and outputs the corresponding RDI bypass configuration signal and RDI bypass configuration valid signal to the subsequent circuit.

[0060] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present invention. (See reference...) Figure 2 as well as Figure 3The first chip 110 and the second chip 120 can perform data transmission as described in steps S310 to S360. In step S310, the first chip 110 and the second chip 120 communicate. In step S320, the receiving module 122 of the second chip 120 receives a first bypass received data signal 203 and a bypass received clock signal from the transmitting module 114 of the first chip 110. In step S330, the receiving module 122 transmits the first bypass received data signal 203 and the bypass received clock signal to the serial-to-parallel conversion module 123 of the second chip 120. In step S340, the serial-to-parallel conversion module 123 counts the bypass received clock signal to obtain a bypass received frame count value, and samples the first bypass received data signal 203 according to the bypass received frame count value. In this embodiment, the bypass received clock signal serves as a clock strobe signal. The data edges of the first bypass received data signal 203 are aligned with the edges of each pulse of the bypass received clock signal. When the serial-to-parallel conversion module 123 detects a pulse of the bypass receiving clock signal, it counts the bypass receiving frame count and records the data sampling result of the first bypass receiving data signal 203. When the bypass receiving frame count reaches a specific value, the serial-to-parallel conversion module 123 can sample at the corresponding parallel data sampling position to generate parallel data.

[0061] In step S350, the serial-to-parallel conversion module 123 determines the bypass glitch clearing count value based on the bypass glitch clearing counter start signal. In this embodiment, the serial-to-parallel conversion module 123 generates a bypass reception valid indication signal based on the clock domain of the bypass reception clock signal. Furthermore, the serial-to-parallel conversion module 123 synchronizes the bypass reception valid indication signal to the clock domain of the bypass normally open clock signal to generate the bypass glitch clearing counter start signal. In this embodiment, when the bypass reception frame count value is greater than or equal to the clearing counter start threshold value, the serial-to-parallel conversion module 123 starts counting the bypass glitch clearing count value.

[0062] In step S360, when the bypass glitch clearing count value is equal to the bypass glitch clearing counter threshold value, the serial-to-parallel conversion module 123 resets the bypass received frame count value.

[0063] In one embodiment, the bypass receive frame count is reset during the idle interval between two bypass data packets. Alternatively, the bypass receive frame count is reset during the idle interval between bypass data packets within a single bypass data packet. This effectively avoids data sampling errors caused by glitches in the bypass receive clock signal during the idle interval between two bypass data packets or between bypass data packets within a single bypass data packet.

[0064] Figure 4This is a flowchart illustrating the reset bypass receive frame count value according to an embodiment of the present invention. (See reference) Figures 2 to 4 In the above embodiments, the specific implementation of resetting the bypass receive frame count value can be achieved as follows: steps S401 to S410. In step S401, the serial-to-parallel conversion module 123 sets relevant parameters to generate a bypass receive valid indication signal. Specifically, when the bypass receive frame count value is greater than or equal to the clear counter start threshold, the serial-to-parallel conversion module 123 sets the bypass receive valid indication signal to 1 (e.g., sets the signal level to high). When the bypass receive frame count value is less than the clear counter start threshold, the serial-to-parallel conversion module 123 sets the bypass receive valid indication signal to 0 (e.g., sets the signal level to low).

[0065] In step S402, the serial-to-parallel conversion module 123 synchronizes the bypass receive valid indication signal to the clock domain of the bypass normally open clock signal to generate a bypass glitch clearing counter start signal. In step S403, the serial-to-parallel conversion module 123 starts counting the bypass glitch clearing count value according to the bypass glitch clearing counter start signal. Specifically, the serial-to-parallel conversion module 123 starts counting the bypass glitch clearing count value on the rising edge of the bypass receive valid indication signal. In step S404, when the bypass glitch clearing count value equals the bypass glitch clearing counter threshold value, the serial-to-parallel conversion module 123 resets the bypass glitch clearing count value to zero and generates an asynchronous clear signal for the bypass receive frame counter.

[0066] In one embodiment, the bypass glitch clearing counter threshold is equal to the number of bits in the bypass data packet count plus the number of idle intervals between bypass data packets, minus the clearing counter start threshold, minus the synchronization count, and minus the safety margin. The number of bits in the bypass data packet count represents the number of unit intervals (UI) of a bypass data packet, and its value can be, for example, 64. The number of idle intervals between bypass data packets represents the minimum number of UIs during the idle interval between two bypass data packets, and its value can be, for example, 32. The clearing counter start threshold represents the threshold value for starting to count the bypass glitch clearing count, and its value can be, for example, 1 or 5. The synchronization count represents the clock cycles required to synchronize the bypass receive valid indication signal to the clock domain of the bypass normally open clock signal, and its value can be, for example, 3. The safety margin represents the number of unit intervals from the next bypass data packet when the bypass receive frame count is asynchronously reset, and its value can be, for example, 3. In this regard, the smaller the safety margin value, the larger the range that can be cleared of burrs, but the safety margin needs to be taken into account.

[0067] To illustrate further, when the first chip 110 and the second chip 120 are operating in the link training phase, the interaction of bypass data packets between them is relatively dense, resulting in a small interval between each bypass data packet. Therefore, the number of glitches between two bypass data packets generally does not exceed five. Thus, the clear counter start threshold can be set to 5, and the bypass glitch clear counter threshold can be 85. When the first chip 110 and the second chip 120 are operating in the active phase, the interval between bypass data packet interactions between them is longer (affected by chip temperature and crosstalk between data lines). The number of glitches between the two bypass data packets may increase and accumulate over a longer period. Therefore, the clear counter start threshold can be set to 1, and the bypass glitch clear counter threshold can be 89.

[0068] In step S405, the serial-to-parallel conversion module 123 asynchronously resets the bypass received frame count value using an asynchronous clear signal from the bypass received frame counter. For example, the serial-to-parallel conversion module 123 can asynchronously reset the lower-order bits (e.g., bits [5:0]) of the bypass received frame count value. In step S406, the serial-to-parallel conversion module 123 determines whether the bypass data packet length of the bypass received data signal is the first length based on the bypass data packet type code. In one embodiment, the first length can be a 64-bit data length, but the invention is not limited thereto. The first length can be determined according to different usage requirements or UCIe protocol specifications.

[0069] When the serial-to-parallel conversion module 123 determines that the length of the bypass data packet of the bypass received data signal is the first length, in step S407, the serial-to-parallel conversion module 123 resets the bypass received frame count value to the first reset value. The first reset value can be, for example, 0, but the present invention is not limited thereto. When the serial-to-parallel conversion module 123 determines that the length of the bypass data packet of the bypass received data signal is not the first length, in step S408, the serial-to-parallel conversion module 123 determines whether the bypass glitch clearing count value is greater than or equal to the first length threshold value and less than the second length threshold value. The second length threshold value is greater than the first length threshold value. When the bypass glitch clearing count value is greater than or equal to the first length threshold value, in step S409, the serial-to-parallel conversion module 123 resets the bypass received frame count value to the second reset value. The second reset value can be, for example, 64, but the present invention is not limited thereto. When the bypass glitch clearing count value is less than the first length threshold value, in step S410, the serial-to-parallel conversion module 123 resets the bypass received frame count value to the third reset value. The third reset value may be, for example, 0, but the invention is not limited thereto. The first reset value may be, for example, the same as the third reset value, but the invention is not limited thereto either.

[0070] Therefore, in this embodiment, since the bypass receive frame count value can be properly reset, the problem of data sampling error caused by glitches in the bypass receive clock signal during the idle interval between two bypass data packets or during the idle interval between bypass data packets of a bypass data packet can be effectively avoided.

[0071] Figure 5 This is a data timing diagram of multiple signals according to an embodiment of the present invention. (Reference) Figure 2 as well as Figure 5 For example, the receiving module 122 of the second chip 120 can receive data from the transmitting module 114 of the first chip 110, such as... Figure 5 The second bypass receive data signal RSD and the bypass receive clock signal RSC are shown. The second bypass receive data signal RSD and the first bypass receive data signal 203 are different representations of the bypass receive data signal in different figures and embodiments. Both are bypass receive data signals. The second bypass receive data signal RSD is used to transmit two 64-bit bypass data packets during the period from time t0 to time t3. During the period from time t0 to time t1 (64 UIs), the second bypass receive data signal RSD may transmit, for example, one bypass data packet, which may include, for example, data B[0] to B

[63] , where m is between 0 and 63. During the period from time t2 to time t3 (64 UIs), the second bypass receive data signal RSD may transmit, for example, another bypass data packet, which may include, for example, data B[0] to B

[63] . During the idle interval from time t1 to time t2 (greater than or equal to 32 UIs), the second bypass received data signal RSD is operable at a low level, and the bypass received clock signal RSC is also operable at a low level. The receiving module 122 provides the second bypass received data signal RSD and the bypass received clock signal RSC to the serial-to-parallel conversion module 123. The serial-to-parallel conversion module 123 can count the bypass received clock signal RSC to obtain a bypass received frame count value SC, and sample the second bypass received data signal RSD to generate a 64-bit parallel second sampled data signal SD. The second sampled data signal SD and the first sampled data signal 204 are different representations of sampled data signals in different figures and embodiments; both are sampled data signals.

[0072] During the period from time t0 to time t1, the serial-to-parallel conversion module 123 determines that the data packet of the second bypass received data signal RSD is 64 bits. Therefore, when the bypass received frame count value SC counts to 64, the serial-to-parallel conversion module 123 resets it to zero and samples the data D0 to D63 sampled during the period from time t0 to time t1 as parallel data. The serial-to-parallel conversion module 123 can sample the data B[0] to B

[63] of the second bypass received data signal RSD during the period from time t0 to time t1 to generate a second sampled data signal SD with corresponding data D0 to D63. Then, since the bypass received clock signal RSC glitches during the idle interval from time t1 to time t2, the serial-to-parallel conversion module 123 incorrectly counts the bypass received frame count value SC as 1 during the idle interval from time t1 to time t2.

[0073] To avoid data sampling errors, the serial-to-parallel conversion module 123 generates a bypass reception valid indication signal based on the clock domain of the bypass reception clock signal RSC, and synchronizes the bypass reception valid indication signal to the clock domain of the bypass normally open clock signal SCA to generate a bypass glitch clearing counter start signal.

[0074] The bypass normally open clock signal SCA can be, for example, a clock signal with a frequency of 800 MHz. The serial-to-parallel conversion module 123 determines the bypass glitch clearing count value SCC based on the bypass glitch clearing counter start signal. Furthermore, when the bypass glitch clearing count value SCC equals the bypass glitch clearing counter threshold (i.e., the bypass glitch clearing count value equals N), the serial-to-parallel conversion module 123 resets the bypass glitch clearing count value SCC to zero and generates an asynchronous clear signal SFC for the bypass receive frame counter. Therefore, during the idle interval from time t1 to time t2, the serial-to-parallel conversion module 123 asynchronously resets the bypass receive frame counter count value SC using the pulse signal of the asynchronous clear signal SFC, wherein the bypass receive frame counter count value SC can be reset to 0.

[0075] In this way, the serial-to-parallel conversion module 123 can sample the data B[0] to B

[63] of the second bypass received data signal RSD during the period from time t2 to time t3 to generate a second sampled data signal SD with corresponding data D0 to D63. The serial-to-parallel conversion module 123 can correctly sample the serial data B[0] to B

[63] during the period from time t2 to time t3 into parallel data D0 to D63, without recording the missampled data caused by glitches during the idle interval from time t1 to time t2.

[0076] Furthermore, the bypass glitch clearing counter threshold value in this embodiment can be calculated using the following formula (1). In formula (1), the symbol N represents the bypass glitch clearing counter threshold value. The symbol SDN represents the number of bits of bypass data packets. The symbol SIN represents the number of idle intervals between bypass data packets. The symbol M represents the clearing counter start threshold value. The symbol SN represents the number of synchronization steps. The symbol SM represents the safety margin value.

[0077] N = SDN + SIN - M - SN - SM (1)

[0078] like Figure 5 As shown, the period from time t0 to time t1 corresponds to the number of bypass data packet bits, SDN. The period from time t1 to time t2 can correspond to the number of idle intervals between bypass data packets, SIN. During the period from time t0 to time t1, the period from when the bypass normally open clock signal SCA counts to the clear counter start threshold M and the bypass glitch clear counter value SCC starts counting is the synchronization count SN. During the period from time t1 to time t2, the period from when the bypass glitch clear counter value SCC counts to the bypass glitch clear counter threshold N and the next bypass data packet is received is the safety margin value SM. Furthermore, the relevant values ​​and signal settings in the above example embodiment can be referred to the above... Figures 1 to 4 The embodiments are described in detail, so they will not be elaborated further.

[0079] Figure 6 This is a data timing diagram of multiple signals according to another embodiment of the present invention. (See reference) Figure 2 as well as Figure 6 For example, the receiving module 122 of the second chip 120 can receive data from the transmitting module 114 of the first chip 110, such as... Figure 6The second bypass receive data signal RSD and bypass receive clock signal RSC are shown. The second bypass receive data signal RSD is used to transmit a bypass data packet during the period from time t0 to time t3. During the period from time t0 to time t1 (64 UIs), the second bypass receive data signal RSD may, for example, transmit the header data of the bypass data packet, wherein the header data may, for example, include data B[0] to B

[63] . During the period from time t2 to time t3 (64 UIs), the second bypass receive data signal RSD may, for example, transmit the payload data of the bypass data packet, wherein the payload data may, for example, include data B

[64] to B

[127] . During the idle interval from time t1 to time t2 (greater than or equal to 32 UIs), the second bypass receive data signal RSD may operate at a low level, and the bypass receive clock signal RSC also operates at a low level. The receiving module 122 provides the second bypass receive data signal RSD and the bypass receive clock signal RSC to the serial-to-parallel conversion module 123. The serial-to-parallel conversion module 123 can count the bypass receive clock signal RSC to obtain the bypass receive frame count value SC, and sample the second bypass receive data signal RSD to generate the second sampled data signal SD.

[0080] During the period from time t0 to time t1, the serial-to-parallel conversion module 123 determines that the data packet of the second bypass received data signal RSD is 128 bits. Therefore, when the bypass received frame count value SC counts to 64, the serial-to-parallel conversion module 123 performs parallel data sampling, and when the bypass received frame count value SC counts to 128, the serial-to-parallel conversion module 123 performs the next parallel data sampling and resets the bypass received frame count value SC to zero. The serial-to-parallel conversion module 123 can sample the data B[0] to B

[63] of the second bypass received data signal RSD during the period from time t0 to time t1 to generate a second sampled data signal SD with corresponding data D0 to D63. However, since the bypass received clock signal RSC glitches during the idle interval from time t1 to time t2, the serial-to-parallel conversion module 123 incorrectly increases the count value of the bypass received frame count value SC by 1 (i.e., from count 64 to 65) during the idle interval from time t1 to time t2.

[0081] To avoid data sampling errors, the serial-to-parallel conversion module 123 generates a bypass reception valid indication signal based on the clock domain of the bypass reception clock signal RSC. Furthermore, the serial-to-parallel conversion module 123 synchronizes the bypass reception valid indication signal to the clock domain of the bypass normally open clock signal SCA to generate a bypass glitch clearing counter start signal. The serial-to-parallel conversion module 123 determines the bypass glitch clearing count value SCC based on the bypass glitch clearing counter start signal. When the bypass glitch clearing count value SCC equals the bypass glitch clearing counter threshold value (i.e., the bypass glitch clearing count value SCC equals N), the serial-to-parallel conversion module 123 resets the bypass glitch clearing count value SCC to zero and generates an asynchronous clear signal SFC for the bypass reception frame counter. Therefore, during the idle interval from time t1 to time t2, the serial-to-parallel conversion module 123 uses the pulse signal of the asynchronous clear signal SFC to asynchronously reset the bypass reception frame counter count value SC, where the bypass reception frame counter count value SC can be reset to 64.

[0082] In this way, the serial-to-parallel conversion module 123 can sample the data B

[64] to B

[127] of the second bypass received data signal RSD during the period from time t2 to time t3 to generate a second sampled data signal SD with corresponding data D64 to D127. The serial-to-parallel conversion module 123 can correctly sample the serial data B

[64] to B

[127] during the period from time t2 to time t3 as parallel data D64 to D127 without recording the missampled data caused by glitches during the idle interval from time t1 to time t2.

[0083] In addition, the bypass burr removal counter threshold value N in this embodiment can also be calculated by the above formula (1), and can be referred to the above. Figure 5 Description of the embodiments. Furthermore, the relevant numerical and signal settings in the above exemplary embodiments can be found in the above description. Figures 1 to 4 The embodiments are described in detail, so they will not be elaborated further.

[0084] Figure 7 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention. (See reference) Figure 7In one embodiment, the artificial intelligence chip 700 may include a first chip 110 and a second chip 120. The first chip 110 and the second chip 120 are used to realize inter-chip communication based on general chip interconnect technology. The first chip 110 and the second chip 120 can form a data transmission system. For relevant implementation methods and technical details regarding the first chip 110 and the second chip 120, please refer to the descriptions of the above embodiments. Furthermore, the data transmission method between the first chip 110 and the second chip 120 can also refer to the processes of the above embodiments, thus obtaining sufficient illustrations, suggestions, and implementation details. In addition, in another embodiment, the number of chips in the artificial intelligence chip 700 is not limited to... Figure 7 The first core 110 and the second core 120 are shown.

[0085] In one embodiment, the artificial intelligence chip 700 can be any one of a central processing unit, a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0086] In summary, the UCIe-based data transmission method, computer-readable storage medium, and artificial intelligence chip of this invention reset the bypass receive frame count during the idle interval between two bypass data packets during bypass communication. Alternatively, the bypass receive frame count is reset during the idle interval between bypass data packets of one bypass data packet, ensuring accurate sampling of bypass data packets. This effectively improves the stability and reliability of data transmission in bypass communication between chips, thereby ensuring the system's data transmission performance. The UCIe-based data transmission method, computer-readable storage medium, and artificial intelligence chip of this invention effectively avoid data sampling errors caused by glitches in the bypass receive clock signal during the idle interval between two bypass data packets or during the idle interval between bypass data packets of one bypass data packet.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A UCIe-based data transmission method, wherein a first core communicates with a second core, characterized in that, The data transmission method includes: The second chip receives bypass reception data signals and bypass reception clock signals from the first chip's transmission module through the receiving module. The bypass received data signal and the bypass received clock signal are transmitted by the receiving module to the serial-to-parallel conversion module of the second chip. The bypass receive clock signal is counted by the serial-to-parallel conversion module to obtain the bypass receive frame count value, and the bypass receive data signal is sampled according to the bypass receive frame count value; The serial-to-parallel conversion module determines the bypass glitch clearing count value based on the bypass glitch clearing counter start signal; and When the bypass glitch clearing count value equals the bypass glitch clearing counter threshold value, the bypass received frame count value is reset through the serial-to-parallel conversion module.

2. The data transmission method based on UCIe according to claim 1, characterized in that, Also includes: The serial-to-parallel conversion module generates a bypass reception valid indication signal based on the clock domain of the bypass reception clock signal; as well as The bypass receive valid indication signal is synchronized to the clock domain of the bypass normally open clock signal by the serial-to-parallel conversion module to generate the bypass glitch clearing counter start signal.

3. The data transmission method based on UCIe according to claim 2, characterized in that, The step of counting the bypass burr removal count value includes: When the bypass received frame count value is greater than or equal to the bypass glitch clearing counter start threshold value, the bypass glitch clearing counter value is started to be counted through the serial-to-parallel conversion module.

4. The UCIe-based data transmission method according to claim 3, characterized in that, The bypass glitch clearing counter threshold value is equal to the number of bits of bypass data packets plus the number of idle intervals between bypass data packets, minus the bypass glitch clearing counter start threshold value, minus the number of synchronization beats, and minus the safety margin value. Wherein, the number of bits of the bypass data packet is used to represent the number of unit time intervals of a bypass data packet; The number of idle intervals between bypass data packets is used to represent the number of minimum unit time intervals during the idle interval between two bypass data packets; The synchronization beat count is used to represent the clock cycles consumed in synchronizing the bypass receive valid indication signal to the clock domain of the bypass normally open clock signal; The safety margin value is used to represent the number of unit time intervals between the next bypass data packet and the asynchronous reset of the bypass received frame count value.

5. The UCIe-based data transmission method according to claim 2, characterized in that, The step of counting the bypass burr removal count value includes: The bypass glitch clearing count value is started counting on the rising edge of the valid indication signal received in the bypass via the serial-to-parallel conversion module.

6. The data transmission method based on UCIe according to claim 1, characterized in that, The steps for resetting the bypass receive frame count value include: When the bypass glitch clearing count value equals the bypass glitch clearing counter threshold value, the bypass glitch clearing count value is reset to zero by the serial-to-parallel conversion module, and an asynchronous clearing signal for the bypass receive frame counter is generated; and The bypass receive frame count value is asynchronously reset using the asynchronous clear signal of the bypass receive frame counter through the serial-to-parallel conversion module.

7. The data transmission method based on UCIe according to claim 1, characterized in that, The steps for resetting the bypass receive frame count value include: When the serial-to-parallel conversion module determines that the length of the bypass data packet of the bypass received data signal is the first length based on the bypass data packet type code, the serial-to-parallel conversion module resets the bypass received frame count value to the first reset value.

8. The UCIe-based data transmission method according to claim 7, characterized in that, The step of resetting the bypass receive frame count value further includes: When the serial-to-parallel conversion module determines that the length of the bypass data packet in the bypass received data signal is not the first length, the serial-to-parallel conversion module determines whether the bypass glitch clearing count value is greater than or equal to the first length threshold and less than the second length threshold, so as to reset the bypass received frame count value to the second reset value. The second length threshold value is greater than the first length threshold value.

9. The UCIe-based data transmission method according to claim 8, characterized in that, The step of resetting the bypass receive frame count value further includes: When the bypass glitch clearing count is greater than or equal to the first length threshold and less than the second length threshold, the bypass received frame count is reset to the second reset value via the serial-to-parallel conversion module; and When the bypass glitch clearing count value is less than the first length threshold value, or greater than or equal to the second length threshold value, the bypass received frame count value is reset to the third reset value through the serial-to-parallel conversion module.

10. The UCIe-based data transmission method according to claim 1, characterized in that, The bypass receive frame count is reset during the idle interval between two bypass data packets.

11. The UCIe-based data transmission method according to claim 1, characterized in that, The bypass receive frame count is reset during the idle interval between bypass packets of a bypass packet.

12. A computer-readable storage medium for storing a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the UCIe-based data transmission method according to any one of claims 1 to 11.

13. An artificial intelligence chip, characterized in that, include: First core; as well as The second core is coupled to the first core and is used to communicate with the first core. The receiving module of the second chip receives a bypass reception data signal and a bypass reception clock signal from the transmitting module of the first chip, and the receiving module transmits the bypass reception data signal and the bypass reception clock signal to the serial-to-parallel conversion module of the second chip. The serial-to-parallel conversion module counts the bypass receive clock signal to obtain a bypass receive frame count value, samples the bypass receive data signal based on the bypass receive frame count value, and determines the bypass glitch clearing count value based on the bypass glitch clearing counter start signal. When the bypass glitch clearing count value is equal to the bypass glitch clearing counter threshold value, the bypass received frame count value is reset by the serial-to-parallel conversion module.

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