Manufacturing method of NORD type flash memory

Abstract

The invention provides a manufacturing method of an NORD type flash memory. The method comprises the following steps: forming a control gate structure and a floating gate structure; depositing and flattening a word line conductive layer; etching back the word line conductive layer to enable the top surface height of the word line conductive layer to be lower than the top surface height of the control gate structure; by using the height difference, the top surface of the control gate structure is kept exposed when the dielectric side wall is formed; finally, a silicide layer is formed on the exposed top surface. Through the self-alignment process, uniform and complete silicification of the control gate is realized, so that the circuit resistance is remarkably reduced, and the working speed and the production yield of the device are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a NORD-type flash memory. Background Technology

[0002] Flash memory, as a key non-volatile semiconductor memory device, has been widely used in mobile communication devices, solid-state drives (SSDs), embedded systems, and other fields due to its high integration, low power consumption, and rewritable characteristics. NORD-type flash memory is a common architecture, and its memory cells typically include a tunneling oxide layer, a floating gate (FG), an inter-polyelectric (IPD), a control gate (CG), and word lines (WL) for selecting and driving the memory cells on a semiconductor substrate.

[0003] With the continuous evolution of semiconductor process nodes and the market demand for higher-performance chips, the read and write speeds of flash memory devices have become one of the key indicators for measuring their performance. In traditional NORD flash memory manufacturing processes, the control gate is typically formed from doped polysilicon. However, doped polysilicon itself has a relatively high resistivity. When the control gate is used as a long conductor running through the entire memory array, its high resistance and the RC delay formed by parasitic capacitance significantly limit the signal transmission rate, becoming a technical bottleneck restricting the improvement of device operating frequency and overall read and write speeds.

[0004] To address this issue, the industry commonly employs a technique of forming a low-resistivity metal silicide layer on the top surface of the polysilicon conductive layer (such as the gate or control gate). Through self-aligned silicide processing, metal silicides such as titanium silicide (TiSix), cobalt silicide (CoSix), or nickel silicide (NiSix) can be simultaneously formed on the exposed polysilicon and source / drain regions, thereby significantly reducing line resistance.

[0005] However, existing technologies face significant challenges when applying conventional siliconization processes to the manufacturing of NORD-type flash memory. In many known process flows, the formation sequence and geometry of various structures within the device make it difficult to completely and uniformly expose the top surface of the control gate during siliconization. Specifically, when forming dielectric sidewalls for electrical isolation of word lines (WLs) or other structures, due to the conformal deposition characteristics of the process, the sidewall material (typically silicon oxide or silicon nitride) not only forms on the sidewalls of the target structure but often also covers the top surface of adjacent control gates. This covering effect acts like an unintended mask, hindering the subsequent reaction between the metal and the polysilicon of the control gate.

[0006] As a result, the silicide layer can only form in scattered areas on top of the control gate that are not covered by sidewalls, or it cannot form at all. This incomplete and uneven silicide formation significantly reduces the effectiveness of reducing the control gate resistance, and the size and morphology of the silicide region are difficult to control precisely, resulting in extremely poor process consistency and stability. This not only fails to effectively improve device speed but may also introduce new defects, affecting device performance reliability and production yield.

[0007] Therefore, there is an urgent need in the field for an innovative method for manufacturing NORD-type flash memory that can effectively solve the problem of the control gate top surface being covered without affecting the structure and performance of other devices, thereby forming a uniform and complete low-resistance silicide layer on it, so as to significantly improve the operating speed and overall performance of the device. Summary of the Invention

[0008] The purpose of this invention is to provide a method for manufacturing a NORD-type flash memory, which aims to solve the technical problem in the prior art where the sidewall structure covers the top surface of the control gate, resulting in incomplete siliconization and excessively high control gate line resistance, thereby limiting the operating speed of the device.

[0009] To achieve the above and other related objectives, the present invention provides a method for manufacturing a NORD-type flash memory, wherein the memory includes a memory array region, a peripheral logic device region, and a flash memory strip region located between the two on a semiconductor substrate, and includes at least:

[0010] Step 1: Form a stacked structure, which includes a floating gate layer on the memory array area and the peripheral logic device area, and a control gate layer covering the three areas;

[0011] Step 2: Perform patterning etching to form the key structures of the device, wherein the patterning etching includes:

[0012] (a) A hard mask layer is formed on the stacked structure;

[0013] (b) Perform a first etching, the first etching through the hard mask layer to etch the control gate layer to form a control gate structure in the memory array region, and simultaneously etch the hard mask layer and the floating gate layer below it in the flash strip region to form control gate contact holes;

[0014] (c) After the first etching, a second etching is performed to etch the floating gate layer within the memory array region to form a floating gate structure;

[0015] Step 3: Deposit and planarize the word line conductive layer;

[0016] Step 4: Perform an etch-back process on the word line conductive layer so that the top surface height of the word line conductive layer is lower than the top surface height of the control gate structure, thereby creating a height difference between the two.

[0017] Step 5: Forming a dielectric sidewall, which fills a groove formed by the height difference and located between the word line conductive layer and the control gate structure;

[0018] Step 6: Keep the top surface of the control gate structure exposed and form a silicide layer on the exposed top surface of the control gate structure.

[0019] Preferably, in step one, before forming the floating gate layer, a pad oxide layer is formed on the semiconductor substrate.

[0020] Preferably, in step one, the stacked structure further includes an interpolar dielectric layer located between the floating gate layer and the control gate layer.

[0021] Preferably, the interpolar dielectric layer comprises an oxide-nitride-oxide stack.

[0022] Preferably, prior to step two, the method further includes: etching the control gate layer in the flash memory stripe region to form a first trench that predefines word line contact holes; and in step two (b), the first etching further includes etching the hard mask layer located in the first trench to form a concave structure.

[0023] Preferably, after step two (b) and before step two (c), the method further includes forming a first sidewall on the sidewall of the control gate structure.

[0024] Preferably, in step three, before depositing the word line conductive layer, the method further includes forming a tunneling oxide layer on the exposed surface of the semiconductor substrate.

[0025] Preferably, in step three, the planarization is performed using a chemical mechanical planarization process, and the chemical mechanical planarization process stops on the hard mask layer.

[0026] Preferably, after step four and before step five, the method further includes: removing the stacked structure on the peripheral logic device region; sequentially depositing a gate dielectric layer and a gate conductive layer in the peripheral logic device region; and patterning the gate conductive layer to form a peripheral gate structure.

[0027] Preferably, in step five, the dielectric sidewall is also formed on the sidewall of the peripheral gate structure.

[0028] Preferably, before step five, the method further includes: selectively removing the word line conductive layer located in the bit line region and the control gate contact hole region of the memory array region.

[0029] Preferably, in step five, the dielectric sidewall is also formed on the sidewall of the memory cell composed of the word line conductive layer and the control gate structure / floating gate structure.

[0030] Preferably, in step five, the dielectric material on the word line conductive layer formed in the first trench is removed during the back etching to expose its upper surface.

[0031] Preferably, in step six, the step of forming the silicide layer further includes forming a silicide on the top surface of the semiconductor substrate exposed in the bit line region.

[0032] Preferably, in step six, the step of forming the silicide layer further includes: forming a silicide on the exposed upper surface of the word line conductive layer within the first trench.

[0033] Preferably, in step six, the step of forming the silicide layer further includes: forming a silicide on the exposed upper surface of the peripheral gate structure.

[0034] Preferably, within the memory array region, the width of the word line structure formed by the word line conductive layer is no greater than 80 nm.

[0035] Preferably, the floating gate layer, the control gate layer, the word line conductive layer, and the peripheral gate structure comprise polysilicon.

[0036] Preferably, the dielectric sidewall and the first sidewall are made of a material selected from silicon oxide, silicon nitride, or a combination thereof.

[0037] Preferably, in step six, the formation of the silicide layer employs a self-aligned silicide process.

[0038] Preferably, after step six, the method further includes: depositing an interlayer dielectric layer; and forming contact holes in the interlayer dielectric layer to make electrical contact with the silicide layer formed by the method.

[0039] As described above, the manufacturing method of the NORD-type flash memory of the present invention has the following beneficial effects:

[0040] This invention solves the problem of sidewalls covering the top surface of the control gate in existing technologies by actively reducing the word line height and using the resulting height difference to control the formation position of the dielectric sidewalls, thus allowing the top surface of the control gate to be completely exposed. This ensures that a uniform and continuous low-resistance silicide layer can be formed on the entire control gate, thereby significantly reducing the line resistance of the control gate, effectively reducing RC delay, and ultimately greatly improving the read / write speed and operating frequency of the flash memory device. Attached Figure Description

[0041] Figure 1 This is a schematic flowchart of a method for manufacturing a NORD-type flash memory according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic cross-sectional view of the structure after the formation of the laminated structure according to an embodiment of the present invention.

[0043] Figure 3 This is a schematic cross-sectional view of the structure after a first trench is formed in the flash memory stripe region according to an embodiment of the present invention.

[0044] Figure 4 This is a schematic cross-sectional structure diagram of the hard mask layer after its formation, according to an embodiment of the present invention.

[0045] Figure 5 This is a schematic cross-sectional view of the structure after performing a first etching to form a control gate structure and a control gate contact hole, according to an embodiment of the present invention.

[0046] Figure 6 This is a schematic cross-sectional view of the structure after performing a second etching to form a floating gate structure, according to an embodiment of the present invention.

[0047] Figure 7 This is a schematic cross-sectional structure diagram of the tunneling oxide layer after its formation, according to an embodiment of the present invention.

[0048] Figure 8 This is a schematic cross-sectional structure diagram of the word line conductive layer after deposition and planarization according to an embodiment of the present invention.

[0049] Figure 9 This is a schematic cross-sectional structure diagram of the word line conductive layer after being etched back according to an embodiment of the present invention.

[0050] Figure 10 This is a schematic cross-sectional structure diagram of the peripheral logic device region after removing the stacked layers according to an embodiment of the present invention.

[0051] Figure 11 This is a schematic cross-sectional structure diagram of a peripheral logic device region after depositing a gate conductive layer according to an embodiment of the present invention.

[0052] Figure 12 This is a schematic cross-sectional view of the peripheral gate structure after it has been formed, according to an embodiment of the present invention.

[0053] Figure 13 This is a schematic cross-sectional structure diagram of the present invention after selectively removing a portion of the word line conductive layer;

[0054] Figure 14 This is a schematic cross-sectional structure diagram of the medium sidewall after it has been formed, according to an embodiment of the present invention.

[0055] Figure 15 This is a schematic cross-sectional structure diagram of the silicide layer after its formation, according to an embodiment of the present invention.

[0056] Figure 16 This is a schematic diagram of the final contact hole layout according to an embodiment of the present invention. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] This invention provides a method for manufacturing a NORD-type flash memory. The memory includes a memory array region, a peripheral logic device region, and a flash memory strip region located between the two on a semiconductor substrate 101. By employing differentiated process flows in different regions, the performance of the memory cells and the integration density of the peripheral logic circuits can be optimized simultaneously, achieving single-chip integration of high-density storage and high-speed logic.

[0059] Please see Figure 1 The method includes:

[0060] Step 1: Forming a stacked structure, which includes a floating gate layer 103 on the memory array area and the peripheral logic device area, and a control gate layer 105 covering the three areas, forming a structure as follows: Figure 2 The structure shown.

[0061] In some embodiments, step one further includes forming a pad oxide layer 102 on the semiconductor substrate 101 before forming the floating gate layer 103. The pad oxide layer 102 can improve the interface quality between the floating gate layer 103 and the semiconductor substrate 101, reduce interface defects, and also play a certain protective role in subsequent etching processes.

[0062] In some embodiments, in step one, the stacked structure further includes an inter-electrode dielectric layer 104 located between the floating gate layer 103 and the control gate layer 105. The inter-electrode dielectric layer 104 is used to achieve electrical isolation between the floating gate 103 and the control gate 105, and its thickness and dielectric constant directly affect the coupling ratio and data retention characteristics of the memory cell.

[0063] In some embodiments, the inter-electrode dielectric layer 104 comprises an oxide-nitride-oxide (ONO) stack. The ONO stack structure utilizes the excellent charge blocking capability of the silicon nitride layer and the good interface characteristics of the upper and lower silicon oxide layers to effectively prevent charge leakage in the floating gate 103, thereby ensuring that the flash memory device has excellent data retention capability.

[0064] Step 2: Perform patterning etching to form the key structures of the device. Patterning etching includes:

[0065] (a) A hard mask layer 106 is formed on the stacked structure, forming a structure such as Figure 4 The structure shown;

[0066] (b) A first etching is performed, in which the control gate layer 105 is etched through the hard mask layer 106 to form a control gate structure in the memory array region. Simultaneously, the hard mask layer 106 and the floating gate layer 103 beneath it are etched in the flash memory strip region. The patterned floating gate layer in the flash memory strip region serves as the connection area for the control gate contact holes, forming a structure as shown in the image. Figure 5 The structure shown;

[0067] (c) After the first etching, a second etching is performed to etch the floating gate layer 103 within the memory array region, forming a floating gate structure, as shown in the image. Figure 6 The structure shown.

[0068] This unique step-by-step etching sequence first precisely defines the outline of the control gate 105 and the key contact hole positions through a single photolithography and etching process. Then, the floating gate 103 below is defined using a self-alignment method, which enables high-precision pattern transfer and alignment, laying a solid foundation for the formation of subsequent device structures and effectively simplifying the process flow.

[0069] In some embodiments, prior to step two, the method further includes: etching the control gate layer 105 in the flash memory stripe region to form a first trench that predefines a word line contact hole, forming a... Figure 3 The structure shown; and, in step two (b), the first etching further includes etching the hard mask layer 106 located in the first trench to form a concave structure, which can serve as an isolation structure. By pre-defining the trenches of the word line contact holes, complex patterning tasks can be decomposed, reducing the difficulty of a single photolithography operation and improving the process window and yield.

[0070] In some embodiments, after step two (b) and before step two (c), the method further includes forming a first sidewall 107 on the sidewall of the control gate structure. The first sidewall 107 can effectively protect the sidewall of the control gate structure formed in the first etching from damage or deformation during the subsequent second etching process, and can also serve as a self-alignment mask for etching the floating gate layer 103, further improving the alignment accuracy between the floating gate 103 and the control gate 105.

[0071] Step 3: Deposit and planarize the word line conductive layer 109 to form a layer like... Figure 8 The structure shown. Filling the word line conductive layer 109 into the trenches formed in step two helps to achieve a higher degree of global planarization, providing a flat surface for subsequent photolithography and etching processes, thereby improving process window and patterning accuracy.

[0072] In some embodiments, step three, before depositing the word line conductive layer 109, further includes: forming a tunneling oxide layer 108 on the exposed surface of the semiconductor substrate 101, forming a layer such as... Figure 7 The structure shown is as follows. The tunneling oxide layer 108 is a core component of the flash memory cell. It is the channel through which channel electrons are injected into or pulled out of the floating gate 103 via the quantum tunneling effect. Its thickness and quality directly determine the erase and write speed, durability, and reliability of the memory cell.

[0073] In some embodiments, in step three, planarization is performed using a chemical mechanical planarization (CMP) process, and the CMP process stops on the hard mask layer 106. By using the hard mask layer 106 as the stop layer for CMP, the endpoint of planarization can be precisely controlled, ensuring that the word line conductive layer 109 in all areas is planarized to a uniform height. This avoids problems caused by excessively light or heavy polishing and ensures the uniformity and consistency of subsequent etch-back steps.

[0074] Step 4: Perform an etch-back process on the word line conductive layer 109, so that the top surface height of the word line conductive layer 109 is lower than the top surface height of the control gate structure, thereby creating a height difference between the two, forming a structure as shown in the image. Figure 9 The structure shown is shown. This step is the core technical feature of this invention. By actively reducing the height of the word line 109, a groove or step structure is artificially created between the word line 109 and the adjacent control gate 105. This height difference is the physical basis for the subsequent selective sidewall formation and exposure of the top surface of the control gate 105, thereby solving the technical problem in the prior art where the top surface of the control gate is covered by the sidewall.

[0075] In some embodiments, after step four and before step five, the method further includes: removing the stacked structure on the peripheral logic device region to form a structure as shown in the figure. Figure 10The structure shown; a gate dielectric layer 110 and a gate conductive layer 111 are sequentially deposited in the peripheral logic device region to form a structure as shown. Figure 11 The structure shown; and the patterned gate conductive layer 111 to form the peripheral gate structure 111, forming as shown Figure 12 The structure shown illustrates that placing the formation of the high-performance peripheral logic device gate 111 after the main high-temperature process in the memory array region avoids the impact of the high-temperature process on the doping distribution and performance of the logic device, which is beneficial for realizing the integration of high-performance logic circuits with the memory array.

[0076] In some embodiments, prior to step five, the method further includes: selectively removing the word line conductive layer 109 located in the bit line region and the control gate contact hole region of the memory array region, forming a layer as shown in the figure. Figure 13 The structure shown is as follows. This removal step precisely defines the boundaries of the final memory cells and contact holes, patterns the continuous word line conductive layer 109 into individual word lines, and exposes the underlying semiconductor substrate 101 or floating gate layer 103 in the bit line region and contact hole region, preparing for the subsequent formation of bit line contacts and control gate contacts.

[0077] Step 5: Forming dielectric sidewalls 112. Dielectric sidewalls 112 fill the grooves formed by the height difference between the word line conductive layer 109 and the control gate structure, forming a shape as shown in the figure. Figure 14 The structure is shown. Because the word line 109 is lower in height, during anisotropic etching to form sidewalls, the sidewall material preferentially fills the grooves formed in step four and is mainly retained on the sidewalls of the word line 109. The top surface of the control gate 105, being higher, has its dielectric material completely removed. This self-aligned sidewall formation method precisely exposes the entire top surface of the control gate 105 for subsequent siliconization without the need for an additional mask.

[0078] In some embodiments, in step five, the dielectric sidewall 112 is also formed on the sidewall of the peripheral gate structure 111. By forming the sidewall structure simultaneously in the memory array region and the peripheral logic device region through a single sidewall formation process, the overall process flow is simplified, and production costs are reduced. The sidewalls on the peripheral gate 111 are typically used to define the extent of the subsequently implanted lightly doped drain (LDD) and source / drain regions to suppress short-channel effects and improve the reliability of the logic device.

[0079] In some embodiments, in step five, the dielectric sidewall 112 is also formed on the sidewall of the memory cell, which is composed of the word line conductive layer 109 and the control gate structure / floating gate structure. The sidewall formed on the sidewall of the memory cell can provide good electrical isolation for the memory cell, prevent crosstalk between adjacent memory cells, and protect the stacked structure of the memory cells from damage in subsequent processes.

[0080] In some embodiments, in step five, the dielectric material on the word line conductive layer 109 formed in the first trench is removed during the back etching process to expose its upper surface. This selective removal process ensures that the top of the contact hole region (i.e., the first trench) used to connect the word lines is the conductive word line material 109, rather than the insulating sidewall material, thereby guaranteeing the subsequent formation of low-resistance electrical contacts.

[0081] Step Six: Keep the top surface of the control gate structure exposed, and form a silicide layer 113 on the exposed top surface of the control gate structure, forming a layer such as... Figure 15 The structure shown illustrates this. A uniform, continuous, low-resistance metal silicide layer 113 can be formed on the completely exposed top surface of the control gate 105, significantly reducing the line resistance of the control gate 105 and decreasing RC delay. This greatly improves the transmission speed of electrical signals on the control gate 105, ultimately effectively increasing the overall read / write speed and operating frequency of the NORD-type flash memory device to meet the demands of high-speed applications. Simultaneously, uniform silicide formation also significantly improves device reliability and production yield, avoiding performance fluctuations caused by incomplete silicide formation.

[0082] In some embodiments, step six, forming the silicide layer 113, further includes forming a silicide on the top surface of the semiconductor substrate 101 exposed in the bit line region. By performing a single self-aligned silicide process, silicide is formed on the surfaces of the source and drain regions (i.e., the bit line regions) simultaneously with the formation of the control gate 105 silicide. This integrated reduction of the transistor's contact resistance and source-drain series resistance further enhances the device's driving capability and overall performance.

[0083] In some embodiments, step six, forming the silicide layer 113, further includes forming a silicide on the exposed upper surface of the word line conductive layer 109 within the first trench. Forming a silicide on top of the word line contact area effectively reduces the contact resistance between the subsequently formed metal contact plug and the word line 109, improving the reliability of the electrical connection.

[0084] Preferably, in step six, the step of forming the silicide layer 113 further includes: forming a silicide on the exposed upper surface of the peripheral gate structure.

[0085] In some embodiments, within the memory array region, the width of the word line structure formed by the word line conductive layer 109 is no greater than 80 nm.

[0086] In some embodiments, the floating gate layer 103, the control gate layer 105, the word line conductive layer 109, and the peripheral gate structure 111 comprise polysilicon. Alternatively, depending on different process nodes and performance requirements, amorphous silicon, metal gate materials (such as TiN, TaN, W, etc.), or combinations thereof, can be used to construct these conductive layers.

[0087] In some embodiments, the dielectric sidewall 112 and the first sidewall 107 are made of a material selected from silicon oxide, silicon nitride, or combinations thereof. For example, a multilayer sidewall structure of silicon oxide / silicon nitride can be used to take advantage of the etching selectivity of different materials and achieve more complex process control.

[0088] In some embodiments, in step six, the formation of the silicide layer 113 employs a self-aligned silicide process. The self-aligned silicide process requires no additional photomask, automatically forms silicide on all exposed silicon surfaces, has simple process steps, good compatibility with standard CMOS processes, and is the industry's mainstream low-resistance interconnect technology.

[0089] More specifically, the self-aligned salicide process for forming the silicide layer 113 in step six may include the following detailed steps:

[0090] First, the wafer undergoes a pre-cleaning process before metal deposition. This step is crucial; for example, a brief wet cleaning with a dilute hydrofluoric acid (dHF) solution can be used to effectively remove the native oxide layer on all exposed silicon surfaces, including the control gate structure, word line conductive layer 109, and semiconductor substrate 101. This ensures that the subsequently deposited metal can directly contact the clean silicon surface, which is essential for forming a high-quality, low-contact-resistance silicide interface.

[0091] Subsequently, one or more metal films are conformally deposited across the entire wafer surface using vacuum deposition methods such as physical vapor deposition (PVD). This metal film can selectively contain one or more of titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), or their alloys, depending on the specific process node and performance requirements. In some advanced processes, a metal stack is typically deposited; for example, a nickel (Ni) layer is deposited first as the main reacting metal, followed by a titanium nitride (TiN) layer as a protective capping or barrier layer. This capping layer can prevent the main reacting metal from being oxidized during subsequent heat treatment and helps to control the silicide reaction.

[0092] After metal deposition, a first rapid thermal annealing is performed. This annealing process is carried out at a relatively low temperature, with the aim of ensuring that the deposited metal (e.g., nickel) reacts only with the directly contacting exposed silicon surfaces (i.e., the surfaces of the control gate 105, source / drain regions, etc.) to form a high-resistivity, metal-rich metastable silicide phase (e.g., Ni₂Si). Metal deposited on the insulating material surfaces such as the dielectric sidewalls 112 does not react, demonstrating the "self-aligned" characteristic of the process.

[0093] Following the first thermal annealing, a selective wet etching process is employed to completely remove any unreacted metal and its overlay (if present). For example, a sulfuric acid-hydrogen peroxide mixture (SPM) or a similar chemical formulation can be used, designed to efficiently etch the metal itself but with an extremely low etching rate for the already formed metastable silicide phase and insulating dielectric layers (such as silicon oxide or silicon nitride), thus precisely preserving the silicide 113 formed only on the silicon surface.

[0094] Finally, a second rapid thermal annealing is performed. This annealing is carried out at a higher temperature than the first thermal annealing. The purpose of this high-temperature step is to drive a phase transition in the metastable silicide phase, transforming it into the final desired stable silicide phase with extremely low resistivity (e.g., from high-resistivity Ni₂Si to low-resistivity NiSi). After these two thermal annealing steps, a uniform, low-resistivity, and self-aligned metal silicide layer 113 is formed on the silicon surface in all predetermined areas, thereby achieving the technical effects of the present invention.

[0095] In some embodiments, after step six, the method further includes: depositing an interlayer dielectric (ILD) layer to cover the entire device structure; and forming contact holes in the interlayer dielectric layer, the contact holes making electrical contacts with the silicide layer 113 of the control gate structure 105, the silicide layer 113 of the word line conductive layer 109, and the silicide layer 113 on the semiconductor substrate 101 of the bit line region, respectively. The interlayer dielectric layer is used to achieve electrical isolation between different conductive parts of the device, while the contact holes serve as vertical conductive channels to reliably lead out electrical signals from the underlying devices (such as the control gate 105, word line 109, and source / drain regions) to connect to the upper metal interconnect network, thereby forming a complete, functional integrated circuit. By directly contacting the low-resistance silicide layer 113, the contact holes themselves can ensure low contact resistance, which is crucial for maintaining the high-speed performance of the entire circuit.

[0096] After the formation of silicide and interlayer dielectric is completed, the final contact hole layout is as follows: Figure 16 As shown, this layout clearly illustrates the three key contact holes required to connect the lower-level devices to the upper-level metal interconnect network: word line contact holes (WLCTs), control gate contact holes (CGCTs), and bit line contact holes (BLCTs).

[0097] Word line contact vias (WLCTs) are strategically positioned at the ends of word lines 109 (the darker lateral stripes in the figure), i.e., the flash memory strip region. As shown in the figure, the word lines 109 in this region are wider, and the dielectric sidewall material at their top has been selectively removed in previous process steps, exposing the underlying word line conductive layer 109 and the silicide layer 113 thereon. The WLCTs are formed on this exposed surface to provide electrical pathways for the corresponding word lines 109 to apply row strobe signals during memory operations.

[0098] Control gate contact holes (CGCTs) are formed directly on the top surface of the continuous control gate structure 105 (the brighter lateral stripes in the figure). Thanks to the unique process employed in this invention, the top surface of the control gate 105 is fully exposed, forming a low-resistance silicide layer 113. Therefore, the CGCTs can form high-quality, low-resistance ohmic contacts with this silicide layer 113, which is crucial for rapidly applying the high-voltage pulses required for programming or erasing the control gate 105. In terms of layout, the CGCTs can be arranged at any suitable location on the control gate stripe 105 according to design requirements, such as at the edge of the memory array or between specific cells.

[0099] Bit line contact vias (BLCTs) are distributed in the region between adjacent word lines 109 and are typically arranged in columns along the vertical direction. These contact vias pass through the interlayer dielectric layer and connect to the source and drain regions (i.e., active regions) within the semiconductor substrate 101 where silicide 113 has already been formed. Subsequent metal interconnect processes will form vertically extending bit lines through these BLCTs for transmitting data signals during read and write operations. These bit lines, together with the lateral word lines 109 and the control gate 105, form an orthogonal memory matrix.

[0100] In summary, this layout provides an efficient and compact interconnect solution. Through the manufacturing method of this invention, contact holes with different functions can be precisely formed on optimized target areas with a low-resistance silicide layer 113, ensuring excellent electrical performance and high reliability for the entire NORD-type flash memory array.

[0101] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a NORD-type flash memory, wherein the memory includes a memory array region, a peripheral logic device region, and a flash memory strip region located between the two on a semiconductor substrate, characterized in that, At least including: Step 1: Form a stacked structure, which includes a floating gate layer on the memory array area and the peripheral logic device area, and a control gate layer covering the three areas; Step 2: Perform patterning etching to form the key structures of the device, wherein the patterning etching includes: (a) A hard mask layer is formed on the stacked structure; (b) Perform a first etching, the first etching through the hard mask layer to etch the control gate layer to form a control gate structure in the memory array region, and simultaneously etch the hard mask layer and the floating gate layer below it in the flash strip region to form control gate contact holes; (c) After the first etching, a second etching is performed to etch the floating gate layer within the memory array region to form a floating gate structure; Step 3: Deposit and planarize the word line conductive layer; Step 4: Perform an etch-back process on the word line conductive layer so that the top surface height of the word line conductive layer is lower than the top surface height of the control gate structure, thereby creating a height difference between the two. Step 5: Forming a dielectric sidewall, which fills a groove formed by the height difference and located between the word line conductive layer and the control gate structure; Step 6: Keep the top surface of the control gate structure exposed and form a silicide layer on the exposed top surface of the control gate structure.

2. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: In step one, before forming the floating gate layer, a pad oxide layer is also formed on the semiconductor substrate.

3. The method for manufacturing a NORD-type flash memory according to claim 1 or 2, characterized in that: In step one, the stacked structure further includes an interpolar dielectric layer located between the floating gate layer and the control gate layer.

4. The method for manufacturing a NORD-type flash memory according to claim 3, characterized in that: The interpolar dielectric layer comprises an oxide-nitride-oxide stack.

5. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: Prior to step two, the method further includes: etching the control gate layer in the flash memory strip area to form a first trench that predefines word line contact holes; and in step two (b), the first etching further includes etching the hard mask layer located in the first trench to form a concave structure.

6. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: After step 2(b) and before step 2(c), the method further includes: forming a first sidewall on the sidewall of the control gate structure.

7. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: In step three, before depositing the word line conductive layer, a tunneling oxide layer is formed on the exposed surface of the semiconductor substrate.

8. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: In step three, the planarization is performed using a chemical mechanical planarization process, and the chemical mechanical planarization process stops on the hard mask layer.

9. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: After step four and before step five, the process further includes: removing the stacked structure on the peripheral logic device region; sequentially depositing a gate dielectric layer and a gate conductive layer in the peripheral logic device region; and patterning the gate conductive layer to form a peripheral gate structure.

10. The method for manufacturing a NORD-type flash memory according to claim 9, characterized in that: In step five, the dielectric sidewall is also formed on the sidewall of the peripheral gate structure.

11. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: Prior to step five, the method further includes: selectively removing the word line conductive layer located in the bit line region of the memory array region and the control gate contact hole region.

12. The method for manufacturing a NORD-type flash memory according to claim 1 or 11, characterized in that: In step five, the dielectric sidewall is also formed on the sidewall of the memory cell composed of the word line conductive layer and the control gate structure / floating gate structure.

13. The method for manufacturing a NORD-type flash memory according to claim 5, characterized in that: In step five, the dielectric material on the word line conductive layer formed in the first trench is removed during the back etching to expose its upper surface.

14. The method for manufacturing a NORD-type flash memory according to claim 1 or 11, characterized in that: In step six, the step of forming the silicide layer further includes forming a silicide on the top surface of the semiconductor substrate exposed in the bit line region.

15. The method for manufacturing a NORD-type flash memory according to claim 13, characterized in that: In step six, the step of forming the silicide layer further includes: forming a silicide on the exposed upper surface of the word line conductive layer within the first trench.

16. The method for manufacturing a NORD-type flash memory according to claim 9, characterized in that: In step six, the step of forming the silicide layer further includes forming a silicide on the exposed upper surface of the peripheral gate structure.

17. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: Within the memory array region, the width of the word line structure formed by the word line conductive layer is no greater than 80 nm.

18. The method for manufacturing a NORD-type flash memory according to claim 1 or 9, characterized in that: The floating gate layer, the control gate layer, the word line conductive layer, and the peripheral gate structure comprise polysilicon.

19. The method for manufacturing a NORD-type flash memory according to claim 1 or 6, characterized in that: The dielectric sidewall and the first sidewall are made of a material selected from silicon oxide, silicon nitride, or a combination thereof.

20. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: In step six, the formation of the silicide layer employs a self-aligned silicide process.

21. The method for manufacturing a NORD-type flash memory according to claim 1, characterized in that: Following step six, the method further includes: depositing an interlayer dielectric layer; and forming contact holes in the interlayer dielectric layer to make electrical contact with the silicide layer formed by the method.

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