Semiconductor memory device

Abstract

A semiconductor memory device according to some example embodiments may include: a source plate including a semiconductor material; and a molded structure on a bottom surface of the source plate, the molded structure including a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked with each other in a first direction, the first direction being perpendicular to the bottom surface of the source plate, each of the plurality of gate electrodes and the plurality of molded insulating layers extending in a second direction, the second direction is parallel to the bottom surface of the source plate; and a plurality of channel structures penetrating the molding structure in the first direction, and each of the plurality of channel structures includes a channel hole extending in the first direction, a charge storage structure on an inner wall of the channel hole, and a channel layer on the charge storage structure.

Description

Technical Field

[0001] Various example embodiments relate to a semiconductor memory device. Background Technology

[0002] In electronic systems requiring data storage, the demand for semiconductor memory devices capable of storing high-capacity data is increasing. Therefore, methods to increase the data storage capacity of semiconductor memory devices are being investigated. For example, methods for increasing the data storage capacity of semiconductor devices have been proposed, where the semiconductor device includes a three-dimensional arrangement of memory cells instead of a conventional two-dimensional arrangement. Summary of the Invention

[0003] To address one or more problems (e.g., the problems described above and / or others not explicitly described herein), various example embodiments provide a semiconductor memory device.

[0004] A semiconductor memory device according to some example embodiments may include: a source plate comprising a semiconductor material; a molded structure on the bottom surface of the source plate, the molded structure including a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on top of each other in a first direction perpendicular to the bottom surface of the source plate, each of the plurality of gate electrodes and the plurality of molded insulating layers extending in a second direction parallel to the bottom surface of the source plate; and a plurality of channel structures extending through the molded structure in the first direction, each of the plurality of channel structures including a channel via extending in the first direction, a charge storage structure on the inner wall of the channel via, and a channel layer on the charge storage structure. The source plate includes a first conductivity type impurity region and a second conductivity type impurity region, and the channel layer extends along the bottom surface of the source plate in the second direction.

[0005] A semiconductor memory device according to some example embodiments may include: a peripheral circuit structure; and a first cell structure, wherein the peripheral circuit structure includes a peripheral circuit substrate, a plurality of circuit elements on the peripheral circuit substrate, a metal layer connected to each of the plurality of circuit elements, and an interlayer insulating layer on the peripheral circuit substrate to bury the plurality of circuit elements and the metal layer, the first cell structure including a first source plate, the first source plate including a semiconductor material, a first conductivity type impurity region and a second conductivity type impurity region; a first molding structure including a plurality of gate electrodes and a plurality of molding insulating layers alternately stacked on the bottom surface of the first source plate and in a first direction perpendicular to the bottom surface of the first source plate, each of the plurality of gate electrodes and the plurality of molding insulating layers extending in a second direction parallel to the bottom surface; a plurality of first channel structures penetrating the first molding structure in the first direction, each of the plurality of first channel structures including a channel hole extending in the first direction, a charge storage structure on the inner wall of the channel hole, and a channel layer on the charge storage structure; and a first line below the plurality of first channel structures, and the channel layer extending along the bottom surface of the first source plate in the second direction.

[0006] According to some example embodiments, a semiconductor memory device may include: a source plate comprising a semiconductor material, the source plate including a first conductivity type impurity region and a second conductivity type impurity region; a molded structure on the bottom surface of the source plate, the molded structure including a plurality of gate electrodes and a plurality of molded insulating layers alternately stacked on top of each other in a first direction perpendicular to the bottom surface of the source plate, each of the plurality of gate electrodes and the plurality of molded insulating layers extending in a direction parallel to the bottom surface of the source plate; a plurality of channel structures penetrating the molded structure in the first direction, each of the plurality of channel structures including a channel hole extending in the first direction, a charge storage structure on the inner wall of the channel hole, and a... The system includes a channel layer on a charge storage structure, the channel layer being in contact with a source plate; a block separation structure extending through the molded structure in a first direction, with a first conductivity type impurity region on the block separation structure; and a bit line beneath the plurality of channel structures. The channel layer extends along the bottom surface of the source plate in a second direction, perpendicular to the first direction. The channel layer includes a channel array region and a block separation region. The channel array region includes the plurality of channel structures arranged along a second direction perpendicular to the first direction and a third direction perpendicular to each other. The block separation region includes a block separation structure extending in the second direction and separating the channel array region into a plurality of blocks. The block separation structure includes a plurality of block separation structures spaced apart in a third direction.

[0007] According to some example embodiments of this disclosure, in an erase operation, an erase voltage can be applied by forming an impurity region on a source plate disposed above a channel via, such that a sufficient amount of erase voltage can be applied to the channel layer of the channel structure without the need for a separate complex structure for the erase operation (e.g., GIDL WL (gate-induced drainleakage word line)).

[0008] In addition, according to various example embodiments, a first conductivity type impurity region for programming operations and a second conductivity type impurity region for erasing operations are formed separately on the source plate SP, thereby reducing or minimizing interference between the charge movement paths in programming operations and the charge movement paths in erasing operations, and providing a semiconductor memory device with improved reliability and / or stability.

[0009] The various advantages and effects of this disclosure are not limited to those described above, and can be more readily understood in the process of describing particular aspects of this disclosure. Attached Figure Description

[0010] The above-described objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of various exemplary embodiments with reference to the accompanying drawings.

[0011] Figure 1 This is a conceptual circuit diagram illustrating a memory array region of a semiconductor device according to various example embodiments.

[0012] Figure 2 These are example layout diagrams provided to explain semiconductor memory devices according to various example embodiments.

[0013] Figure 3 It is along Figure 2 The sectional view taken from section AA.

[0014] Figure 4 In order to explain about Figure 3 An enlarged view of the semiconductor memory device in region EX2 is provided.

[0015] Figure 5 In order to explain about Figure 3 An enlarged view of region EX2 provided according to various example embodiments of a semiconductor memory device.

[0016] Figure 6 It is about Figure 2 Plan view of the source plate in region EX1.

[0017] Figure 7 It is along Figure 6The sectional view taken from section BB.

[0018] Figure 8 It is along Figure 6 The sectional view taken by section CC.

[0019] Figure 9 It is about Figure 2 A plan view of the source plate in region EX1 according to various example embodiments.

[0020] Figure 10 It is along Figure 9 The sectional view taken from section DD.

[0021] Figure 11 It is about Figure 2 A plan view of the source plate in region EX1 according to various example embodiments.

[0022] Figure 12 It is along Figure 11 The sectional view taken from the section EE.

[0023] Figures 13 to 24 These diagrams are provided to explain methods of manufacturing a semiconductor device according to various exemplary embodiments. Figures 13 to 24 This shows the intermediate stages of manufacturing.

[0024] Figure 25 These diagrams are provided to explain semiconductor memory devices according to various example embodiments.

[0025] Figure 26 This is a schematic diagram illustrating a concept of an electronic system including a semiconductor memory device according to various example embodiments.

[0026] Figure 27 This is a perspective view schematically illustrating an electronic system including a 3D semiconductor memory device according to various example embodiments. Detailed Implementation

[0027] In the following description, various exemplary embodiments will be described with reference to the accompanying drawings.

[0028] Figure 1 This is a circuit diagram that conceptually illustrates the memory array region MA of a semiconductor device.

[0029] Reference Figure 1 The memory array of the semiconductor device may include a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR disposed between the common source line CSL and the multiple bit lines BL. The common source line CSL, the multiple cell strings CSTR, and the multiple bit lines BL may be arranged along a first direction D1.

[0030] The common-source line CSL may extend in a second direction D2 perpendicular to the first direction. In some example embodiments, multiple common-source lines CSL may be arranged in two dimensions. For example, multiple common-source lines CSL may be spaced apart from each other and may extend individually in the second direction D2. The same voltage may be applied to the common-source lines CSL, or different voltages may be applied to be individually controlled.

[0031] Multiple bit lines BL can be arranged in two dimensions. For example, multiple bit lines BL can be spaced apart from each other and can extend in a third direction D3 that intersects the second direction D2. Each bit line BL can be connected in parallel with multiple cell strings CSTR.

[0032] Multiple cell strings (CSTRs) can be combined to a common-source line (CSL). Multiple cell strings (CSTRs) can be positioned between the common-source line (CSL) and multiple bit lines (BL). Each of the multiple cell strings (CSTRs) may include a ground select transistor (GST), a memory cell transistor (MCT), and a string select transistor (SST). The ground select transistor (GST), the memory cell transistor (MCT), and the string select transistor (SST) can be connected in series with each other.

[0033] Memory cell transistors (MCTs) can be connected in series between ground select transistors (GSTs) and string select transistors (SSTs). Each MCT may include an information storage area capable of storing information. For example, each MCT may include a data storage element.

[0034] Multiple ground select transistors (GSTs) may exist that are electrically connected to the common-source line (CSL). Multiple string select transistors (SSTs) may exist that are electrically connected to the bit line (BL).

[0035] The ground select line GSL, multiple word lines WL, and serial select line SSL can be positioned between the common source line CSL and the bit line BL. The ground select transistor GST can be controlled by the ground select line GSL. For example, the ground select line GSL can be used as the gate electrode of the ground select transistor GST. The common source line CSL can be connected to the source of the ground select transistor GST. The serial select transistor SST can be controlled by the serial select line SSL. The memory cell transistor MCT can be controlled by multiple word lines WL. For example, the serial select line SSL can be used as the gate electrode of the serial select transistor SST, and the multiple word lines WL can be used as the gate electrode of the memory cell transistor MCT.

[0036] Figure 2 This is an example layout diagram provided to explain semiconductor memory devices. Figure 3 It is along Figure 2 The sectional view taken from section AA. Figure 4 In order to explain about Figure 3 An enlarged view of the semiconductor memory device in region EX2 is provided. Figure 5 In order to explain about Figure 3 An enlarged view of region EX2 provided according to various example embodiments of a semiconductor memory device.

[0037] Reference Figures 2 to 5 A semiconductor memory device according to some example embodiments may include a memory cell region (CELL) and a peripheral circuit region (PERI).

[0038] A memory cell region (CELL) may include a cell array region (R1) and an extension region (R2). A memory cell array includes multiple memory cells (e.g., Figure 1 The gate electrode 112 (MA) can be formed in the cell array region R1. For example, the channel structure CS, bit line BL, gate electrode 112, etc., which will be described below, can be arranged in the cell array region R1. An extension region R2 can be provided around the cell array region R1. The gate electrode 112, which will be described below, can be stacked in the extension region R2 in a stepped manner.

[0039] The memory cell region (CELL) may include a molded structure (MS), a channel structure (CS), a source structure (SS), and a drain structure (DS).

[0040] The molded structure MS may include a plurality of gate electrodes 112 and a plurality of molded insulating layers 114 that can be alternately stacked on top of each other. The gate electrodes 112 may correspond to word lines. The molded structure MS may be disposed on the bottom surface of the source plate SP forming the source structure SS. Each of the plurality of gate electrodes 112 and the plurality of molded insulating layers 114 may be alternately stacked on top of each other in a first direction perpendicular to the bottom surface of the source plate SP, and may extend in a second direction parallel to the bottom surface of the source plate SP. In the cell array region R1, the molded structure MS may include a structure in which the plurality of gate electrodes 112 and molded insulating layers 114 are alternately stacked on top of each other.

[0041] Multiple gate electrodes 112 may be stacked in a stepped manner in the extended region R2. For example, multiple gate electrodes 112 may extend to different lengths along the second direction D2. Thus, steps may be formed between the multiple gate electrodes 112.

[0042] Multiple channel structures CS can be formed on the molded structure MS of the cell array region R1. The multiple channel structures CS can extend in a vertical direction (hereinafter referred to as the first direction D1) intersecting the upper surface of the molded structure MS and penetrate the molded structure MS. For example, the multiple channel structures CS can have a cylindrical shape (e.g., a cylindrical shape) extending in the first direction D1. In some example embodiments, the width of the channel structures CS can narrow as the distance from the upper surface of the molded structure MS increases. According to the design, the width of the channel structures CS can widen as the distance from the upper surface of the molded structure MS increases.

[0043] like Figure 4 As shown, each of the plurality of channel structures CS may include a channel hole CH_H extending in a first direction D1 and a charge storage structure 124 and a channel layer 122 sequentially stacked on the inner wall of the channel hole CH_H.

[0044] In some example embodiments, the diameter of the channel aperture CH_H may decrease as the distance from the source plate SP increases. However, the various example embodiments are not limited to this. For example, the diameter of the channel aperture CH_H may be substantially the same at all vertical heights.

[0045] The channel layer 122 may extend in the first direction D1 and penetrate the molded structure MS. Although the channel layer 122 is shown to have a cup shape, this is merely an example. For example, the channel layer 122 may have various shapes (such as cylindrical, squared-cylindrical, filled-cylindrical, etc.). For example, the channel layer 122 may include semiconductor materials (such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures), but the example embodiment is not limited thereto.

[0046] Charge storage structure 124 may be disposed between channel layer 122 and molded structure MS. Charge storage structure 124 may be disposed between each of gate electrodes 112 and channel layer 122. For example, charge storage structure 124 may extend along the outer surface of channel layer 122. For example, charge storage structure 124 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. However, the exemplary embodiments are not limited thereto. For example, high-k materials may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0047] In some example embodiments, the channel layer 122 may further extend on the upper surface of the molded structure MS in a second direction D2 and a third direction D3 perpendicular to the first direction D1. For example, the channel layer 122 may extend from the outer wall of the channel hole CH_H and along the bottom surface of the source plate SP. In this case, the charge storage structure 124 may be disposed on the upper surface of the molded structure MS and between the channel layer 122 and the upper surface of the molded structure MS. For example, as Figure 4 As shown, the charge storage structure 124 and the channel layer 122 can be sequentially disposed on the upper surface of the molded structure MS.

[0048] In some example embodiments, the channel structure CS may further include a padding layer 128. (See also...) Figure 5The pad 128 may be positioned at one end of the channel structure CS (e.g., in the upper region of the channel structure CS). The pad 128 may be disposed on the inner wall of the channel layer 122. The pad 128 may be formed to connect to the channel layer 122. For example, the pad 128 may comprise polysilicon, metal, etc., which may be doped with impurities, but the example embodiment is not limited thereto. Meanwhile, Figure 5 The illustration shows that the pad 128 is stacked with the gate electrode 112 at the top of the molded structure MS in a horizontal direction (e.g., in the third direction), but the pad 128 may be stacked with two or more gate electrodes 112 at the top of the molded structure MS in a horizontal direction.

[0049] In some example embodiments, multiple channel structures CS can be arranged in a zigzag pattern. For example, as... Figure 2 As shown, multiple channel structures CS can be arranged to intersect each other in the second direction D2 and the third direction D3. A zigzag arrangement of multiple channel structures CS can further improve the integration density of the semiconductor memory device. In some example embodiments, the multiple channel structures CS can be arranged in a honeycomb pattern.

[0050] In some example embodiments, a dummy channel structure DCH may be formed in the molded structure MS of the extension region R2. The dummy channel structure DCH may be formed in a shape similar to that of the channel structure CS to reduce the stress applied to the molded structure MS in the extension region R2.

[0051] In some example embodiments, the charge storage structure 124 may be formed of multiple layers. For example, the charge storage structure 124 may include a tunnel insulating film 124a, a charge storage film 124b, and a barrier insulating film 124c that may be sequentially stacked on the outer surface of the channel layer 122.

[0052] For example, the tunnel insulating film 124a may comprise silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)), the charge storage film 124b may comprise silicon nitride, and the barrier insulating film 124c may comprise silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). However, the example embodiments are not limited thereto.

[0053] In some example embodiments, the channel structure CS may also include a fill pattern 126. The fill pattern 126 may be formed to fill the interior of the channel layer 122. For example, the fill pattern 126 may include an insulating material (e.g., silicon oxide), but the example embodiments are not limited thereto.

[0054] The source structure SS can be disposed on the molded structure MS. The source structure SS may include a source plate SP, a contact pad SC, and a first interlayer insulating film 152.

[0055] The source plate SP can extend along the upper surface of the molded structure MS. The source plate SP can be completely disposed on the upper surface of the molded structure MS. The source plate SP can be in direct or indirect contact with the channel layer 122 of the channel structure CS. For example... Figure 4 As shown, if the channel layer 122 is disposed on the upper surface of the molded structure MS, the source plate SP can be disposed on the channel layer 122 and in direct contact with the channel layer 122. Figure 5 As shown, if the pad 128 is disposed on the channel structure CS, the source plate SP can be electrically connected to the channel layer 122 through the pad 128 and can also contact a portion of the channel layer 122.

[0056] The source plate SP can be connected to the channel layer 122 to serve as the common source line of the semiconductor memory device (e.g., Figure 2 The CSL (Channel Layer Solvent) is configured. For example, contact pads SC connected to the upper part of multiple channel structures CS can be formed in the first interlayer insulating film 152. That is, the channel structure CS can be electrically connected to the common source line through the source plate SP and the contact pads SC.

[0057] The first interlayer insulating film 152 may be disposed on the source plate SP. For example, the first interlayer insulating film 152 may include at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but the example embodiments are not limited thereto.

[0058] The source plate SP may comprise polysilicon or metal doped with impurities. In some example embodiments, the source plate SP may be (p-) polysilicon doped with a low concentration of p-type impurities. However, the example embodiments are not limited thereto.

[0059] Return to reference Figure 2 The block separation structure WLC can extend in the second direction D2 to separate or divide the molding structure MS. The molding structure MS can be separated by multiple block separation structures WLC to form multiple memory cell blocks. For example, two adjacent block separation structures WLC can define a memory cell block between them. Multiple channel structures CS can be provided in each of the memory cell blocks defined by the block separation structures WLC.

[0060] The number of channel structures CS arranged in a zigzag pattern along the third direction D3 within a memory cell block can vary, and is not limited to, for example... Figure 2 The example embodiment shown is shown.

[0061] In some example embodiments, the block-separated structure WLC may include an insulating material. For example, the insulating material may fill the block-separated structure WLC. For example, the insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the example embodiments are not limited thereto.

[0062] In some example embodiments, although not shown, a string separation structure may be formed in the molded structure MS. The string separation structure may extend in the second direction D2 to cut through the gate electrode 112. The string separation structure may cut through a portion of the gate electrode 112 disposed at the top. Each memory cell block defined by the block partition structure WLC may be divided by the string separation structure to form multiple string regions. For example, the string separation structure may define two string regions in one memory cell block.

[0063] The unit contact structure 170 can be connected to the gate electrode 112 in the extension region R2. The unit contact structure 170 can extend in the first direction D1 and penetrate the molding structure MS. The unit contact structure 170 can be connected to the pad region of each of the gate electrodes 112.

[0064] Each of the gate electrodes 112 can be connected to Figure 2 The ground select line GSL, multiple word lines WL, and serial select line SSL correspond to each other. Furthermore, in some example embodiments, the gate electrode adjacent to the ground select line GSL, or the gate electrode adjacent to the serial select line SSL, may be a dummy semiconductor layer.

[0065] For example, the molded insulating layer 114 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the example embodiments are not limited thereto. For example, the molded insulating layer 114 may include silicon oxide.

[0066] The drain structure DS can be disposed under the molded structure MS. The drain structure DS may include bit line BL, bit line contact BLC, bit line contact pad BLP, and second interlayer insulating film 154.

[0067] Bit lines BL can be formed beneath the molded structure MS and the second interlayer insulating film 154. Bit lines BL can extend in the third direction D3 and intersect with the block separation structure WLC. Furthermore, bit lines BL can extend in the third direction D3 and connect to a plurality of channel structures CS arranged along the third direction D3. For example, bit line contact pads BLP and bit line contacts BLC, connected to the lower portion of each of the channel structures CS, can be formed in the second interlayer insulating film 154. Bit lines BL can be electrically connected to the channel structures CS via bit line contact pads BLP and bit line contacts BLC.

[0068] The peripheral circuit region PERI may include a peripheral circuit substrate 200, a plurality of circuit elements PT, a metal layer 260, and an interlayer insulating layer 240. The plurality of circuit elements PT are formed on the peripheral circuit substrate 200, the metal layer 260 is connected to each of the plurality of circuit elements PT, and the interlayer insulating layer 240 is formed on the peripheral circuit substrate 200 to bury the plurality of circuit elements PT and the metal layer 260.

[0069] The peripheral circuit substrate 200 may be disposed below the drain structure DS. For example, the upper surface of the peripheral circuit substrate 200 may face the lower surface of the drain structure DS. For example, the peripheral circuit substrate 200 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate). However, the example embodiment is not limited thereto. Optionally, the peripheral circuit substrate 200 may also include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, etc.

[0070] Circuit element PT can be formed on peripheral circuit substrate 200. Circuit element PT can form peripheral circuitry that controls the operation of the semiconductor memory device. For example, circuit element PT may include control logic, row decoder, page buffer, etc.

[0071] For example, a circuit element PT may include a transistor, but the example embodiment is not limited thereto. For example, a circuit element PT may include not only various active elements (such as transistors), but also various passive elements (such as capacitors, registers, and inductors).

[0072] Figures 6 to 8 This is a diagram provided to explain semiconductor memory devices. Figure 6 It is relative to Figure 2 Plan view of the source plate in region EX1. Figure 7 It is along Figure 6 The sectional view taken from section BB. Figure 8 It is along Figure 6 The cross-sectional view taken from section CC. For ease of description, refer to the above. Figures 1 to 5 Components or operations that have already been described and overlap with those will be briefly described or will not be described.

[0073] In some example embodiments, the source plate SP may include a first conductivity type impurity region 132 and a second conductivity type impurity region 134. The first conductivity type impurity region 132 may be a region doped with n-type impurities. Furthermore, the second conductivity type impurity region 134 may be a region doped with p-type impurities. The impurity concentration of the second conductivity type impurity region 134 may be higher than the impurity concentration of the semiconductor material of the source plate SP.

[0074] In some example embodiments, the first conductivity type impurity region 132 of the source plate SP may be in contact with the channel layer 122. For example, as Figure 7 As shown, at least a portion of a surface of the first conductivity type impurity region 132 may be in direct contact with the channel layer 122.

[0075] A source plate SP may be disposed on the upper surface of a molded structure MS. When viewed from the upper surface of the molded structure MS, the upper surface may include a channel array region CSA and a block separation region WLCA. The channel array region CSA may represent a region comprising multiple channel structures CS disposed along a second direction D2 and a third direction D3, which are perpendicular to a first direction D1. Furthermore, the block separation region WLCA may include block separation structures WLC configured to extend along the second direction D2 to separate the channel array region CSA into multiple blocks. The multiple block separation structures WLC may be arranged to be spaced apart from the channel array region CSA along the third direction D3.

[0076] In some example embodiments, such as Figure 6 As shown, the first conductivity type impurity region 132 can extend in the second direction D2 on the block separation region WLCA. Figure 7 As shown, the first conductivity type impurity region 132 may be superimposed on the block separation structure WLC in the first direction D1.

[0077] In some example embodiments, the second conductivity type impurity region 134 may be spaced apart from the channel array region CSA in the second direction D2 and may extend in the third direction D3. For example, as Figure 6 and Figure 8 As shown, the second conductivity type impurity region 134 may not be superimposed with the channel array region CSA and the block separation region WLCA along the first direction D1. That is, the second conductivity type impurity region 134 may be set independently without being superimposed with the channel structure CS and the block separation structure WLC along the first direction D1.

[0078] In some example embodiments, a first contact pad SC1 may be formed on a first conductivity type impurity region 132. By applying a desired (and / or optionally predetermined) programming voltage via the first contact pad SC1, the channel structure CS can receive charge (electrons) through the source plate SP, and thus perform a programming operation (or a read operation).

[0079] In some example embodiments, a second contact pad SC2 may be formed on the upper surface of the second conductivity type impurity region 134. By applying a desired (and / or optionally predetermined) erase voltage via the second contact pad SC2, the channel structure CS can receive current through the source plate SP (i.e., due to electron migration), and thus perform an erase operation.

[0080] Specifically, during the programming operation, a programming voltage can be applied between the gate electrode 112 and the channel layer 122. For example, a relatively high DC voltage can be applied to the gate electrode 112, resulting in charge (electrons) being trapped in the charge storage film 124b. During the erasure operation, a desired (and / or optionally predetermined) erasure voltage can be applied via the second contact pad SC2. As a result, the charge trapped in the charge storage film 124b can leave to the channel layer 122.

[0081] Thus, according to various example embodiments, an erase voltage can be applied during the erase operation to a defect region (e.g., a second conductivity type defect region 134) formed in the source plate SP above the channel via CH_H, such that a sufficient amount of erase voltage can be applied to the channel layer of the channel structure without requiring a separate structure (e.g., GIDLWL) for the erase operation. Furthermore, the first conductivity type defect region for programming operations and the second conductivity type defect region for erasing operations are formed separately on the source plate SP, thereby reducing or minimizing interference between the charge movement paths during programming operations and the charge movement paths during erasing operations, and providing a semiconductor memory device with improved reliability and / or stability.

[0082] Figure 9 and Figure 10 These diagrams are provided to explain semiconductor memory devices according to various example embodiments. Figure 9 It is about Figure 2 A plan view of the source plate in region EX1 according to various example embodiments. Figure 10 It is along Figure 9 The sectional view taken from section DD. For ease of description, refer to the above. Figures 1 to 8 Components or operations that have already been described and overlap with those will be briefly described or will not be described.

[0083] In some example embodiments, the first conductivity type impurity region 132a and the second conductivity type impurity region 134a may be alternately arranged along the second direction D2 on the block separation structure WLC of the block separation region WLCA. For example, as Figure 9 As shown, a first conductivity type impurity region 132a may be disposed in the block separation region WLCA and extend in the second direction D2. A second conductivity type impurity region 134a may be disposed in the block separation region WLCA and spaced apart from the adjacent first conductivity type impurity region 132a in the second direction D2. The second conductivity type impurity region 134a may extend in the second direction D2. (Refer to...) Figure 10 The second conductivity type impurity region 134a can be spaced apart from the block separation structure WLC. In this case, the second conductivity type impurity region 134a can be superimposed on the block separation structure WLC in the first direction D1.

[0084] Figure 11 and Figure 12 This is a diagram illustrating a semiconductor memory device according to various example embodiments. Figure 11 It is about Figure 2 A plan view of the source plate in region EX1 according to various example embodiments. Figure 12 It is along Figure 11 The cross-sectional view taken from section EE. For ease of description, refer to the above. Figures 1 to 10 Components or operations that have already been described and overlap with those will be briefly described or will not be described.

[0085] In some example embodiments, a first conductivity type impurity region 132b may be disposed on the block separation structure WLC of the block separation region WLCA and extend in the second direction D2. Furthermore, a second conductivity type impurity region 134b may be disposed in a portion of the source plate SP corresponding to (or adjacent to) the channel array region CSA.

[0086] The channel array region CSA may include multiple channel column regions CCA in which several channel structures CS are arranged (or extended) along the second direction D2. In this case, as Figure 11 As shown, the second conductivity type impurity region 134b may be disposed in at least one of the plurality of channel column regions CCA (e.g., CCAa, CCAb).

[0087] Reference Figure 12 The second conductivity type impurity region 134b may be spaced apart from the channel structure CS. The distance between the second conductivity type impurity region 134b and the channel structure CS may be a desired (and / or optionally predetermined) distance that does not cause interference with the movement path of charges according to programmed operations through the first conductivity type impurity region 132b. The second conductivity type impurity region 134b may be superimposed on the channel structure CS in the first direction D1.

[0088] Figures 13 to 24 These diagrams are provided to explain methods for manufacturing a semiconductor device according to various exemplary embodiments. Figures 13 to 24 This illustrates an intermediate stage of the manufacturing process. The following description will focus primarily on the method used to manufacture the cell array region R1 of the semiconductor device. Figures 13 to 24 .

[0089] Reference Figure 13 A method for manufacturing a semiconductor memory device according to some example embodiments may include forming a stacked structure S_ST on a substrate (or peripheral circuit substrate) 200.

[0090] The substrate 200 may be a silicon substrate, or may include other materials (such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide), but the example embodiments are not limited thereto. Although not shown, an etch stop film may be formed on the substrate 200. The etch stop film may include a material that has etch selectivity relative to the substrate 200. For example, the etch stop film may include a silicon nitride film, but the example embodiments are not limited thereto.

[0091] A stacked structure S_ST may be formed on substrate 200. The stacked structure S_ST may include a molded insulating layer 114 and a sacrificial layer 116 alternately stacked on top of each other. The sacrificial layer 116 may include a material with etch selectivity relative to the molded insulating layer 114. For example, the molded insulating layer 114 may include a silicon oxide film. The sacrificial layer 116 may include a silicon nitride film. However, the exemplary embodiments are not limited thereto. In various exemplary embodiments, the molded insulating layer 114 may be an insulating film, and the sacrificial layer 116 may be a conductive film.

[0092] Reference Figure 14 A channel hole CH_H can be formed that penetrates the molded insulating layer 114 and the sacrificial layer 116. The channel hole CH_H can be formed such that a portion of the upper surface of the substrate 200 is etched to extend into the substrate 200.

[0093] Reference Figure 15 A charge storage structure 124, a channel layer 122, and a filling pattern 126 can be sequentially formed in the channel hole CH_H. The process of forming the charge storage structure 124 can be performed in the following order: forming a barrier insulating film 124c, forming a charge storage film 124b on the barrier insulating film 124c, and forming a tunnel insulating film 124a on the charge storage film 124b. The channel layer 122 and the charge storage structure 124 can extend on the upper surface of the stacked structure S_ST.

[0094] Reference Figure 16 and Figure 17 An intermediate insulating film (MIF) can be formed on the channel layer 122, and a block separation structure (WLC) can be formed through the intermediate insulating film (MIF) and the stacked structure S_ST. Although not shown, an etch stop film can be formed between the substrate 200 and the stacked structure S_ST, and in this case, the block separation structure WLC can be etched up to the location of the etch stop film.

[0095] Reference Figure 18The sacrificial layer 116 can be selectively removed via a block separation structure WLC. In this case, the molded insulating layer 114 can be retained. The gate electrode 112 can be formed in the empty space created by the removal of the sacrificial layer 116. As a result, a molded structure MS defined by the gate electrode 112 and the molded insulating layer 114 can be formed. The intermediate insulating film MIF can be removed.

[0096] Reference Figures 19 to 22 A source structure SS can be formed on a molded structure MS. For example, the source structure SS can be formed on the upper surface (or first surface) of the molded structure MS. First, a source plate SP can be formed on the molded structure MS. The source plate SP may comprise p-type (p-) polysilicon with a low doping concentration. For example, the impurity concentration of the source plate SP may be lower than the impurity concentration (p+) of the second conductivity type impurity region.

[0097] A first conductivity type impurity region 132 and a second conductivity type impurity region 134 may be formed in a portion of the source electrode SP. The first conductivity type impurity region 132 and the second conductivity type impurity region 134 may be formed in a desired (and / or optionally predetermined) region of the source electrode SP. For example, as... Figure 21 As shown, a first conductivity type impurity region 132 can be formed on the block-separated structure WLC, and as... Figure 22 As shown, a second conductivity type impurity region 134 can be formed in a region on the first direction D1 that is not superimposed with the channel structure CS and the block separation structure WLC. However, the example embodiment is not limited thereto, and since reference has been made to... Figures 6 to 12 The locations of the first conductivity type impurity region 132 and the second conductivity type impurity region 134 have been described in detail, therefore repeated descriptions of them will be omitted. After the first conductivity type impurity region 132 and the second conductivity type impurity region 134 are formed in a portion of the source plate SP, a first interlayer insulating film 152 may be formed on the source plate SP. A first contact pad SC1 may be formed in the first conductivity type impurity region 132 and the first interlayer insulating film 152, and a second contact pad SC2 may be formed in the second conductivity type impurity region 134 and the first interlayer insulating film 152.

[0098] Reference Figure 23 and Figure 24A drain structure DS can be formed on the lower surface (or second surface) of the molded structure MS. First, a carrier wafer CWF can be attached to the source structure SS. The source structure SS and the molded structure MS can be reversed, such that the carrier wafer CWF at the top is rotated to the bottom. A second interlayer insulating film 154 can be formed on the second surface of the molded structure MS. Bit line contact pads BLP and bit line contacts BLC can be formed. The bit line contact pads BLP and BLC can partially penetrate the second interlayer insulating film 154 and the channel structure CS to connect to the channel layer 122. The bit line contact pads BLP can be omitted. In addition, bit lines BL can be formed on the second interlayer insulating film 154 and the bit line contacts BLC.

[0099] The results can be provided for reference as above. Figures 1 to 12 The semiconductor memory device described.

[0100] Figure 25 These diagrams are provided to explain semiconductor memory devices according to various example embodiments. Figure 25 The first unit structure ST1 and the second unit structure ST2 are as shown above. Figures 1 to 12 The semiconductor memory devices described herein, and which may be described by reference above. Figures 13 to 24 Semiconductor memory devices manufactured using the same or similar methods as described.

[0101] Reference Figure 25 In some example embodiments, the semiconductor memory device may include input and output interface (I / O), peripheral circuit structure (PER), first cell structure (ST1), and second cell structure (ST2). The semiconductor memory device can be electrically connected to a controller that controls and / or manages the semiconductor memory device via the input and output interface (I / O).

[0102] The peripheral circuit structure PER may include a peripheral circuit substrate (e.g., Figure 3 The peripheral circuit substrate), and multiple circuit elements formed on the peripheral circuit substrate (e.g., Figure 3 Multiple circuit elements PT), and metal layers connected to each of the multiple circuit elements (e.g., Figure 3 260), an interlayer insulating layer formed on the peripheral circuit substrate to bury multiple circuit elements and metal layers (e.g., Figure 3 240), and the lower bonding metal formed on the interlayer insulating layer (e.g., Figure 3 BD0).

[0103] The first unit structure ST1 may include a source structure SS1, a first molded structure MS1, multiple first channel structures CS1, a first line BL1, and a first bonding metal BD1. The source structure SS1 includes a first source plate SP1 containing semiconductor material. The first molded structure MS1 includes multiple gate electrodes 112 and multiple molded insulating layers 114 disposed on the bottom surface of the first source plate SP1 and alternately stacked on top of each other. The multiple first channel structures CS1 penetrate the first molded structure MS1 in a first direction D1. The first line BL1 is disposed below the multiple first channel structures CS1, and the first bonding metal BD1 is disposed below the first line BL1. The first bonding metal BD1 may be bonded to a lower bonding metal BD0 above the peripheral circuit structure PER. The first source plate SP1 may include a first conductivity type impurity region (e.g., a region doped with n-type impurities) and a second conductivity type impurity region (e.g., a region doped with p-type impurities). Each of the plurality of gate electrodes 112 and the plurality of molded insulating layers 114 may be spaced apart in a first direction D1 perpendicular to the bottom surface of the first source plate SP1, and may extend in a second direction D2 parallel to the bottom surface of the first source plate SP1. Each of the plurality of first channel structures CS1 may include a channel hole extending in the first direction D1 and a charge storage structure and a channel layer sequentially stacked on the inner wall of the channel hole. Furthermore, the first unit structure ST1 may include a second bonding metal BD2 on the source structure SS1. In some example embodiments, the first unit structure ST1 may also include a first drain structure DS1.

[0104] The first unit structure ST1 can be disposed on the peripheral circuit structure PER. The peripheral circuit structure PER and the first unit structure ST1 can be connected to each other through the lower bonding metal BD0 and the first bonding metal BD1. Each of the lower bonding metal BD0 and the first bonding metal BD1 can be formed of aluminum, copper, tungsten, etc., but the example embodiment is not limited thereto.

[0105] In some example embodiments, the semiconductor memory device may further include a second cell structure ST2 on a first cell structure ST1. The second cell structure ST2 may include a source structure SS2, a third bonding metal BD3, a second molding structure MS2, a plurality of second channel structures CS2, and a second bit line BL2. The source structure SS2 includes a second source plate SP2 containing semiconductor material. The third bonding metal BD3 is disposed below the second source plate SP2. The second molding structure MS2 includes a plurality of gate electrodes 112 and a plurality of molded insulating layers 114 arranged alternately stacked on the second source plate SP2. The plurality of second channel structures CS2 penetrate the second molding structure MS2 in a first direction D1. The second bit line BL2 is disposed on the plurality of second channel structures CS2. The second source plate SP2 may include a first conductivity type impurity region (e.g., a region doped with n-type impurities) and a second conductivity type impurity region (e.g., a region doped with p-type impurities). Each of the plurality of gate electrodes 112 and the plurality of molded insulating layers 114 may be spaced apart in a first direction D1 perpendicular to the bottom surface of the second source plate SP2, and may extend in a second direction D2 parallel to the bottom surface of the second source plate SP2. Each of the plurality of second channel structures CS2 may include a channel hole extending in the first direction D1 and charge storage structures and channel layers sequentially stacked on the inner wall of the channel hole. In some example embodiments, the second cell structure ST2 may also include a second drain structure DS2.

[0106] The second unit structure ST2 may be disposed on the first unit structure ST1, with the top and bottom of the second unit structure ST2 being reversed compared to the first unit structure ST1. The first unit structure ST1 and the second unit structure ST2 may be joined by a second bonding metal BD2 and a third bonding metal BD3. The second bonding metal BD2 and the third bonding metal BD3 may be formed of aluminum, copper, tungsten, etc., but the example embodiment is not limited to this.

[0107] Figure 26 This is a schematic diagram of an electronic system 1000 including a semiconductor device 1100.

[0108] Reference Figure 26 Electronic system 1000 may include semiconductor device 1100 and controller 1200 electrically connected to semiconductor device 1100. Electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0109] For example, semiconductor device 1100 may be a non-volatile memory device, such as the one described above. Figures 1 to 25 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common-source line CSL, a word line WL, a first gate-up line UL1, a second gate-up line UL2, a first gate-down line LL1, a second gate-down line LL2, and a memory cell string CSTR between the bit line BL and the common-source line CSL.

[0110] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified according to various example embodiments.

[0111] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may each be the gate electrode of the lower transistors LT1 and LT2. Word line WL may be the gate electrode of the memory cell transistor MCT, and gate upper lines UL1 and UL2 may each be the gate electrode of the upper transistors UT1 and UT2.

[0112] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from within the first structure 1100F to the second structure 1100S.

[0113] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one memory cell transistor selected from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input and output pads 1101 electrically connected to the logic circuit 1130. The input and output pads 1101 can be electrically connected to the logic circuit 1130 via input and output connection wiring 1135 extending from within the first structure 1100F and into the second structure 1100S.

[0114] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to some example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0115] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 operates according to desired (and / or optionally predetermined) firmware and controls NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted via NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. Upon receiving control commands from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0116] Figure 27 This is a perspective view schematically illustrating an electronic system 2000 including a 3D semiconductor memory device according to various example embodiments.

[0117] Reference Figure 27 The electronic system 2000 according to various example embodiments may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 disposed to the main substrate 2001.

[0118] The main substrate 2001 may include a connector 2006, which includes multiple pins that attach to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. For example, the electronic system 2000 may communicate with the external host using any of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Express (PIC-Express), Serial Advanced Technology Attachment (SATA), Mobile Physical Layer for Universal Flash Memory (M-Phy), Compute Fast Link (CXL), Universal Chipset Interconnect Express (UCIe), etc. For example, the electronic system 2000 may operate via power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0119] The controller 2002 can record data in or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0120] DRAM 2004 can be a buffer memory used to mitigate the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in electronic system 2000 can also operate as a high-speed cache memory and can also provide space for temporary data storage during the control operation of semiconductor package 2003. If electronic system 2000 includes DRAM 2004, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0121] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0122] The package substrate 2100 may be a printed circuit board including package pad 2130. Each of the semiconductor chips 2200 may include input and output pads 2210. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a vertical channel structure 3220. Each of the semiconductor chips 2200 may include the aforementioned 3D semiconductor memory device.

[0123] For example, the connection structure 2400 may be a bonding wiring that electrically connects the input and output pads 2210 and the package pad 2130. In each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other using a bonding wiring method and may be electrically connected to the package pad 2130 of the package substrate 2100. According to some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other via through electrodes (through-silicon vias, also known as "through-silicon vias") instead of a bonding wiring type connection structure 2400.

[0124] For example, controller 2002 and semiconductor chip 2200 may be included in a single package. For example, controller 2002 and semiconductor chip 2200 may be mounted on a separate intermediate substrate different from the main substrate 2001, and controller 2002 and semiconductor chip 2200 may be connected to each other via wiring disposed on the intermediate substrate.

[0125] Any element disclosed above may include processing circuitry and / or be implemented in processing circuitry, which is hardware such as including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0126] Although various exemplary embodiments have been described above with reference to specific and limited examples and drawings, the exemplary embodiments are not limited thereto, and it is self-evident that those skilled in the art can make various changes and modifications within the equivalent scope of the technical concept and the claims described herein.

Claims

1. A semiconductor memory device, comprising: Source plate, including semiconductor materials; A molded structure, on the bottom surface of a source plate, includes a plurality of gate electrodes and a plurality of molded insulating layers stacked alternately on each other in a first direction perpendicular to the bottom surface of the source plate, and each of the plurality of gate electrodes and the plurality of molded insulating layers extends in a second direction parallel to the bottom surface of the source plate. as well as Multiple channel structures extend through a molded structure in a first direction. Each of the multiple channel structures includes a channel aperture, a charge storage structure, and a channel layer. The channel aperture extends in the first direction, the charge storage structure is on the inner wall of the channel aperture, and the channel layer is on the charge storage structure. The source plate includes a first conductivity type impurity region and a second conductivity type impurity region, and The channel layer extends along the bottom surface of the source plate in the second direction.

2. The semiconductor memory device according to claim 1, wherein, The diameter of the channel aperture decreases as the distance from the source plate increases.

3. The semiconductor memory device according to claim 1, wherein, The channel layer is in contact with the source plate.

4. The semiconductor memory device according to claim 1, wherein, The first conductivity type impurity region is in contact with the channel layer.

5. The semiconductor memory device according to claim 1, wherein, The charge storage structure of each of the plurality of channel structures is located between the molded structure and the channel layer.

6. The semiconductor memory device according to claim 1, wherein, The molded structure also includes a block separation structure extending in the first direction, and The first type of conductivity impurity region is located on the block-separated structure.

7. The semiconductor memory device according to claim 1, further comprising: The channel array region includes the plurality of channel structures arranged along a second direction and a third direction, the second direction and the third direction being perpendicular to the first direction and perpendicular to each other; as well as The block separation region includes multiple block separation structures that extend in the second direction and separate the channel array region into multiple blocks. The multiple block separation structures in the block separation region are spaced apart in a third direction.

8. The semiconductor memory device according to claim 7, wherein, The first conductivity type impurity region extends in the second direction on the plurality of block separation structures, and The first contact pad is located on the impurity region of the first conductivity type.

9. The semiconductor memory device according to claim 7, wherein, The second conductivity type impurity region is not superimposed on the channel array region and block separation region along the first direction.

10. The semiconductor memory device according to claim 9, wherein, The second conductivity type impurity region is spaced apart from the channel array region in the second direction and extends upward in the third direction. The second contact pad is on the upper surface of the second type of conductive impurity region.

11. The semiconductor memory device according to claim 7, wherein, The first conductivity type impurity region is located on the plurality of block separation structures and extends in the second direction. The second conductivity type impurity region is located in the region of the source plate adjacent to the channel array region.

12. The semiconductor memory device according to claim 11, wherein, The channel array region includes multiple channel column regions. The plurality of channel column regions include the plurality of channel structures extending along the second direction, and The second conductivity type impurity region is located in one or more of the plurality of channel column regions.

13. The semiconductor memory device according to claim 7, wherein, The first conductivity type impurity region and the second conductivity type impurity region are alternately arranged along the second direction on each block separation structure of the block separation region.

14. The semiconductor memory device according to claim 1, wherein, The semiconductor material of the source plate includes polycrystalline silicon doped with p-type impurities. The first conductivity type impurity region is the region doped with n-type impurities. The second conductivity type impurity region is doped with p-type impurities, and The impurity concentration in the second conductivity type impurity region is higher than the impurity concentration in the semiconductor material of the source plate.

15. A semiconductor memory device, comprising: Peripheral circuit structure; as well as The first unit structure, in terms of the peripheral circuit structure... The peripheral circuit structure includes: Peripheral circuit substrate; Multiple circuit elements are located on an external circuit substrate; A metal layer, connected to each of the plurality of circuit elements; and An interlayer insulating layer is placed on the peripheral circuit substrate to bury the plurality of circuit elements and metal layers. The first unit structure includes: The first source plate includes a semiconductor material, a first conductivity type impurity region, and a second conductivity type impurity region. A first molded structure includes a plurality of gate electrodes and a plurality of molded insulating layers stacked alternately on the bottom surface of a first source plate in a first direction perpendicular to the bottom surface of the first source plate, each of the plurality of gate electrodes and the plurality of molded insulating layers extending in a second direction parallel to the bottom surface of the first source plate. A plurality of first channel structures extend through a first molding structure in a first direction. Each of the plurality of first channel structures includes a channel aperture, a charge storage structure, and a channel layer. The channel aperture extends in the first direction, the charge storage structure is on the inner wall of the channel aperture, and the channel layer is on the charge storage structure. The first line is located below the plurality of first channel structures, and The channel layer extends along the bottom surface of the first source plate in the second direction.

16. The semiconductor memory device of claim 15, further comprising: The channel array region includes multiple channel structures arranged along a second direction and a third direction, the second direction and the third direction being perpendicular to the first direction and perpendicular to each other; as well as The block separation region includes multiple block separation structures that extend in the second direction and separate the channel array region into multiple blocks. The multiple block separation structures in the block separation region are spaced apart in a third direction.

17. The semiconductor memory device of claim 16, wherein, The first conductivity type impurity region is on the block separation region and extends in the second direction, and The second conductivity type impurity region is not superimposed on the channel array region and block separation region along the first direction.

18. The semiconductor memory device of claim 16, wherein, The first conductivity type impurity region is on the block separation region and extends in the second direction, and The second conductivity type impurity region is located in the region of the first source plate adjacent to the channel array region.

19. The semiconductor memory device of claim 16, further comprising: The second unit structure is based on the first unit structure. The second unit structure includes: The second source plate includes a semiconductor material and includes a first conductivity type impurity region and a second conductivity type impurity region. The third bonding metal is located below the second source electrode plate; A second molded structure, above the second source plate, includes a plurality of gate electrodes and a plurality of molded insulating layers that are alternately stacked on top of each other in a first direction perpendicular to the bottom surface of the first source plate. A plurality of second channel structures extend through a second molding structure in a first direction. Each of the plurality of second channel structures includes a channel aperture, a charge storage structure, and a channel layer. The channel aperture extends in the first direction, the charge storage structure is on the inner wall of the channel aperture, and the channel layer is on the charge storage structure. The second bit line is on the plurality of second channel structures.

20. A semiconductor memory device, comprising: The source plate includes a semiconductor material, and the source plate includes a first conductivity type impurity region and a second conductivity type impurity region. A molded structure, on the bottom surface of a source plate, includes a plurality of gate electrodes and a plurality of molded insulating layers stacked alternately on each other in a first direction perpendicular to the bottom surface of the source plate, each of the plurality of gate electrodes and the plurality of molded insulating layers extending in a second direction parallel to the bottom surface of the source plate. Multiple channel structures extend through a molded structure in a first direction. Each of the multiple channel structures includes a channel aperture, a charge storage structure, and a channel layer. The channel aperture extends in the first direction, the charge storage structure is on the inner wall of the channel aperture, the channel layer is on the charge storage structure, and the channel layer is in contact with the source plate. Multiple block-separated structures penetrate the molded structure in a first direction, and a first conductivity type impurity region is located on the multiple block-separated structures; as well as Bit lines are located below the plurality of channel structures. The channel layer extends along the bottom surface of the source plate in a second direction, which is perpendicular to the first direction. The channel layer includes a channel array region and a block separation region. The channel array region includes a plurality of channel structures arranged along a second direction and a third direction perpendicular to a first direction, the second direction and the third direction being perpendicular to each other. The block separation region includes a plurality of block separation structures extending in the second direction and separating the channel array region into a plurality of blocks. The multiple block separation structures in the block separation region are spaced apart in a third direction.

Images