SiC VDMOSFET structure integrated with graphene heat dissipation channel and process thereof

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a SiC VDMOSFET structure integrated with a graphene heat dissipation channel and a process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprising an N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer, a graphene layer being arranged between the P well layer and the N well layer, the upper and lower ends of the graphene layer being in direct contact with the N well layer and the P well layer respectively, a metal layer being arranged in the P+ layer, and the top end of the metal layer being in direct contact with the source. The graphene layer is introduced between the P well layer and the N well layer, and is brought into Ohmic contact with the metal layer, thereby constructing an efficient vertical heat dissipation path, significantly improving the heat dissipation capacity of the device, effectively reducing the working temperature, and thereby improving the reliability and power density of the device, and being suitable for high-power and high-frequency application scenarios.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a SiCVD MOSFET structure with integrated graphene heat dissipation channels and its process. Background Technology

[0002] Traditional SiC VDMOSFET devices face severe self-heating effects and thermal management challenges in high power density and high frequency applications. Their heat dissipation capacity is limited by the thermal conductivity of the semiconductor material itself and the efficiency of traditional metal heat dissipation structures, resulting in decreased reliability and performance degradation of the devices in high-temperature environments, which restricts their application in more demanding conditions. Existing technologies often use external heat dissipation or complex packaging to improve heat dissipation, but this often introduces additional thermal resistance, increases process complexity and cost, and makes it difficult to achieve efficient vertical heat dissipation within the chip.

[0003] Furthermore, an existing patent (CN117673189A) discloses a graphene MOS detector for improving photoresponse and its fabrication method, belonging to the field of semiconductor optoelectronic integration. This existing patent suffers from low heat dissipation efficiency and decreased reliability due to self-heating effects in high-power and high-frequency applications, as well as the additional thermal resistance, high process complexity, and cost introduced by traditional heat dissipation solutions such as external heat dissipation or complex packaging. Moreover, the existing patent's method of improving photoresponse through metal structures and high-temperature processes may compromise silicon-based integration compatibility. Summary of the Invention

[0004] This invention provides a SiC VDMOSFET structure and its process with integrated graphene heat dissipation channels to solve existing technical problems, thereby solving the problems of low heat dissipation efficiency and decreased reliability caused by self-heating effect.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a SiC VDMOSFET structure with integrated graphene heat dissipation channels, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P+ layer, a P well layer, and an N well layer, wherein a graphene layer is disposed between the P well layer and the N well layer, and the upper and lower ends of the graphene layer are in direct contact with the N well layer and the P well layer, respectively;

[0006] The P+ layer has a metal layer inside, the top of the metal layer is in direct contact with the source electrode, and the inner side of the metal layer is in ohmic contact with the graphene layer.

[0007] Furthermore, a lower heat dissipation layer is provided on both sides of the single MOS cell and inside the N substrate layer. The lower heat dissipation layer is composed of several non-contact graphene rods, and the top end of each graphene rod extends into the interior of the N diffusion layer, while the bottom end of the graphene rod is in ohmic contact with the drain electrode.

[0008] Furthermore, an N+ layer is formed in a single MOS cell between two adjacent P-well layers by ion implantation. This N+ layer is located directly below the gate and in contact with the P-well layer.

[0009] Furthermore, the N+ layer has a central heat dissipation layer in the middle region, which is made of graphene and has its top end in direct contact with the gate.

[0010] Furthermore, the central heat dissipation layer also has a contact layer inside, the top of which is in direct contact with the gate, and both the contact layer and the gate are made of polycrystalline silicon.

[0011] Furthermore, the surface of the graphene layer is etched with several grooves, the contents of which are deposited with contact particles, the tips of which are in direct contact with the N-well layer.

[0012] Furthermore, both the metal layer and the contact particles are made of tantalum nitride or titanium nitride.

[0013] Furthermore, an N-sector layer is formed inside the N-well layer and near the gate side by ion implantation. One side of the N-sector layer is in direct contact with the P-well layer, and the other side of the N-sector layer is in ohmic contact with the source.

[0014] A process for integrating a graphene heat dissipation channel SiC VDMOSFET structure includes:

[0015] S1. An N diffusion layer is epitaxially grown on an N substrate, and a P+ layer, a P well layer, and an N well layer are formed by ion implantation.

[0016] S2. A graphene layer is grown at the interface between the P-well layer and the N-well layer by chemical vapor deposition, so that its upper and lower ends are in direct contact with the N-well layer and the P-well layer, respectively.

[0017] S3. In the P+ layer region, a contact hole is formed by etching, and a metal layer is deposited so that its top end contacts the subsequently formed source electrode, and its inner side forms an ohmic contact with the graphene layer.

[0018] S4. Deposit the gate dielectric layer and polysilicon gate, and pattern them;

[0019] S5. Deposit source and drain metal layers and perform alloying treatment to complete device fabrication.

[0020] This invention provides a SiC VDMOSFET structure and its process with integrated graphene heat dissipation channels. Compared with existing technologies, the advantages achieved by this method are:

[0021] 1. This invention introduces a graphene layer between the P-well layer and the N-well layer and forms an ohmic contact with the metal layer to create an efficient vertical heat dissipation path, which significantly improves the heat dissipation capacity of the device, effectively reduces the operating temperature, and thus improves the reliability and power density of the device, making it suitable for high-power and high-frequency applications.

[0022] 2. This invention forms a heat dissipation channel from the drain to the middle of the chip by setting a lower heat dissipation layer composed of graphene rods in the N substrate layer, which greatly reduces the overall thermal resistance of the device and enhances its stability and lifespan under high temperature environment. It is especially suitable for high temperature and high power operation conditions.

[0023] 3. By setting an N+ layer between adjacent P-well layers and integrating a graphene-based central heat dissipation layer, this invention not only optimizes carrier injection efficiency but also achieves rapid heat dissipation in the gate region, effectively suppressing the formation of local hot spots and improving the uniformity and overall performance of the device.

[0024] 4. By setting a polysilicon contact layer in the central heat dissipation layer and making it in direct contact with the gate, the present invention maintains good electrical compatibility and further enhances the interface heat conduction, making the heat dissipation structure more tightly integrated into the device, thereby improving the efficiency and stability of thermal management.

[0025] 5. This invention significantly enhances the electrothermal contact performance between graphene and the N-well layer by etching grooves on the surface of the graphene layer and depositing tantalum nitride or titanium nitride contact particles, thereby improving the mechanical stability and thermal distribution uniformity of the interface, while also helping to reduce contact resistance and improve the overall electrical characteristics of the device.

[0026] 6. By introducing an N-sector layer and forming an ohmic contact with the source electrode, this invention optimizes the current path and electric field distribution of the device. Combined with the excellent heat dissipation characteristics of the graphene layer, it achieves a synergistic improvement in electrothermal performance, enabling the device to exhibit higher efficiency and reliability in high-power applications. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of Embodiment 3 of the present invention;

[0030] Figure 4This is a schematic diagram of Embodiment 4 of the present invention;

[0031] Figure 5 This is a schematic diagram of Embodiment 5 of the present invention;

[0032] Figure 6 This is a schematic diagram of Embodiment Six of the present invention.

[0033] In the diagram: 1. Drain; 2. Source; 3. Gate; 4. N-substrate layer; 5. N-diffusion layer; 6. P+ layer; 7. P-well layer; 8. N-well layer; 9. Graphene layer; 10. Metal layer; 11. Lower heat dissipation layer; 12. N+ layer; 13. Central heat dissipation layer; 14. Contact layer; 15. Contact particles; 16. N-sector layer. Detailed Implementation

[0034] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 1 As shown, a process for an integrated graphene heat dissipation channel SiC VDMOSFET structure includes:

[0036] Step 1: An N-diffusion layer 5 is epitaxially grown on the N-substrate layer 4, and a P+ layer 6, a P-well layer 7, and an N-well layer 8 are formed by ion implantation. By precisely epitaxially growing the N-diffusion layer on the N-substrate and using ion implantation to form the P+, ​​P-well, and N-well layers, the basic structure of the device is controllably constructed. This provides an ideal interface and doping distribution for the subsequent integration of heat dissipation channels, ensuring that the device has good breakdown characteristics and electrical performance.

[0037] Step 2: A graphene layer 9 is grown at the interface between the P-well layer 7 and the N-well layer 8 using chemical vapor deposition, so that its upper and lower ends are in direct contact with the N-well layer 8 and the P-well layer 7, respectively. By using chemical vapor deposition to directly grow the graphene layer at the interface between the P-well and N-well, a high-quality heterogeneous combination of graphene and semiconductor materials is achieved, forming an efficient vertical heat dissipation path, which significantly improves the thermal conductivity of the device and fundamentally improves the problem of heat accumulation during high-power operation.

[0038] Step 3: In the P+ layer 6 region, a contact hole is formed by etching, and a metal layer 10 is deposited so that its top end contacts the subsequently formed source electrode 2, and its inner side forms an ohmic contact with the graphene layer 9. By selectively etching to form a contact hole and depositing a metal layer, a reliable ohmic contact is formed with the graphene layer while achieving source electrode contact. This not only optimizes the current transport path and reduces contact resistance, but also further enhances thermal management capabilities and improves the overall performance and stability of the device.

[0039] Step 4: Deposit the gate dielectric layer and polysilicon gate 3, and pattern them; By depositing and patterning the gate dielectric layer and polysilicon gate, precise control of the channel region is achieved, ensuring the switching characteristics and frequency response of the device. At the same time, the polysilicon material is well compatible with the heat dissipation structure, which helps to achieve synergistic optimization between electrical performance and thermal management.

[0040] Step 5: Deposit source electrode 2 and drain electrode 1 metal layers and perform alloying treatment to complete device fabrication. By depositing and alloying the source and drain electrode metal layers, the final interconnection of the device is completed, achieving low-resistance and reliable electrode contact. The alloying treatment further improves the interface characteristics and thermal stability, ensuring that the device still has excellent electrothermal performance and service life under high power and high temperature environments.

[0041] Example 1

[0042] like Figure 1 As shown, according to one aspect of the present invention, a SiCVD MOSFET structure with integrated graphene heat dissipation channels is provided, comprising a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a P+ layer 6, a P-well layer 7, and an N-well layer 8. A graphene layer 9 is disposed between the P-well layer 7 and the N-well layer 8, and the upper and lower ends of the graphene layer 9 are in direct contact with the N-well layer 8 and the P-well layer 7, respectively. A metal layer 10 is disposed inside the P+ layer 6, the top end of the metal layer 10 is in direct contact with the source 2, and the inner side of the metal layer 10 is in ohmic contact with the graphene layer 9.

[0043] By introducing a graphene layer 9 between the P-well layer 7 and the N-well layer 8, a vertical heat dissipation channel is constructed using the high thermal conductivity of graphene, which significantly improves the heat dissipation efficiency of the device. At the same time, the ohmic contact between the metal layer 10 and the graphene layer 9 further optimizes thermal management and current distribution, reduces contact resistance, and enhances the reliability and power density of the device.

[0044] Example 2

[0045] like Figure 2 As shown, a lower heat dissipation layer 11 is provided on both sides of a single MOS cell and inside the N-substrate layer 4. The lower heat dissipation layer 11 is composed of several non-contact graphene rods, with the top end of each graphene rod extending into the interior of the N-diffusion layer 5, and the bottom end of the graphene rod making ohmic contact with the drain 1. The lower heat dissipation layer 11, composed of graphene rods, is disposed in the N-substrate layer 4, extending from the drain 1 to the N-diffusion layer 5, forming a heat dissipation path from the bottom to the middle of the chip. This effectively conducts heat away from the drain, reduces thermal resistance, and improves operational stability at high temperatures.

[0046] Example 3

[0047] like Figure 3 As shown, an N+ layer 12 is formed in a single MOS cell between two adjacent P-well layers 7 via ion implantation. This N+ layer 12 is located directly below the gate 3 and in contact with the P-well layers 7. A central heat dissipation layer 13, made of graphene, is provided in the middle region of the N+ layer 12, and its top end is in direct contact with the gate 3. By implanting N+ layers 12 between adjacent P-well layers 7 and placing a central heat dissipation layer 13 made of graphene in its central region, this structure not only improves carrier injection efficiency but also rapidly conducts heat concentrated below the gate 3 to the source 2 region through the graphene layer, alleviating the generation of hot spots.

[0048] Example 4

[0049] like Figure 4 As shown, a contact layer 14 is also provided inside the central heat dissipation layer 13. The top of the contact layer 14 is in direct contact with the gate 3, and both the contact layer 14 and the gate 3 are made of polysilicon. By placing the polysilicon contact layer 14 in the central heat dissipation layer 12 and directly contacting the gate 3, the electrical compatibility between the gate 3 and the heat dissipation layer 13 is ensured, and the good interface characteristics of polysilicon enhance the heat conduction efficiency, further optimizing the thermal management performance of the device.

[0050] Example 5

[0051] like Figure 5 As shown, several grooves are etched on the surface of the graphene layer 9, and contact particles 15 are deposited in the grooves. The tips of the contact particles 15 are in direct contact with the N-well layer 8. Both the metal layer 10 and the contact particles 15 are made of tantalum nitride or titanium nitride. Etching grooves on the surface of the graphene layer 9 and depositing tantalum nitride or titanium nitride contact particles 15 enhances the electrical and thermal contact between the graphene and the N-well layer 8, improves interface stability and heat dissipation uniformity, and reduces contact resistance.

[0052] Example 6

[0053] like Figure 6 As shown, several trenches are etched on the surface of the graphene layer 9, and contact particles 15 are deposited in the trenches. The tops of the contact particles 15 are in direct contact with the N-well layer 8. An N-fan-shaped layer 16 is formed inside the N-well layer 8, near the gate 3, by ion implantation. One side of the N-fan-shaped layer 16 is in direct contact with the P-well layer 7, and the other side of the N-fan-shaped layer 16 is in 2-ohm contact with the source. By implanting N-fan-shaped layers 16 in the N-well layer 8 and making them in 2-ohm contact with the source, the current path and electric field distribution are optimized. Combined with the heat dissipation capability of the graphene layer 9, an electrothermal synergistic design is achieved, significantly improving the overall performance and reliability of the device.

[0054] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A SiCVD MOSFET structure with integrated graphene heat dissipation channels, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (6), a P-well layer (7), and an N-well layer (8), characterized in that: A graphene layer (9) is provided between the P-well layer (7) and the N-well layer (8), and the upper and lower ends of the graphene layer (9) are in direct contact with the N-well layer (8) and the P-well layer (7), respectively. The P+ layer (6) has a metal layer (10) inside, the top of the metal layer (10) is in direct contact with the source (2), and the corresponding side of the adjacent metal layer (10) in a single MOS cell is in ohmic contact with the graphene layer (9).

2. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 1, characterized in that: A lower heat dissipation layer (11) is provided on the left and right sides of a single MOS cell and inside the N substrate layer (4). The lower heat dissipation layer (11) is composed of several non-contact graphene rods, and the top of each graphene rod extends into the interior of the N diffusion layer (5). The bottom of the graphene rod is in ohmic contact with the drain (1).

3. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 2, characterized in that: An N+ layer (12) is formed by ion implantation in a single MOS cell and between two adjacent P-well layers (7). The N+ layer (12) is located directly below the gate (3) and in contact with the P-well layer (7).

4. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 3, characterized in that: The N+ layer (12) has a central heat dissipation layer (13) in the middle region. The central heat dissipation layer (13) is made of graphene material, and the top of the central heat dissipation layer (13) is in direct contact with the gate (3).

5. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 4, characterized in that: The central heat dissipation layer (13) is further provided with a contact layer (14), the top of the contact layer (14) is in direct contact with the gate (3), and both the contact layer (14) and the gate (3) are made of polycrystalline silicon.

6. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 1, characterized in that: The surface of the graphene layer (9) is etched with several grooves, the contents of which are deposited with contact particles (15), the top of which is in direct contact with the N-well layer (8).

7. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 6, characterized in that: The contact particles (15) are made of either tantalum nitride or titanium nitride.

8. The SiCVD MOSFET structure with integrated graphene heat dissipation channel according to claim 6, characterized in that: An N-sector layer (16) is formed by ion implantation inside the N-well layer (8) and on the side near the gate (3). One side of the N-sector layer (16) is in direct contact with the P-well layer (7), and the other side of the N-sector layer (16) is in ohmic contact with the source (2).

9. A process for integrating a graphene heat dissipation channel SiCVD MOSFET structure, characterized in that, The SiCVDMOSFET structure with integrated graphene heat dissipation channel as described in claim 1, wherein the process of the SiCVDMOSFET structure with integrated graphene heat dissipation channel includes: S1. An N diffusion layer (5) is epitaxially grown on an N substrate layer (4), and a P+ layer (6), a P well layer (7) and an N well layer (8) are formed by ion implantation. S2. A graphene layer (9) is grown at the interface between the P-well layer (7) and the N-well layer (8) by chemical vapor deposition, so that its upper and lower ends are in direct contact with the N-well layer (8) and the P-well layer (7) respectively. S3. A contact hole is formed in the P+ layer (6) region by etching, and a metal layer (10) is deposited so that its top end contacts the subsequently formed source electrode (2), and its inner side forms an ohmic contact with the graphene layer (9); S4. Deposit the gate dielectric layer and the polysilicon gate (3), and pattern it; S5. Deposit source (2) and drain (1) metal layers and perform alloying treatment to complete device fabrication.

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