Cascode GaN device and preparation method thereof

Abstract

The invention relates to the field of semiconductors, and discloses a cascode GaN device and a preparation method thereof, and the cascode GaN device comprises a lead frame base island, an MOS chip and a GaN chip. A first conductive region serving as a source electrode of the GaN device is arranged on the lead frame base island; a source electrode of the MOS chip is arranged on the back surface, and a grid electrode and a drain electrode are arranged on the front surface; a source electrode on the back surface of the MOS chip is electrically connected with the first conductive region; the GaN chip is stacked on the MOS chip, a source electrode, a grid electrode and a drain electrode of the GaN chip are arranged on the front surface of the GaN chip, a source electrode of the GaN chip is also arranged on the back surface of the GaN chip, and the source electrode on the back surface of the GaN chip is electrically connected with the drain electrode on the front surface of the MOS chip; or the front surface of the MOS chip is also provided with a source electrode, the front surface of the GaN chip is provided with a drain electrode, the back surface of the GaN chip is provided with a source electrode and a grid electrode, and the source electrode and the grid electrode on the back surface of the GaN chip are correspondingly and electrically connected with the drain electrode and the source electrode on the front surface of the MOS chip. The size of the GaN device can be reduced, and the cost of the GaN device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a common-source, common-gate GaN device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) is a third-generation wide-bandgap semiconductor material. In applications requiring high temperature, high pressure, and high frequency, its semiconductor devices exhibit superior characteristics compared to Si-based semiconductor devices. GaN FET devices currently primarily come in two structures: depletion mode (D-mode) and enhancement mode (E-mode).

[0003] A cascode GaN device is composed of a high-voltage depletion-mode GaN power device and a low-voltage enhancement-mode Si MOSFET (metal-oxide-semiconductor field-effect transistor). Its structure indicates that when no gate voltage is applied and the drain-source voltage is greater than zero, it operates in forward blocking mode; when the gate voltage exceeds the threshold voltage of the Si MOSFET, the device conducts forward; and once the Si MOSFET conducts in reverse, the device operates in reverse conducting mode.

[0004] Currently, traditional depletion-mode GaN chips are typically large in area and have a single-sided electrode structure, with all electrodes located on the front side and the back side being an insulating structure. They lack double-sided conductivity and cannot be directly connected to circuits by stacking them on other chips. Therefore, the Cascode structure primarily involves a MOS chip 4 connected in series with the GaN chip 5 via a substrate 3 (e.g., ...). Figure 1 As shown), such a structure requires the use of... Figure 1 The substrate 3 (substrate chip) shown serves as the medium, and a wire bonding process is required, i.e., multiple leads 6 are used to complete the interconnection between chips. The product manufacturing process is relatively complex, involves many steps, and has a high cost.

[0005] Another type of Cascode GaN device, as disclosed in Chinese patent application CN111430335B, involves stacking a MOS chip on the surface of a GaN chip to form a series connection. However, this structure requires the GaN chip to be large enough, and its surface electrode area must also be large enough to accommodate the MOS chip, which is not conducive to product cost control and device miniaturization.

[0006] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0007] The purpose of this invention is to provide a cascode GaN device and its fabrication method, which can reduce the size of the cascode GaN device, simplify the manufacturing process, reduce product cost, and improve its electrical performance.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A common-source, common-gate GaN device includes a leadframe base island, a MOS chip, and a GaN chip; A first conductive region is provided on the lead frame base island, and the first conductive region is configured as the source of the GaN device. The source of the MOS chip is disposed on its back side, and the gate and drain of the MOS chip are disposed on its front side; the MOS chip is disposed in the first conductive region, and the source on its back side is electrically connected to the first conductive region. The GaN chip is stacked on the MOS chip, and the GaN chip is electrically connected to the MOS chip in the following manner: The source, gate, and drain of the GaN chip are disposed on its front side, and a second conductive region is disposed on the back side of the GaN chip. The second conductive region is electrically connected to the source on the front side of the GaN chip, and the second conductive region on the back side of the GaN chip is electrically connected to the drain on the front side of the MOS chip. or, The MOS chip also has its source on its front side, the GaN chip has its drain on its front side, and the GaN chip has its source and gate on its back side. The source on the back side of the GaN chip is electrically connected to the drain on the front side of the MOS chip, and the gate on the back side of the GaN chip is electrically connected to the source on the front side of the MOS chip.

[0009] Furthermore, following any or a combination of the aforementioned technical solutions, the source, gate, and drain of the GaN chip are disposed on its front side, and a second conductive region is disposed on the back side of the GaN chip. The second conductive region is electrically connected to the source of the GaN chip on its front side through a via, and a conductive layer is disposed on the inner wall of the via. The second conductive area on the back of the GaN chip is bonded and electrically connected to the drain of the MOS chip via conductive adhesive.

[0010] Furthermore, following any or a combination of the aforementioned technical solutions, the GaN chip further includes an insulating substrate, on which the through-hole is provided, and a metal layer is simultaneously grown on the front side of the insulating substrate, the inner wall of the through-hole, and the back side of the insulating substrate to obtain the source electrode and the second conductive region of the GaN chip that are electrically connected.

[0011] Furthermore, following any or a combination of the aforementioned technical solutions, the source electrode on the back of the MOS chip is electrically connected to the first conductive region of the lead frame base island by welding or by means of conductive adhesive. The gate of the MOS chip is electrically connected to the gate of the GaN device via bonding leads. The drain of the GaN chip is electrically connected to the drain of the GaN device via bonding leads. The gate of the GaN chip is electrically connected to the first conductive region via a bonding wire.

[0012] Furthermore, as described above, or in combination of any one or more of the aforementioned technical solutions, the drain area of ​​the MOS chip is larger than the area of ​​the GaN chip; and / or, The GaN chip has a metal layer covering its entire back surface, and the metal layer is configured as the second conductive region.

[0013] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, the MOS chip also has its source on the front side, the source of the GaN chip is disposed above the drain of the MOS chip, and the gate of the GaN chip is disposed above the source of the MOS chip. The source of the GaN chip and the drain of the MOS chip, as well as the gate of the GaN chip and the source of the MOS chip, are synchronously welded together via eutectic bonding.

[0014] Furthermore, following any or a combination of the aforementioned technical solutions, the source electrode on the back of the MOS chip is electrically connected to the first conductive region of the lead frame base island by welding or by means of conductive adhesive. The gate of the MOS chip is electrically connected to the gate of the GaN device via bonding leads. The drain of the GaN chip is electrically connected to the drain of the GaN device via bonding leads.

[0015] Furthermore, following any one or a combination of the aforementioned technical solutions, the source and drain of the GaN chip are arranged adjacent to each other, the source and drain of the MOS chip are arranged adjacent to each other, and the gate on the front side of the MOS chip is arranged on the side away from its drain.

[0016] Furthermore, based on any or a combination of the aforementioned technical solutions, the minimum distance between the source and drain of the GaN chip is not less than 100 μm.

[0017] Furthermore, following any one or a combination of the aforementioned technical solutions, the lead frame base island is configured as an independent base island, and the lead frame base island is separated from the gate and drain of the GaN device.

[0018] Furthermore, following any or a combination of the aforementioned technical solutions, the lead frame base island, the MOS chip, and the GaN chip are encapsulated in EMC resin.

[0019] According to another aspect of the present invention, a method for fabricating a cascode GaN device is provided, comprising the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on its back side, and the gate and drain of the MOS chip are located on its front side. The source, gate and drain of the GaN chip are located on its front side, and the source of the GaN chip is also located on its back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, and the source on the back of the GaN chip is electrically connected to the drain on the front of the MOS chip through conductive adhesive. GaN device semi-finished product is obtained by electrically connecting other electrodes through bonding wires, including: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires, and electrically connecting the gate of the GaN chip to the source of the GaN device on the front side of the lead frame base island through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

[0020] According to another aspect of the present invention, a method for fabricating a cascode GaN device is provided, comprising the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on both the front and back sides. The gate and drain of the MOS chip are located on the front side. The drain of the GaN chip is located on the front side and the source and gate are located on the back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, with the source of the GaN chip disposed above the drain of the MOS chip and the gate of the GaN chip disposed above the source of the MOS chip. The source of the GaN chip and the drain of the MOS chip, as well as the gate of the GaN chip and the source of the MOS chip, are simultaneously welded using eutectic bonding. To obtain a GaN device semi-finished product by electrically connecting other electrodes through bonding wires, the method includes: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, and electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

[0021] The beneficial effects of the technical solution provided by this invention are as follows: a. The first cascode GaN device provided by this invention combines the source setting technology of LV MOS backplane and the technology of connecting the source on the front side of GaN to its back side through through-hole. It uses GaN chip stacked on MOS chip, and the source on the back side of MOS chip is electrically connected to the first conductive area on the front surface of the lead frame base island. This realizes that only the drain and gate of GaN chip and the gate of MOS chip need three bonding leads, and saves a substrate. It reduces the size of Cascode GaN device, simplifies the manufacturing process of Cascode GaN device, reduces product cost and improves its electrical performance. b. The second type of cascode GaN device provided by the present invention has its source on both the front and back sides of the MOS chip, its gate and source on the back side of the GaN chip, and only its drain on the front side. The GaN chip is stacked on the MOS chip, and a eutectic bonding process is used to interconnect the gate of the GaN chip with the source of the MOS chip, and the source of the GaN chip with the drain of the MOS chip. In the end, only the drain of the GaN chip and the gate of the MOS chip need to be electrically connected to the drain and gate of the GaN device through bonding wires, which further reduces the number of wires and also saves a substrate. This achieves the reduction of the size of the Cascode GaN device, simplifies the manufacturing process of the Cascode GaN device, reduces product cost, and obtains GaN devices with better electrical performance. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a common-source, common-gate GaN device in the prior art; Figure 2 A schematic diagram of the structure of a first type of MOS chip provided as an exemplary embodiment of the present invention; Figure 3 A top-view perspective schematic diagram of a first GaN chip provided as an exemplary embodiment of the present invention; Figure 4 A perspective view of a three-dimensional structure of a first GaN chip provided as an exemplary embodiment of the present invention; Figure 5 A schematic diagram of the structure of a first GaN device provided as an exemplary embodiment of the present invention; Figure 6 A schematic diagram of the structure of a second MOS chip provided as an exemplary embodiment of the present invention; Figure 7 A side view schematic diagram of a second GaN chip provided as an exemplary embodiment of the present invention; Figure 8 A top view schematic diagram of a second GaN chip provided as an exemplary embodiment of the present invention; Figure 9 A schematic diagram of the structure of a second GaN device provided as an exemplary embodiment of the present invention; Figure 10 A cross-sectional schematic diagram of a first GaN chip provided as an exemplary embodiment of the present invention.

[0024] The reference numerals in the accompanying drawings include: 1-lead frame base island, 11-first conductive region, 2-conductive adhesive, 3-substrate, 4-MOS chip, 5-GaN chip, 51-second conductive region, 52-through hole, 6-lead, 61-first bonding lead, 62-second bonding lead, 63-third bonding lead, 64-fourth bonding lead, 65-fifth bonding lead, 71-gate of GaN device, 72-drain of GaN device, S-source, D-drain, G-gate. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0027] To address the shortcomings of existing technologies, this invention aims to establish, for the first time, a GaN stacked on an LV MOS (Low Voltage Metal-Oxide-Semiconductor Field-Effect Transistor) using technologies such as GaN Die, MOS Die, lead frame base island, high-precision surface mounting, thermo-ultrasonic bonding, and molding, thereby completing the electrical characteristics of a Cascode GaN power device. This will achieve a reduction in the size of the Cascode GaN device while simplifying its manufacturing process, lowering product costs, and improving its electrical performance.

[0028] In one embodiment of the present invention, a common-source, common-gate GaN device is provided, such as... Figures 2 to 5 As shown, it includes a lead frame base island 1, a MOS chip 4, and a GaN chip 5.

[0029] like Figure 2 As shown, the source of the MOS chip 4 is disposed on its back side, and the gate and drain of the MOS chip 4 are disposed on its front side.

[0030] like Figure 3 and Figure 4As shown, the source, gate, and drain of the GaN chip 5 are disposed on its front side, and a second conductive region 51 is disposed on the back side of the GaN chip 5. The second conductive region 51 is electrically connected to the source on the front side of the GaN chip 5.

[0031] like Figure 5 As shown, the lead frame base island 1 and the gate 71 and drain 72 of the GaN device are separately disposed. A first conductive region 11 is disposed on the upper surface, i.e. the front surface, of the lead frame base island 1. The first conductive region 11 is configured as the source of the GaN device.

[0032] The MOS chip 4 is disposed on the lead frame base island 1. The back side of the MOS chip 4 is attached to the first conductive region 11, and the source electrode on its back side is electrically connected to the first conductive region 11. Specifically, the source electrode on the back side of the MOS chip 4 is electrically connected to the first conductive region 11 on the lead frame base island 1 by soldering or by means of conductive adhesive.

[0033] The GaN chip 5 is stacked on the MOS chip 4, and the second conductive region 51 on the back of the GaN chip 5 is electrically connected to the drain on the front of the MOS chip 4.

[0034] Preferably, the GaN chip 5 provided in this embodiment uses sapphire as an insulating substrate, and the through-hole 52 is formed on the insulating substrate. An integral metal layer is simultaneously grown on the front side of the insulating substrate, the inner wall of the through-hole 52, and the back side of the insulating substrate, thus achieving that the source electrode is provided on both the front and back sides of the GaN chip 5. Figure 10 As shown.

[0035] The second conductive region 51 on the back side of the GaN chip 5 is bonded and electrically connected to the drain of the MOS chip 4 via conductive adhesive. Preferably, the drain area of ​​the MOS chip 4 is larger than the area of ​​the GaN chip 5, that is, the GaN chip 5 is disposed in the drain region on the front side of the MOS chip 4. More preferably, the back side of the GaN chip 5 is fully covered by a metal layer, which is configured as the second conductive region 51. This enables a reliable connection between the source of the GaN chip 5 and the drain of the MOS chip 4.

[0036] In this embodiment, the gate of the MOS chip 4 is electrically connected to the gate of the GaN device via bonding leads; the drain of the GaN chip 5 is electrically connected to the drain of the GaN device via bonding leads; and the gate of the GaN chip 5 is electrically connected to the first conductive region 11 via bonding leads.

[0037] The lead frame base island 1, MOS chip 4 and GaN chip 5 are encapsulated in EMC resin. Figures 1 to 10In this context, S represents the source of the device / chip, D represents the drain of the device / chip, and G represents the gate of the device / chip.

[0038] The cascode GaN device provided in this embodiment combines LVMOS backplane S-electrode technology and GaN-S-electrode vias to connect the S-terminal to the backplane. It uses high-voltage GaN stacked on top of the LVMOS for packaging. The LVMOS has an S-electrode on its lower surface, meaning the MOS S-terminal does not require wire bonding. The upper surface has D and G electrodes, with the D-electrode having a large area. The high-voltage GaN is attached to the D region of the LVMOS, and the GaN uses vias to connect the S-electrode to its backplane. Therefore, the connection between GaN S and MOS D is achieved through surface mounting. Ultimately, only three bonding leads are needed for GaN D, GaN G, and MOS G, saving one substrate. This reduces the size of the Cascode GaN device while simplifying its manufacturing process, lowering product costs, and improving its electrical performance.

[0039] The common-source, common-gate GaN device provided in this embodiment is fabricated using the following steps.

[0040] The design incorporates MOS and GaN chips. The source of the MOS chip is located on its back side, while the gate and drain are located on its front side. The source, gate, and drain of the GaN chip are located on its front side, and the source is also located on its back side. The source on the front and back sides of the GaN chip are electrically connected through vias with metal layers on their inner walls.

[0041] The design separates the leadframe base island and the gate and drain of the GaN device. The source of the GaN device is located on the front side of the leadframe base island. The leadframe base island and the gate and drain of the GaN device are not directly connected; instead, they are connected via a wire bonding process (WB). The source of the GaN device is located in the first conductive region on the front side of the leadframe base island. The pins 1 / 2 / 3 correspond to the gate (G), drain (D), and source (S), respectively, or alternatively, they can correspond to the gate (G), source (S), and drain (D). Figure 5 The positions of the gate 71 and the drain 72 of the GaN device can be interchanged.

[0042] The MOS chip and conductive adhesive 2 are bonded to the lead frame base island using a high-precision bonding device. The source of the LVMOS of this invention is directly soldered to the first conductive region of the lead frame base island to form the source of the GaN device, replacing the traditional wire bonding. This almost eliminates parasitic parameters generated by interconnection, reduces the key parameter Ron (on-resistance) of the product, increases the current performance of the product, and improves the electrical performance of the product.

[0043] The GaN chip's back substrate and conductive adhesive are bonded to the front D electrode area of ​​the LVMOS using a high-precision die bonding device, achieving the welding interconnection between the GaN chip's S electrode and the LVMOS's D electrode. Similarly, by welding the GaN chip's source and the LVMOS's front drain, the traditional wire bonding is replaced, almost eliminating parasitic parameters generated by the interconnection, reducing the critical parameter Ron, and saving on substrate chips.

[0044] After the adhesive used to bond the lead frame base island, MOS chip, and GaN chip to the die has cured, the product to be bonded to the WB is cleaned with Plasma.

[0045] The cleaned WB product is wire-bonded to obtain a GaN device semi-finished product, including: electrically connecting the gate of the GaN chip to the source of the GaN device on the front side of the lead frame base island through a first bonding wire 61; electrically connecting the gate of the MOS chip to the gate of the GaN device through a second bonding wire 62; and electrically connecting the drain of the GaN chip to the drain of the GaN device through a third bonding wire 63.

[0046] The GaN device semi-finished products (dies, wires, lead frame base islands, etc.) are encapsulated with EMC resin through molding process to obtain the encapsulated product, thereby realizing the electrical and heat dissipation functions of the device.

[0047] The packaged product undergoes electroplating and cutting to remove excess parts such as the lead frame base island and pin fixing ribs, thus separating individual GaN devices. Finally, the individual GaN devices are subjected to electrical performance testing to eliminate defective products, obtaining GaN power devices that meet both electrical performance and appearance standards.

[0048] In another embodiment of the present invention, a common-source, common-gate GaN device is provided, such as... Figures 6 to 9 As shown, it includes a lead frame base island 1, a MOS chip 4, and a GaN chip 5.

[0049] like Figure 5 As shown, the lead frame base island 1 and the gate 71 and drain 72 of the GaN device are separately disposed. A first conductive region 11 is disposed on the upper surface, i.e. the front surface, of the lead frame base island 1. The first conductive region 11 is configured as the source of the GaN device.

[0050] like Figure 8 As shown, the MOS chip 4 has its source electrode on both its front and back sides, and its gate and drain electrodes are located on its front side. In this invention, the front and back sides are opposite to each other. In the accompanying drawings, the front side is the visible surface of the device / chip, and the back side is the invisible surface of the device / chip.

[0051] like Figure 6 and Figure 7 As shown, in this embodiment, the drain of the GaN chip 5 is disposed on its front side, and the source and gate of the GaN chip 5 are disposed on its back side.

[0052] The MOS chip 4 is disposed on the lead frame base island 1. The back side of the MOS chip 4 is attached to the first conductive region 11, and the source electrode on its back side is electrically connected to the first conductive region 11. Specifically, the source electrode on the back side of the MOS chip 4 is electrically connected to the first conductive region 11 on the lead frame base island 1 by soldering or by means of conductive adhesive.

[0053] The GaN chip 5 is stacked on the MOS chip 4, with the source of the GaN chip 5 positioned above the drain of the MOS chip 4, and the gate of the GaN chip 5 positioned above the source of the MOS chip 4. The source and drain of the GaN chip 5, and the gate and source of the MOS chip 4, are simultaneously bonded together via eutectic bonding. Preferably, the minimum distance between the source and drain of the GaN chip is not less than 100 μm to ensure insulation between the different electrodes.

[0054] The gate of the MOS chip 4 is electrically connected to the gate of the GaN device via bonding leads; the drain of the GaN chip 5 is electrically connected to the drain of the GaN device via bonding leads. Preferably, the source and drain of the GaN chip 5 are arranged adjacent to each other, and the source and drain of the MOS chip 4 are arranged adjacent to each other. The gate on the front side of the MOS chip is located on the side away from its drain, which makes it less likely for the leads to intersect during wiring.

[0055] The lead frame base island 1, MOS chip 4 and GaN chip 5 are encapsulated in EMC resin.

[0056] The cascode GaN device provided in this embodiment combines LV MOS backplane and front surface S-electrode technology (dual S-electrode), a partial G-electrode on the back of GaN and no G-electrode on the front, and a eutectic bonding process between the MOS chip and the GaN chip. This achieves interconnection between the GaN G-electrode and the MOS S-electrode, and between the GaN S-electrode and the MOS D-electrode, resulting in only two sets of wire bonding: GaN D and MOS G. Compared to the previous embodiment, this further reduces wire bonding and also saves one substrate (substrate chip). This achieves a reduction in the size of the Cascode GaN device while simplifying the manufacturing process, reducing product costs, and obtaining GaN devices with superior electrical performance.

[0057] The common-source, common-gate GaN device provided in this embodiment is fabricated using the following steps.

[0058] The design incorporates MOS and GaN chips. The MOS chip has its source on both the front and back sides, and its gate and drain on the front side. The GaN chip has its drain on the front side, and its source and gate on the back side. Preferably, the back side of the MOS chip is entirely covered by a metal layer, serving as its source. A portion of the front side of the MOS chip has its source, adjacent to its drain. The GaN chip has its gate in a portion of its back side and its source in another portion. The GaN chip does not have a drain on its back side; instead, its drain is either located in a portion of the front side or its drain is entirely covered on the front side.

[0059] The design separates the leadframe base island and the gate and drain of the GaN device. The source of the GaN device is located on the front side of the leadframe base island. The leadframe base island and the gate and drain of the GaN device are not directly connected; instead, they are connected via a wire bonding process (WB). The source of the GaN device is located in the first conductive region on the front side of the leadframe base island. The pins of the GaN device, pins 1 / 2 / 3, correspond to either G (gate), D (drain), or S (source), i.e., G (gate), S (source), or D (drain). Figure 5 The positions of the gate 71 and the drain 72 of the GaN device can be interchanged.

[0060] The MOS chip and conductive adhesive 2 are bonded to the lead frame base island using a high-precision bonding device. The source of the LVMOS of this invention is directly soldered to the first conductive region of the lead frame base island to form the source of the GaN device, replacing the traditional wire bonding. This almost eliminates parasitic parameters generated by interconnection, reduces the key parameter Ron (on-resistance) of the product, increases the current performance of the product, and improves the electrical performance of the product.

[0061] The GaN chip is attached to the MOS chip using a high-precision die-attachment device. The source of the GaN chip is positioned above the drain of the MOS chip, and the gate of the GaN chip is positioned above the source of the MOS chip. Eutectic bonding is used to simultaneously weld the source and drain of the GaN chip, as well as the gate and source of the MOS chip. This invention uses eutectic bonding technology to interconnect the G electrode of GaN with the S electrode of MOS, replacing traditional wire bonding, and to interconnect the S electrode of GaN with the D electrode of MOS, replacing traditional wire bonding. This reduces the Ron parameter of the product and improves its electrical performance.

[0062] After the adhesive used to bond / weld the chip dies, which connect the lead frame base island, MOS chip, and GaN chip in sequence, has cured, the product to be welded is cleaned with Plasma.

[0063] The cleaned WB product is bonded with wires to obtain a GaN device semi-finished product, including: electrically connecting the gate of the MOS chip to the gate of the GaN device through the fourth bonding wire 64, and electrically connecting the drain of the GaN chip to the drain of the GaN device through the fifth bonding wire 65.

[0064] The GaN device semi-finished products (dies, wires, lead frame base islands, etc.) are encapsulated with EMC resin through molding process to obtain the encapsulated product, thereby realizing the electrical and heat dissipation functions of the device.

[0065] The packaged product undergoes electroplating and cutting to remove excess parts such as the lead frame base island and pin fixing ribs, thus separating individual GaN devices. Finally, the individual GaN devices are subjected to electrical performance testing to eliminate defective products, obtaining GaN power devices that meet both electrical performance and appearance standards.

[0066] It should be noted that the above-described embodiments of the common-source cascode GaN device fabrication method and their corresponding common-source cascode GaN device embodiments belong to the same inventive concept. All contents of the common-source cascode GaN device embodiments are incorporated into the corresponding common-source cascode GaN device fabrication embodiments by reference.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0068] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A cascode GaN device, characterized in that, It includes a lead frame base island (1), a MOS chip (4), and a GaN chip (5). A first conductive region (11) is provided on the lead frame base island (1), and the first conductive region (11) is configured as the source of the GaN device; The source of the MOS chip (4) is disposed on its back side, and the gate and drain of the MOS chip (4) are disposed on its front side; the MOS chip (4) is disposed in the first conductive region (11), and the source on its back side is electrically connected to the first conductive region (11); The GaN chip (5) is stacked on the MOS chip (4), and the GaN chip (5) is electrically connected to the MOS chip (4) in the following manner: The source, gate and drain of the GaN chip (5) are disposed on its front side, and a second conductive region (51) is disposed on the back side of the GaN chip (5). The second conductive region (51) is electrically connected to the source on the front side of the GaN chip (5), and the second conductive region (51) on the back side of the GaN chip (5) is electrically connected to the drain on the front side of the MOS chip (4). or, The MOS chip (4) also has its source on the front side, the drain of the GaN chip (5) is located on its front side, and the source and gate of the GaN chip (5) are located on its back side. The source on the back side of the GaN chip (5) is electrically connected to the drain on the front side of the MOS chip (4), and the gate on the back side of the GaN chip (5) is electrically connected to the source on the front side of the MOS chip (4).

2. The cascode GaN device according to claim 1, characterized in that, The source, gate and drain of the GaN chip (5) are disposed on its front side, and a second conductive region (51) is disposed on the back side of the GaN chip (5). The second conductive region (51) is electrically connected to the source of the GaN chip (5) on the front side through a through hole (52). A conductive layer is disposed on the inner wall of the through hole (52). The second conductive area (51) on the back of the GaN chip (5) is bonded and electrically connected to the drain of the MOS chip (4) by conductive adhesive.

3. The cascode GaN device according to claim 2, characterized in that, The GaN chip (5) also includes an insulating substrate, on which the through hole (52) is provided. Metal layers are grown simultaneously on the front side of the insulating substrate, the inner wall of the through hole (52) and the back side of the insulating substrate to form the source electrode and the second conductive region (51) of the GaN chip (5) that are electrically connected.

4. The cascode GaN device according to claim 2, characterized in that, The source electrode on the back of the MOS chip (4) is electrically connected to the first conductive region (11) on the lead frame base island (1) by welding or by conductive adhesive. The gate of the MOS chip (4) is electrically connected to the gate of the GaN device through bonding leads; The drain of the GaN chip (5) is electrically connected to the drain of the GaN device through bonding leads; The gate of the GaN chip (5) is electrically connected to the first conductive region (11) via a bonding wire.

5. The cascode GaN device according to claim 1, characterized in that, The drain area of ​​the MOS chip (4) is larger than the area of ​​the GaN chip (5); and / or, The back of the GaN chip (5) is fully covered by a metal layer, which is configured as the second conductive region (51).

6. The cascode GaN device according to claim 1, characterized in that, The MOS chip (4) also has its source on the front side, the source of the GaN chip (5) is disposed above the drain of the MOS chip (4), and the gate of the GaN chip (5) is disposed above the source of the MOS chip (4). The source of the GaN chip (5) and the drain of the MOS chip (4), as well as the gate of the GaN chip (5) and the source of the MOS chip (4), are synchronously welded together by eutectic bonding.

7. The cascode GaN device according to claim 6, characterized in that, The source of the MOS chip (4) on the back side is electrically connected to the first conductive region (11) on the lead frame base island (1) by welding or by conductive adhesive; the gate of the MOS chip (4) is electrically connected to the gate of the GaN device by bonding wire; the drain of the GaN chip (5) is electrically connected to the drain of the GaN device by bonding wire.

8. The cascode GaN device according to claim 6, characterized in that, The source and drain of the GaN chip (5) are arranged adjacent to each other, the source and drain of the MOS chip (4) are arranged adjacent to each other, and the gate on the front side of the MOS chip (4) is arranged on the side away from its drain; and / or, The minimum distance between the source and drain of the GaN chip (5) is not less than 100 μm.

9. The cascode GaN device according to claim 1, characterized in that, The leadframe base island (1) is configured as an independent base island, and the leadframe base island (1) is separated from the gate and drain of the GaN device; and / or, The lead frame base island (1), MOS chip (4) and GaN chip (5) are encapsulated in EMC resin.

10. A method for fabricating a cascode GaN device, characterized in that, Includes the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on its back side, and the gate and drain of the MOS chip are located on its front side. The source, gate and drain of the GaN chip are located on its front side, and the source of the GaN chip is also located on its back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, and the source on the back of the GaN chip is electrically connected to the drain on the front of the MOS chip through conductive adhesive. GaN device semi-finished product is obtained by electrically connecting other electrodes through bonding wires, including: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires, and electrically connecting the gate of the GaN chip to the source of the GaN device on the front side of the lead frame base island through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

11. A method for fabricating a cascode GaN device, characterized in that, Includes the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on both the front and back sides. The gate and drain of the MOS chip are located on the front side. The drain of the GaN chip is located on the front side and the source and gate are located on the back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, with the source of the GaN chip disposed above the drain of the MOS chip and the gate of the GaN chip disposed above the source of the MOS chip. The source of the GaN chip and the drain of the MOS chip, as well as the gate of the GaN chip and the source of the MOS chip, are simultaneously welded using eutectic bonding. To obtain a GaN device semi-finished product by electrically connecting other electrodes through bonding wires, the method includes: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, and electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

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