Manufacturing method of CMOS (Complementary Metal Oxide Semiconductor) device

Abstract

The invention relates to a manufacturing method of a CMOS (Complementary Metal Oxide Semiconductor) device, which optimizes the manufacturing process of a tensile stress film and a compressive stress film and ensures that an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) can adopt a stress technology at the same time. The stress films (the tensile stress film and the pressure stress film) corresponding to the NMOS area and the PMOS area are subjected to ultraviolet curing treatment, H in the films is removed, the H is prevented from entering the device during subsequent annealing, the short-channel effect is weakened, the negative bias temperature instability is relieved, the device performance is improved, and the reliability of the device during working is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a method for fabricating a CMOS device. Background Technology

[0002] In the continuous development of semiconductor manufacturing technology, stress memory technology (SMT) has become an effective means to improve the performance of complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs). With the advancement of Moore's Law, the number of transistors per unit area and transistor performance are increasingly affected by miniaturization effects. Between generations, the growth in the number of transistors and the improvement in performance both show a slowing trend. Stress memory technology is a crucial method in strained silicon technology for catching up with Moore's Law.

[0003] In stress memory technology, HDP deposition is primarily used to form tensile stress films on top of NMOS transistors and compressive stress films on top of PMOS transistors, followed by annealing to ensure tensile stress is stored in the NMOS channel and compressive stress in the PMOS channel. However, when using chemical vapor deposition (CVD) to prepare the films, the source gas is a mixture of silane (SiH4) and ammonia (NH3), resulting in a large amount of hydrogen (H) in the deposited films. After annealing, this large amount of H diffuses into the device. This H diffuses into the source and drain regions of the device, causing boron doping in the PMOS source and drain regions to diffuse into the channel region, exacerbating the short-channel effect. Furthermore, it combines with Si dangling bonds at the silicon / oxygen interface to form Si-H bonds. When the device is in operation, the gate generates a high electric field, which easily breaks Si-H bonds, causing Si dangling bonds to appear. These dangling bonds attract charges, transforming into positively charged interface traps. Furthermore, the number of such interface traps increases with the increase of gate bias voltage and temperature, enhancing the negative bias temperature instability (NBTI) effect and further adversely affecting the performance and reliability of the device.

[0004] It is evident that traditional methods involve complex processes and repeated surface treatments of materials without considering the protection of the reliability of NMOS and PMOS devices, resulting in relatively poor performance and reliability of the obtained CMOS devices. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for fabricating CMOS devices to address the aforementioned problems. By adding a UV curing step, device performance can be improved and the reliability of the device during operation can be ensured.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for fabricating a CMOS device, comprising:

[0008] A semiconductor substrate is provided, wherein an NMOS region and a PMOS region are disposed on the semiconductor substrate, and a gate is disposed corresponding to the NMOS region and the PMOS region and source / drain ion implantation has been completed;

[0009] An etching barrier layer is deposited on the semiconductor substrate;

[0010] A tensile stress film is deposited on the surface of the etching barrier layer, and the tensile stress film is subjected to a first ultraviolet curing treatment.

[0011] Remove the tensile stress film from the PMOS region;

[0012] A compressive stress film is deposited on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region, and the compressive stress film is subjected to a second ultraviolet curing treatment.

[0013] Remove the compressive stress film from the surface of the tensile stress film in the NMOS region;

[0014] The tensile stress film and the compressive stress film are subjected to rapid annealing.

[0015] One embodiment of the process of depositing a tensile stress film on the surface of the etch barrier layer includes:

[0016] Tensile stress films were deposited on the surface of the etching barrier layer using a PECVD process.

[0017] One embodiment of the process of depositing a tensile stress film on the surface of the etch barrier layer includes:

[0018] A high-tensile-stress film is deposited n times on the surface of the etching barrier layer using the PECVD process. Each high-tensile-stress film is subjected to plasma nitriding treatment, and a low-tensile-stress film is deposited on the surface of the nth high-tensile-stress film to form the tensile-stress film, where n≥1.

[0019] In one embodiment, the first ultraviolet curing process includes:

[0020] The semiconductor substrate with the tensile stress film deposited is placed in the cavity;

[0021] The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0022] The tensile stress film was cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

[0023] In one embodiment, the first ultraviolet curing process includes:

[0024] The semiconductor substrate with the tensile stress film deposited is placed in the cavity;

[0025] The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0026] The tensile stress film was cured three times using ultraviolet light with a wavelength of 365nm-400nm, with each curing interval of 8-12 minutes. The intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 Each curing time is 32s-80s;

[0027] Nitrogen annealing was performed for 25-35 minutes at a temperature range of 380℃-420℃.

[0028] One embodiment of the process of depositing a compressive stress film on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region includes:

[0029] The compressive stress film is deposited using HDP-CVD or SACVD processes, and then subjected to nitrogen annealing.

[0030] In one embodiment, the second ultraviolet curing process includes:

[0031] The semiconductor substrate with the deposited compressive stress film is placed in the cavity;

[0032] The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0033] The compressive stress film is cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light is 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

[0034] In one embodiment, the second ultraviolet curing process includes:

[0035] The semiconductor substrate with the deposited compressive stress film is placed in the cavity;

[0036] The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0037] The compressive stress film is cured three times using ultraviolet light with a wavelength of 365nm-400nm, wherein...

[0038] The first curing step uses 150mW / cm 2 -180mW / cm 2 Cured by high-intensity ultraviolet light, curing time 30s-50s;

[0039] After naturally cooling to 180℃-220℃, use 180mW / cm 2 -220mW / cm 2 A second curing process is performed using ultraviolet light with high intensity, with a curing time of 20-40 seconds.

[0040] After naturally cooling to room temperature, use 220mW / cm 2 -250mW / cm 2 A third curing process is performed using ultraviolet light with high intensity, with a curing time of 20-30 seconds.

[0041] Nitrogen annealing was performed at a temperature range of 340℃-360℃ for 18-22 minutes.

[0042] In one embodiment, the semiconductor substrate is <100> Crystal orientation.

[0043] In one embodiment, the tensile stress film and the compressive stress film are made of silicon nitride.

[0044] The CMOS device fabrication method disclosed in this invention involves ultraviolet curing of the stress films (tensile stress film and compressive stress film) corresponding to the NMOS and PMOS regions to remove hydrogen from the films. This method ensures that stress technology is used for both NMOS and PMOS while preventing hydrogen from entering the device during subsequent annealing. This reduces the short-channel effect, alleviates the temperature instability under negative bias, improves device performance, and ensures the reliability of the device during operation. Attached Figure Description

[0045] Figure 1 This is a flowchart of a CMOS device fabrication method provided in an embodiment of the present invention;

[0046] Figures 2-12 This is a schematic diagram of a CMOS device fabrication process provided in an embodiment of the present invention.

[0047] In the figure, 201 is the isolation structure; 202 is the semiconductor substrate; 203 is the gate dielectric layer; 204 is the gate material layer; 205 is the spacer structure; 206 is the sidewall structure; 207 is the etch barrier layer; 208 is the tensile stress film; 209 is the photoresist; 210 is the compressive stress film; 211 is the source / drain region of the NMOS region; and 212 is the source / drain region of the PMOS region. Detailed Implementation

[0048] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0050] One embodiment of the present invention discloses a method for fabricating a CMOS device, such as... Figure 1 As shown, it includes:

[0051] A semiconductor substrate is provided, wherein an NMOS region and a PMOS region are disposed on the semiconductor substrate, and a gate is disposed corresponding to the NMOS region and the PMOS region and source / drain ion implantation has been completed;

[0052] An etching barrier layer is deposited on the semiconductor substrate;

[0053] A tensile stress film is deposited on the surface of the etching barrier layer, and the tensile stress film is subjected to a first ultraviolet curing treatment.

[0054] Remove the tensile stress film from the PMOS region;

[0055] A compressive stress film is deposited on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region, and the compressive stress film is subjected to a second ultraviolet curing treatment.

[0056] Remove the compressive stress film from the surface of the tensile stress film in the NMOS region;

[0057] The tensile stress film and the compressive stress film are subjected to rapid annealing.

[0058] The CMOS device fabrication method disclosed in this embodiment performs ultraviolet curing on the stress films (tensile stress film and compressive stress film) corresponding to the NMOS region and PMOS region respectively to remove H from the film. This can ensure that both NMOS and PMOS use stress technology at the same time, while preventing H from entering the device during subsequent annealing. This reduces the short channel effect, alleviates the temperature instability of negative bias, improves device performance, and ensures the reliability of the device during operation.

[0059] In another embodiment, the semiconductor substrate is <100> Crystal orientation substrate. <100> Crystal-oriented semiconductor substrates can effectively avoid the effects of tensile stress on PMOS devices through their isotropic thermal expansion coefficient, optimized thin film stress matching, and high strain transfer efficiency. At the same time, they can provide an ideal substrate environment for compressive stress films, significantly improving the hole mobility and device performance of PMOS.

[0060] In another embodiment, the tensile stress film and the compressive stress film are made of silicon nitride. Although the tensile stress film and the compressive stress film are made of the same material, their fabrication processes (gas ratio, temperature, plasma conditions, etc.) and stress modulation mechanisms (lattice mismatch, ion bombardment) are fundamentally different, ultimately leading to different functions in semiconductor devices. Specifically, the tensile stress film optimizes the electron mobility of NMOS, while the compressive stress film optimizes the hole mobility of PMOS or is used for structural strengthening. This differentiated stress modulation is also one of the core technologies of "strain engineering" in advanced CMOS processes.

[0061] In another embodiment, the process of depositing a tensile stress film on the surface of the etch barrier layer includes: depositing a tensile stress film on the surface of the etch barrier layer using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process.

[0062] Specifically, the process includes the following steps:

[0063] The semiconductor substrate is placed in the processing chamber, with the temperature controlled between 375℃ and 450℃ to avoid thermal damage to the underlying structure while ensuring reactivity and compatibility with most substrate requirements. The pressure in the processing chamber is maintained at 2 Torr-8 Torr to ensure stable plasma generation and uniform gas diffusion. Silane (SiH4) is used as the silicon source (flow rate 20 sccm-50 sccm), and ammonia (NH3) is used as the nitrogen source (flow rate 80 sccm-150 sccm), with their ratio controlled at 1:4-1:7 (adjusting the ratio stabilizes the stoichiometry of the tensile stress film, ensuring adequate nitrogen content to support tensile stress). Nitrogen (N2) is used as a dilution gas (flow rate 300 sccm-400 sccm) to optimize deposition uniformity. A combination of high and low frequency RF power is used: high frequency (13.56MHz, 150W-250W) is used to excite the plasma, and low frequency (400kHz, 80W-120W) controls the ion bombardment energy to enhance film densification, which is crucial for tensile stress formation. The stress value of the finally deposited tensile stress film is stable from 0 MPa to +1.5 GPa, and the thickness is 300 Å to 800 Å (which can be adjusted within this range according to device requirements, and the uniformity is controlled within ±5%), taking into account both process stability and equipment versatility.

[0064] In another embodiment, the process of depositing a tensile stress film on the surface of the etch barrier layer includes: depositing a high-tensile stress film n times on the surface of the etch barrier layer using a PECVD process, and performing plasma nitriding treatment on each deposited high-tensile stress film to increase the nitrogen content on the surface of the high-tensile stress film, making the surface of the high-tensile stress film more dense. Then, a low-tensile stress film is deposited on the surface of the nth high-tensile stress film to form the tensile stress film, where n ≥ 1. The tensile stress and hydrogen content of the low-tensile stress film are both lower than those of the high-tensile stress film.

[0065] Preferably, a high-tensile stress film is deposited three times on the surface of the etching barrier layer using a PECVD process.

[0066] It should be noted that the low-stress film refers to a tensile stress film with a low tensile stress value, which is also a type of tensile stress film.

[0067] In another embodiment, the first ultraviolet curing process includes:

[0068] The semiconductor substrate with the tensile stress film deposited is placed in the cavity;

[0069] The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0070] The tensile stress film was cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

[0071] This treatment can promote the breaking of hydrogen bonds and the recombination of Si-N bonds in the tensile stress film, effectively improving the film's density and stress stability.

[0072] In another embodiment, the first ultraviolet curing process includes:

[0073] The semiconductor substrate with the tensile stress film deposited is placed in the cavity;

[0074] The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0075] The tensile stress film was cured three times using ultraviolet light with a wavelength of 365nm-400nm, with each curing interval of 8-12 minutes. The intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

[0076] The process involves several steps. The first curing step breaks approximately 70% of the hydrogen bonds in the tensile stress film and re-forms Si-N bonds. During this interval, nitrogen purging (approximately 40 L / min) allows the semiconductor substrate to cool naturally to room temperature, eliminating localized stress concentrations. The second curing step further decomposes the remaining hydrogen bonds and strengthens the network structure. After cooling again, a third curing step is performed to form more stable Si-N bonds. After each curing cycle, a nitrogen purging process is conducted for 8-12 minutes (temperature maintained at 360℃-400℃). After three curing cycles, a nitrogen annealing treatment is performed for 25-35 minutes (temperature 380℃-420℃). This process reduces the hydrogen content of the tensile stress film from an initial 8% to below 1.2%, increases the absolute value of the tensile stress to 1.2 GPa-1.5 GPa, and controls the intra-wafer stress uniformity within ±3.5%, significantly improving the density and long-term stress stability of the tensile stress film.

[0077] Furthermore, the first UV curing process can be optimized for tensile stress films formed by n-stage deposition of high-tensile stress films, specifically including:

[0078] After each deposition of a high-stress film, UV curing is performed to make the surface of the high-stress film denser, but this is time-consuming and costly, and should be carefully considered. Alternatively, after completing n depositions of high-stress films and plasma nitriding, a single UV curing treatment can be performed before depositing a low-stress film. This ensures the overall curing effect of the high-stress film and allows for better integration with the low-stress film after deposition, accumulating higher stress. The final result may not be as good as the former, but the cost is lower.

[0079] In another embodiment, the process of depositing a compressive stress film on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region includes:

[0080] The compressive stress film is deposited using either HDP-CVD (High-Density Plasma Chemical Vapor Deposition) or SACVD (Sub-Atmospheric Chemical Vapor Deposition) processes, and then subjected to nitrogen annealing. The compressive stress film deposited using HDP-CVD typically exhibits better pore-filling capability than that produced by SACVD; therefore, this embodiment of the invention preferably uses a compressive stress film deposited using HDP-CVD. The specific steps include:

[0081] The semiconductor substrate is placed in the reaction chamber, and the temperature of the semiconductor substrate is controlled between 180℃ and 280℃. The pressure in the reaction chamber is maintained between 1.5Pa and 3.5Pa (11mTorr-26mTorr), which effectively balances plasma density and gas diffusion rate. Process gases are introduced in proportion: silane (SiH4, flow rate 25sccm-35sccm), ammonia (NH3, flow rate 120sccm-140sccm), and nitrogen (N2, flow rate 1200sccm-1400sccm) to form a SiH4:NH3 ratio of 1:4 to 1:5 (ensuring excess nitrogen atoms to promote the formation of nitrogen-rich silicon nitride structures, which is key to compressive stress generation). Nitrogen is used as a dilution gas to optimize plasma distribution uniformity. The RF power is set as follows: ICP power 1200W-1400W (2.45GHz) to excite high-density plasma, and bias power 80W-120W (373kHz-400kHz) to regulate ion bombardment energy (controlled within a moderate range to avoid excessive bombardment leading to stress reversal). The deposition time is adjusted according to the target thickness (e.g., approximately 3-4 minutes for 300nm deposition), resulting in a silicon nitride thin film (compressive stress film) with a compressive stress value of -1.0GPa to -1.3GPa, thickness uniformity <±4%, and intra-wafer stress consistency <±3%. Finally, the compressive stress film is subjected to nitrogen annealing (850±20℃, 25-35 minutes) to further eliminate internal molecular defects, stabilize the compressive stress state, and ensure long-term device reliability.

[0082] It should be noted that for the tensile stress film and the compressive stress film, it is necessary to balance the uniformity of the film. Methods include controlling the uniformity of gas flow during deposition, thermal annealing, and chemical mechanical polishing. Preferably, this invention ensures the uniformity of the film by controlling the uniformity of gas flow, thereby eliminating some steps and saving costs.

[0083] In another embodiment, the second ultraviolet curing process includes:

[0084] The semiconductor substrate with the deposited compressive stress film is placed in the cavity;

[0085] The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0086] The compressive stress film is cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light is 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

[0087] In another embodiment, the second ultraviolet curing process includes:

[0088] The semiconductor substrate with the deposited compressive stress film is placed in the cavity;

[0089] The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0090] The compressive stress film is cured three times using ultraviolet light with a wavelength of 365nm-400nm, wherein...

[0091] The first curing step uses 150mW / cm 2 -180mW / cm 2 UV curing with high intensity for 30-50 seconds promotes the breakage of surface hydrogen bonds and the initial recombination of Si-N bonds in the compressive stress film, increasing the absolute value of compressive stress by about 100 MPa.

[0092] After naturally cooling to 180℃-220℃ (approximately 5 minutes after the first curing), to avoid stress relaxation due to high temperature accumulation, then apply 180mW / cm². 2 -220mW / cm 2 A second curing process using intense ultraviolet light, with a curing time of 20-40 seconds, is performed to further stimulate the mid-layer bonding reconstruction of the compressive stress film, thereby further increasing the compressive stress by 150 MPa.

[0093] After naturally cooling to room temperature (approximately 8 minutes after the second curing), apply 220mW / cm². 2 -250mW / cm 2 A third curing process using intense ultraviolet light is performed for 20-30 seconds to enhance the stability of the overall network structure. After each curing, nitrogen purging (flow rate 30L / min) is maintained for 1 minute to form a gas "barrier" and prevent oxygen atoms from intruding.

[0094] Nitrogen annealing was performed at a temperature range of 340℃-360℃ for 18-22 minutes to eliminate local stress fluctuations.

[0095] The hydrogen content of the final compressive stress film can be reduced from more than 7% to less than 2%, the absolute value of compressive stress is stabilized at -1.2 to -1.5 GPa, the uniformity within the film is controlled within ±3%, and the long-term stability of stress (1000-hour test) decay rate is less than 5%.

[0096] As can be seen, the CMOS device fabrication method disclosed in this embodiment of the invention removes H from the stress film by performing ultraviolet curing treatment on the stress film corresponding to the NMOS and PMOS regions. This ensures that stress technology is used for both NMOS and PMOS while preventing H from entering the device during subsequent annealing. This reduces the short-channel effect, alleviates the temperature instability of negative bias, improves device performance, and ensures the reliability of the device during operation.

[0097] The CMOS device fabrication method disclosed in this invention will now be described through a specific embodiment.

[0098] like Figures 2-12 As shown, the method for fabricating the CMOS device includes:

[0099] Step S1: Provide a semiconductor substrate and form a gate structure and sidewalls on the semiconductor substrate.

[0100] like Figure 2 As shown, a semiconductor substrate 202 is provided. The semiconductor substrate 202 can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), etc. As an example, single-crystal silicon is selected to form the semiconductor substrate 202 in this embodiment. The substrate crystal orientation can be selected; in this embodiment, the substrate is selected... <100> Crystal orientation.

[0101] In the semiconductor substrate 202, an isolation structure 201 is formed by ion implantation. This shallow trench isolation (STI) structure separates the source and drain ion implantation regions of the NMOS device region and the PMOS device region, thus dividing the semiconductor substrate 202 into NMOS and PMOS regions. Various well structures (PMOS fabricated in N-wells and NMOS fabricated in P-wells) are also integrated within the semiconductor substrate 202; for simplicity, these are not shown.

[0102] A gate structure is constructed on a semiconductor substrate 202. As an example, this gate structure may include a gate dielectric layer 203 and a gate material layer 204 stacked sequentially from bottom to top. The gate dielectric layer 203 may be an oxide layer (such as a silicon dioxide layer), and the gate material layer 204 may be a polysilicon layer. Furthermore, as an example, spacer structures 205 and sidewall structures 206 adjacent to both sides of the gate structure are also formed on the semiconductor substrate 202. The spacer structure 205 may include at least one oxide layer and / or at least one nitride layer; the sidewall structure 206 includes at least one nitride layer.

[0103] Step S2: Complete source and drain ion implantation in the NMOS and PMOS regions through ion implantation.

[0104] like Figure 3As shown, lightly doped source / drain regions are formed in the semiconductor substrates 202 on both sides of the gate structure (the channel region between the source / drain regions is simplified and not shown in the diagram). The source / drain region 211 in the NMOS region is doped with n-type impurities, and the source / drain region 212 in the PMOS region is doped with p-type impurities.

[0105] Step S3: Deposit an etch barrier layer on the semiconductor substrate.

[0106] like Figure 4 As shown, an etch barrier layer 207 is grown on a semiconductor substrate 202 using a chemical vapor deposition process, covering the gate structure and simultaneously covering the P-well, N-well, and STI region. The etch barrier layer 207 can be made of silicon nitride, silicon oxynitride, or silicon oxide, and the deposition method for the etch barrier layer 207 can be CVD, LPCVD, or PECVD, with a thickness of 20Å-80Å (60Å in this embodiment).

[0107] Step S4: Deposit a tensile stress film (silicon nitride film).

[0108] like Figure 5 As shown, a tensile stress film 208 is deposited on the surface of the etch barrier layer 207. In this embodiment, the tensile stress film 208 is a silicon nitride film, which can improve the electron mobility of the NMOS device and enhance the device performance through lattice stress.

[0109] Specifically, the semiconductor substrate is placed in a processing chamber, with the substrate temperature controlled at 400°C and the chamber pressure maintained at 6 Torr. Silane (SiH4) is used as the silicon source (flow rate 30 sccm), and ammonia (NH3) is used as the nitrogen source (flow rate 120 sccm), with a ratio controlled at 1:4. Nitrogen (N2) is used as a dilution gas (flow rate 350 sccm) to optimize deposition uniformity. A combination of high and low frequency RF power is used: high frequency (13.56 MHz, 200 W) is used to excite the plasma, and low frequency (400 kHz, 100 W) is used to modulate the ion bombardment energy. The final deposited tensile stress film has a stable stress value of 1.2 GPa and a thickness of 600 Å.

[0110] Step S5: Perform the first ultraviolet curing treatment on the film.

[0111] like Figure 6 As shown, after the deposition of the 208 tensile stress film, it needs to be subjected to ultraviolet (UV) curing treatment to further optimize the film performance. UV curing treatment can promote the breaking of hydrogen bonds and the recombination of Si-N bonds in the film, effectively improving the film's density and stress stability.

[0112] It is important to note that the time and temperature during the UV curing process directly affect the stress value and are crucial to this invention. Insufficient light or inadequate irradiation time can lead to incomplete curing, leaving a large number of unreacted monomers in the material. Slow curing in the later stages will cause continuous shrinkage, accumulating stress and increasing the stress value. However, if the curing time is too long, the material will be over-cured, leading to excessive cross-linking of molecular chains, increased rigidity, decreased toughness, and weakened stress relaxation ability, which may also increase the stress value. Temperature also has a significant impact on stress: low temperatures reduce the curing speed, restrict the activity of molecular chain segments, and easily accumulate shrinkage stress, leading to an increase in stress value. High temperatures may accelerate oxygen inhibition polymerization; if the temperature exceeds the tolerance range of the photoinitiator or substrate, it may cause the initiator to decompose and fail, and the substrate to undergo thermal deformation, generating additional stress. Furthermore, increasing the temperature can accelerate solvent evaporation and moisture evaporation, accelerating the oxidation and thermochemical reactions of the stress film, thus speeding up the curing speed. However, at excessively high temperatures, the curing speed does not increase significantly; instead, it may cause the stress film to yellow or darken in color, and may also cause shrinkage deformation of the substrate, or even warping and cracking, thereby increasing the stress value. Therefore, in addition to adding the ultraviolet curing step, the setting of various parameters in the ultraviolet curing process is also very important and worthy of attention.

[0113] Specifically, the first UV curing treatment of the film includes:

[0114] The semiconductor substrate with the tensile stress film deposited is placed in the cavity;

[0115] The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0116] The tensile stress film was cured three times using ultraviolet light with a wavelength of 385 nm, with each curing cycle spaced 10 minutes apart. During the intervals, nitrogen purging (flow rate of approximately 40 L / min) was maintained, allowing the wafer to cool naturally to room temperature. The intensity of the ultraviolet light was 200 mW / cm². 2 The total energy density is 100 mJ / cm², and the curing time is 60 s. After each curing cycle, a 10-minute nitrogen purging process is performed (temperature maintained at 380℃). After three curing cycles, a 30-minute nitrogen annealing treatment (400℃) is performed. This process reduces the hydrogen content of the tensile stress film from the initial 8% to below 1.2%, increases the absolute value of the tensile stress to 1.2 GPa-1.5 GPa, and controls the stress uniformity within the film to within ±3.5%, significantly improving the density and long-term stress stability of the tensile stress film.

[0117] Step S6: Photoresist is applied to the surface of the tensile stress film 208, and the photoresist above the PMOS region is removed by development to expose the PMOS region.

[0118] Photoresist 209 is applied over the NMOS and PMOS regions, and then the photoresist 209 over the PMOS region is removed by a development process to expose the PMOS region (e.g., NMOS and PMOS regions). Figure 7 (As shown). This step lays the foundation for subsequent selective etching, ensuring differentiated processing between the NMOS and PMOS regions.

[0119] Positive photoresist (such as AZ4620) was used for coating, forming a 1.0μm-1.5μm thick layer by spin coating (3000rpm, 30s). This was followed by soft baking at 90℃-110℃ for 1-2 minutes to enhance film adhesion. An i-line (365nm) light source with an energy of 200mJ / cm²-300mJ / cm² was used for exposure to ensure sufficient exposure of the PMOS region. Development was performed using 0.26N TMAH developer at 23±1℃ for 60-90 seconds to completely dissolve and remove the photoresist in the PMOS region while preserving the photoresist in the NMOS region, providing a precise mask for subsequent etching processes.

[0120] Step S7: Etch the tensile stress film in the PMOS region.

[0121] like Figure 8 As shown, after photoresist patterning is completed, the tensile stress film 208 in the PMOS region needs to be selectively etched to expose the underlying PMOS device structure. This step requires precise control of the etching process parameters to ensure high selective etching of the silicon nitride film while avoiding damage to the underlying material.

[0122] Specifically, inductively coupled plasma (ICP) etching technology is employed, using a CHF3 / O2 mixed gas (flow ratio 9:1) as the etching gas source. Process parameters are set as follows: ICP power 200W-300W, RF bias power 50W-100W, chamber pressure 5mTorr-20mTorr, and wafer temperature 20℃-40℃. Under these conditions, silicon nitride exhibits an etching selectivity of 3:1 for photoresist and >100:1 for the underlying oxide, ensuring high directionality and precision in the etching process.

[0123] The etching endpoint was monitored in real time using optical emission spectroscopy (OES). The etching process was automatically terminated when a sharp drop in the intensity of the SiF4 characteristic peak (795 nm) was detected. After etching, N2 / O2 plasma was used to remove the resist (N2 50 sccm, O2 15 sccm, RF450W, 7 mTorr), followed by cleaning with 0.1% HF solution for 30 s to remove surface residues. The final etched morphology had a sidewall perpendicularity >88° and a surface roughness Ra <0.3 nm, providing a good interface for subsequent processes.

[0124] Step S8: Deposit a compressive stress film using HDP-CVD process.

[0125] like Figure 9 As shown, a compressive stress film 210 is deposited on the surface of the etch barrier layer 207 in the PMOS region and the surface of the tensile stress film 208 in the NMOS region using HDP-CVD process to optimize the performance of the PMOS device. This film, by introducing compressive stress, can significantly improve the hole mobility in the PMOS device.

[0126] Specifically, the semiconductor substrate is placed in the reaction chamber, with the substrate temperature controlled at 220°C and the chamber pressure maintained at 2.5 Pa. Process gases, silane (SiH4, flow rate 25 sccm), ammonia (NH3, flow rate 120 sccm), and nitrogen (N2, flow rate 1300 sccm), are introduced in a specific ratio to form a SiH4:NH3 ratio of 1:4. The radio frequency power is set as follows: ICP power 1300 W (2.45 GHz) to excite high-density plasma, and bias power 100 W (385 kHz) to regulate the ion bombardment energy (controlled within a moderate range to avoid excessive bombardment leading to stress reversal). The deposition time is approximately 4 minutes, yielding a silicon nitride thin film (compressive stress film) with a compressive stress value of -1.0 GPa to -1.3 GPa, thickness uniformity <±4%, and intra-wafer stress consistency <±3%. Finally, the compressive stress film is subjected to nitrogen annealing (850±20℃, 30min) to further eliminate molecular defects inside the film, stabilize the compressive stress state, and ensure the long-term reliability of the device.

[0127] Step S9: Perform ultraviolet curing treatment on the compressive stress film.

[0128] like Figure 10 As shown, after the compressive stress film 210 is deposited, it needs to be cured with ultraviolet light (UVcure) to further optimize the film performance and improve the device reliability.

[0129] The semiconductor substrate with the deposited compressive stress film is placed in the cavity;

[0130] The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%.

[0131] The compressive stress film is cured three times using ultraviolet light with a wavelength of 380 nm, wherein,

[0132] The first curing step uses 150mW / cm 2 Intensive ultraviolet light curing for 40 seconds promotes the breakage of surface hydrogen bonds and the initial recombination of Si-N bonds in the compressive stress film, increasing the absolute value of compressive stress by about 100 MPa.

[0133] After naturally cooling to 200℃ (5 minutes after the first curing), to avoid stress relaxation due to high temperature accumulation, then apply 200mW / cm². 2 A second curing process using intense ultraviolet light for 30 seconds was performed to further stimulate the mid-layer bonding reconstruction of the compressive stress film, thereby increasing the compressive stress by 150 MPa.

[0134] After naturally cooling to room temperature (8 minutes after the second curing), apply 250 mW / cm². 2 A third curing process using high-intensity ultraviolet light is performed for 24 seconds to enhance the overall stability of the network structure. After each curing process, nitrogen purging (flow rate 30 L / min) is maintained for 1 minute to prevent oxygen atom intrusion.

[0135] Nitrogen annealing at 350℃ for 20 minutes eliminates local stress fluctuations. The hydrogen content of the resulting compressive stress film can be reduced from more than 7% initially to less than 2%, the absolute value of the compressive stress is stabilized between -1.2GPa and -1.5GPa, the intra-sheet uniformity is controlled within ±3%, and the long-term stress stability (1000-hour test) decay rate is less than 5%.

[0136] Step S10: Photoresist is applied to the surface of the compressive stress film 210, and the photoresist above the NMOS region is removed by development to expose the NMOS region.

[0137] After the compressive stress film 210 is deposited, photoresist 209 is applied over the NMOS and PMOS regions. The photoresist 209 over the PMOS region is then removed using a development process to expose the NMOS region (e.g., ...). Figure 11 As shown in the image, this prepares the image for subsequent etching. This step requires precise control of the photoresist coating and development parameters to ensure the accuracy and reliability of the pattern transfer.

[0138] Specifically, a positive photoresist (such as AZ4620) is used for coating, and a uniform photoresist layer with a thickness of 1.0μm-1.5μm is formed by spin coating (3000rpm, 30s). Before coating, the wafer is pretreated with HMDS (75℃-120℃, nitrogen purging) to enhance the adhesion between the photoresist and the silicon nitride surface. The soft baking process is carried out in stages: first, pre-baking at 60℃ for 30s, then increasing to 110℃ for 1min to reduce stress gradient and ensure the quality of the photoresist film.

[0139] The exposure process uses an i-line (365nm) light source with an energy set to 250mJ / cm². 2 -300mJ / cm 2The NMOS region is selectively exposed using a photomask. Alignment accuracy is controlled within ±0.5μm to ensure precise alignment between the pattern and the underlying device. Development is performed using a 0.26 NTMAH solution (23±1℃) for 75-90 seconds, combined with dynamic spray development (pressure 0.8 bar, nozzle movement speed 150 mm / s) to ensure complete dissolution of the photoresist in the NMOS region while preserving the integrity of the photoresist in the PMOS region.

[0140] After development, the photoresist is rinsed with deionized water (8 L / min, 30 s) and dried by nitrogen purging (1000 rpm, 10 s), followed by post-baking (130 °C, 8 min) to enhance its etching resistance. The final photoresist pattern has a linewidth deviation of <±5% and an edge roughness Ra <50 nm, providing a reliable mask for the subsequent selective etching of silicon nitride films.

[0141] Step S11: Etch the compressive stress film in the NMOS region.

[0142] like Figure 12 As shown, after photoresist patterning is completed, the compressive stress film 210 in the NMOS region needs to be selectively etched to expose the underlying NMOS device structure. This step requires precise control of etching process parameters to ensure high selective etching of the silicon nitride film while avoiding damage to the underlying material.

[0143] Specifically, inductively coupled plasma (ICP) etching technology is employed, using a CF4 / N2 / O2 mixed gas (flow ratio 6:2:1) as the etching gas source. Process parameters are set as follows: ICP power 1200W-1500W, RF bias power 150W, chamber pressure 5-10mTorr, and wafer temperature 200℃. Under these conditions, silicon nitride achieves an etching selectivity of 40:1 for photoresist and >100:1 for the underlying oxide, ensuring high directionality and precision in the etching process.

[0144] The etching endpoint was monitored in real time using optical emission spectroscopy (OES). The etching process was automatically terminated when a sharp drop in the intensity of the SiF4 characteristic peak (795 nm) was detected. After etching, N2 / O2 plasma was used for resist removal (N2 50 sccm, O2 15 sccm, RF450W, 7 mTorr), followed by cleaning with 0.1% HF solution for 30 s to remove surface residues. The final etched morphology had a sidewall perpendicularity >89° and a surface roughness Ra <0.2 nm, providing a good interface for subsequent processes.

[0145] Step S12: Perform rapid thermal annealing on the tensile stress film and the compressive stress film to store the tensile stress generated by the tensile stress film remaining on the NMOS region and the compressive stress generated by the compressive stress film remaining on the PMOS region in the corresponding NMOS and PMOS channels, respectively.

[0146] Rapid thermal annealing (RTA) is used to precisely memorize stress into the NMOS and PMOS channels, enhancing device performance. This step promotes the transfer of thin-film stress to the semiconductor substrate through short-time, high-temperature processing.

[0147] The annealing process is performed using an RTA device under a nitrogen protective atmosphere. For the NMOS region, the wafer is rapidly heated to 900℃-1050℃ and held for 5s-30s to effectively transfer the lattice stress generated by the tensile stress film 208 to the channel, thereby improving electron mobility. For the PMOS region, the annealing temperature is set to 800℃-950℃ and held for 5s-20s to ensure that the stress generated by the compressive stress film 210 is fully applied to the channel, thereby enhancing hole mobility.

[0148] Rapid thermal annealing, through precise temperature profile control (heating rate ≥100℃ / s, cooling rate ≥50℃ / s), avoids damage to the device structure caused by prolonged high temperatures, while ensuring efficient stress transfer. This process can improve NMOS channel electron mobility by 15%-30% and PMOS channel hole mobility by 10%-20%, significantly optimizing transistor electrical performance.

[0149] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The terms "first" and "second" used in this document are for distinction only and are not intended to limit the content of this invention.

[0150] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a CMOS device, characterized in that, include: A semiconductor substrate is provided, wherein an NMOS region and a PMOS region are disposed on the semiconductor substrate, and a gate is disposed corresponding to the NMOS region and the PMOS region and source / drain ion implantation has been completed; An etching barrier layer is deposited on the semiconductor substrate; A tensile stress film is deposited on the surface of the etching barrier layer, and the tensile stress film is subjected to a first ultraviolet curing treatment. Remove the tensile stress film from the PMOS region; A compressive stress film is deposited on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region, and the compressive stress film is subjected to a second ultraviolet curing treatment. Remove the compressive stress film from the surface of the tensile stress film in the NMOS region; The tensile stress film and the compressive stress film are subjected to rapid annealing.

2. The method for fabricating a CMOS device according to claim 1, characterized in that, The process of depositing a tensile stress film on the surface of the etch barrier layer includes: Tensile stress films were deposited on the surface of the etching barrier layer using a PECVD process.

3. The method for fabricating a CMOS device according to claim 1, characterized in that, The process of depositing a tensile stress film on the surface of the etch barrier layer includes: A high-tensile-stress film is deposited n times on the surface of the etching barrier layer using the PECVD process. Each high-tensile-stress film is subjected to plasma nitriding treatment, and a low-tensile-stress film is deposited on the surface of the nth high-tensile-stress film to form the tensile-stress film, where n≥1.

4. The method for fabricating a CMOS device according to claim 2 or 3, characterized in that, The first ultraviolet curing process includes: The semiconductor substrate with the tensile stress film deposited is placed in the cavity; The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%. The tensile stress film was cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

5. The method for fabricating a CMOS device according to claim 2 or 3, characterized in that, The first ultraviolet curing process includes: The semiconductor substrate with the tensile stress film deposited is placed in the cavity; The chamber is heated to 350℃-400℃ and purged with nitrogen to reduce the oxygen content to below 0.5%. The tensile stress film was cured three times using ultraviolet light with a wavelength of 365nm-400nm, with each curing interval of 8-12 minutes. The intensity of the ultraviolet light was 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 Each curing time is 32s-80s; Nitrogen annealing was performed for 25-35 minutes at a temperature range of 380℃-420℃.

6. The method for fabricating a CMOS device according to claim 1, characterized in that, The process of depositing a compressive stress film on the surface of the etch barrier layer in the PMOS region and the surface of the tensile stress film in the NMOS region includes: The compressive stress film is deposited using HDP-CVD or SACVD processes, and then subjected to nitrogen annealing.

7. The method for fabricating a CMOS device according to claim 6, characterized in that, The second ultraviolet curing process includes: The semiconductor substrate with the deposited compressive stress film is placed in the cavity; The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%. The compressive stress film is cured using ultraviolet light with a wavelength of 365nm-400nm, wherein the intensity of the ultraviolet light is 150mW / cm². 2 -250mW / cm 2 The total energy density is 80 mJ / cm³. 2 -120mJ / cm 2 The curing time is 32s-80s.

8. The method for fabricating a CMOS device according to claim 6, characterized in that, The second ultraviolet curing process includes: The semiconductor substrate with the deposited compressive stress film is placed in the cavity; The chamber is heated to 320℃-380℃ and purged with nitrogen to reduce the oxygen content to below 0.5%. The compressive stress film is cured three times using ultraviolet light with a wavelength of 365nm-400nm, wherein... The first curing step uses 150mW / cm 2 -180mW / cm 2 Curing with intense ultraviolet light, curing time 30s-50s; After naturally cooling to 180℃-220℃, use 180mW / cm 2 -220mW / cm 2 A second curing process is performed using ultraviolet light with high intensity, with a curing time of 20-40 seconds. After naturally cooling to room temperature, use 220mW / cm 2 -250mW / cm 2 A third curing process is performed using ultraviolet light with high intensity, with a curing time of 20-30 seconds. Nitrogen annealing was performed at a temperature range of 340℃-360℃ for 18-22 minutes.

9. The method for fabricating a CMOS device according to claim 1, characterized in that, The semiconductor substrate is <100> Crystal orientation.

10. The method for fabricating a CMOS device according to claim 1, characterized in that, The tensile stress film and the compressive stress film are made of silicon nitride.

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