Preparation method of diamond layer and gallium nitride heterogeneous integrated CMOS (Complementary Metal-Oxide-Semiconductor Transistor) and CMOS device

Abstract

The invention discloses a preparation method of a diamond layer and gallium nitride heterogeneous integrated CMOS (Complementary Metal-Oxide-Semiconductor Transistor) and a CMOS device. The preparation method comprises the following steps: providing a wafer, and growing a diamond layer on the wafer; preparing a first pattern structure on the surface of the wafer; growing a GaN / AlGaN material layer on the surface of the first pattern structure, and forming two-dimensional electron gas in the GaN / AlGaN material layer; preparing a second pattern structure on the surface of the GaN / AlGaN material layer; forming two-dimensional hole gas on the surface of the diamond layer; and preparing the CMOS device based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer. The advantages of a gallium nitride-based N-type electronic device and a diamond layer-based P-type device are fully utilized, so that the prepared CMOS device is compatible with the unique advantages of two wide bandgap semiconductor materials, can be applied to the fields of high frequency, high voltage, high temperature, efficient heat dissipation and the like, and provides a solution for a next-generation high-power and high-reliability electronic system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS and a CMOS device. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) technology is the cornerstone of the semiconductor industry, and its low power consumption, high integration, and reliability support almost all modern electronic systems. As silicon-based CMOS approaches its physical limits, fabricating CMOS on new materials (such as GaN, SiC, and diamond layers) has become a key path for the continued evolution of the technology, while also driving the development of cutting-edge fields such as power electronics and quantum computing.

[0003] Two-dimensional electron gases (2DEGs) formed at the interface of gallium nitride-based heterojunction materials can achieve carrier mobilities exceeding 2000 cm² / Vs. Gallium nitride-based N-type electronic devices can meet the requirements of high frequency and high efficiency in power electronics applications, but the lack of high-performance P-type devices hinders their application in power semiconductors.

[0004] Diamond layers, as a typical example of ultra-wide bandgap semiconductors, also possess advantages such as a large bandgap, high carrier mobility, and high carrier saturation velocity. Treating intrinsic diamond layer substrates in hydrogen plasma allows the formation of a two-dimensional hole gas (2DHG) layer on the surface. By optimizing the surface treatment process and reducing ionized impurity scattering, the carrier mobility on the surface of hydrogen-terminated diamond layers can reach as high as 680 cm² / Vs. Diamond-based P-type devices have already found excellent applications in high-speed switching and other fields, but the lack of high-performance N-type devices hinders the development of diamond-based semiconductor devices.

[0005] Currently, fabricating CMOS inverters on materials is one of the important research goals of ultra-wide bandgap semiconductor materials. However, for gallium nitride and diamond layer materials, it is difficult to achieve stable P-type and N-type regions at the same time, which makes it difficult to fabricate CMOS devices. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS, as well as a CMOS device.

[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a diamond layer and a gallium nitride heterogeneous integrated CMOS, comprising: Provide wafers, and grow diamond layers on the wafers; A first patterned structure is fabricated on the surface of a wafer; the depth of the first patterned structure extends to the surface where the diamond layer is in contact with the wafer; A GaN / AlGaN material layer is grown on the surface of the first patterned structure, and a two-dimensional electron gas is formed within the GaN / AlGaN material layer. A second patterned structure is fabricated on the surface of a GaN / AlGaN material layer; the second patterned structure coincides with the patterned structure of the first patterned structure and extends to the surface where the diamond layer meets the wafer. Two-dimensional cavitation is formed on the surface of the diamond layer; CMOS devices are fabricated based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer.

[0008] In a second aspect, the present invention provides a CMOS device heterogeneously integrated with a diamond layer and gallium nitride, comprising: wafers; A diamond layer is located on one side of the wafer; two-dimensional cavitation is formed on the surface of the diamond layer. The first pattern structure is located on the wafer, and the depth of the first pattern structure extends to the surface where the diamond layer is in contact with the wafer. A GaN / AlGaN material layer is located on the surface of the first patterned structure; a two-dimensional electron gas is formed within the GaN / AlGaN material layer. The second patterned structure is located on the surface of the GaN / AlGaN material layer; the second patterned structure coincides with the patterned position of the first patterned structure, and its depth extends to the surface where the diamond layer meets the wafer. The PMOS device is disposed on the surface of the diamond layer at the position corresponding to the second pattern structure. The NMOS device is disposed on the surface of the GaN / AlGaN material layer; wherein, the gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device.

[0009] This invention provides a method for fabricating a diamond-based N-type CMOS and a gallium nitride (GaN) heterogeneous integrated CMOS, as well as a CMOS device. The method includes providing a wafer, growing a diamond layer on the wafer, fabricating a first patterned structure on the wafer surface, growing a GaN / AlGaN material layer on the surface of the first patterned structure, forming a two-dimensional electron gas within the GaN / AlGaN material layer, fabricating a second patterned structure on the surface of the GaN / AlGaN material layer, forming a two-dimensional hole gas on the surface of the diamond layer, and fabricating a CMOS device based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer. This invention fully utilizes the advantages of both gallium nitride-based N-type electronic devices and diamond-based P-type devices, enabling the fabricated CMOS device to combine the unique advantages of two wide-bandgap semiconductor materials. It can be applied in fields such as high frequency, high voltage, high temperature, and efficient heat dissipation, providing a solution for next-generation high-power, high-reliability electronic systems.

[0010] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic flowchart of a method for fabricating a diamond layer and a gallium nitride heterostructure integrated CMOS according to an embodiment of the present invention; Figures 2 to 7 This is a schematic diagram illustrating the process of fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a CMOS device with heterogeneous integration of a diamond layer and gallium nitride provided in an embodiment of the present invention; Figure 9 This is a top view of a CMOS device with heterogeneous integration of a diamond layer and gallium nitride provided in an embodiment of the present invention. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0013] See Figure 1 This invention provides a method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS, the specific steps of which include: S10. Provide a wafer and grow a diamond layer on the wafer.

[0014] For example, a wafer is provided, the material of which may be silicon or silicon carbide. The wafer is placed in a solution with a volume ratio of H₂O₂:NH₄OH:H₂O = 1:1:5 and ultrasonically cleaned at 70°C for 10 minutes to remove organic contaminants and particles. Then, the wafer is placed in a solution with a volume ratio of H₂O₂:HCl:H₂O = 1:1:6 and ultrasonically cleaned at 70°C for 10 minutes to remove metallic impurities. Finally, the wafer is rinsed in a large amount of deionized water and dried with nitrogen gas.

[0015] Next, the cleaned wafer is placed in a nanodiamond layer suspension and sonicated for 20 minutes to increase the nucleation density. Then, the wafer is placed in an MPCVD (Metal-Organic Chemical Vapor Deposition) instrument, and hydrogen (H2), 3%-5% methane (CH4), 30 ppm nitrogen, and 30 ppm oxygen are introduced to grow a diamond layer at 800-900°C. Optionally, the thickness of the diamond layer is greater than 300 μm. The surface of the grown diamond layer is then polished, and the first structure after diamond layer growth is as follows: Figure 2 As shown.

[0016] S20. Prepare a first patterned structure on the wafer surface.

[0017] The depth of the first pattern structure extends to the surface where the diamond layer meets the wafer.

[0018] Optionally, in step S20, the fabrication of a first patterned structure on the wafer surface may specifically include: S201, Thinning the wafer.

[0019] The wafer is made of silicon or silicon carbide, and the thickness of the thinned wafer is less than 1 mm. .

[0020] For example, wafer thinning can be achieved using methods such as mechanical polishing, dry deep etching, and solution etching. Specifically, [the following steps are taken]. Figure 2 The diamond layer of the first structure shown is protected by a UV film. The wafer is then placed face up in the sample stage of a wafer thinning machine to reduce its thickness to 100 mm. The following steps are performed: The first structure is removed, and the diamond layer is placed face up under UV light to reduce the adhesion of the UV film, allowing the first structure to be peeled off from the UV film under low stress. Then, the wafer face of the first structure is placed in a deep silicon etching machine, and the wafer thickness is further etched to 10 μm in a fluorine-based gas atmosphere. The following steps are followed. Finally, ICP (Inductively Coupled Plasma) equipment is used to reduce the wafer thickness to 1. The following results are obtained: Figure 3 The second structure shown.

[0021] S202. Prepare a first patterned structure on the thinned wafer surface.

[0022] Exemplarily, a first patterned structure is fabricated on the thinned wafer surface using photolithography. Specifically, firstly, photoresist AZ6112 is dropped onto the center of the wafer surface of the second structure using a dropper, with a rotation speed of 4000 r / min and a time of 30 seconds. Then, the second structure is placed on a hot plate and heated at 100°C for 120 seconds. Next, the second structure is placed in a photolithography machine and exposed under a pre-customized first patterned structure mask for 0.91 seconds, followed by development in a developer solution for 27 seconds. The second structure is then placed on a hot plate and heated at 120°C for 120 seconds. Next, the second structure is placed in an ICP device to etch away the exposed areas of the wafer. Finally, the remaining photoresist is washed away with acetone, alcohol, and deionized water, and the second structure is dried with nitrogen gas to obtain the desired result. Figure 4 The third structure shown.

[0023] Here, the first graphic structure is a periodically arranged graphic.

[0024] S30. A GaN / AlGaN material layer is grown on the surface of the first pattern structure, and a two-dimensional electron gas is formed within the GaN / AlGaN material layer.

[0025] Optionally, in step S30, growing a GaN / AlGaN material layer on the surface of the first patterned structure may specifically include: sequentially growing a GaN material layer and an AlGaN material layer on the surface of the first patterned structure. The thickness of the GaN material layer is greater than the thickness of the AlGaN material layer.

[0026] For example, a wafer with the third structure facing upwards is placed in an MOCVD nitride epitaxial growth system. A thick GaN material layer is grown on the surface of the first patterned structure, and a thin AlGaN material layer is grown on the side of the GaN material layer away from the first patterned structure, resulting in the following: Figure 5 The fourth structure shown.

[0027] S40. Prepare a second patterned structure on the surface of the GaN / AlGaN material layer.

[0028] The second pattern structure overlaps with the pattern position of the first pattern structure, and its depth extends to the surface where the diamond layer meets the wafer.

[0029] The method for fabricating the second patterned structure on the surface of the GaN / AlGaN material layer is the same as that for fabricating the first patterned structure, and will not be repeated here. It should be noted that before exposure, the second patterned structure must be aligned with the first patterned structure under the lithography lens to obtain the final result as shown below. Figure 6 The fifth structure shown.

[0030] S50, Two-dimensional cavitation gas is formed on the surface of the diamond layer.

[0031] For example, the fifth structure can be processed in a hydrogen atmosphere to form hydrogen terminals on the exposed diamond layer surface, generating two-dimensional cavitation gas. Hydrogen atmosphere processing methods include, but are not limited to, placing the fifth structure in an MPCVD device, a plasma coating machine, or a RIE (Reactive Ion Etching) device. For instance, molybdenum (Mo) can be used as a metal mask to cover the GaN / AlGaN material region, exposing the diamond layer surface region. This exposed diamond layer surface region can then be treated with hydrogen plasma in an MPCVD device to form two-dimensional cavitation gas on the diamond layer surface, resulting in a structure like... Figure 7 The sixth structure shown.

[0032] S60. CMOS devices are fabricated based on two-dimensional electron gas of GaN / AlGaN material layers and two-dimensional hole gas on the surface of diamond layers.

[0033] For example, CMOS devices with on-chip interconnects, common gate and common drain can be directly fabricated by photolithography on the GaN / AlGaN material layer and the diamond layer. Alternatively, NMOS devices can be fabricated by photolithography on the GaN / AlGaN material layer and PMOS devices can be fabricated by photolithography on the diamond layer material surface. Finally, the gates of the two devices are connected with gold wires using a wire bonding machine, and the drains of the two devices are connected with gold wires to form a CMOS device with heterogeneous integration of diamond layer and gallium nitride.

[0034] Optionally, in step S60, the fabrication of a CMOS device based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer may specifically include: S601. A PMOS device is fabricated based on the two-dimensional cavitation gas at the position corresponding to the second pattern structure on the surface of the diamond layer.

[0035] Optionally, in step S601, the PMOS device is fabricated based on the two-dimensional cavitation gas at the position corresponding to the second patterned structure on the surface of the diamond layer. This may specifically include: S6011. Fabricate the gate dielectric layer, source, and drain of the PMOS device at the positions corresponding to the second pattern structure on the surface of the diamond layer. The two-dimensional hole gas is located on the side of the diamond layer closest to the wafer.

[0036] S6012. The gate of the PMOS device is fabricated on the side of the gate dielectric layer away from the diamond layer.

[0037] For example, refer to Figure 8 and Figure 9 If a two-dimensional hole is located on the side of the diamond layer closest to the wafer, the gate dielectric layer, source, and drain of the PMOS device are fabricated on the diamond layer surface at the location corresponding to the second pattern structure. Then, the gate electrode is fabricated on the side of the gate dielectric layer furthest from the diamond layer.

[0038] S602. An NMOS device is fabricated based on the two-dimensional electron gas at the interface between the GaN and AlGaN material layers in a GaN / AlGaN material layer.

[0039] For example, refer to Figure 8 and Figure 9 If a two-dimensional hole is located on the side of the diamond layer closest to the wafer, the gate dielectric layer, source, and drain of the PMOS device are fabricated on the diamond layer surface at the location corresponding to the second pattern structure. Then, the gate electrode is fabricated on the side of the gate dielectric layer furthest from the diamond layer.

[0040] Optionally, in step S602, an NMOS device is fabricated based on the two-dimensional electron gas at the interface between the GaN material layer and the AlGaN material layer in the GaN / AlGaN material layer, including: S6021. A gate dielectric layer, a source, and a drain of an NMOS device are fabricated on the surface of a GaN / AlGaN material layer. The source and drain of the NMOS device are connected to the interface between the GaN material layer and the AlGaN material layer in the GaN / AlGaN material layer.

[0041] The two-dimensional electron gas is located at the interface between the GaN and AlGaN material layers in the GaN / AlGaN material layer.

[0042] S6022. The gate of the NMOS device is fabricated on the side of the gate dielectric layer away from the GaN / AlGaN material layer.

[0043] For example, refer to Figure 8 and Figure 9 Since the two-dimensional electron gas is located at the interface between the GaN and AlGaN material layers in the GaN / AlGaN material layer, the gate dielectric layer, source, and drain of the NMOS device are fabricated on the surface of the GaN / AlGaN material layer, and the source and drain of the NMOS device are connected to the interface between the GaN and AlGaN material layers. Then, the gate electrode is fabricated on the side of the gate dielectric layer away from the GaN / AlGaN material layer.

[0044] Finally, the gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device, thus completing the fabrication of the diamond layer and gallium nitride heterogeneous integrated CMOS device.

[0045] In addition, the source of an NMOS device is used to connect to a low-level voltage (such as ground GND), while the source of a PMOS device is used to connect to a high-level voltage (such as power supply VDD).

[0046] Optionally, the electrode materials used in NMOS and PMOS devices include one or more of Ti, Au, Pt, Ni, and Al, and the gate dielectric layer materials used include one or more of SiO2, Al2O3, MoO3, HfO2, and MgF2.

[0047] For example, alumina (Al2O3) can be used as the gate dielectric layer of the PMOS and NMOS devices, a Ti / Au combination can be used as the gate of the PMOS and NMOS devices, a Ti / Al / Ni / Au combination can be used as the source and drain of the NMOS device, and a Ti / Au combination can be used as the source and drain of the PMOS device. Furthermore, the gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device, via pads (i.e., connection and test points). The material of the pads includes, but is not limited to, one or more of Cu, Al, and Au. For example, a Cu / Au combination can be used as the pad to interconnect the drains of the PMOS and NMOS devices.

[0048] This embodiment provides a method for fabricating a diamond-based and gallium nitride (GaN) heterogeneous integrated CMOS. A wafer is provided, and a diamond layer is grown on the wafer. A first patterned structure is fabricated on the wafer surface. A GaN / AlGaN material layer is grown on the surface of the first patterned structure, and a two-dimensional electron gas is formed within the GaN / AlGaN material layer. A second patterned structure is fabricated on the surface of the GaN / AlGaN material layer. A two-dimensional hole gas is formed on the surface of the diamond layer. Based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer, a CMOS device is fabricated. This invention fully utilizes the advantages of gallium nitride-based N-type electronic devices and diamond-based P-type devices, enabling the fabricated CMOS device to combine the unique advantages of two wide-bandgap semiconductor materials. It can be applied in fields such as high frequency, high voltage, high temperature, and efficient heat dissipation, providing a solution for next-generation high-power, high-reliability electronic systems.

[0049] Combination Figure 8 and Figure 9 This application also provides a CMOS device with heterogeneous integration of a diamond layer and gallium nitride, comprising: wafers; A diamond layer is located on one side of the wafer; two-dimensional cavitation is formed on the surface of the diamond layer. The first pattern structure is located on the wafer, and the depth of the first pattern structure extends to the surface where the diamond layer is in contact with the wafer. A GaN / AlGaN material layer is located on the surface of the first patterned structure; a two-dimensional electron gas is formed within the GaN / AlGaN material layer. The second patterned structure is located on the surface of the GaN / AlGaN material layer; the second patterned structure coincides with the patterned position of the first patterned structure, and its depth extends to the surface where the diamond layer meets the wafer. The PMOS device is disposed on the surface of the diamond layer at the position corresponding to the second pattern structure. The NMOS device is disposed on the surface of the GaN / AlGaN material layer; wherein, the gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device.

[0050] For the specific structure of this CMOS device, please refer to the content of the fabrication method of diamond layer and gallium nitride heterogeneous integrated CMOS provided in the first aspect, which will not be repeated here.

[0051] This invention fully utilizes the advantages of gallium nitride-based N-type electronic devices and diamond-based P-type devices, enabling the fabricated CMOS devices to be compatible with the unique advantages of two wide-bandgap semiconductor materials. It can be applied to fields such as high frequency, high voltage, high temperature, and efficient heat dissipation, providing a solution for the next generation of high-power, high-reliability electronic systems.

[0052] It should be noted that, in terms of structure, since it is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0053] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0054] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0055] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0056] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS, characterized in that, include: A wafer is provided, on which a diamond layer is grown; A first patterned structure is fabricated on the surface of the wafer; The depth of the first patterned structure extends to the surface where the diamond layer meets the wafer; A GaN / AlGaN material layer is grown on the surface of the first patterned structure, and a two-dimensional electron gas is formed within the GaN / AlGaN material layer. A second patterned structure is fabricated on the surface of the GaN / AlGaN material layer; the second patterned structure coincides with the patterned position of the first patterned structure and extends to the surface where the diamond layer meets the wafer; Two-dimensional cavitation gas is formed on the surface of the diamond layer; CMOS devices are fabricated based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer.

2. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 1, characterized in that, The fabrication of CMOS devices based on the two-dimensional electron gas of the GaN / AlGaN material layer and the two-dimensional hole gas on the surface of the diamond layer includes: A PMOS device is fabricated based on the two-dimensional cavitation gas at the position on the surface of the diamond layer corresponding to the second pattern structure. An NMOS device is fabricated based on the two-dimensional electron gas at the interface between the GaN and AlGaN material layers in the GaN / AlGaN material layer. The gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device.

3. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 2, characterized in that, The fabrication of a PMOS device based on the two-dimensional cavitation gas at the position corresponding to the second patterned structure on the surface of the diamond layer includes: A gate dielectric layer, source, and drain of a PMOS device are fabricated on the surface of the diamond layer at the position corresponding to the second pattern structure, and the two-dimensional hole gas is located on the side of the diamond layer closer to the wafer. The gate of the PMOS device is fabricated on the side of the gate dielectric layer away from the diamond layer.

4. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 3, characterized in that, The fabrication of an NMOS device based on the two-dimensional electron gas at the interface between the GaN and AlGaN material layers in the GaN / AlGaN material layer includes: A gate dielectric layer, source, and drain of an NMOS device are fabricated on the surface of the GaN / AlGaN material layer. The source and drain of the NMOS device are connected to the interface between the GaN material layer and the AlGaN material layer in the GaN / AlGaN material layer. The two-dimensional electron gas is located at the interface between the GaN material layer and the AlGaN material layer in the GaN / AlGaN material layer. The gate of the NMOS device is fabricated on the side of the gate dielectric layer away from the GaN / AlGaN material layer.

5. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 4, characterized in that, The electrode materials used in the NMOS and PMOS devices include one or more of Ti, Au, Pt, Ni, and Al, and the gate dielectric layer materials include one or more of SiO2, Al2O3, MoO3, HfO2, and MgF2.

6. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 1, characterized in that, The process of fabricating the first patterned structure on the wafer surface includes: The wafer is thinned; the wafer is made of silicon or silicon carbide, and the thickness of the thinned wafer is less than 1 mm. ; The first patterned structure is fabricated on the thinned wafer surface.

7. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 1, characterized in that, The step of growing a GaN / AlGaN material layer on the surface of the first patterned structure includes: The GaN material layer and the AlGaN material layer are grown sequentially on the surface of the first patterned structure, wherein the thickness of the GaN material layer is greater than the thickness of the AlGaN material layer.

8. The method for fabricating a diamond layer and gallium nitride heterogeneous integrated CMOS according to claim 1, characterized in that, The thickness of the diamond layer is greater than 300. .

9. A CMOS device heterogeneously integrated with a diamond layer and gallium nitride, characterized in that, include: wafers; A diamond layer is located on one side of the wafer; two-dimensional cavitation is formed on the surface of the diamond layer; A first patterned structure is located on the wafer, and the depth of the first patterned structure extends to the surface of the diamond layer that is in contact with the wafer; A GaN / AlGaN material layer is located on the surface of the first patterned structure; A two-dimensional electron gas is formed within the GaN / AlGaN material layer; The second patterned structure is located on the surface of the GaN / AlGaN material layer; the second patterned structure coincides with the patterned position of the first patterned structure, and extends to the surface where the diamond layer meets the wafer; A PMOS device is disposed on the surface of the diamond layer at a position corresponding to the second pattern structure. An NMOS device is disposed on the surface of the GaN / AlGaN material layer; wherein the gate of the PMOS device is connected to the gate of the NMOS device, and the drain of the PMOS device is connected to the drain of the NMOS device.

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