AlGaInP red LED chip structure with polarization-induced tunneling junction and preparation method

Abstract

The application discloses an AlGaInP red LED chip structure with a polarization-induced tunnel junction and a preparation method. The chip structure comprises, from bottom to top, a GaAs substrate, an n-type GaAs buffer layer, an n-type etching stop layer, an n-type GaAs ohmic contact layer, an n-type confinement layer, an undoped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an insertion layer and an n-type ohmic contact layer. The p-type AlGaInP polarization-induced doping layer introduces a piezoelectric polarization electric field through Al composition gradient design, and induces the formation of a high-density two-dimensional hole gas. The high-Al-composition insertion layer and the n-type ohmic contact layer form a tunnel junction. The application fundamentally solves the problems of low p-type doping efficiency and high resistivity of high-Al-composition AlGaInP material, simplifies the epitaxial structure and chip process, reduces the chip series resistance, improves the luminous efficiency and yield, and has significant technical and commercial value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Micro LED display, in particular to an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof. BACKGROUND

[0002] AlGaInP red light LED is widely used in display, lighting, optical communication and other fields due to its high luminous efficiency, good stability and long service life. However, there are still significant technical bottlenecks in the preparation and performance of existing AlGaInP red light LED, mainly in the following aspects:

[0003] 1. Low p-type doping efficiency: In the prior art, magnesium (Mg) is generally used as the p-type dopant of AlGaInP material. However, in high aluminum (Al) component p-type AlGaInP, the ionization energy of Mg acceptor increases significantly, resulting in insufficient hole concentration in the p-type region (usually difficult to meet the high conductivity requirement of the device) and high resistivity. If the conductivity is improved by increasing the Mg doping concentration, the self-compensation effect will be induced, forming Mg-related deep level defects or complexes, and introducing dislocations, non-radiative recombination centers, etc., which will damage the crystal quality. Not only the hole concentration and conductivity cannot be effectively improved, but also the luminous efficiency of the device is reduced. In addition, the low hole mobility of p-type AlGaInP further exacerbates the high resistance problem.

[0004] 2. Complex manufacturing process and high cost: In order to alleviate the high resistance problem of the p-type region, the existing scheme usually designs a multi-layer p-type epitaxial structure (such as p-type spacer layer, p-type confinement layer, p-type superlattice structure, p-type hole supply layer and p-type ohmic contact layer, etc.), which leads to complicated epitaxial growth steps and increased time consumption. At the same time, in the subsequent chip preparation, metalization process needs to be carried out for the p-type region and the n-type region respectively to prepare the ohmic contact electrode, which has many process steps and low fault tolerance, not only increasing the manufacturing cost, but also reducing the chip production yield.

[0005] The above problems seriously restrict the performance improvement and industrialization cost control of AlGaInP red light LED, and an innovative structure and preparation method are needed to break through the p-type doping bottleneck and simplify the process. SUMMARY

[0006] The present application aims to overcome the technical defects of existing red light Micro LED, and provides an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof, which aims to: without relying on high-concentration Mg doping, improve the hole concentration and conductivity of the p-type region through the polarization-induced mechanism; introduce a tunnel junction to synergistically enhance the conductivity of the p-type region, solve the p-type doping bottleneck of high Al component AlGaInP; simplify the epitaxial structure and chip process, reduce the manufacturing cost, and improve the chip yield and light emitting performance.

[0007] To solve the above technical problems, the technical scheme adopted by the present application is:

[0008] An AlGaInP red LED chip structure with a polarization-induced tunnel junction, from bottom to top, comprises: a GaAs substrate, an n-type GaAs buffer layer, an n-type etching stop layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, an undoped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an intercalation layer and an n-type ohmic contact layer.

[0009] The composition of the p-type AlGaInP polarization-induced doping layer gradually changes from to , wherein the Al component =0.6-0.7, =0.9-1, the component ratio =0.5, =0.7.

[0010] The Al component of the intercalation layer =0.8-1, and forms a tunnel junction with the n-type ohmic contact layer.

[0011] The Al component of the n-type ohmic contact layer =0.8-1, and the component ratio =0.5.

[0012] In a preferred embodiment, the wafer size of the GaAs substrate is 2-12 inches, the thickness is 350-650 μm, and the bevel angle is 2-15°.

[0013] In a preferred embodiment, the doping source of the n-type GaAs buffer layer is disilane, the doping concentration is , and the thickness is 100-300 nm; the doping source of the n-type GaAs ohmic contact layer is disilane, the doping concentration is , and the thickness is 10-50 nm.

[0014] In a preferred embodiment, the quantum well pairs of the undoped InGaP / quantum well structure are 1-5 pairs, the InGaP well layer thickness is 1.5-4.5 nm, the Al component of the barrier layer =0.6-0.9, and the component ratio =0.5, and the thickness is 4-10 nm.

[0015] In a preferred embodiment, the p-type Al component of the spacer layer =0.8-0.9, and the component ratio =0.5, the doping source is bis-magnesium, and the doping concentration is , and the thickness is 30-100 nm.

[0016] The application also provides a preparation method of an AlGaInP red LED chip structure with a polarization-induced tunnel junction, which adopts metal organic chemical vapor deposition (MOCVD) technology and comprises the following steps:

[0017] S1, epitaxially growing an n-type GaAs buffer layer on a GaAs substrate;

[0018] S2, epitaxially growing an n-type etching stop layer on the n-type GaAs buffer layer;

[0019] S3, epitaxially growing an n-type GaAs ohmic contact layer on the n-type etching stop layer;

[0020] S4, epitaxially growing an n-type limiting layer on the n-type GaAs ohmic contact layer;

[0021] S5, epitaxially growing an undoped InGaP / quantum well structure on the n-type limiting layer;

[0022] S6, epitaxially growing a p-type spacer layer on the undoped InGaP / quantum well structure;

[0023] S7, epitaxially growing a p-type AlGaInP polarization-induced doping layer on the p-type spacer layer;

[0024] S8, epitaxially growing a high-Al-component insertion layer on the p-type AlGaInP polarization-induced doping layer;

[0025] S9, epitaxially growing an n-type ohmic contact layer on the insertion layer to obtain an epitaxial wafer;

[0026] S10, performing bonding, substrate removal, mesa structure preparation, passivation and single-step metallization treatment on the epitaxial wafer to obtain a chip.

[0027] In a preferred solution, in step S2, the n-type The growth temperature of the etching barrier layer is 700-780℃, the growth rate is 0.2-0.7nm / s, the doping source is disilane, and the doping concentration is , and the thickness is 100-300nm.

[0028] In a preferred solution, in step S7, the growth temperature of the p-type AlGaInP polarization-induced doping layer is 700-780℃, the growth rate is 0.2-0.5nm / s, the doping source is dimethyl magnesium, and the doping concentration is , the thickness is 30-100nm, and the component is gradually changed by adjusting the flow ratio of trimethyl aluminum and trimethyl gallium.

[0029] In a preferred solution, in step S8, the growth temperature of the high-Al-component The growth source of the insertion layer is trimethyl aluminum, trimethyl gallium and arsine, the growth temperature is 700-780℃, the growth rate is 0.2-0.5nm / s, and the thickness is 10-40nm.

[0030] In a preferred solution, in step S10, the diameter of the mesa structure is 1-50μm; the passivation layer material is , or , prepared by atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD); single-step metallization is prepared by electron beam evaporation or sputtering process, and Cr / Au or Ti / Al / Ni / Au electrodes are prepared.

[0031] By using the above technical solutions, the application has the following beneficial effects compared with the prior art:

[0032] 1. Breakthrough of p-type doping bottleneck: through the Al component gradual change design of the p-type AlGaInP polarization-induced doping layer, the piezoelectric polarization electric field is introduced to induce the formation of high-density two-dimensional hole gas (2DHG), without relying on high-concentration Mg doping, the hole concentration and conductivity of the p-type region can be improved, and the problems of self-compensation effect and crystal quality damage of high-Al-component AlGaInP are solved; at the same time, the tunnel junction increases the net hole concentration of the p-type region through the electron tunneling effect, and cooperatively enhances the conductivity;

[0033] 2. Simplify the structure and process: the composite structure of “p-type AlGaInP spacer layer + polarization-induced doping layer + tunnel junction” is used to replace the traditional multi-layer p-type epitaxial structure (such as superlattice, hole-providing layer, etc.), which reduces the number and time of epitaxial growth; and the ohmic contact layers on the p-side (connected through the tunnel junction) and the n-side are both n-type doped, and only single-step metallization is needed to prepare electrodes on both sides, which simplifies the chip process and reduces the manufacturing cost;

[0034] 3, performance and yield are significantly improved: compared with traditional chips, the series resistance of the chip is 20 mA, the current density is reduced by 25% (from 12 mA to 9 mA), the luminous efficiency at 625nm wavelength is increased by 18% (from 22lm / W to 26lm / W), the production yield is increased from 71% to 85%, and the chip has high luminous performance and industrialization advantages. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0036] Figure 1 It is a schematic diagram of the AlGaInP red light LED chip structure with polarization-induced tunnel junction of the present application;

[0037] Figure 2 It is a flowchart of the preparation method of the AlGaInP red light LED chip structure with polarization-induced tunnel junction of the present application;

[0038] 1, GaAs substrate; 2, n-type GaAs buffer layer; 3, n-type etching stop layer; 4, n-type GaAs ohmic contact layer; 5, n-type limiting layer; 6, non-doped InGaP / quantum well structure; 7, p-type spacer layer; 8, p-type AlGaInP polarization-induced doping layer; 9, insertion layer; 10, n-type ohmic contact layer. DETAILED DESCRIPTION

[0039] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0040] It should be noted that the terms "first", "second" and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or apparatus comprising a list of steps or units does not necessarily limit the steps or units to those clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products or apparatuses.

[0041] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0042] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned partial terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0043] In addition, the terms "mount", "set", "provided with", "connected", "connected", "sleeved" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or a monolithic structure; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0045] Embodiment one

[0046] Please refer to Figure 1 An AlGaInP red LED chip structure with polarization-induced tunneling junction, from bottom to top, comprises the following functional layers in order:

[0047] GaAs substrate 1: The wafer size is 2-12 inches, the thickness is 350-650μm, and the bevel angle is 2-15°, which provides stable support for subsequent epitaxial layers;

[0048] n-type GaAs buffer layer 2: grown on GaAs substrate 1, the doping source is silane, and the doping concentration is [missing information]. With a thickness of 100-300nm, it is used to provide a flat, low-defect epitaxial growth surface and improve the crystal quality of the epitaxial layer;

[0049] n-type Etching barrier layer 3: grown on n-type GaAs buffer layer 2, wherein the Al composition x = 0.1-0.4, the composition ratio y = 0.5, the doping source is silane, and the doping concentration is [missing information]. With a thickness of 100-300nm, it is used in subsequent chip manufacturing processes to precisely control substrate removal and etching depth;

[0050] n-type GaAs ohmic contact layer 4: grown on n-type On the etch barrier layer 3, the doping source is silane, and the doping concentration is [missing information]. With a thickness of 10-50 nm, it is used to form a low-resistance ohmic contact with the metal electrode later;

[0051] n-type Confinement layer 5: grown on n-type GaAs ohmic contact layer 4, wherein the Al component =0.7-1, component ratio =0.5, the doping source is silane, and the doping concentration is With a thickness of 150-500 nm, it is used to confine the overflow of charge carriers in the quantum well structure and improve the charge carrier recombination efficiency;

[0052] Undoped InGaP / Quantum well structure 6: grown in n-type On the confinement layer 5, where the barrier layer Al component =0.6-0.9, component ratio =0.5; the number of quantum well pairs is 1-5, and the InGaP well layer thickness is 1.5-4.5 nm. The barrier layer is 4-10nm thick and is the core light-emitting region of the LED, where charge carriers recombine and radiate red light;

[0053] p-type Spacer layer 7: grown on undoped InGaP / On quantum well structure 6, where the Al component =0.8-0.9, component ratio =0.5, the doping source is magnesia-dicenocene, and the doping concentration is , thickness of 30-100nm, used to connect quantum well structure and polarization-induced doping layer, to optimize carrier transport path;

[0054] p-type AlGaInP polarization-induced doping layer 8: grown on p-type spacer layer 7, with component gradually changing from to , wherein Al component =0.6-0.7, =0.9-1, component ratio =0.5, =0.7; doping source is bis-magnesium, doping concentration is , thickness of 30-100nm; gradient strain is introduced by Al component gradient design, to induce generation of piezoelectric polarization electric field, and further to form high-density two-dimensional hole gas (2DHG) near layer interface, to significantly improve p-type region hole concentration and conductivity;

[0055] insertion layer 9: grown on p-type AlGaInP polarization-induced doping layer 8, wherein Al component =0.8-1, thickness of 10-40nm, together with lower p-type AlGaInP polarization-induced doping layer 8 and upper n-type ohmic contact layer 10 forms tunneling junction, to provide barrier structure for tunneling effect;

[0056] n-type ohmic contact layer 10: grown on high-Al-component insertion layer 9, wherein Al component =0.8-1, component ratio =0.5, doping source is disilane, doping concentration is , thickness of 30-100nm; together with high-Al-component insertion layer 9, forms tunneling junction, under reverse bias, p-type region electrons can pass through the barrier by quantum tunneling effect to inject into this layer, to equivalently increase p-type region net hole concentration; meanwhile, this layer is n-type doped, and can form low-resistance ohmic contact with metal electrode.

[0057] Embodiment two

[0058] Please refer to Figure 2 , the application further provides a preparation method of AlGaInP red LED chip structure with polarization-induced tunneling junction, which adopts metal organic chemical vapor deposition (MOCVD) technology for epitaxial growth, and the specific steps are as follows:

[0059] S1, n-type GaAs buffer layer 2 growth: placing GaAs substrate 1 in MOCVD reaction cavity, with disilane as doping source, trimethyl gallium (TMGa) and hydrogen arsenide ( Using hydrogen as the growth source and hydrogen as the carrier gas, an n-type GaAs buffer layer 2 was epitaxially grown at a temperature of 620-700℃ and a growth rate of 0.2-0.7 nm / s, with the doping concentration controlled at [value missing]. Thickness is 100-300nm;

[0060] S2, n type Etching barrier layer 3 growth: On n-type GaAs buffer layer 2, silane is used as the dopant source, and trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine are added. Using α as the growth source and hydrogen as the carrier gas, n-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.7 nm / s. Etch barrier layer 3 (x=0.1-0.4, y=0.5), controlling the doping concentration to be... Thickness is 100-300nm;

[0061] S3, n-type GaAs ohmic contact layer 4 growth: In n-type On the etch barrier layer 3, silane is used as the dopant source, and trimethylgallium (TMGa) and arsenide ( Using hydrogen as the growth source and hydrogen as the carrier gas, an n-type GaAs ohmic contact layer 4 was epitaxially grown at a temperature of 620-700℃ and a growth rate of 0.1-0.3 nm / s, with the doping concentration controlled at [value missing]. Thickness is 10-50nm;

[0062] S4, n type Growth of confinement layer 5: On the n-type GaAs ohmic contact layer 4, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and phosphine (…) are grown using silane as the dopant source. Using α as the growth source and hydrogen as the carrier gas, n-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. Restriction layer 5 ( =0.7-1, =0.5), controlling the doping concentration to be Thickness is 150-500nm;

[0063] S5, undoped InGaP / Quantum well structure 6 growth: in n-type On confinement layer 5, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine ( Using hydrogen as the growth source and hydrogen as the carrier gas, InGaP well layers were epitaxially grown alternately at a growth rate of 0.1-0.2 nm / s at a temperature of 700-780℃. Barrier layer =0.6-0.9, =0.5), forming 1-5 pairs of non-doped InGaP / AlGaInP quantum well structure Quantum well structure 6, controlling InGaP well layer thickness to be 1.5-4.5 nm, barrier layer thickness to be 4-10 nm;

[0064] S6, p-type Spacer layer 7 growth: on non-doped InGaP / AlGaInP quantum well structure 6, using metallocene (Cp2Mg) as a doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as growth sources, hydrogen as carrier gas, epitaxially growing p-type InGaP spacer layer 7 at a growth rate of 0.2-0.5 nm / s at a temperature of 700-780°C; Quantum well structure 6, controlling InGaP well layer thickness to be 1.5-4.5 nm, barrier layer thickness to be 4-10 nm; ) as a doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as growth sources, hydrogen as carrier gas, epitaxially growing p-type InGaP spacer layer 7 at a growth rate of 0.2-0.5 nm / s at a temperature of 700-780°C; =0.8-0.9, =0.5), controlling the doping concentration to be 1E18-1E19 cm-3 and the thickness to be 30-100 nm; S7, p-type AlGaInP polarization-induced doping layer 8 growth: on p-type InGaP spacer layer 7, using metallocene (Cp2Mg) as a doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as growth sources, hydrogen as carrier gas, epitaxially growing p-type AlGaInP polarization-induced doping layer 8 at a growth rate of 0.2-0.5 nm / s at a temperature of 700-780°C; Quantum well structure 6, controlling InGaP well layer thickness to be 1.5-4.5 nm, barrier layer thickness to be 4-10 nm;

[0065] S7, p-type AlGaInP polarization-induced doping layer 8 growth: on p-type InGaP spacer layer 7, using metallocene (Cp2Mg) as a doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as growth sources, hydrogen as carrier gas, epitaxially growing p-type AlGaInP polarization-induced doping layer 8 at a growth rate of 0.2-0.5 nm / s at a temperature of 700-780°C; Quantum well structure 6, controlling InGaP well layer thickness to be 1.5-4.5 nm, barrier layer thickness to be 4-10 nm; ) as a doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as growth sources, hydrogen as carrier gas, epitaxially growing p-type InGaP spacer layer 7 at a growth rate of 0.2-0.5 nm / s at a temperature of 700-780°C; =0.6-0.7, =0.5) to =0.9-1, =0.7), controlling the doping concentration to be 1E18-1E19 cm-3 and the thickness to be 30-100 nm; S8, Interlayer 9 growth: on p-type AlGaInP polarization-induced doping layer 8, using trimethylaluminum (TMAl), trimethylgallium (TMGa) and arsine (AsH3) as growth sources, hydrogen as carrier gas, epitaxially growing high Al component Interlayer 9 (

[0066] S8, Interlayer 9 growth: on p-type AlGaInP polarization-induced doping layer 8, using trimethylaluminum (TMAl), trimethylgallium (TMGa) and arsine (AsH3) as growth sources, hydrogen as carrier gas, epitaxially growing high Al component Interlayer 9 ( ​​​=0.8-1), control thickness is 10-40nm;

[0067] S9, n-type Ohmic contact layer 10 growth: in high Al component On the insertion layer 9, with ethylsilane as the doping source, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine (PH3) as the growth source, hydrogen as the carrier gas, epitaxially grown at a growth rate of 0.2-0.5nm / s at a temperature of 700-780℃, n-type Ohmic contact layer 10 (n-type =0.8-1, =0.5), control the doping concentration to be , and the thickness is 30-100nm, to obtain an epitaxial wafer;

[0068] S10, chip post-process:

[0069] Bonding the above epitaxial wafer with a Si-based CMOS driving chip to realize electrical connection and thermal management;

[0070] By chemical etching process, the GaAs substrate 1, n-type GaAs buffer layer 2 and n-type Etching stop layer 3, exposing n-type GaAs ohmic contact layer 4;

[0071] Using photolithography and dry etching process to form a mesa structure with a diameter of 1-50μm on the exposed epitaxial layer, defining the chip light emitting area;

[0072] Using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD) equipment to deposit , Or Passivation layer on the mesa structure sidewall, to prevent chip surface leakage and environmental erosion;

[0073] By photolithography and etching process to open holes on the passivation layer, respectively exposing n-type GaAs ohmic contact layer 4 and n-type Ohmic contact layer 10; using electron beam evaporation or sputtering process for single-step metallization to prepare metal electrodes (such as Cr / Au or Ti / Al / Ni / Au), while forming n-side and p-side (through tunnel junction connection) ohmic contact, completing chip preparation.

[0074] Example three

[0075] The application provides a preparation method of an AlGaInP red light LED chip structure with a polarization-induced tunnel junction, comprising the following steps:

[0076] ​S1, Substrate preparation and growth of n-type GaAs buffer layer 2:

[0077] Substrate preparation: A 4-inch GaAs substrate 1, 500 μm thick, with a 10° bevel angle, was selected and cleaned (acetone sonication → ethanol sonication → deionized water rinsing → After drying, place it in the MOCVD reaction chamber;

[0078] n-type GaAs buffer layer 2 growth: using silane as the dopant source (flow rate 5 sccm), TMGa (flow rate 20 sccm) and (Flow rate 500 sccm) is the growth source, Using a carrier gas (flow rate 10 L / min), a reaction temperature of 650 °C, and a growth rate of 0.5 nm / s, an n-type GaAs buffer layer 2 with a thickness of 200 nm was grown. The doping concentration was... ;

[0079] S2, n-type Etching barrier layer 3 growth: silane flow rate 5 sccm, TMAl (flow rate 8 sccm), TMGa (flow rate 12 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) is the growth source. Carrier gas 10 L / min, temperature 750℃, growth rate 0.4 nm / s, growing n-type Etching barrier layer 3 (x=0.2, y=0.5), 200 nm thick, doping concentration... ;

[0080] S3,n-type GaAs ohmic contact layer 4 growth: silane flow rate 10 sccm, TMGa (flow rate 20 sccm) (Flow rate 500 sccm) Carrier gas 10 L / min, temperature 650℃, growth rate 0.2 nm / s, growth of n-type GaAs ohmic contact layer 4, thickness 30 nm, doping concentration... ;

[0081] S4, n type Growth of confinement layer 5: silane flow rate 5 sccm, TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growing n-type Restriction layer 5 ( =0.9, =0.5), thickness 300nm, doping concentration ;

[0082] S5, undoped InGaP / Quantum well structure 6 growth: TMAl (flux 15 sccm), TMGa (flux 5 sccm), TMIn (flux 15 sccm) (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.15 nm / s; alternating growth of 3 pairs of InGaP well layers (3 nm thick) and... Barrier layer ( =0.8, =0.5mm thick (7nm), forming a quantum well structure;

[0083] S6, p type Spacer layer 7 growth: Magnesium dicerocene flow rate 8 sccm, TMAl (flow rate 16 sccm), TMGa (flow rate 4 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, p-type growth Spacer layer 7 ( =0.85, =0.5), thickness 60nm, doping concentration ;

[0084] S7,p-type AlGaInP polarization-induced doped layer 8 growth: Magnesium pyrocene flux 8 sccm, TMIn (flux 15 sccm). (Flow rate 600 sccm) Carrier gas flow rate 10 L / min, temperature 750℃, growth rate 0.3 nm / s; initial stage TMAl flow rate 12 sccm, TMGa flow rate 8 sccm (corresponding to...) ( =0.6, =0.5), and gradually increase the TMA1 flow rate to 18 sccm and decrease the TMAGa flow rate to 2 sccm (corresponding to 0.5) over time. ( =0.9, =0.7), total thickness 60nm, doping concentration ;

[0085] S8, Insertion layer 9 growth: TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm) (Flow rate 500 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growth Insertion layer 9 ( =0.9), thickness 20nm;

[0086] S9, n-type Ohmic contact layer 10 growth: silane flow rate 10 sccm, TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growing n-type Ohmic contact layer 10 ( =0.9, =0.5), thickness 60nm, doping concentration ;

[0087] S10, chip back-end process:

[0088] The epitaxial wafer and the Si-based CMOS driver are connected by gold-gold bonding (temperature 300℃, pressure 5MPa);

[0089] use : : An etchant solution with a ratio of 3:1:10 was used to etch and remove GaAs substrate 1, n-type GaAs buffer layer 2, and n-type GaAs buffer layer 3 at 60°C. Etch barrier layer 3 to expose n-type GaAs ohmic contact layer 4;

[0090] Photolithography defines the mesa pattern, and dry etching ( / Plasma forms a Mesa structure with a diameter of 20 μm;

[0091] PECVD deposition Passivation layer (100nm thick), photolithography and etching to expose n-type GaAs ohmic contact layer 4 and n-type Ohmic contact layer 10;

[0092] Electron beam evaporation was used to prepare Cr / Au electrodes (Cr thickness 50 nm, Au thickness 500 nm), completing the ohmic contact on both sides in a single step to obtain the final chip.

[0093] Performance testing and comparison:

[0094] The chip prepared in Example 3 and a conventional AlGaInP red LED chip (containing a p-type AlInP confinement layer 5, a p-type AlGaInP superlattice, a p-type GaP hole supply layer, and a heavily doped p-type GaP ohmic contact layer) are subjected to performance testing, and the testing conditions are as follows: room temperature, forward current 20 mA, and the testing results are shown in the following table.

[0095]

[0096] The testing results show that the chip of the present application is significantly superior to the conventional chip in terms of resistance, luminous efficiency, and yield, thereby verifying the effectiveness of the technical solution.

[0097] Finally, it should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the present application, and although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacements to some of the technical features, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An AlGaInP red LED chip structure with a polarization-induced tunneling junction, characterized in that, From bottom to top, the layers consist of: GaAs substrate, n-type GaAs buffer layer, and n-type... Etching barrier layer, n-type GaAs ohmic contact layer, n-type Confinement layer, undoped InGaP / Quantum well structure, p-type Spacer layer, p-type AlGaInP polarization-induced doped layer, Insertion layer and n-type Ohmic contact layer; The composition of the p-type AlGaInP polarization-induced doped layer is from Gradient to Al component =0.6-0.7、 =0.9-1, component ratio =0.5、 =0.7; The Al components of the insertion layer =0.8-1, and is similar to n-type The ohmic contact layer forms a tunnel junction; The n-type Al composition of ohmic contact layer =0.8-1, component ratio =0.

5.

2. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The GaAs substrate has a wafer size of 2-12 inches, a thickness of 350-650 μm, and a bevel angle of 2-15°.

3. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The doping source for the n-type GaAs buffer layer is silane, and the doping concentration is [missing information]. The thickness is 100-300 nm; the doping source of the n-type GaAs ohmic contact layer is silane, and the doping concentration is... The thickness is 10-50nm.

4. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The undoped InGaP / The quantum well structure has 1-5 quantum well pairs, and the InGaP well layer thickness is 1.5-4.5 nm. Al composition of the barrier layer =0.6-0.9, component ratio =0.5, thickness is 4-10nm.

5. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The p-type Al components of the spacer layer =0.8-0.9, component ratio =0.5, the doping source is magnesia-dicenocene, and the doping concentration is The thickness is 30-100nm.

6. A method for fabricating an AlGaInP red LED chip structure with a polarization-induced tunneling junction as described in any one of claims 1-5, characterized in that, The metal-organic chemical vapor deposition (MOCVD) technique is employed, including the following steps: S1, an n-type GaAs buffer layer is epitaxially grown on a GaAs substrate; S2, epitaxial growth of n-type GaAs buffer layer. Etching barrier layer; S3, in n-type An n-type GaAs ohmic contact layer is epitaxially grown on an etch barrier layer; S4, epitaxial growth of n-type GaAs ohmic contact layer. Constraint layer; S5, in n-type Epitaxial growth of undoped InGaP / on confinement layer Quantum well structure; S6, in undoped InGaP / Epitaxial growth of p-type quantum well structures Spacer layer; S7, in p-type p-type AlGaInP polarization-induced doped layer is epitaxially grown on the spacer layer; S8, high Al composition epitaxially grown on a p-type AlGaInP polarization-induced doped layer. Insertion layer; S9, in Epitaxial growth of n-type on the insertion layer An ohmic contact layer is used to obtain an epitaxial wafer; S10, the epitaxial wafer is bonded, substrate removed, mesa structure prepared, passivated and single-step metallized to obtain a chip.

7. The preparation method according to claim 6, characterized in that, In step S2, n-type The etch barrier layer was grown at a temperature of 700-780℃, a growth rate of 0.2-0.7 nm / s, and the doping source was silane with a doping concentration of [missing information]. The thickness is 100-300nm.

8. The preparation method according to claim 6, characterized in that, In step S7, the growth temperature of the p-type AlGaInP polarization-induced doped layer is 700-780℃, the growth rate is 0.2-0.5 nm / s, the dopant source is magnesia-diocene, and the doping concentration is [missing information]. The thickness is 30-100nm; the composition is gradually changed by adjusting the flow ratio of trimethylaluminum to trimethylgallium.

9. The preparation method according to claim 6, characterized in that, In step S8, the high-Al component The growth source for the insertion layer is trimethylaluminum, trimethylgallium and arsenide, the growth temperature is 700-780℃, the growth rate is 0.2-0.5nm / s, and the thickness is 10-40nm.

10. The preparation method according to claim 6, characterized in that, In step S10, the diameter of the mesa structure is 1-50 μm; the passivation layer material is... , or It is prepared by atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD); Single-step metallization employs electron beam evaporation or sputtering processes to prepare Cr / Au or Ti / Al / Ni / Au electrodes.

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