Method, system and apparatus for bit value placement in polarization coding

Abstract

Polarization codes for wireless communications are constructed to accommodate channel conditions. An input bit is encoded by a polar code to obtain an encoded bit, and the encoded bit is decoded to obtain a decoded input bit. The polar code provides or includes a bit index for placing a value of the input bit prior to encoding. The bit indices include a first set of bit indices for placing values of a first subset of the input bits, a second set of bit indices for placing values of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed on one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed on two or more bit indices of the second set of bit indices.

Description

[0001] Cross-references to related applications

[0002] This application relates to the following Patent Cooperation Treaty (PCT) applications filed together by the same applicant on the same date:

[0003] PCT application entitled “Methods, Systems, and Apparatus for Non-Sequential Decoding of Polar Codes”;

[0004] PCT application entitled “Methods, Systems, and Apparatus for Encoded Bit Reduction in Polar Coding”;

[0005] PCT application entitled "Methods, Systems, and Apparatus for Protograph-based Low Density Parity Check Coding"

[0006] This application also relates to the following U.S. provisional patent applications filed on the same date:

[0007] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Partial Code Rate Reduction in Polar Coding”;

[0008] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding”;

[0009] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Low-complexity Decoding”;

[0010] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Incremental Redundancy”;

[0011] A U.S. provisional patent application entitled "Methods, Systems, and Apparatus for Channel-dependent Error Correction Coding". Technical Field

[0012] This application relates to encoding, and more particularly to placing bit values ​​on bit indices in polar coding. Background Technology

[0013] In wireless communication, channel conditions change rapidly and slowly due to fading effects and other factors. Therefore, channel coding is usually designed to adapt to channel conditions. Adaptive modulation and coding schemes (MCS) are a powerful method to combat constantly changing channel conditions, in which the modulation order, code length, and code rate can be changed in real time.

[0014] Adapting to channel conditions requires channel coding that can flexibly change code length and code rate in a fine-grained manner, while maintaining good error correction performance in all possible configurations. This fine-grained flexibility in channel coding remains a challenge.

[0015] Low-density parity-check (LDPC) codes and other probabilistic codes resemble random codes more naturally, making them suitable for flexibility. However, algebraic codes such as Reed-Muller (RM) codes and Bose-Chaudhuri-Hocquenghem (BCH) codes are less flexible than probabilistic codes. This is because their inherent coding structure may be disrupted when the code length or code rate changes. Polar codes possess characteristics of both probabilistic and algebraic codes. Therefore, the flexibility of polar codes lies between that of probabilistic and algebraic codes.

[0016] Rate matching (including techniques such as puncturing and shortening) is a technique used to achieve rate-compatible polar codes, such as those used in the fifth-generation (5G) new radio (NR) 3GPP standard. However, the flexibility offered by traditional polar code rate matching methods is insufficient to support more advanced communication features, such as fine-grained incremental-redundancy hybrid automatic repeat request (IR-HARQ).

[0017] A more flexible channel coding method is needed. Summary of the Invention

[0018] This invention includes embodiments related to bit value placement in polar coding. The embodiments disclosed herein may be useful, for example, for providing any one or more of the following features: coupling shorter codes or code blocks together to achieve self-decoding of shorter codes or code blocks, and checksum functionality between information bits.

[0019] According to one aspect of the invention, a method involves encoding input bits using a polar code to obtain encoded bits and outputting the encoded bits. The polar code includes bit indices for placing values ​​of the input bits prior to encoding, the bit indices comprising: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0020] Another method involves receiving encoded bits and decoding them to obtain decoded input bits. The received encoded bits are encoded using a polar code that includes bit indices for placing the values ​​of the input bits before encoding. The bit indices include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0021] According to an embodiment, an apparatus includes an encoder and an interface. The encoder is used to encode input bits using polar codes to obtain encoded bits, and the interface is coupled to the encoder for outputting the encoded bits. The polar codes include bit indices for placing values ​​of the input bits before encoding. The bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0022] According to another embodiment, the apparatus includes: an interface for encoded bits that have been encoded using a polar code; and a decoder coupled to the interface for decoding the encoded bits to obtain decoded input bits. As in other embodiments, the polar code includes bit indices for placing values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0023] In other device embodiments, the device may include a processor for causing the device to perform the methods disclosed herein.

[0024] The apparatus may include a processor and a non-transitory computer-readable storage medium coupled to the processor and storing a program for execution by the processor.

[0025] Storage media do not necessarily need to be implemented in or in conjunction with such a device. For example, a computer program product may be or include a non-transitory computer-readable medium that stores a program for execution by a processor.

[0026] A program stored in a computer-readable storage medium may include instructions for performing or causing a processor to perform any of the methods disclosed herein.

[0027] For example, the program may include instructions for or to cause the processor to: encode input bits using a polar code to obtain encoded bits, and output the encoded bits. As in other embodiments, the polar code includes bit indices for placing values ​​of the input bits before encoding, the bit indices including: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed at a bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0028] In another embodiment, the program includes instructions for, or for causing, the processor to: receive encoded bits encoded by a polar code, and decode the encoded bits to obtain decoded input bits. The polar code includes bit indices for placing values ​​of the input bits prior to encoding. The bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0029] A system is also disclosed, which may include a first communication device and a second communication device. The first communication device is used to transmit encoded bits that have been encoded using polar codes, and the second communication device is used to receive the encoded bits from the first communication device and decode the encoded bits to obtain decoded input bits. The polar code includes bit indices for placing the values ​​of the input bits before encoding. The bit indices include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0030] This invention includes these and other aspects or embodiments. Attached Figure Description

[0031] To gain a more complete understanding of the present embodiments and their advantages, reference is now made to the following description taken by way of example, in conjunction with the accompanying drawings.

[0032] Figure 1 This is a simplified diagram of a communication system.

[0033] Figure 2 yes Figure 1 A block diagram of an exemplary communication system.

[0034] Figure 3 Examples of exemplary electronic devices and base stations are shown.

[0035] Figure 4 The unit or module in the device is shown.

[0036] Figure 5 This is a trellis diagram of an example of a polar code.

[0037] Figure 6A This is a block diagram of an apparatus according to an embodiment.

[0038] Figure 6B This is a block diagram illustrating the placement of bit values ​​on bit indices according to an embodiment.

[0039] Figure 6C This is a block diagram illustrating an example bit index to tag mapping.

[0040] Figure 6D This is a block diagram illustrating the use of bit tags to place bit values ​​on bit indices according to an embodiment.

[0041] Figure 7 This is a block diagram of code coupling according to an embodiment.

[0042] Figure 8 This is a block diagram of code coupling according to another embodiment.

[0043] Figure 9 This is a block diagram of code coupling and recursive bit value placement according to an embodiment.

[0044] Figure 10 This is a block diagram of code coupling and recursive bit placement according to another embodiment.

[0045] Figure 11 This is a block diagram showing the placement of bit values ​​according to an embodiment.

[0046] Figure 12 This is a block diagram showing the placement of bit values ​​according to an embodiment.

[0047] Figure 13 This is a block diagram showing the bit values ​​placed according to another embodiment.

[0048] Figure 14 This is an exemplary mesh diagram and a block diagram of several features according to the embodiments disclosed herein.

[0049] Figure 15 This is a flowchart of a more general exemplary method according to an embodiment. Detailed Implementation

[0050] For the purpose of illustration, specific exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0051] The embodiments described herein represent information sufficient to practice the claimed subject matter and illustrate methods for practicing such subject matter. Upon reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the claimed subject matter and will recognize that the application of these concepts is not specifically described herein. It should be understood that these concepts and applications are within the scope of the invention and the appended claims.

[0052] refer to Figure 1 A simplified schematic diagram of a communication system is provided as an illustrative example and not a limitation. Communication system 100 includes a radio access network 120. Radio access network 120 may be a next-generation (e.g., sixth-generation, 6G or later) radio access network or a traditional (e.g., 5G, 4G, 3G, or 2G) radio access network. In radio access network 120, one or more electric devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (generally referred to as 110) may be interconnected with each other or connected to one or more network nodes (170a, 170b, generally referred to as 170). Core network 130 may be part of the communication system and may depend on or be independent of the radio access technology used in communication system 100. Communication system 100 also includes a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160.

[0053] Figure 2An exemplary communication system 100 is illustrated. Typically, the communication system 100 enables multiple wireless or wired components to transmit data and other content. The purpose of the communication system 100 may be to provide content, such as voice, data, video, and / or text, via broadcast, multicast, and unicast. The communication system 100 can operate by sharing resources (e.g., carrier spectrum bandwidth) among its constituent components. The communication system 100 may include terrestrial communication systems and / or non-terrestrial communication systems. The communication system 100 can provide a wide range of communication services and applications (e.g., earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery, and mobility). The communication system 100 can provide high availability and robustness through the joint operation of terrestrial and non-terrestrial communication systems. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can enable a heterogeneous network comprising multiple layers. Compared to traditional communication networks, heterogeneous networks can achieve better overall performance through efficient multi-link joint operation, more flexible function sharing, and faster physical layer link switching between terrestrial and non-terrestrial networks.

[0054] Terrestrial communication systems and non-terrestrial communication systems can be considered subsystems of a communication system. Figure 2 In the example shown, communication system 100 includes electronic devices (EDs) 110a, 110b, 110c, and 110d (commonly referred to as ED 110), radio access networks (RANs) 120a and 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. RANs 120a and 120b include corresponding base stations (BSs) 170a and 170b, which are commonly referred to as terrestrial transmit and receive points (T-TRPs) 170a and 170b. The non-terrestrial communication network 120c includes access nodes 172, which are commonly referred to as non-terrestrial transmit and receive points (NT-TRPs) 172.

[0055] Alternatively or additionally, any ED 110 can be used to access, connect to, or communicate with any T-TRP 170a, 170b, and NT-TRP 172, the Internet 150, the core network 130, the PSTN 140, other networks 160, or any combination thereof. In some examples, ED 110a can transmit uplink and / or downlink traffic with T-TRP 170a via terrestrial air interface 190a. In some examples, ED 110a, ED 110b, ED 110c, and ED 110d can also communicate directly with each other via one or more sidelink air interfaces 190b. In some examples, ED 110d can transmit uplink and / or downlink traffic with NT-TRP 172 via non-terrestrial air interface 190c.

[0056] Air interfaces 190a and 190b can use similar communication technologies, such as any suitable wireless access technology. For example, communication system 100 can implement one or more channel access methods in air interfaces 190a and 190b, such as code division multiple access (CDMA), space division multiple access (SDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA). Air interfaces 190a and 190b can use other higher-dimensional signal spaces, which may involve combinations of orthogonal and / or non-orthogonal dimensions.

[0057] The non-terrestrial air interface 190c enables communication between the ED 110d and one or more NT-TRP 172s via a wireless link (or simply a link). For some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection for multicast transmission between a group of ED 110s and one or more NT-TRP 175s.

[0058] RAN 120a and RAN 120b communicate with core network 130 to provide various services, such as voice, data, and other services, to ED 110a, ED 110b, and ED 110c. RAN 120a and RAN 120b and / or core network 130 may communicate directly or indirectly with one or more other RANs (not shown), which may (or may not) be directly served by core network 130 and may (or may not) use the same radio access technology as RAN 120a, RAN 120b, or both. Core network 130 may also serve as a gateway between (i) RAN 120a and RAN 120b, or ED 110a, ED 110b, ED 110c, or both, and (ii) other networks (e.g., PSTN 140, Internet 150, and other networks 160). In addition, some or all of ED 110a, ED 110b, and ED 110c may include the ability to communicate with different wireless networks via different wireless links using different wireless technologies and / or protocols. Instead of wireless communication (or other than wireless communication), ED 110a, ED 110b, and ED 110c may also communicate with service providers or exchanges (not shown) via wired communication channels and with the Internet 150. PSTN 140 may include a circuit-switched telephone network for providing plain old telephone service (POTS). The Internet 150 may include computer networks and / or subnets (internal networks) and include protocols such as Internet Protocol (IP), Transmission Control Protocol (TCP), and User Datagram Protocol (UDP). ED 110a, ED 110b, and ED 110c may be multimode devices capable of operating according to multiple wireless access technologies and may include multiple transceivers required to support these technologies.

[0059] Figure 3Another example of ED 110 and base stations 170a, 170b, and / or 170c is shown. ED 110 is used to connect people, things, machines, etc. ED 110 can be widely used in various scenarios, such as cellular communication, device-to-device (D2D), vehicle-to-everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), machine-type communication (MTC), Internet of Things (IoT), virtual reality (VR), augmented reality (AR), industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, autonomous delivery, and mobility.

[0060] Each ED 110 represents any suitable end-user equipment used for wireless operation and may include (or be referred to as) devices such as: user equipment (UE), wireless transmit / receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular phone, station (STA), machine-type communication (MTC) device, personal digital assistant (PDA), smartphone, laptop, computer, tablet, wireless sensor, consumer electronics device, smartbook, vehicle, automobile, truck, bus, train, IoT device, industrial equipment, or devices within the aforementioned devices (e.g., communication modules, modems, or chips). Next-generation ED 110 may be referred to using other terms. Base station 170a and base station 170b are both T-TRPs and are referred to hereinafter as T-TRP 170. Also... Figure 3 As shown, NT-TRP is referred to below as NT-TRP 172. Each ED 110 connected to T-TRP 170 and / or NT-TRP 172 may be dynamically or semi-statically enabled (i.e., established, activated, or enabled), disabled (i.e., released, deactivated, or disabled), and / or configured in response to one or more of the following: connectivity availability and connectivity necessity.

[0061] ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is shown. Alternatively, one, some, or all of the antennas 204 may be panels. For example, the transmitter 201 and receiver 203 may be integrated as a transceiver. The transceiver is used to modulate data or other content for transmission by at least one antenna 204 or by a network interface controller (NIC). The transceiver may also be used to demodulate data or other content received by at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and / or for processing signals received wirelessly or wiredly. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals.

[0062] ED 110 includes at least one memory 208. Memory 208 stores instructions and data used, generated, or acquired by ED 110. For example, memory 208 may store software instructions or modules executed by one or more processing units (e.g., processor 210) for implementing some or all of the functions and / or embodiments described herein. Each memory 208 includes one or more of any suitable volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, processor cache, etc.

[0063] ED 110 may also include one or more input / output devices (not shown) or interfaces (e.g. Figure 1 (Wired interface of Internet 150 in the network). Input / output devices can interact with users or other devices in the network. Each input / output device includes any suitable structure for providing or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touchscreen, including network interface communication.

[0064] ED 110 includes a processor 210 for performing operations including: those related to preparing transmissions for uplink transmissions to NT-TRP 172 and / or T-TRP 170; those related to processing downlink transmissions received from NT-TRP 172 and / or T-TRP 170; and those related to processing sidelink transmissions to and from another ED 110. Processing operations related to preparing transmissions for uplink transmissions may include operations such as encoding, modulation, transmit beamforming, and generating symbols for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulation, and decoding of received symbols. According to an embodiment, receiver 203 may receive downlink transmissions (possibly using receive beamforming), and processor 210 may extract signaling from the downlink transmissions (e.g., by detecting and / or decoding signaling). Examples of signaling may be reference signals transmitted by NT-TRP 172 and / or T-TRP 170. In some embodiments, processor 210 performs transmit beamforming and / or receive beamforming based on beam direction indications (e.g., beamangle information (BAI)) received from T-TRP 170. In some embodiments, processor 210 may perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as operations related to detecting synchronization sequences, decoding, and acquiring system information. In some embodiments, processor 210 may perform channel estimation using reference signals received from NT-TRP 172 and / or T-TRP 170.

[0065] Although not shown, processor 210 may form part of transmitter 201 and / or receiver 203. Although not shown, memory 208 may form part of processor 210.

[0066] The processing components of processor 210, transmitter 201, and receiver 203 may each be implemented by the same or different processors, which execute instructions stored in memory (e.g., memory 208). Alternatively, some or all of the processing components of processor 210, transmitter 201, and receiver 203 may each be implemented using dedicated circuitry, such as a programmable field-programmable gate array (FPGA), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC).

[0067] In some implementations, T-TRP 170 may be known by other names, such as base station, basetransceiver station (BTS), wireless base station, network node, network device, network-side device, transmit / receive node, NodeB, evolved NodeB (eNodeB or eNB), home eNodeB, next-generation NodeB (gNB), transmission point (TP), site controller, access point (AP) or wireless router, relay station, ground node, ground network device, ground base station, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc. T-TRP 170 can be a macro base station, pico base station, relay node, host node, or a combination thereof. T-TRP 170 may refer to the aforementioned equipment or a device within the aforementioned equipment (e.g., a communication module, modem, or chip).

[0068] In some embodiments, portions of T-TRP 170 may be distributed. For example, some modules of T-TRP 170 may be located remotely from the device housing the antenna 256 for T-TRP 170 and may be coupled to the device housing the antenna 256 via a communication link (not shown) sometimes referred to as a fronthaul (e.g., a common public radio interface, CPRI). Therefore, in some embodiments, the term T-TRP 170 may also refer to modules on the network side that perform processing operations such as determining the location of ED 110, resource allocation (scheduling), message generation, and encoding / decoding, and are not necessarily part of the device housing the antenna 256 of T-TRP 170. These modules may also be coupled to other T-TRPs. In some embodiments, T-TRP 170 may actually be multiple T-TRPs that work together, for example, using coordinated multicast transmissions, to serve ED 110.

[0069] T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is shown. Alternatively, one, some, or all of the antennas 256 may be a panel. The transmitter 252 and receiver 254 may be integrated as a transceiver. T-TRP 170 also includes a processor 260 for performing operations, including operations related to: preparing transmissions for downlink transmission to ED 110; processing uplink transmissions received from ED 110; preparing transmissions for backhaul transmission to NT-TRP 172; and processing transmissions received from NT-TRP 172 via backhaul. Processing operations related to preparing transmissions for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., multiple input multiple output (MIMO) precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to receiving transmissions in the uplink or via backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. Processor 260 may also perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as generating the contents of a synchronization signal block (SSB), generating system information, etc. In some embodiments, processor 260 also generates beam direction indications, such as a BAI, which can be scheduled by scheduler 253 for transmission. Processor 260 performs other network-side processing operations described herein, such as determining the location of ED 110, determining where to deploy NT-TRP 172, etc. In some embodiments, processor 260 may generate signaling, for example, to configure one or more parameters of ED 110 and / or one or more parameters of NT-TRP 172. Any signaling generated by processor 260 is transmitted by transmitter 252. It should be noted that the term "signaling" as used herein may alternatively be referred to as control signaling. Dynamic signaling can be transmitted in the control channel (e.g., the physical downlink control channel, PDCCH), while static or semi-static higher-layer signaling can be included in data packets transmitted in the data channel (e.g., the physical downlink shared channel, PDSCH).

[0070] Scheduler 253 may be coupled to processor 260. Scheduler 253 may be included within T-TRP 170 or operate separately from T-TRP 170. Scheduler 253 may schedule uplink, downlink, and / or backhaul transmissions, including issuing scheduling authorizations and / or configuring schedule-free (“configured authorizations”) resources. T-TRP 170 also includes memory 258 for storing information and data. Memory 258 stores instructions and data used, generated, or acquired by T-TRP 170. For example, memory 258 may store software instructions or modules executed by processor 260 for implementing some or all of the functions and / or embodiments described herein.

[0071] Although not shown, processor 260 may form part of transmitter 252 and / or receiver 254. Furthermore, although not shown, processor 260 may implement scheduler 253. Although not shown, memory 258 may form part of processor 260.

[0072] The processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can each be implemented by one or more processors, which may be the same or different, to execute instructions stored in memory (e.g., memory 258). Alternatively, some or all of the processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can be implemented using dedicated circuitry such as FPGAs, GPUs, or ASICs.

[0073] It should be noted that the NT-TRP 172 is shown as an example of a drone only, and the NT-TRP 172 can be implemented in any suitable non-terrestrial form. Furthermore, the NT-TRP 172 may use other names in some implementations, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is shown. Alternatively, one, some, or all of the antennas may be panels. The transmitter 272 and receiver 274 may be integrated as a transceiver. The NT-TRP 172 also includes a processor 276 for performing operations, including operations related to: preparing transmissions for downlink transmissions to ED 110; processing uplink transmissions received from ED 110; preparing transmissions for backhaul transmissions to T-TRP 170; and processing transmissions received from T-TRP 170 via backhaul. Processing operations related to preparing a transmission for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing transmissions received in the uplink or received via backhaul may include operations such as receive beamforming, demodulating the received signal, and decoding the received symbols. In some embodiments, processor 276 performs transmit beamforming and / or receive beamforming based on beam direction information (e.g., BAI) received from T-TRP 170. In some embodiments, processor 276 may generate signaling, for example, to configure one or more parameters of ED 110. In some embodiments, NT-TRP 172 implements physical layer processing but does not implement higher-level functions such as medium access control (MAC) or radio link control (RLC) layer functions. Since this is only an example, more generally, NT-TRP 172 may implement higher-level functions in addition to physical layer processing.

[0074] The NT-TRP 172 also includes a memory 278 for storing information and data. Although not shown, a processor 276 may form part of the transmitter 272 and / or the receiver 274. Although not shown, the memory 278 may form part of the processor 276.

[0075] The processing components of processor 276, transmitter 272, and receiver 274 may each be implemented by the same or different one or more processors, which execute instructions stored in memory (e.g., memory 278). Alternatively, some or all of the processing components of processor 276, transmitter 272, and receiver 274 may be implemented using dedicated circuitry such as a programmable FPGA, GPU, or ASIC. In some embodiments, NT-TRP 172 may actually be multiple NT-TRPs that work together, for example, through coordinated multipoint transmissions, to serve ED 110.

[0076] T-TRP 170, NT-TRP 172 and / or ED 110 may include other components, but for clarity these components are omitted.

[0077] according to Figure 4 One or more steps of the methods in the embodiments provided herein may be performed by the corresponding units or modules. Figure 4 The diagram illustrates units or modules within a device (e.g., in ED 110, T-TRP 170, or NT-TRP 172). For example, signals may be transmitted by a transmitting unit or a transmitting module. Signals may be received by a receiving unit or a receiving module. Signals may be processed by a processing unit or a processing module. Other steps may be performed by artificial intelligence (AI) or machine learning (ML) modules. The respective units or modules may be implemented using hardware, one or more components or devices executing software, or a combination thereof. For example, one or more of the units or modules may be integrated circuits, such as a programmable FPGA, GPU, or ASIC. It should be understood that if the aforementioned modules are implemented using software executed by a processor, etc., these modules may be acquired by the processor, in whole or in part, for processing in single or multiple instances, individually or together, and these modules themselves may include instructions for further deployment and instantiation.

[0078] Additional details regarding ED 110, T-TRP 170, and NT-TRP 172 are known to those skilled in the art. Therefore, for clarity, these details are omitted herein.

[0079] Having considered communication more generally above, we now turn to specific exemplary embodiments.

[0080] Successive cancellation (SC) is a fundamental decoding algorithm for polar codes. In SC decoding, all frozen bits and information bits are decoded bit-by-bit according to the defined decoding order of the polar code. By convention, the decoding order is the natural order of the polar code bit indices where all frozen bits and information bits are placed. Therefore, this traditional decoding order is called the "natural order." Before decoding the current bit, the bits preceding the natural order are always decoded first.

[0081] Successive cancellation list (SCL) is an enhanced decoding algorithm for polar codes, in which multiple (L) SCL decoding instances are performed. Each instance is called a "decoding path". During decoding of each binary bit, both the "0" and "1" branches are expanded to each path, creating 2L paths. All 2L paths are then compared, with the L most likely paths retained and the L least likely paths discarded (or pruned). Path expansion and pruning operations are performed during the decoding of each information bit until all information bits have been decoded. Finally, the most likely path is selected as the decoded output.

[0082] The working principle of CRC-aided successive cancellation list (CA-SCL) decoding is almost the same as that of SCL, except that in the last step, the path most likely to pass the CRC check is selected as the decoding output.

[0083] The working principle of parity-check successive cancellation list (PC-SCL) decoding is almost the same as that of SCL. The difference is that when decoding parity-check (PC) bits, the parity check value of the preceding associated bits is used as the bit decision result. In code construction, in addition to frozen bits and information bits, PC bits are also generated.

[0084] Polar codes are linear block codes. For a polar code of length N, its generator matrix is ​​G. N Its encoding process is as follows in, And it is a binary input vector. And it is a binary code vector. The N×N binary generator matrix is... in, And it is a polarization kernel matrix (also known as an Arikan kernel or Arikan matrix). This represents the Kronecker product operation, and n = log₂N.

[0085] By encoding K information bits into N code bits, with K < N, a code rate R = K / N < 1 is obtained. This means that only a fraction of the is used to carry information bits, and the remaining bits of the

[0086] are typically set to fixed values and are called frozen bits. The set of information bits (or information set) can be denoted by I, and the set of frozen bits (or frozen set) can be denoted by F. Sometimes there is also an additional set of PC bits, denoted by P. The frozen bits are known and are usually set to all zeros before decoding, so they do not carry any information. The PC bits are parity-check bits for a subset of the information bits and are thus known once the associated information bits are decoded. The decoding of a polar code attempts to recover all the information bits.

[0087] Figure 5 is a trellis diagram of an example of a polar code, where N = 8 and K = 4. Each "butterfly structure" in the figure is a polarization, and a butterfly structure is shown by example on the Figure 5 right side of the In the example shown, the unshaded circles on the left represent the information set I = {u4, u6, u7, u8}, and the shaded circles represent the frozen set F = {u1, u2, u3, u5}.

[0088] Figure 5 the input vector u on the left in Figure 5 and the code vector x on the right in

[0089] Thus, polar codes can be considered to provide or include bit indices, bit positions, bit channels, or sub-channels for bit values. These bit indices, bit positions, bit channels, or sub-channels are not necessarily used only for the bits to be encoded. For example, vector elements u1…u N It is also referenced in decoding, so the decoded bit value can be similarly associated with bit index, bit position, bit channel, or sub-channel.

[0090] exist Figure 5 To the right of the code vector x, the code vector x also includes multiple elements located at bit positions or bit indices. The bit value at the i-th bit index in the input vector u has some influence on multiple code bits in the code vector x, but the bit value at the i-th bit index in the input vector u is the main contributor to the value of the corresponding code bit at the i-th bit index in the code vector x. In this sense, for polar codes, the input vector bit index or bit position can be considered to correspond to, be associated with, or be related to the code vector bit index or bit position. This is the case for polar codes; for other types of codes, there may be different input / code bit correspondences, relationships, or associations.

[0091] Regarding encoding, the encoding process can be represented in any of a variety of ways. For example, encoding can be described as encoding bits to obtain encoded bits or generating encoded bits. For example, the encoding process described above... This can be represented as generating or otherwise acquiring an encoded input (input vector u in this example) including bits or bit values ​​for encoding, to acquire or generate multiple encoded bits (code vector x in this example).

[0092] From an encoding perspective, for example, the bit value of an element in an input vector u can be called the value to be encoded or a bit, or the value or bit used for encoding. A block of bits or bit values ​​used for encoding is sometimes also called a code block. For example, the bit value of an element in a code vector x can be called an encoded bit or coded bit, and such a block of bits can be called a codeword.

[0093] From a decoding perspective, decoding can be referred to as decoding encoded bits, codewords, or codes, or, for example, decoding, obtaining, or recovering (encoded) bits or bit values ​​from encoded bits, codewords, or codes. In the context of decoding, the bit values ​​of elements in vector u can be referred to as decoded or recovered bits or bit values.

[0094] In 5G NR, PC polar codes are adopted to increase the minimum code distance of traditional polar codes. In PC polar codes, the value of a parity-check bit (also simply referred to as a parity-check bit) is determined by the information bits before it (i.e., the information bits before the parity-check bit in the natural encoding and decoding order of the polar code). Specifically, the determination of the parity-check bit can be a binary linear combination of a subset of the previous information bits. The binary linear combination is specified by the PC function and can be expressed as:

[0095] u i +u j +…+u k =0,

[0096] where i < j < … < k are bit indices. In this example, k is the largest index in the PC function, called the PC bit, and its value is the binary sum of all other bits in the PC function, and these bits are the previous bits with lower bit indices.

[0097] The PC bit positions of the PC set are selected from the indices in the non-frozen bit set (i.e., the above information set I) with the minimum row weight in the polar transformation matrix G N . The non-frozen bit set is the complement of the frozen set.

[0098] The 5G NR polar code uses a simple and hardware-friendly PC function at fixed intervals. When the fixed interval is set to 5, for the PC bit u k with index k, its value is based on all previous information bits at intervals of 5, and set u k =u k–5 +u k–10 +u k–15 +…. The PC bit can be easily generated by a cyclic shift register with the same length as the fixed interval. See "Parity-Check Polar Coding for 5G and Beyond" by H. Zhang et al., 2018 IEEE International Conference on Communications (ICC), 2018, pp. 1 - 7, doi: 10.1109 / ICC.2018.8422462.

[0099] PC polar codes have also been proposed to support IR-HARQ. In one implementation, PC bits are used to couple multiple retransmissions to a longer polar code with additional coding gain. See M.-M. Zhao, G. Zhang, C. Xu, H. Zhang, R. Li, and J. Wang, “An Adaptive IR-HARQ Scheme for Polar Codes by Polarizing Matrix Extension,” IEEE Communications, Vol. 22, No. 7, pp. 1306-1309, July 2018, doi:10.1109 / LCOMM.2018.2825370.

[0100] In the PC function used for IR-HARQ, some information bits are copied from the initial transmitted code block to the retransmitted code block. This one-to-one parity check between two shorter code blocks effectively couples the two code blocks into a longer code block.

[0101] For example, consider the initial transmission of a polar code (M1=8, K=5), where {u0,u1,u2,u3,u4} is the information set, {u5,u6,u7} is the frozen set, the bit indices are in descending order of reliability, and the transmitted code bits are c0, c1, c2, c3, c4, c5, c6, c7. In the first retransmission, four additional code bits c8, c9, c1, c2, c3, c4, c5, c6, c7 are transmitted. 10 c 11 These 4 code bits are coupled with the initial 8 bits to form a polar code (M2 = 12, K = 5). This coupling is achieved by copying the value of u4 to u8 during encoding, thereby generating a PC function u4 + u8 = 0 (or equivalently, u8 = u4). The smallest index in this PC function corresponds to the PC bit (u4 in this case). During decoding, u8 is decoded into information bits, while u4 is decoded into PC bits using the PC function u4 + u8 = 0 (or equivalently, u8 = u4). In this example, {u0, u1, u2, u3, u8} is the information set, {u4} is the PC set, and {u5, u6, u7, u9, u8} is the PC set. 10 ,u 11} represents the frozen set. In the second retransmission, four additional code bits c are transmitted. 12 c 13 c 14 c 15 This forms a polar code (M3=16, K=5), but no new PC bits are generated in the second retransmission.

[0102] Existing PC polar codes are used to improve minimum code distance or to couple short code blocks into longer code blocks. However, they have several drawbacks.

[0103] For example, consider the 5G NR polar codes that currently use PC functions at fixed intervals. While the method for generating PC functions may be simple, it is also limited in design space; for instance, a PC function can only be defined to place a parity bit value on a single bit index. Placing bit values ​​on two or more bit indices would involve many PC functions, which could be overly complex to describe and implement.

[0104] Furthermore, the PC function that copies the value of u4 to u8 during encoding, as described above by example, can only couple two blocks. This type of PC function generation method is limited because it does not support coupling more than two blocks.

[0105] The previously proposed PC function generation (information bit duplication) method for IR-HARQ couples one or more of the least reliable information bits from the initial transmission (u4 in the example above) with one or more of the most reliable bit positions in the retransmission (u8 in the exemplary first retransmission above). For example, this rule can lead to severe performance degradation when the coupled code blocks have very different lengths.

[0106] In the example above, when it comes to supporting more general coupling between multiple code blocks, the PC function description is also inefficient in describing, defining, or specifying how these functions are performed in, for example, communication standards or specifications.

[0107] Another potential problem with the example provided above is the presence of many frozen bits in current PC polar codes. These frozen bits are typically set to zero (or another known value) and do not carry any information, which can negatively impact code performance.

[0108] Some of the embodiments disclosed herein are intended to address and provide a more general approach to coupling shorter polar codes or codewords together. When coupling more than two code blocks, the description (e.g., in communication standards or specifications) and implementation (e.g., in hardware) of the PC function in current PC-based bit methods are not efficient.

[0109] The disclosed embodiments may also, or alternatively, relate to the technical problem of implementing self-decoding of polar codes. All information bits can still be recoverable when only a subset of the code bits of a self-decoding polar code is received (e.g., this is possible under deep fading).

[0110] In some embodiments, bits that provide or support check type features can carry additional information. This differs from traditional techniques where PC bits do not carry information.

[0111] The bit value placement disclosed herein involves placing bit values ​​on bit indices used for encoding. In some embodiments, this may involve assigning tags to bit values ​​(or equivalently, assigning bit values ​​to tags) and assigning tags (and thus bit values) to bit indices (or equivalently, assigning bit indices to tags (and thus bit values)) for encoding. These features may be equivalently, or more generally, referred to as placing bit values ​​on bit indices.

[0112] Although tags are mentioned in the context of many embodiments of the invention, not all embodiments necessarily involve tags. Tags are proposed as a convenient way to manage the placement of bit values ​​on bit indices, but bit value placement is not in any way limited to the use of tags. Bit values ​​can be placed on bit indices without first assigning the bit value to a tag (or assigning a tag to a bit value). The features disclosed herein in conjunction with tags can also be applied to bit values, or alternatively.

[0113] Now let's look at an example using labels, where K represents the number of input bits to be encoded. Labels in {1, 2…K} (or equivalently, {0, 1…K–1}) can be assigned to each input bit and thus associated with each input bit. In the input vector used for encoding... In this process, bit indices with the same binary value are assigned the same label, thus being associated with the same label; or in other words, the same label is assigned to those bit positions in the input vector.

[0114] More generally, bit indices with the same binary value are assigned the same bit value, thus associating them with the same bit value; in other words, the same bit value is assigned to those bit indices in the input vector. Bit values ​​are placed (possibly using labels) on bit indices for encoding. The same bit value is placed on multiple bit indices and can be considered for assignment to and / or association with multiple bit indices. In some embodiments, such bit value placement can be used to create a form of check type function for any bit indices sharing the same bit value and the same label. A check type function is created when multiple bit indices are associated with the same bit value or label. When the same bit value is placed on two bit indices (e.g., associated with the same label), the check type function is paired and associates the two bit indices and the bit values ​​on those bit indices with each other. In some embodiments, because the same bit value is placed on multiple bit indices and associated with the same label, the relationship between the corresponding check type functions or bit indices (and correspondingly, the bit values ​​on those bit indices) can be considered to have a higher dimension or order than two (where two would be paired). Alternatively, the corresponding check type function or relation can be considered as a relationship between any pair of multiple pairwise functions or multiple bit indices, with the same bit value placed on multiple bit indices, or with the same label assigned to multiple bit indices (and the bit values ​​on those commonly labeled bit indices).

[0115] In some embodiments, a longer code block to be encoded is divided or segmented into several shorter code blocks (also referred to herein as sub-code blocks or sub-blocks), and a set of bit values ​​or tags (or a subset of such a set) is placed or assigned to each code block and the sub-channel or coded bit position associated with each code block. Code blocks in which overlapping sets of bit values ​​are placed or tag sets including one or more of the same tags are assigned are effectively coupled to each other through one or more common bit values ​​or one or more tags. The common bit values ​​or tags associated with multiple code blocks not only create a check type function or relationship between individual bit indices and bits, but also couple the information bits, code blocks, and encoded code bits together.

[0116] The embodiments disclosed herein differ fundamentally from the existing methods described above.

[0117] For example, according to one aspect of the invention, bit values ​​or tag sets (or subsets) are placed on or assigned to bit indices, rather than allocating a code rate (or equivalently, the number of information bits). The code rate of a codeword is not fixed. In bit indices with the same bit values ​​or tags, the bits decoded first can be used as information bits and counted in the code rate, while other bits on indices sharing the same bit values ​​or tags are determined based on the bit values ​​or tags and are not counted in the code rate. Therefore, using bit value placement as disclosed herein, the code rate may be uncertain during code construction and encoding, and thus bit value placement is not equivalent to code rate allocation.

[0118] Determining these sizes, considering the size of the bit values ​​or tag set (or subset) allocated to each code block, also differs from rate allocation. According to embodiments described herein, bit values ​​or tags can be assigned to bit indices across multiple code blocks, whereas in rate allocation, information bits can only be allocated to one code block. For example, in conventional techniques, a long code block used for encoding might have K bits, where K... - K bits are allocated to the upper sub-block. + Each bit is allocated to the next sub-block, and it is strictly guaranteed that: K = K - +K + Using the sub-block and bit value placement as disclosed herein, long code blocks can have a set of bit values ​​or tags L, where, for example, a subset L - Assigned to the upper sub-block, subset L + It is assigned to the next sub-block. Certain bit values ​​or tags can appear simultaneously in L. - and L + In this context, |L| represents the size of the tag set L. In some embodiments, the following may apply: |L| ≤ |L - |+|L + |

[0119] Bit values ​​or labels can be assigned based on any of a variety of parameters or criteria. For example, embodiments may involve assigning bit values ​​or labels based on one or more of reliability, bit index, etc., according to any of a variety of rules. Reliability can be considered as a measure or indication of how likely a bit value will be correctly decoded or decodeable at the decoder. Other related terms or descriptors include capacity, probability or likelihood of error, and probability or likelihood of error-free decoding. Reliability is used primarily herein, but the features disclosed herein in the context of reliability may also be applied, or alternatively, to other measures or indicators of capacity, probability or likelihood of error, probability or likelihood of error-free decoding, or ranking or preference among bit indices to place input bit values ​​used for encoding.

[0120] These and other aspects and embodiments are described in further detail below, at least.

[0121] Before encoding, bit indices or positions (sub-channels) of bit values ​​can be assigned and associated with tags; this is one possible way to place bit values ​​on bit indices. These bit indices include at least the information bit index of the value of the input bit to be encoded (also referred to herein as the information bit), and may also include the frozen bit index of frozen bits set to predetermined known bit values. For both information bits and frozen bits, the frozen bit position can be marked as "0" or other values ​​not used for information bits, and the information bit positions (K) can be marked as l∈{1,2…K}. More generally, the information bit index is used to place the input bit value, while the frozen bit index is used to place the predetermined value. Code construction and encoding can be performed based on the bit value placement.

[0122] For multiple bit indices assigned the same tag or with the same bit value, once the bit value of any of these bit indices is decoded, the remaining bits at the indices with the same bit value or tag are immediately known, because the relation or check type function is created through common, shared bit values ​​or tags. Decoding the input bit of the first bit index among the bit indices with the same bit value or tag can be based on polar codes, while decoding the other bit indices associated with the same bit value or tag can be simplified to placing the bit value at the same value as the first decoded input bit, based on the tag or the same bit value being placed at those other bit indices. In this sense, in terms of encoding and decoding, the first decoded bit is treated as an information bit. The other information bits at the bit indices associated with the same bit value or tag do not need to undergo the same decoding as normally applied to information bits, and in this sense can be considered a form of check bit.

[0123] Figure 6A This is a block diagram of an apparatus that can implement or support the embodiments disclosed herein. Exemplary apparatus 600 includes an encoded bit index selector 602, a polar encoder 604 coupled to the encoded bit index selector, and an optional rate matching module 606 coupled to the polar encoder. Input bits for encoding are shown as input transport blocks (TBs) or payload bits, and (optionally, rate-matched) encoded bits are shown as the output of apparatus 600. In the illustrated example, an interface for transmitting or otherwise outputting encoded bits may be provided, incorporated into, or coupled to the polar encoder 604 and the rate matching module 606.

[0124] The encoding or transmitting side features or functions, as well as other features or functions described herein, can be implemented in any of a variety of ways, such as in one or more components of hardware, firmware, or execution software. This invention is not limited to any particular type of implementation; for example, implementation details may differ between different devices.

[0125] In the exemplary device 600, an encoded bit index selector 602 represents a logic unit that, for example by executing software, places bit values ​​on bit indices for encoding by a polar encoder 604. The polar encoder 604 is used, for example by executing software, to encode input bits to obtain encoded bits. A rate matching module 606 is used, for example by executing software, to perform rate matching and may include a cyclic buffer for storing the encoded bits from the polar encoder 604.

[0126] Device 600 is intended to be an illustrative example only. Embodiments are not in any way limited to the implementations shown. Device embodiments may include fewer, additional, and / or different components.

[0127] More generally, the means for providing or supporting the features disclosed herein can be implemented in any of a variety of ways. The means or components thereof (e.g., the encoded bit index selector 602, the polar encoder 604, the rate matching module 606, or the processor) can be used, or the program can include instructions for or to cause the processor to: encode input bits and output encoded bits. Other features disclosed herein, including decoding-side or receiving-side features, can be similarly implemented in the means embodiments. For example, the means may include an interface for receiving encoded bits and a decoder for decoding the encoded bits to obtain decoded input bits, and these and / or other components may be used to provide or support other features. The means need not include these specific components, and therefore, generally, the means or components thereof (e.g., the processor) can be used, or the program may include instructions for or to cause the processor to: perform or otherwise provide or support the decoding-side or receiving-side features disclosed herein.

[0128] Figure 6B This is a block diagram illustrating the placement of bit values ​​at bit indices according to an embodiment. Bit value placement can involve or be based on a mapping from bit indices (or bit positions) to bit values, and may also be referred to as a mapping from bit values ​​to bit indices or bit positions, or a mapping between bit indices or bit positions and bit values. This mapping can be either a one-to-one mapping or a many-to-one mapping.

[0129] A one-to-one mapping can be defined or represented as i→p, where, for example, i is... Figure 6B The bit index of the bit position in the input vector shown, p is Figure 6BThe input sequence is shown as an index of a bit value in a sequence of bit values. For example, the input vector bit u is mapped one-to-one with each bit value. i If there is only one frozen bit, it can be either a frozen bit or an information bit of the input bit value that is not placed on any other bit index. In this sense, a one-to-one mapped information bit is an information bit that has not been checked by any other information bits in the input vector. This mapping can be called a direct mapping between bit values ​​and bit indices because it does not use labels. Figure 6B The mapping N→K in the diagram is an example of a direct one-to-one mapping.

[0130] A many-to-one mapping can be defined or represented as {i1,i2,i3…}→p, where i1, i2, i3… are bit indices of bit positions, and p is the index of the bit value to which these bit indices are mapped. For example, the mapping {i,j,k}→p is related to a check type function or relation u. i =u j =u k Consistent. In {i,j,k}, if bit u is decoded first... j Then the other bits u i and u k Take the same u j The decoded value, and in this sense u i and u k It is an information bit, but can be considered a form of check bit. A many-to-one mapping from a bit index to a bit value (or a one-to-many mapping from a bit value to a bit index) is a direct mapping between a bit value and multiple bit indices, and vice versa. Figure 6B The mapping of input bit values ​​a1 and a2 is an example of a direct one-to-many or many-to-one mapping.

[0131] exist Figure 6B In the input sequence bit values, the input bit values ​​include the input bit values ​​(a i The input bit sequence represents the input block for channel coding, and the bit values ​​in this bit sequence are denoted by a1, a2, ..., a... K This indicates that K represents the number of bits to be encoded. Based on... Figure 6B The bit index / value index mapping shown on the right places the bit values ​​in the input bit sequence and the predetermined bit values ​​of the frozen bits (0 in the example shown) into the binary input vector u1, u2, ..., u that has polar coding applied. N The arrows between the input sequence bit values ​​and the input vector bit values ​​are intended to indicate the bit value positions, according to which the input vector bit values ​​are placed as input sequence bit values. For completeness, also... Figure 6B The image shows the placement of the predetermined bit value 0 for the frozen bit.

[0132] Figure 6B The example shown illustrates the predetermined freezing of bit values ​​0 and the placement of bits in the binary input vector u1, u2, ..., u N The input bit values ​​a1, a2, ..., a in the bit index are... K Using the notation introduced above, if i→p represents a one-to-one mapping or {…i…}→p represents a many-to-one mapping, then u i =a p .

[0133] The placement of the predetermined value 0 of all frozen bits and the input bit values ​​of the input bit sequence {1,2…K} can be described by a mapping sequence. i∈{1,2…N} represents the bit index of the bit position used for encoding, and l∈{0,1…K} represents the predetermined value 0 of the frozen bits and the input bit values ​​a1,a2,…,a…k ... K The bit value index, a one-to-one mapping i→p can be used with l(u i The many-to-one mapping {i,j,k}→p can be represented by l(ui)=l(uj)=l(uk)=p, and the mapping sequence can be represented by l(u1),l(u2),…,l(uj)=p. N ) represents, where N is the mother code length or the total number of bit indices. For Figure 6B In the example shown, the mapping sequence can be described as {0,0,0,...,1,2,...,1,2,3,...,K}.

[0134] In some embodiments, bit value placement may involve tags. The mapping from bit index (or bit position) to tag (also referred to as the mapping from tag to bit index or bit position, or the mapping between bit index or bit position and tag) can be a one-to-one mapping or a many-to-one mapping, just like the bit index / bit value mapping.

[0135] A one-to-one mapping using tags can be defined or represented as i→p, where i is the bit index of the bit position as described above, and p is the index of the tag. For example, the input vector bit u is mapped one-to-one with the tag. i If there is only one frozen bit, it can be a frozen bit or an information bit that does not share a tag with any other information bits (and is not verified by any other information bits in some sense).

[0136] A many-to-one mapping using tags can be defined or represented as {i1,i2,i3…}→p, where i1, i2, i3… are the bit indices of the bit positions as described above, and p is the index of the tag to which these bit indices are mapped. For example, the mapping {i,j,k}→p is related to a check type function or relation u. i =u j =uk Consistent. In {i,j,k}, if bit u is decoded first... j Then the other bits u i and u k Take the same u j The decoded value, and in this sense u i and u k It is an information bit, but can be considered a form of check bit.

[0137] Figure 6C This is a block diagram illustrating an exemplary bit index to tag mapping. Figure 6C In this document, the mapping from bit index to tag is represented by the bit index on the left and the tag index on the right. The mapping above is a one-to-one mapping, and the mapping below is a many-to-one mapping. Tag mapping is optional, and bit indexes can alternatively be mapped directly to bit values ​​or indices instead of via tags, as described above and elsewhere in this document. In some embodiments, using tag mapping instead of direct mapping may be preferred. For example, when the bit values ​​of input bits are unknown in the text of a communication standard or specification, tags can be used to represent the input bit values. Therefore, it is more convenient to describe bit mapping and bit value allocation by using tags as a reference form for bit values. Tag-based descriptions can also be logically clearer when describing different functions, such as readout and allocation rules or conditions, which will be described below.

[0138] Figure 6D This is a block diagram illustrating the use of bit tags to place bit values ​​at bit indices according to an embodiment. Figure 6D In this context, the input sequence bit values ​​include the input data bit values ​​(a i ), and for completeness, the predetermined bit value 0 is also shown. Figure 6D The diagram also illustrates the bit values ​​of a tag sequence, where each individual element in the sequence is a tag assigned to a bit position or bit in the input vector used for encoding. Arrows between bit values ​​and tag sequence bit values ​​indicate tag assignment and the setting or allocation of bit values ​​to tags. Tags include those uniquely assigned to and associated with bit positions in the input sequence, as well as frozen bit tags in the illustrated example. For encoding the input bit sequence, tags are set to the bit values ​​of the input bits. This can be equivalently referred to as tags assigned to input bits or input sequence bits (or values), or as tags assigned to input bits or input sequence bits (or values). The relationship between each of the K input bits and its assigned tag is unique, because each input bit has only one uniquely assigned tag, and no single tag is assigned to any other input bit. This can be considered as another form of one-to-one mapping between input bit positions (or bits) in the input bit sequence and their corresponding tags.

[0139] Figure 6D The input bit sequence in the code represents the input block for channel coding, and the bit values ​​in this bit sequence are denoted by a1, a2, ..., a k Let K be the number of bits to be encoded. The tag sequence is represented by l0, l1, l2, ..., l K This indicates that each label l1, l2, ..., l K It is associated with the input bit position and the input bit to be encoded; if it is tag l0, it is associated with a predetermined frozen bit value. Based on Figure 6D The labels and bit index / label mapping shown on the right assign predetermined bit values ​​and bit values ​​in the input bit sequence to the binary input vector u1, u2, ..., u that has been polar-coded. N The bit index in the input vector. The arrow between the tag sequence bit value and the input vector bit value is intended to indicate the assignment of the tag to the bit position in the input vector, and the bit value assignment, according to which the input vector bit value is set to a predetermined bit value or the input sequence bit value.

[0140] exist Figure 6B and Figure 6D In the bit placement examples shown (without labels and with labels respectively), the predetermined frozen bit value 0 and the input bit values ​​a1, a2, ..., a K Placed at the bit index. For each tag, the bit value is assigned as the tag sequence l0, l1, l2, ..., l K The value of , where l0 = 0 (or any predetermined frozen bit value), and l p =a p Where p = 1, 2, ..., K. Then, the bit values ​​are 0, a1, a2, ..., a K (Optionally, the bit values ​​assigned as labels) are placed in the binary input vector u1, u2, ..., u N In the bit index. Using the notation introduced above, if i→p represents a one-to-one mapping or {…i…}→p represents a many-to-one mapping, then u i =a p (or l in the marking example) p )

[0141] The mapping sequence describing the placement of bit values ​​can include the bit value indices from the previous example, or the labels from the label implementation. A one-to-one mapping i→p can be represented by l(u i The expression ) = p represents a many-to-one mapping {i,j,k} → p, which can be represented by l(u i )=l(u j )=l(u k The mapping sequence can be represented as l(u1), l(u2), ..., l(u...).N ) represents, where N is the mother code length or the total number of bit indices. For Figure 6D The example shown can be described as {l0,l0,l0,...,l1,l2,...,l1,l2,l3,...,l K}

[0142] For example, mapping sequences can be defined in communication standards or specifications, or generated according to procedures specified by such standards or specifications (whether mapping sequences represented or defined using bit value indexing or labels). Generating such mapping sequences online is one possible option.

[0143] In some embodiments, bit value placements as disclosed herein, including but not limited to bit tags, may be used in conjunction with coupled or nested codes.

[0144] One option for code coupling is to divide a code block into multiple shorter, non-overlapping code blocks (also referred to herein as sub-code blocks or sub-blocks) and assign a set (or a subset of that set) of bit values ​​or tags to the bit indices in each code block. If bits in multiple code blocks have the same bit value or tag, that bit value or tag couples these code blocks together, and therefore also couples their corresponding coded blocks (also referred to herein as codewords). There can be more than one common bit value or tag that couples code blocks and coded blocks together in this way. Multiple coded blocks can be further coupled together by performing an XOR operation on the bits of these coded blocks.

[0145] Figure 7 This is a block diagram of code coupling according to an embodiment. Figure 7 The examples shown include code coupling based on mapping sequences and code coupling based on XOR.

[0146] B represents the number of code blocks (three, determined by...). Figure 7 (represented by the input vector in K) i Let K1 represent the number of information bits in the i-th code block. Without loss of generality, consider an illustrative example where K1 <K2<…<K B , among which, Figure 7 In this case, B = 3. At least K must be allocated. i The most reliable bit positions are used to encode the information bits in the i-th code block. In embodiments that support a many-to-one mapping of multiple bit positions to a single bit value or tag within a single code block, K is assigned. i More than one of the most reliable bit positions.

[0147] For ease of reference, the bit values, tag set, or subset of the i-th code block are represented by L. iThis indicates that the bit values ​​or tag set of a code block are a subset of the bit values ​​or tag set of another code block. Specifically, any of the following conditions should be met (where, in...). Figure 7 In the middle, B=3):

[0148] (as in) Figure 7 (in the example)

[0149] and and And...and

[0150] The code blocks do not overlap, and for this example, it is assumed that the length of each code block is a power of 2. Other code block lengths are possible; a power of 2 is just an example.

[0151] By performing an XOR operation (such as...) Figure 7 (As illustrated by example), or potentially combining codewords or portions of codewords in some other way, coupled codewords already coupled to one or more other codewords via common bit values ​​or labels in their corresponding input vectors can be further coupled to each other. Figure 7 In the middle, c i The coupled codeword is obtained as follows: c i =c' i ⊕c' j The codewords combined to obtain coupled codewords can have the same or different lengths. See again... Figure 7 If c' i and c' j Having different lengths N i and N j And N i <N j Then only a subset of the bits of the longer codeword, such as c' j The last N in i code bits (or the first N) i One code bit, or N i Another subset of the code bits is XORed with c' i The codewords are combined. The XOR operation is an example of combination; in other embodiments, other types of combination can be used to combine codewords to obtain coupled codewords.

[0152] Below are two exemplary ways to couple codewords through combination, particularly through the XOR operation in these illustrative examples.

[0153] Example 1:

[0154]

[0155] Example 2:

[0156]

[0157] These are illustrative and non-limiting examples, and the embodiments are not in any way limited to these or any other type of codeword combination.

[0158] like Figure 7 As illustrated by the example, even if the code blocks (which are the input vectors in the diagram) do not overlap, the bit values ​​or tag sets of the code blocks may overlap, such as... As shown. The bit positions in each code block are associated with common, shared bit values ​​or tags (l p There is also a many-to-one mapping between them, with public, shared bit values ​​or tags (l) p In fact, the code blocks are coupled together. Figure 7 The code blocks and codewords in the code are coupled in two ways: by bit value placement (e.g., using tags) and by codeword combination. Bit value placement (instead of bit tags or no tags) can be used in conjunction with the codeword combination shown, or independently of the codeword combination.

[0159] According to another possible option for code coupling, the code block comprises multiple overlapping nested code blocks, and a set of bit values ​​or tags (or a subset of that set) is placed on or assigned to a bit index in each code block. Figure 8 This is a block diagram of code coupling according to this embodiment. In the example shown, for example, a larger code block (in Figure 8 The middle part is shown as u, which is consistent with Figure 6 and Figure 7 (The symbols in the code are consistent) including shorter code blocks u + and u - Code blocks u and u + Having the same bit value or tag set (L=L) + However, code block u + Bit values ​​or tag set L + subset L - For u - The set of bit values ​​or tags can be referred to as u in a larger code block u. + The patch. This will be explained in more detail below.

[0160] exist Figure 8 In this context, u represents a larger code block. + Represents a shorter code block with the same bit values ​​or tag set, u - is u + The complement of the block satisfies u = [u - ⊕u + ,u + ]. u、u + and u -The corresponding numbers of information bits for encoding are K, K + and K - respectively, and K - < K + < K. Their corresponding bit values or label sets are denoted by L, L + and L - respectively.

[0161] At least allocate the most reliable K, K + and K - bit positions for encoding the information bits in u, u + and u - respectively. For ease of reference, the corresponding information sets of u, u + and u - are denoted by I, I + and I - respectively.

[0162] The K - bit positions allocated for u - are all subsets of the K bit positions of u's information bits, but the K + bit positions allocated for u + are not subsets of the K bit positions of u's information bits.

[0163] L + = L, and L - = l(I - ) = l(I + \I), where l(I) represents the bit value or label set corresponding to the information set I, and I + \ is the difference of the information sets between I + and I. For simplicity, the bit value or label "0" for frozen bits is not included in this example, but the bit value or label set can always include a predetermined bit value or a label assigned with zero or another frozen bit value.

[0164] The property or condition L + = L supports self - decoding of the code block u + , which means that even if not all signals in u - are received, the code block u + can be self - decoded from the encoded bits because u + includes all the information bits in u, or equivalently, L + includes all the labels in L.

[0165] In some embodiments, the bit value placement or marking can be done recursively to construct longer codes, where u + can be further divided into u+- and u ++ , and / or where u - It can be further divided into u -- and u -+ More generally, u * It can be further divided into u *- and u *+ , where * represents any block bit sequence consisting of nested + and - blocks of shorter code.

[0166] There are several ways to provide recursive bit value placement via bit tags or other means. Figure 9 This is a block diagram of code coupling and recursive bit value placement according to an embodiment. Figure 9 The example shown can be considered a less aggressive option for recursive bit value placement or marking, since only one shorter code block is divided or split into shorter blocks.

[0167] According to this option, given the maximum mother code length N0 and the information length K, only one of the shorter code blocks in each level or stage is recursively divided into a shorter code block until the length of the shorter code block becomes less than K, or equivalently, as long as the length of the shorter code block is at least K, or greater than or equal to K. For K input bits, the transmission code length K is the absolute minimum code length that potentially supports correct decoding of the input bits. In practice, the expected shortest transmission code length is N'>K.

[0168] The shorter code blocks further subdivided at each level or stage are preferably those with the same bit values ​​or tag set as the longest code block u. *+ Code blocks to implement u *+ Self-decoding of code blocks. Although it is alternatively possible to recursively divide the padded blocks u in a similar manner. *- However, recursively partitioning only the supplementary block u *- Self-decoding is not provided because the padding u *- The bit values ​​or tag set are only code blocks u *+ A subset of the bit values ​​or tag set (and the bit values ​​or tag set of code block u).

[0169] Figure 9 This shows how to recursively use u *+ The code block is divided into shorter code blocks u *+- and u *++ The preferred option. At each level or stage of the recursive code block partitioning, the following tag set attributes or conditions must be satisfied: L *+ =L * (like Figure 9 (as shown on the right) and Also for L *- =l(I *- )=l(I *+ \I* Although this example primarily refers to recursively dividing a code block into multiple shorter code blocks, bit values ​​can also be placed recursively through bit tagging or other methods.

[0170] Here is an example of pseudocode for a recursive function:

[0171] N = N0;

[0172] While N>N'

[0173] Denote the current block by u*, and its bit indices by 1:N;

[0174] Allocate the most reliable K * bit indices for encoding information bits in u* .

[0175] Assign the bit value or label set L * to u*.

[0176] Denote the code block with bit indices 1:N / 2by u* - ,and the code blockwith indices N / 2+1:N by u* + ;

[0177] Allocate the most reliable K *+ and K *- bit indices for encodinginformation bits in u *+ ,and u *- respectively;

[0178] Assign bit value or label sets L *+ and L *- to u* + ,and u* - Respectively, satisfying L *+ =L * and and L*- =l(I *- )=l(I *+ \I * ).

[0179] u*=u* + ;

[0180] N = N / 2;

[0181] End while

[0182] A more aggressive recursive bit value placement method involves recursively dividing multiple shorter code blocks at each level or stage in order to generate a greater number of shorter code blocks. Figure 10 This is a block diagram illustrating code coupling and examples of this recursive bit value placement and code block partitioning or segmentation.

[0183] According to this method, given a maximum parent code length N0 and an information length K, multiple code blocks are recursively divided into multiple shorter code blocks at each level or stage until the length of any shorter code block is less than the information length of its directly longer "parent" block. In other words, code blocks can be recursively divided as long as the length of each shorter code block is at least (meaning greater than or equal to) the information length of its directly parent block. The information length is a possible parameter that can be used to determine when to end the recursive process. Minimum transmission code length N'>K is another example of this parameter.

[0184] Figure 10 An example is shown where u *+ and u *- The code block is recursively divided into shorter code blocks u at each level or stage. *-- / u *-+ and u *+- / u *++ The following bit values ​​or tag set attributes or conditions must be met at each level or stage: L *+ =L * (like Figure 10 (As shown on the right) And L *- =l(I *- )=l(I *+ \I * At least as mentioned above, for the less aggressive example of recursive partitioning, although this more aggressive example mainly refers to recursively dividing a code block into multiple shorter code blocks, bit placement by bit tagging or otherwise is also recursive.

[0185] Here is an example of pseudocode for such recursive functions:

[0186] N = N0;

[0187] Function assign_bit_values(u*,N,K)

[0188] Denote the current block by u*,and its bit indices by 1:N;

[0189] Allocate the most reliable K * bit indices for encoding informationbits in u*.

[0190] Assign the bit value or label set L * to u*.

[0191] Denote the code block with bit indices 1:N / 2by u* - ,and the code blockwith indices N / 2+1:N by u* + ;

[0192] Allocate the most reliable K *+ and K *- bit indices for encodinginformation bits in u* + ,and u* - ,respectively;

[0193] Assign bit value or label sets L *+ and L *- to u* + ,and u* - ,respectively,satisfying L *+ =L * ,and and L *- =l(I *- )=l(I *+ \I * ).

[0194] K *- =|L *- |;

[0195] K*+ =K;

[0196] assign_bit_values(u* - ,N / 2,K *- );

[0197] assign_bit_values(u* + ,N / 2,K *+ );

[0198] End function

[0199] These examples of recursive code block partitioning or splitting and recursive bit value placement are intended to be illustrative and non-limiting. Various variations are possible.

[0200] For example, for a mother code length that is a power of 2, it is preferable to divide a code block into two shorter code blocks at each stage. However, in other embodiments, a longer code block can be divided into more than two shorter code blocks. Typically, in each recursion, the length is N. * The code can be divided into lengths of N. *a N *b N *c ...blocks, as long as N * =N*a+N *b +N *c +... can be used to add blocks. These blocks can include blocks of equal length, blocks of unequal length, blocks of the same length, and one or more other blocks of different length.

[0201] The embodiments are not limited to shorter code blocks of the same length. For example, in each recursion, the two shorter blocks can have different lengths, such as N. *- and N *+ Instead of N * / 2 and N * / 2, as long as N * =N *- +N *+ That's all.

[0202] At least the various options for code coupling have been described in detail above, and there are also several options for assigning bit values ​​or tags, or sets of bit values ​​or tags, to bit indices.

[0203] Referring to the example of recursive bit value placement above, consider assigning them to u respectively. *+ and u *- Bit values ​​or tag set L *+ and L *- It satisfies L *+ =L * , And L*- =l(I *- )=l(I *+ \I * In short, there exists a set of bit values ​​or tags L used for encoding. *- and L *+ and information set I *- and I *+ Each bit value or tag in the set of bits or tags will be assigned to a bit position in the input vector. Assigning a bit value or tag to a bit position actually results in the bit value being placed at a bit index in the input vector to which encoding is to be applied (i.e., placed on a sub-channel). In some embodiments, specific bit value placement rules are specified. Figure 11 This is a block diagram of bit value placement according to such an embodiment, which includes some exemplary bit value placement rules.

[0204] Some embodiments involve determining the shortest code block u with a length greater than K. *+ For example, N' mentioned above, to achieve self-decoding. Bit values ​​or tag set L *+ The bit value or tag in is assigned to u *+ This means that the bit value or tag set L *+ These bit values ​​or tags in are assigned to I *+ The bit index in the array. This allocation can be based on any of a variety of attributes or conditions, such as a predefined order. Examples of predefined orders include u *+ The reliability order and bit index order in the data. Represents a predefined order, bit value, or label. The bit indices i1, i2…i can be assigned in this order for encoding. K*+ However, it can be, u *+ The bit values ​​or tags in the set of tags may have been mapped in the previous iteration. Retain any previous mappings, rather than remapping previously mapped tags.

[0205] For the two's complement block u *- The bit value or tag set is L *- Bit values ​​or tags in the set of bits or tags are assigned to u *- This assignment can be based on a predefined order, such as u *+ The reliability order or bit index order, etc. Bit values ​​or tags are also ordered by another predefined order, such as u. *- The reliability order or bit index order in the data is mapped to I. *- Bit index in.

[0206] Regarding the placement of bit values ​​in the two's complement block, note... Therefore L *- Each bit value or tag in can also be in L *+ Found it. Accordingly, L *- Each bit value or tag in the array has been associated (assigned) to u. *+ The bit index in L. As a result, L *- All bit values ​​or tags have also been assigned to I *+ The bit index in, and therefore can be used by u *+ The predefined order in (r above) *+ (This indicates) sorting. However, L *- Only K in the middle *- There are 1 element, therefore only r *+ c *- K sharing the same bit value or tag *- Each element can be extracted or used to form a shorter sequence. For ease of reference, this shorter sequence can be represented by z. *+ express.

[0207] u *- The entire bit placement process can include two sub-steps or operations, referred to in this paper as "read" and "allocate". Regarding the "read" sub-step or operation, if a predefined order is used... If we represent the set L, then... *- The bit value or tag in can actually be obtained from u *+ The bit value or tag assigned to be read out or otherwise determined as Then, if for u *- Another predefined order of bit values ​​or tag assignments is used It means that, according to z *- The sequence will come from the set L of the previous sub-step. *- The bit values ​​or tags in the data are assigned to bit indices i1, i2, ..., i K*- (in u *- middle). Figure 12 This is a block diagram showing the placement of this type of bit value.

[0208] For the next iteration, u * =[u *- ,u *+ [Regarded as a new u] *+ And repeat the above operation, from bit value or tag set L *+ The bit value or tag in is assigned to the new u *+ start.

[0209] The order r and z above can be chosen based on any of various parameters or standards (e.g., for a specific encoding application) or otherwise obtained. It should be noted that the order of "read" and "allocate" can be based on different rules. For example, "read" can be performed using one rule, while "allocate" can be performed using a different rule.

[0210] In the following examples, both ascending and descending orders are allowed. Other variations are also possible. These examples, like others in this document, are illustrative and non-limiting.

[0211] The first example involves in Bit values ​​or tags are assigned in the sequence based on reliability, for example, where Q i N represents max - The reliability order of the i-th bit in the master code of length -. This can be used... A subset of, i.e., Q(i1), Q(i2)...Q(i K* ), where only the bit index to be allocated is extracted.

[0212] Another example involves indexing by bit (e.g., [1,2,3…N)). max The bit values ​​or tag assignments of the parent code are given, where the index is the bit index of the sub-channel in the parent code. Subsets i1, i2...i can be used. K Only the indexes to be allocated are extracted.

[0213] It is also possible to assign bit values ​​or tags based on code bit interleaving (after encoding), based on... A sequence, where, for example, πi represents the position of the i-th code bit after interleaving in the mother code. Subsets i1, i2, ..., i... can be used. K Only the indexes to be allocated are extracted.

[0214] Another example involves transmission order (e.g.) The sequence is assigned bit values ​​or tags, where T i This indicates the order; the i-th code bit will be transmitted in this order after encoding. Subsets i1, i2, ..., i can be used. K Only the indexes to be allocated are extracted.

[0215] Some embodiments may provide segmentation-based bit value or tag allocation to allow for u *- and u *+ It performs finer-grained segmentation within the segment and assigns bit values ​​or tags within the segmented parts.

[0216] For example, a segmentation-based bit value or tag allocation method involves assigning u *- Divide into equal-sized sub-blocks (sb)1- sb 2- sb 3- ...), determine the number of information bits in these sub-blocks (K1, K2, K3...), and... *+ Divided into sub-blocks (sb) with the same number of information bits (K1, K2, K3...). 1+ sb 2+ sb 3+ ...). Sort the information bit positions according to a predefined order (such as any of the examples provided above) before segmentation. This method can be called the "equal code bit" method, which refers to sorting u... *- Divide into sub-blocks of equal size.

[0217] Another possible approach (which could be called the "equal code bit+" method) involves using u *+ Divide into equal-sized sub-blocks (sb) 1+ sb 2+ sb 3+ ...), determine the number of information bits in these sub-blocks (K1, K2, K3...), and... *- Divided into sub-blocks (sb) with the same number of information bits (K1, K2, K3...). 1- sb 2- sb 3- Similarly, sorting the information bit positions according to a predefined order (such as any of the examples provided above) can be performed before segmentation.

[0218] In another method (which can be called the "equal information bits" method), u *- and u *+ Each is divided into sub-blocks sb 1+ sb 2+ sb 3+ ...and idiot 1- sb 2- sb 3- ..., so that all sub-blocks share their bit values ​​or tag set L *- Each bit contains an equal number of information bits. As in other exemplary segmentation-based allocation methods described above, the ordering of information bit positions according to a predefined order (such as any of the examples provided above) can be performed before segmentation.

[0219] Partition-based allocation can involve two sub-steps or operations, namely "reading" and "allocating" mentioned above. Figure 13 This is a block diagram showing the bit value placement according to this embodiment. For all sub-blocks, sb can be read out in a predefined order as shown by way of example. i+The bit value or tag and assign it to sb i- The "read" and "assign" sub-steps or operations can be essentially the same as described above, but for specific purposes... Figure 13 Each of the multiple sub-blocks in the example shown is executed.

[0220] For example, the read and distribute order, as well as segmentation parameters and methods such as the number of segments, can be specified in communication standards or specifications to facilitate implementation and improve performance. Table 1 below provides several examples.

[0221] Table 1: Exemplary Order

[0222] Reading order Allocation order Split (number, method) reliability Reverse bit index (1, N / A) reliability transmission (4, Equal code bits-) Bit index Reverse bit index (1, N / A) Bit index transmission (4, Equal code bits-)

[0223] For example, mapping sequences can be defined or alternatively defined in communication standards or specifications, or generated according to the procedures specified in those standards or specifications. Online generation of such mapping sequences is a possible option, and these sequences are generated based on any one of one or more parameters (e.g., reliability sequence, interleaving sequence, transmission order, etc.).

[0224] As an illustrative example, the mapping sequence of the (64, 32) polar code is described in Table 2 below. The entries in the odd-numbered rows (rows 1, 3, 5, and 7, italicized) are bit indices, and the entries in the even-numbered rows (rows 2, 4, 6, and 8, bolded) are tags or indices (or other identifiers) of the bit values. As shown, several bit values ​​or tags (8, 11, 1, 13, 4, 15, 17, 26) appear multiple times and are shared by multiple bit indices.

[0225] Table 2: Exemplary Mapping Sequences

[0226]

[0227]

[0228] As can be seen, there is no fixed "rate allocation" between the first 32-bit sub-block and the second 32-bit sub-block because the bit value or tag set |L - | and | L + | is assigned to these two sub-blocks, instead of being assigned information bits. Even if all bits or positions of tag l>0 are considered information bits, in this example |L|=32, |L - |=8,|L + | = 32. Clearly, |L| < |L - |+|L + This differs from traditional rate allocation, where K = K - +K + .

[0229] Various embodiments have been described in detail above. Figure 14 This is an exemplary mesh diagram and a block diagram of several features according to the embodiments disclosed herein.

[0230] exist Figure 14 In this context, the numbers in column 1400 are bit value indices or other identifiers of bit values, or in some embodiments, labels, and several bit indices in column 1400 share the same bit value, indexed or labeled as 0 (frozen), 1, 2, 3, as shown in the figure. Other bit values ​​indexed or labeled as 4, 5, 6 are one-to-one mapped. As in other embodiments, labels are optional and can be used or not used to provide information such as... Figure 14 The bit values ​​shown are placed as indicated.

[0231] In the example illustrated by three polarity transformations 1401, 1403, and 1405, bits are encoded to generate a long codeword comprising three shorter codewords 1402, 1404, and 1406 generated from three shorter codeblocks 1410, 1412, and 1414. Since each of the three shorter codeblocks 1410, 1412, and 1414 includes at least one identical or common bit value, this identical common bit value creates a relationship that effectively couples the resulting three shorter codewords 1402, 1404, and 1406. The three shorter codewords 1402, 1404, and 1406 can optionally be further coupled via a subsequent XOR operation, as shown in this example, to strengthen the relationship between the codewords and further couple them together.

[0232] Figure 14 The three shorter codewords 1402, 1404 and 1406 have lengths of 2, 4 and 8 respectively, and are shown before optional coupling. Figure 14 Combinations of shorter codewords 1402 and 1404 with portions of longer codewords are also shown. For example, codeword 1402 of length 2 can optionally be combined with the last two bits of codeword 1404 of length 4 and the last two bits of codeword 1406 of length 8, and codeword 1404 of length 4 can optionally be combined with the last four bits of codeword 1406 of length 8. Codeword 1406 of length 8 is self-decoding because its corresponding code block 1414 includes all bit values ​​of the input bit sequence.

[0233] For example, in IR-HARQ, an 8-bit codeword 1406 can be transmitted as the initial transmission, a 4-bit codeword 1404 can be transmitted in a retransmission, and a 2-bit codeword 1402 can be transmitted in the final retransmission. If the 8-bit codeword 1406 is self-decoding, it can be decoded first, and if decoding is successful, any retransmissions are avoided. In this example, self-decoding of the 8-bit codeword 1406 could also, or alternatively, enable selective or opportunistic decoding of the 4-bit codeword 1404 (and / or the 2-bit codeword 1402), which may be much less reliable.

[0234] Various aspects of the invention have been described above and are illustrated by way of example in the accompanying drawings. Figure 15 This is a flowchart of a more general exemplary method according to an embodiment. On the left, Figure 15 1500 illustrates operations or features that can be provided or supported at the encoder or transmitter-side device, and in some embodiments, the encoder or transmitter-side device may be or include, for example... Figure 6A The apparatus is illustrated by way of example. On the right, 1550 illustrates operations or features that may be provided or supported at a decoder or receiver-side device, which may include, for example, an interface and a decoder coupled to the interface. For ease of reference, the following description... Figure 15 In the description, a device that can implement or support encoding and / or transmission features is referred to as a first communication device, and a device that can implement or support decoding and / or reception features is referred to as a second communication device. Embodiments may involve any one or both of these devices.

[0235] Referring first to 1500, from the perspective of the transmitting device, at 1508, the output of the coded bits can involve transmitting the coded bits. The coded bits can be transmitted through or via any type of interface, including communication interfaces in the case of transmitting coded bits. The embodiments are not limited in any way to any particular type of interface. For example, a first communication device can transmit coded bits to a second communication device in a wireless communication network. The coded bits are transmitted via 1504 (e.g., by a polar encoder 604). Figure 6A The input bits are obtained by encoding them using polar codes, and can be called coded bits encoded by polar codes.

[0236] Polar codes include or provide bit indices for placing the values ​​of input bits before encoding. The bit indices include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Bit values ​​are placed... Figure 15It is shown at position 1504, but can be considered part of the encoding at position 1506. Similarly, refer again... Figure 6A In some embodiments of the exemplary apparatus, the encoded bit value selector 602 may be used to place bit values ​​on bit indices, or the polar encoder 604 may be used to place bit values ​​on bit indices without an encoded bit value selector. Each value of a first subset of input bits is placed on a bit index of a first set of bit indices by, for example, an encoded bit index selector or a polar encoder (also referred to herein as a one-to-one mapping), and each value of a second subset of input bits is placed on two or more bit indices of a second set of bit indices by, for example, an encoded bit index selector or a polar encoder (also referred to herein as a one-to-many or many-to-one mapping).

[0237] Regarding placing a bit value on one, two, or more bit indices, each bit index provides an opportunity to decode that bit value. Generally, the more bit indices containing the same bit value, the higher the probability of correctly decoding that bit value, because there are more opportunities to decode it.

[0238] For example, refer to Figure 9 Consider a scenario where the blocks in the top row, from left to right, represent code blocks corresponding to the coded bits transmitted in a series of transmissions in the incremental redundancy hybrid automatic repeat request (IR-HARQ) method. The initial transmission might only include the rightmost u... ++++ The corresponding encoded bits for the block; for this, it is expected that each input bit value will be placed at only one bit index used for encoding. Corresponding to the next u +++- The extra coded bits of the block can be used in the initial transmission along with the rightmost u. ++++ The coded bits of the block are transmitted together and placed in u ++++ At least some of the input bit values ​​at the bit index in the block are also placed in u +++- At the bit index within the block. These u... ++++ and u +++- Considering blocks together, some input bit values ​​(of the first subset of input bits mentioned above) are placed at one bit index, while other input bit values ​​(of the second subset mentioned above) are placed at two or more bit indices. Similar notes apply to other code blocks, and in all code blocks, at least some input bit values ​​are placed at two or more bit indices.

[0239] For example, the next transmission or retransmission may include a corresponding Figure 9 u in ++-The coded bits of a code block are transmitted, and so on, until the entire longer codeword, including all the coded bits corresponding to all code blocks, is transmitted, or all input bits are correctly decoded. With each such transmission or retransmission, the probability of correct decoding increases because the incrementally transmitted coded bits provide another opportunity to decode at least some of the input bit values.

[0240] At position 1504, the number of bit indices to which the bit values ​​of the input bits in the aforementioned second subset are placed can depend on any of a variety of factors or conditions. For example, continue to refer to Figure 9 One factor or condition can be the minimum transmission code length. If the minimum transmission code length (referred to above as N') is N max (mother code length) / 2 corresponds to a step size or one level of recursion, each time dividing or splitting in half, such as Figure 9 As shown, the bit values ​​of the input bits in the second subset are likely to be placed on at most two bit indices. Since the probability of placing bit values ​​on more than two bit indices (to obtain a higher probability of correct decoding) is higher for shorter transmission code lengths relative to the longest transmission code length, there are more bit indices available for placing the input bit values ​​overall.

[0241] Turn to Figure 15 At 1502, another operation that may involve acquiring coded bits is shown. For example, acquiring input bits may involve collecting or otherwise receiving data output from one or more devices and / or services, or accessing data in memory.

[0242] As shown at 1508, the method may also involve outputting the encoded bits acquired at 1506. For example, the encoded bits may be output to be stored in memory and / or transmitted, as indicated at 1508. Figure 6A In the exemplary apparatus shown, the encoded bits can be output by the polar encoder 604 via or through an interface, or by the rate matching module 606 via or through an interface if rate matching is performed to reduce the number of encoded bits.

[0243] Implementations may include any or all of the operations shown at 1500. For example, in some implementations, the method may involve bit value placement (e.g., performed by the encoded bit value selector 602 or the polar encoder 604) and encoding (e.g., by the polar encoder 604), as shown at 1504 and 1506, and at 1508, transmitting or otherwise outputting the encoded bits (e.g., by the polar encoder 604 or the rate matching module 606). Other implementations may involve transmitting or otherwise outputting the encoded bits acquired by encoding the input bits with polar codes at 1508. Such implementations are not mutually exclusive, and the method may involve acquisition, placement, and encoding as shown at 1502, 1504, and 1506, and outputting the encoded bits as shown at 1506.

[0244] It can also provide or support other features.

[0245] For example, each value of a second subset of input bits placed at 1504 on two or more bit indices in the second set makes the input bit value known for all bit indices of the corresponding two or more bit indices after decoding the input bit value for any one of the two or more bit indices. This is an example of an encoding or transmitting method feature (bit value placement, e.g., by the encoded bit value selector 602 or polar encoder 604) that enables or supports the decoding or receiving method feature (decoding any one of the two or more bit indices).

[0246] The bit indexes provided by polar codes can be associated with multiple code blocks. Examples are provided elsewhere in this article, and also at least in [the document / section]. Figures 7 to 10 and Figure 14 As shown in the figure. In such embodiments, the second set of bit indices may include bit indices associated with more than one of these code blocks, such as the "+" and "-" code blocks mentioned herein.

[0247] Regarding code block coupling or nesting, for example at 1504, the encoded bit value selector 602 or the polar encoder 604 can place the input bit values ​​of a second subset of the input bits onto both the bit index associated with the first code block and the bit index associated with the second code block among multiple code blocks, thereby coupling the code block and the corresponding codeword together. As discussed in detail above, this is one way to couple code blocks and codewords together.

[0248] In some embodiments, a method may involve combining a first coded bit and a second coded bit combination to obtain a coupled codeword, wherein the first coded bit is obtained by encoding a first code block at 1506, for example by a polar encoder 604, or otherwise corresponding to bits of the first code block, and the second coded bit is obtained by encoding a second code block at 1506, or otherwise corresponding to bits of the first code block. This type of codeword coupling is described by way of example with reference to combinations performed via one or more XOR operations: the combination may include all or a subset of the coded bits of the codeword. Figure 7 and Figure 14 Examples of these are also shown. For instance, a polar encoder 604, or another component coupled to the encoder and used to combine coded bits, can achieve codeword coupling.

[0249] The input bit values ​​can be recursively divided between code blocks during multiple iterations (e.g., by the encoded bit value selector 602 or the polar encoder 604). Figure 8 The example shown involves a single iteration, while Figure 9 and Figure 10 The example in the text involves multiple iterations. Each iteration's code block consists of a shorter code block (the "+" code block in the example above), which includes all the input bit values ​​of the longer code block, and is divided from the longer code block during the iteration.

[0250] A code block can include a code block in which, at 1504, the corresponding input bit value is uniquely placed at the corresponding bit index among a plurality of bit indices; or in other words, a code block in which no input bit value is placed at more than one bit index. In such a code block, the mapping is one-to-one. (Refer to the above...) Figure 9 In the example of the initial transmission of the encoded bits corresponding to the rightmost "+" code block, the initial transmission corresponds to this type of codeword, where the input bit value is uniquely mapped to a bit index associated only with that code block.

[0251] A code block may also or alternatively comprise a code block in which, at 1504, the corresponding input bit value is uniquely placed (e.g., by the encoded input value selector 602 or the polar encoder 604) at the corresponding consecutive bit index in the first part of the code block, and at 1504, the corresponding input bit value is uniquely placed (e.g., by the encoded bit value selector 602 or the polar encoder 604) at the corresponding consecutive bit index in the second part of the code block. These parts of the code block may be an upper part (the higher bit index of the latter half of the code block, also called u-code or plus code) and a lower part (the lower bit index of the first half of the code block, also called v-code). By uniquely placing the corresponding consecutive bit indexes in each part as described above, the encoded bits corresponding to the first part (e.g., u-code) may not include any one-to-many mapping of input bit values, but may have one or more input bit values ​​(e.g., v-code) mapped to both the first and second parts. Therefore, the corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block at 1504 (e.g., by the encoding bit value selector 602 or polar encoder 604) and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block at 1504 (e.g., by the encoding bit value selector 602 or polar encoder 604) can each include: the value of the input bit of the second subset of the input bits placed at the bit index in the first part of the code block and the bit index in the second part of the code block.

[0252] For example, suppose the initial transmission length is 6, the shortest power of 2 mother code length, and the code block length is 8. Let [1,2,3,4,5,6,7,8] represent the bit indices in a code block of length 8. In the example of unique bit value placement above, there is no one-to-many mapping in [5,6,7,8]. In other words, the bit values ​​or tags placed on or assigned to [5,6,7,8] are different. However, one or more bit values ​​or tags can be placed on or assigned to [1,2,3,4]. That is, even if there are no such shared or common bit values ​​or tags individually in each part, bit value or tag sharing can exist between the two halves of a code block, or more generally between the two parts.

[0253] A code block may include a code block in which the values ​​of a second subset of the input bits are placed on two or more bit indices. For example, in one embodiment, a code block other than the shortest code block corresponding to a rate-1 (or maximum rate) transmission code length may include a one-to-two or one-to-many mapping, according to which each of one or more input bit values ​​is mapped to two or more bit indices. For a rate-1 code block corresponding to a rate-1 codeword, such a code block cannot have any mapping other than a one-to-one mapping. If the code rate is 1, the number of bit indices is the same as the number of input bits and input bit values. Therefore, all bit indices are uniquely mapped to a corresponding input bit value among the input bit values, and there are not enough bit indices available to place any single input bit value on multiple bit indices. In other words, each bit index has a different input bit value or tag, and there is no space shared by bit values ​​or tags in the code block.

[0254] In the iterative method, at each iteration, only the shorter code block can be further divided into multiple shorter code blocks. The shorter code blocks include all the input bit values ​​of the longer code block, and are derived from the longer code block. This is consistent with... Figure 9 It is consistent, for example, in Figure 9 In this process, only the "+" code block in each iteration is further divided in the next iteration.

[0255] According to another embodiment, in each iteration, the multiple shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into multiple even shorter code blocks. This is consistent with... Figure 10 It is consistent, for example, in Figure 10 In each iteration, the "-" and "+" code blocks are further subdivided in the next iteration. Multiple shorter code blocks derived from each code block include: a shorter code block ("+" shorter code block), which comprises all the input bit values ​​of the shorter code block, and is a further subdivision of that shorter code block; and another shorter code block ("-" shorter code block), which comprises a subset of these input bit values.

[0256] Some embodiments involve bit tags and labels. Therefore, encoding can involve assigning the value of an input bit and a predetermined bit value to a corresponding label associated with a bit index, and assigning the value of an input bit and the predetermined bit value of the corresponding label to the bit index. Bit value placement in tagging embodiments can involve these assignment operations. For example, an encoded bit value selector 602 or a polar encoder 604 can be used to assign the value of an input bit and a predetermined bit value to a corresponding label associated with a bit index. Similarly, for example, an encoded bit value selector 602 or a polar encoder 604 can be used to assign the value of an input bit and the predetermined bit value of the corresponding label to the bit index.

[0257] Among other tags, a tag includes a subset of tags associated with a second set of bit indices, used to assign each corresponding value of the second subset of input bits to a corresponding two or more bit indices of the second set of bit indices. A tag may also include a single tag, with a predetermined bit value assigned to the single tag, and the single tag is associated with all bit indices in a third set of bit indices.

[0258] Tags can be associated with bit indices based on any of a variety of criteria or conditions, including, for example, one or more of the following: reliability order, bit index order, code-bit interleaving sequence, transmission order, and a predefined order of a subset of the bit index, where the predefined order is based on the order of different subsets of the bit index. More generally, the placement of bit values ​​on a bit index can be based on any of these criteria or conditions, and / or one or more other criteria or conditions. Examples are provided elsewhere in this document, including in references. Figures 11 to 13 Examples.

[0259] Examples of using tags may also involve retrieving tags from a mapping sequence. In the case of tags, the mapping sequence is used to indicate the association between a corresponding tag and a bit index. More generally, bit value placement may be based on a mapping sequence used to indicate the association between a bit value and a bit index.

[0260] Implementation examples may involve Figure 15 Other features or operations not explicitly shown herein. For example, some embodiments may involve transmitting signaling that indicates any of a variety of parameters, such as any one or more of the following: MCS index, code length, code rate, mapping sequence. The transmission of signaling may involve an encoder / encoding device or a transmitter / transmitting device that is sending encoded bits to a decoder / decoder or receiver / receiving device. Transmission may also, or alternatively, involve a decoder / decoder or receiver / receiving device receiving signaling from an encoder / encoding device or a transmitter / transmitting device. Signaling is not necessarily between the communication devices that are sending or receiving encoded bits or only between communication devices. For example, a network device such as a gNB or base station may send signaling to configure parameters at one or more communication devices. Therefore, the method may involve a network device sending signaling, and an encoder / encoding device or transmitter / transmitting device receiving signaling from the network device, and / or a decoder / decoder or receiver / receiving device receiving signaling from the network device.

[0261] At 1550, Figure 15Various decoding and / or receiving correspondences for the feature shown at 1500 are illustrated. From the perspective of the receiving device, receiving at 1552 indicates receiving encoded bits that have been encoded using polar codes. For example, receiving may involve receiving encoded bits from a first communication device via a second communication device in a wireless communication network. The encoded bits can be received through or via any of a variety of types of interfaces, and the embodiments are not limited in any way to any particular type of interface.

[0262] As in other embodiments herein, the polar code includes bit indices for placing the values ​​of the input bits prior to encoding. These bit indices include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. For encoding, each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0263] The decoding at 1554 is intended to illustrate decoding the received encoded bits to obtain the decoded input bits. In some embodiments, the decoder may not be a discrete device, but rather part of a logic block in silicon or an on-chip system used to decode and use the decoded input bits. In other embodiments, for example, as shown at 1556, the decoded input bits are output for processing and / or storage.

[0264] For example, refer to Figure 15 The operation at point 1500, any or all of the features described above in the context of the encoder-side or transmitter-side method can also be applied to or have corresponding features in the decoder-side or receiver-side method. For example, any one or more of the following features may be provided or supported individually or in any combination in the decoder-side or receiver-side method:

[0265] Decoding at 1554 involves decoding the input bit value for any one of the two or more bit indices for each value of a second subset of the input bits placed on two or more bit indices.

[0266] Bit indexes are associated with multiple code blocks;

[0267] The second set of bit indices includes bit indices associated with multiple code blocks in multiple code blocks;

[0268] The input bit values ​​of the second subset of input bits are placed on both the bit index associated with the first code block in the plurality of code blocks and the bit index associated with the second code block in the plurality of code blocks;

[0269] The encoded bits include coupled codewords, which include a combination of first encoded bits obtained by encoding a first code block and second encoded bits obtained by encoding a second code block;

[0270] In multiple iterations, the input bit values ​​have been recursively divided into multiple code blocks;

[0271] Each iteration consists of multiple code blocks, including a shorter code block that contains all the input bit values ​​of a longer code block, which is partitioned from the longer code block during iteration.

[0272] Multiple code blocks comprise a single code block, wherein the corresponding input bit values ​​are uniquely placed at the corresponding bit index among multiple bit indices;

[0273] Multiple code blocks comprise a single code block, wherein the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in the first part of the code block, and the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in the second part of the code block;

[0274] The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bit of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block;

[0275] Multiple code blocks comprise a single code block, wherein the values ​​of the input bits of a second subset of the input bits are placed at two or more bit indices in a plurality of bit indices;

[0276] In each iteration, only the shorter code block is further divided into multiple shorter code blocks. The shorter code block includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

[0277] In each iteration, the multiple shorter code blocks that were divided from the longer code blocks in the previous iteration are each further divided into multiple even shorter code blocks.

[0278] Multiple shorter code blocks are derived from each shorter code block, each of which includes all the input bit values ​​of the shorter code block and is further subdivided from the shorter code block.

[0279] The corresponding label is associated with multiple bit indices;

[0280] By assigning the input bit value and the predetermined bit value to the corresponding tag, and assigning the input bit value and the predetermined bit value of the corresponding tag to multiple bit indices, the input bit value and the predetermined input bit value are placed on multiple bit indices.

[0281] The tags include a subset of tags associated with the second set of bit indices, used to assign each corresponding value of the second subset of input bits to the corresponding two or more bit indices of the second set of bit indices;

[0282] The tag is associated with the bit index based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of the bit index, the predefined order being based on the order of different subsets of the bit index;

[0283] The tag also includes a single tag, a predefined bit value is assigned to a single tag, and the single tag is associated with all bit indices in the third bit index set;

[0284] The method may include retrieving the corresponding tag from a mapping sequence that indicates the association between the corresponding tag and multiple bit indices.

[0285] This invention includes various embodiments, not only method embodiments but also other embodiments, such as apparatus embodiments and embodiments relating to non-transitory computer-readable storage media. Embodiments may be combined individually or in combination with the features disclosed herein.

[0286] The apparatus may include a processor for causing the apparatus to perform the methods or operations disclosed herein by means of, for example, executing a program, or providing or supporting the features disclosed herein. The apparatus may also include a non-transitory computer-readable storage medium coupled to the processor for storing a program for execution by the processor. Figure 3 For example, processors 210, 260, and 276 may be or include one or more processors, and each memory 208, 258, and 278 is an example of a non-transitory computer-readable storage medium in ED 110 and TRP 170 and 172. The non-transitory computer-readable storage medium need not be provided solely in conjunction with a processor, but may, for example, be provided separately in a computer program product.

[0287] As an illustrative example, a program stored in a non-transitory computer-readable storage medium may include instructions for or to cause a processor to: encode input bits using polar codes to obtain encoded bits, and output the encoded bits. The apparatus embodiments are not limited to program-based embodiments. The apparatus may also or alternatively include: an encoder for encoding input bits using polar codes to obtain encoded bits; and an interface coupled to the encoder for outputting the encoded bits. The polar codes include a plurality of bit indices for placing values ​​of the input bits prior to encoding. The bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0288] More generally, a device or its components (e.g., an encoder or a processor) can be used, or a program can include instructions for or to cause the processor to: encode input bits to obtain encoded bits. Such a device or its components (e.g., an interface) can be used, or a program can include instructions for or to cause the processor to: output encoded bits, for example, transmit the encoded bits via a first communication device to a second communication device, for example, in a wireless communication network.

[0289] Embodiments associated with such devices or non-transitory computer-readable storage media may include any one or more of the following features, which are also discussed elsewhere herein:

[0290] For example, each value of a second subset of input bits placed by the input index selector 602 or polar encoder 604 on two or more bit indices in the second set makes the input bit value known for all bit indices of the corresponding two or more bit indices after decoding the input bit value for any one of the two or more bit indices.

[0291] Multiple bit indices are associated with multiple code blocks;

[0292] The second set of bit indices includes bit indices associated with multiple code blocks in multiple code blocks;

[0293] For example, the encoding input index selector 602 or the polar encoder 604 places the input bit values ​​of a second subset of the input bits on both the bit index associated with the first code block in the plurality of code blocks and the bit index associated with the second code block in the plurality of code blocks.

[0294] The device or its components (e.g., an encoder or a processor) may also be used, or the program may include instructions for or to cause the processor to: combine a first encoded bit obtained by encoding a first code block and a second encoded bit obtained by encoding a second code block to obtain a coupled codeword;

[0295] For example, the input index selector 602 or the polar encoder 604 recursively divides the input bit values ​​in multiple code blocks in multiple iterations;

[0296] Each iteration consists of multiple code blocks, including a shorter code block that contains all the input bit values ​​of a longer code block, which is partitioned from the longer code block during iteration.

[0297] Multiple code blocks comprise a single code block, wherein the corresponding input bit values ​​are uniquely placed at the corresponding bit index among multiple bit indices (e.g., by the encoding input index selector 602 or the polar encoder 604).

[0298] Multiple code blocks include a single code block, wherein the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first part of the code block (e.g., by the encoding input index selector 602 or the polar encoder 604), and the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second part of the code block (e.g., by the encoding input index selector 602 or the polar encoder 604).

[0299] The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block (e.g., by the encoding input index selector 602 or polar encoder 604) and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block (e.g., by the encoding input index selector 602 or polar encoder 604) each include: the value of the input bits of the second subset of the input bits placed at the bit index in the first part of the code block and the bit index in the second part of the code block (e.g., by the encoding input index selector 602 or polar encoder 604);

[0300] Multiple code blocks comprise a single code block, wherein the values ​​of the input bits of a second subset of the input bits are (e.g., encoded input index selector 602 or polar encoder 604) placed on two or more bit indices of the multiple bit indices;

[0301] In each iteration, only the shorter code block is further divided into multiple shorter code blocks (e.g., encoded input index selector 602 or polar encoder 604). The shorter code block includes all the input bit values ​​of the longer code block, which is divided from the longer code block.

[0302] In each iteration, the multiple shorter code blocks that were divided from the longer code blocks in the previous iteration are further divided into multiple even shorter code blocks (e.g., by the encoding input index selector 602 or the polar encoder 604).

[0303] (e.g., by an encoded input index selector 602 or a polar encoder 604) Multiple shorter code blocks are divided from each shorter code block, including the shorter code block, which includes all the input bit values ​​of the shorter code block, and the shorter code block is further divided from the shorter code block;

[0304] The apparatus or its components (e.g., the encoded bit index selector 602, the encoder 604, or the processor) may be used, or the program may include instructions for or to cause the processor to: encode the input bit by assigning the value of the input bit and a predetermined bit value to a corresponding tag associated with a plurality of bit indices, and assigning the value of the input bit and the predetermined bit value of the corresponding tag to the plurality of bit indices;

[0305] The tags include a subset of tags associated with the second set of bit indices, used to assign each corresponding value of the second subset of input bits to the corresponding two or more bit indices of the second set of bit indices;

[0306] The tag also includes a single tag, a predefined bit value is assigned to a single tag, and the single tag is associated with all bit indices in the third bit index set;

[0307] The device or its components (e.g., an encoder) may be used, or the program may include instructions for or to cause the processor to: retrieve a corresponding tag from a mapping sequence that indicates the association of a corresponding tag with multiple bit indices.

[0308] For decoder-side or receiver-side devices or computer program products that include a non-transitory computer-readable storage medium to support decoder-side or receiver-side operation, the device may be used, or the program may include instructions for or to cause a processor to: receive encoded bits encoded by a polar code, and decode the encoded bits to obtain decoded input bits. In another embodiment, the device includes: an interface for receiving encoded bits encoded by a polar code; and a decoder coupled to the interface for decoding the encoded bits to obtain decoded input bits. The polar code includes a plurality of bit indices for placing values ​​of input bits prior to encoding, the bit indices including: a first set of bit indices for placing values ​​of a first subset of input bits, a second set of bit indices for placing values ​​of a second subset of input bits, and a third set of bit indices for predetermined bit values. For encoding, each value of the first subset of input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of input bits is placed at two or more bit indices of the second set of bit indices.

[0309] Embodiments associated with such devices or non-transitory computer-readable storage media may include any one or more of the following features, which are also discussed elsewhere herein:

[0310] The device or its components (e.g., an interface or a processor) may be used, or the program may include instructions for or to cause the processor to: receive coded bits from a first communication device via a second communication device in a wireless communication network;

[0311] The apparatus or its components (e.g., a decoder or a processor) may be used, or the program may include instructions for or to cause the processor to: decode the input bit value for any one of the two or more bit indices for each value of a second subset of the input bits placed on two or more bit indices;

[0312] Multiple bit indices are associated with multiple code blocks;

[0313] The second set of bit indices includes bit indices associated with multiple code blocks in multiple code blocks;

[0314] The input bit values ​​of the second subset of input bits are placed on both the bit index associated with the first code block in the plurality of code blocks and the bit index associated with the second code block in the plurality of code blocks;

[0315] The encoded bits include coupled codewords, which include a combination of first encoded bits obtained by encoding a first code block and second encoded bits obtained by encoding a second code block;

[0316] In multiple iterations, the input bit values ​​have been recursively divided into multiple code blocks;

[0317] Each iteration consists of multiple code blocks, including a shorter code block that contains all the input bit values ​​of a longer code block, which is partitioned from the longer code block during iteration.

[0318] Multiple code blocks comprise a single code block, wherein the corresponding input bit values ​​are uniquely placed at the corresponding bit index among multiple bit indices;

[0319] Multiple code blocks comprise a single code block, wherein the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in the first part of the code block, and the corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in the second part of the code block;

[0320] The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bit of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block;

[0321] Multiple code blocks comprise a single code block, wherein the values ​​of the input bits of a second subset of the input bits are placed at two or more bit indices in a plurality of bit indices;

[0322] In each iteration, only the shorter code block is further divided into multiple shorter code blocks. The shorter code block includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

[0323] In each iteration, the multiple shorter code blocks that were divided from the longer code blocks in the previous iteration are each further divided into multiple even shorter code blocks.

[0324] Multiple shorter code blocks are derived from each shorter code block, each of which includes all the input bit values ​​of the shorter code block and is further subdivided from the shorter code block.

[0325] The corresponding label is associated with multiple bit indices;

[0326] By assigning the input bit value and the predetermined bit value to the corresponding tag, and assigning the input bit value and the predetermined bit value of the corresponding tag to multiple bit indices, the input bit value and the predetermined input bit value are placed on multiple bit indices;

[0327] The tags include a subset of tags associated with the second set of bit indices, used to assign each corresponding value of the second subset of input bits to the corresponding two or more bit indices of the second set of bit indices;

[0328] The tag is associated with multiple bit indices based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of bit indices, the predefined order being based on the order of different subsets of bit indices;

[0329] The tag also includes a single tag, a predefined bit value is assigned to a single tag, and the single tag is associated with all bit indices in the third bit index set;

[0330] The device or its components (e.g., a decoder) may be used, or the program may include instructions for or to cause the processor to: retrieve a corresponding tag from a mapping sequence that indicates the association of a corresponding tag with multiple bit indices.

[0331] The device embodiments are not limited in any way to a single device. For example, the system may include a first communication device and a second communication device. The first communication device may be used to transmit encoded bits that have been encoded using polar codes, and the second communication device may be used to receive encoded bits from the first communication device and decode the encoded bits to obtain decoded input bits. As in other embodiments, the polar code may include bit indices for placing the values ​​of the input bits before encoding. The bit indices may include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices.

[0332] The first communication device in the system may also, or alternatively, implement, provide, or support other encoding-side or transmitting-side features disclosed herein, and similarly, the second communication device in the system may also, or alternatively, implement, provide, or support other decoding-side or receiving-side features disclosed herein.

[0333] More generally, other features disclosed herein may also be provided in the method, apparatus and / or system embodiments, either by way of alternatives.

[0334] The embodiments disclosed herein include various aspects of polar coding, including encoding and decoding.

[0335] The disclosed embodiments can provide a fundamental upgrade to polar codes and make polar codes applicable to a wider range of scenarios.

[0336] For example, the disclosed embodiments can be implemented as part of a channel coding scheme and therefore can be applied wherever channel coding is used. This covers a very wide range of scenarios. The flexibility provided by the embodiments disclosed herein helps to make the associated channel coding schemes particularly suitable for wireless communications.

[0337] Possible product deployments that can be implemented or combined with embodiments include network devices (e.g., base stations), access devices (e.g., UEs), robots, sensors, automobiles, drones, and satellites. Examples of service deployments include enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), massive machine-type communications (mMTC) / Internet of Things (IoT), and automotive and industrial scenarios. Examples of network deployments include 5G+, 6G, WiFi, non-terrestrial networks (NTN), optical networks, distributed networks, and self-organizing networks. These are illustrative and non-limiting examples, and other deployments, implementations, or applications are possible.

[0338] Potential advantages of the embodiments disclosed herein include greater design space and more flexible definitions of polar codes and coupled / nested polar codes. The embodiments may also, or alternatively, allow any bit value to be placed on multiple bit indices and provide a concise representation of such bit value placement. As disclosed herein, placing input bit values ​​on multiple bit indices can also help provide or enhance self-decoding by placing the input bit values ​​(rather than, for example, predetermined values ​​used for freezing bits) on more bit indices. In some embodiments, various optional bit placements (including tag allocation rules) can help avoid significant performance penalties and / or improve performance.

[0339] Although this invention pertains to illustrative embodiments, it is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this specification.

[0340] Alternatively or concurrently, features disclosed herein in the context of method embodiments may be implemented in apparatus or computer program product embodiments. Furthermore, while embodiments are described primarily in the context of methods and apparatus, other implementations are contemplated, for example, as instructions stored in one or more non-transitory computer-readable media. These media may store programs or instructions to perform any of the various methods consistent with the present invention.

[0341] Although aspects of the invention have been described with reference to specific features and embodiments thereof, various modifications and combinations may be made without departing from the scope of the invention. Therefore, the specification and drawings are to be regarded only as illustrative of some embodiments of the invention as defined by the appended claims, and any and all modifications, variations, combinations, or equivalents within the scope of the invention are contemplated. Although embodiments and potential advantages have been described in detail, various changes, substitutions, and alterations may be made without departing from the invention as defined by the appended claims. Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, articles of manufacture, compositions of matter, components, methods, and steps described in the specification. Based on the disclosure of the invention, those skilled in the art will readily understand that processes, machines, articles of manufacture, compositions of matter, components, methods, or steps (including those currently existing or later developed) that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the invention. Therefore, the appended claims are intended to include such processes, machines, articles of manufacture, compositions of matter, components, methods, or steps within their scope.

[0342] Furthermore, any module, component, or device executing instructions illustrated herein may include or otherwise access one or more non-transitory computer-readable or processor-readable storage media to store information, such as computer-readable or processor-readable instructions, data structures, program modules, and / or other data. A non-exhaustive list of examples of non-transitory computer-readable or processor-readable storage media includes magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, compact disc read-only memory (CD-ROM), digital video disc or digital versatile disc (DVD), and Blu-ray. Optical discs or other optical storage devices, volatile and non-volatile, removable and non-removable media implemented in any method or technology, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies. Any of these non-transitory computer-readable or processor-readable storage media may be part of a device or may be accessed or connected to a device. Any application or module described herein may be implemented using computer-readable and executable instructions, or a processor may be stored or otherwise stored by such non-transitory computer-readable or processor-readable storage media. Claims (as amended under Article 19 of the Treaty) 1. A method, characterized in that it comprises: Input bits are encoded using polar codes to obtain encoded bits. The polar codes include multiple bit indices for placing the values ​​of the input bits before encoding. These bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits; a second set of bit indices for placing values ​​of a second subset of the input bits; and a third set of bit indices for placing predetermined bit values. Wherein, each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set; Output the encoded bits. 2. The method according to claim 1, characterized in that it further comprises: The first communication device sends the encoded bits to the second communication device in the wireless communication network. 3. The method according to claim 1 or 2, wherein each value of the second subset of the input bit placed on the two or more bit indices in the second set makes the input bit value known for all bit indices of the corresponding two or more bit indices after decoding the input bit value for any one of the two or more bit indices. 4. The method according to any one of claims 1 to 3, wherein the plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks among the plurality of code blocks. 5. The method according to claim 4, wherein the input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks. 6. The method according to claim 5, characterized in that it further comprises: The first encoded bits obtained by encoding the first code block and the second encoded bits obtained by encoding the second code block are combined to obtain a coupled codeword. 7. The method according to any one of claims 1 to 6, characterized in that, in multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein, in each iteration, the multiple code blocks include a shorter code block, the shorter code block including all input bit values ​​of a longer code block, the shorter code block being divided from the longer code block in the iteration. 8. The method according to claim 7, wherein the plurality of code blocks comprises a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices. 9. The method according to claim 7 or 8, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block. 10. The method according to claim 7 or 8, wherein the plurality of code blocks comprises a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices of the plurality of bit indices. 11. The method according to any one of claims 7 to 10, characterized in that, in each iteration, only the shorter code block is further divided into a plurality of shorter code blocks, the shorter code blocks comprising all input bit values ​​of the longer code block, the shorter code blocks being divided from the longer code block. 12. The method according to any one of claims 7 to 10, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block. 13. The method of claim 1, wherein the encoding comprises: assigning the value of the input bit and the predetermined bit value to a corresponding tag associated with the plurality of bit indices, and assigning the value of the input bit and the predetermined bit value of the corresponding tag to the plurality of bit indices, wherein the tag comprises a subset of tags associated with a second set of bit indices for assigning each corresponding value of the second subset of the input bit to a corresponding two or more bit indices of the second set of bit indices. 14. The method of claim 13, wherein the tag is associated with the plurality of bit indices based on any one or more of the following: a reliability order, a bit index order, a code bit interleaving sequence, a transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices. 15. The method according to claim 13 or 14, wherein the tag further comprises a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set. 16. The method according to any one of claims 13 to 15, characterized in that it further comprises: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices. 17. A method, characterized in that it comprises: Receive encoded bits encoded by a polar code, the polar code including a plurality of bit indices for placing the values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set. The method further includes: The encoded bits are decoded to obtain the decoded input bits. 18. The method according to claim 17, wherein the receiving comprises: a second communication device in a wireless communication network receiving the encoded bits from a first communication device. 19. The method according to claim 17 or 18, wherein the decoding comprises: for each value of the second subset of the input bits placed on the two or more bit indices, decoding the input bit value for any one of the two or more bit indices. 20. The method according to any one of claims 17 to 19, wherein the plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks among the plurality of code blocks. 21. The method according to claim 20, wherein the input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks. 22. The method according to claim 21, wherein the encoded bits include a coupled codeword, the coupled codeword including a combination of a first encoded bit obtained by encoding the first code block and a second encoded bit obtained by encoding the second code block. 23. The method according to any one of claims 17 to 19, characterized in that, in multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein, at each iteration, the multiple code blocks include a shorter code block, the shorter code block including all input bit values ​​of a longer code block, the shorter code block being divided from the longer code block at the iteration. 24. The method according to claim 23, wherein the plurality of code blocks comprises a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices. 25. The method according to claim 23 or 24, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block. 26. The method according to claim 23 or 24, wherein the plurality of code blocks comprises a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices of the plurality of bit indices. 27. The method according to any one of claims 23 to 26, characterized in that, in each iteration, only the shorter code block is further divided into a plurality of shorter code blocks, the shorter code blocks comprising all input bit values ​​of the longer code block, the shorter code blocks being divided from the longer code block. 28. The method according to any one of claims 23 to 26, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block. 29. The method of claim 17, wherein a corresponding tag is associated with the plurality of bit indices, and the value of the input bit and a predetermined input bit value are placed on the plurality of bit indices by: assigning the value of the input bit and the predetermined bit value to the corresponding tag, and assigning the value of the input bit and the predetermined bit value of the corresponding tag to the plurality of bit indices, wherein the tag includes a subset of tags associated with the second set of bit indices for assigning each corresponding value of the second subset of the input bit to a corresponding two or more bit indices of the second set of bit indices. 30. The method of claim 29, wherein the tag is associated with the plurality of bit indices based on any one or more of the following: a reliability order, a bit index order, a code bit interleaving sequence, a transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices. 31. The method according to claim 29 or 30, wherein the tag further comprises a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set. 32. The method according to any one of claims 29 to 31, characterized in that it further comprises: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices. 33. An apparatus, characterized in that it comprises: Encoder; The interface is coupled to the encoder. The apparatus is used to perform the method according to any one of claims 1 to 16. 34. An apparatus, characterized in that it comprises: interface; The decoder is coupled to the interface. The apparatus is used to perform the method according to any one of claims 17 to 32. 35. A computer program product, characterized in that it comprises a non-transitory computer-readable medium storing a program for execution by a processor, said program comprising instructions for performing the method according to any one of claims 1 to 32. 36. A system, characterized in that it comprises: A first communication device is configured to transmit encoded bits encoded by a polar code, the polar code including bit indices for placing values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values, wherein each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices; A second communication device is configured to receive the encoded bits from the first communication device and decode the encoded bits to obtain decoded input bits.

Claims

1. A method, characterized in that, include: Input bits are encoded using polar codes to obtain encoded bits. The polar codes include multiple bit indices for placing the values ​​of the input bits before encoding. These bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits; a second set of bit indices for placing values ​​of a second subset of the input bits; and a third set of bit indices for placing predetermined bit values. Wherein, each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set; Output the encoded bits.

2. The method according to claim 1, characterized in that, Also includes: The first communication device sends the encoded bits to the second communication device in the wireless communication network.

3. The method according to claim 1 or 2, characterized in that, Each value of the second subset of the input bits placed on the two or more bit indices in the second set is such that, after decoding the input bit value for any one of the two or more bit indices, the input bit value is known for all bit indices of the corresponding two or more bit indices.

4. The method according to any one of claims 1 to 3, characterized in that, The plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks.

5. The method according to claim 4, characterized in that, The input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks.

6. The method according to claim 5, characterized in that, Also includes: The first encoded bits obtained by encoding the first code block and the second encoded bits obtained by encoding the second code block are combined to obtain a coupled codeword.

7. The method according to any one of claims 1 to 6, characterized in that, In multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein, in each iteration, the multiple code blocks include a shorter code block, which includes all the input bit values ​​of a longer code block, and the shorter code block is divided from the longer code block in the iteration.

8. The method according to claim 7, characterized in that, The plurality of code blocks include a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices.

9. The method according to claim 7 or 8, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block.

10. The method according to claim 7 or 8, characterized in that, The plurality of code blocks include a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices among the plurality of bit indices.

11. The method according to any one of claims 7 to 10, characterized in that, In each iteration, only the shorter code block is further divided into multiple shorter code blocks, each of which includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

12. The method according to any one of claims 7 to 10, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block.

13. The method according to claim 1, characterized in that, The encoding includes: assigning the value of the input bit and the predetermined bit value to a corresponding tag associated with the plurality of bit indices, and assigning the value of the input bit and the predetermined bit value of the corresponding tag to the plurality of bit indices, wherein the tag includes a subset of tags associated with the second set of bit indices for assigning each corresponding value of the second subset of the input bit to a corresponding two or more bit indices of the second set of bit indices.

14. The method according to claim 13, characterized in that, The tag is associated with the plurality of bit indices based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices.

15. The method according to claim 13 or 14, characterized in that, The tag also includes a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set.

16. The method according to any one of claims 13 to 15, characterized in that, Also includes: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices.

17. A method, characterized in that, include: Receive encoded bits encoded by a polar code, the polar code including a plurality of bit indices for placing the values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set. The method further includes: The encoded bits are decoded to obtain the decoded input bits.

18. The method according to claim 17, characterized in that, The receiving includes: a second communication device in a wireless communication network receiving the encoded bits from a first communication device.

19. The method according to claim 17 or 18, characterized in that, The decoding includes: for each value of the second subset of the input bits placed on the two or more bit indices, decoding the input bit value for any one of the two or more bit indices.

20. The method according to any one of claims 17 to 19, characterized in that, The plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks.

21. The method according to claim 20, characterized in that, The input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks.

22. The method according to claim 21, characterized in that, The encoded bits include a coupled codeword, which includes a combination of a first encoded bit obtained by encoding the first code block and a second encoded bit obtained by encoding the second code block.

23. The method according to any one of claims 17 to 19, characterized in that, In multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein, in each iteration, the multiple code blocks include a shorter code block, which includes all the input bit values ​​of a longer code block, and the shorter code block is divided from the longer code block in the iteration.

24. The method according to claim 23, characterized in that, The plurality of code blocks include a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices.

25. The method according to claim 23 or 24, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block.

26. The method according to claim 23 or 24, characterized in that, The plurality of code blocks include a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices among the plurality of bit indices.

27. The method according to any one of claims 23 to 26, characterized in that, In each iteration, only the shorter code block is further divided into multiple shorter code blocks, each of which includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

28. The method according to any one of claims 23 to 26, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block.

29. The method according to claim 17, characterized in that, A corresponding tag is associated with the plurality of bit indices, and the value of the input bit and a predetermined input bit value are placed on the plurality of bit indices in such a way that the value of the input bit and the predetermined bit value are assigned to the corresponding tag, and the value of the input bit and the predetermined bit value of the corresponding tag are assigned to the plurality of bit indices, wherein the tag includes a subset of tags associated with the second set of bit indices for assigning each corresponding value of the second subset of the input bit to a corresponding two or more bit indices of the second set of bit indices.

30. The method according to claim 29, characterized in that, The tag is associated with the plurality of bit indices based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices.

31. The method according to claim 29 or 30, characterized in that, The tag also includes a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set.

32. The method according to any one of claims 29 to 31, characterized in that, Also includes: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices.

33. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 1 to 16.

34. An apparatus, characterized in that, include: An encoder is used to encode input bits using polar codes to obtain encoded bits. The polar codes include a plurality of bit indices for placing the values ​​of the input bits before encoding. The bit indices include: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for placing predetermined bit values. Each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices. An interface, coupled to the encoder, is used to output the encoded bits.

35. The apparatus according to claim 34, characterized in that, The interface is used for: The first communication device sends the encoded bits to the second communication device in the wireless communication network.

36. The apparatus according to claim 34 or 35, characterized in that, Each value of the second subset of the input bits placed on the two or more bit indices in the second set is such that, after decoding the input bit value for any one of the two or more bit indices, the input bit value is known for all the bit indices of the respective two or more bit indices.

37. The apparatus according to any one of claims 34 to 36, characterized in that, The plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks.

38. The apparatus according to claim 37, characterized in that, The input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks.

39. The apparatus according to claim 38, characterized in that, Also used for: The first encoded bits obtained by encoding the first code block and the second encoded bits obtained by encoding the second code block are combined to obtain a coupled codeword.

40. The apparatus according to any one of claims 34 to 39, characterized in that, In multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein at each iteration the multiple code blocks include a shorter code block, which includes all the input bit values ​​of a longer code block, and the shorter code block is divided from the longer code block at the time of the iteration.

41. The apparatus according to claim 40, characterized in that, The plurality of code blocks include a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices.

42. The apparatus according to claim 40 or 41, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block.

43. The apparatus according to claim 40 or 41, characterized in that, The plurality of code blocks include a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices among the plurality of bit indices.

44. The apparatus according to any one of claims 40 to 43, characterized in that, In each iteration, only the shorter code block is further divided into multiple shorter code blocks, each of which includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

45. The apparatus according to any one of claims 40 to 43, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block.

46. ​​The apparatus according to claim 34, characterized in that, The encoder is configured to encode the input bit by: assigning the value of the input bit and the predetermined bit value to a corresponding tag associated with the plurality of bit indices, and assigning the value of the input bit and the predetermined bit value of the corresponding tag to the plurality of bit indices, wherein the tag includes a subset of tags associated with a second set of bit indices, for assigning each corresponding value of the second subset of the input bit to the corresponding two or more bit indices of the second set of bit indices.

47. The apparatus according to claim 46, characterized in that, The tag is associated with the plurality of bit indices based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices.

48. The method according to claim 46 or 47, characterized in that, The tag also includes a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set.

49. The apparatus according to any one of claims 46 to 48, characterized in that, Also used for: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices.

50. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 17 to 32.

51. An apparatus, characterized in that, include: An interface for receiving encoded bits encoded by a polar code, the polar code including a plurality of bit indices for placing the values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values, wherein each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices; A decoder, coupled to the interface, is used to decode the encoded bits to obtain decoded input bits.

52. The apparatus according to claim 51, characterized in that, The interface is used for: The encoded bits are received from the first communication device via a second communication device in a wireless communication network.

53. The apparatus according to claim 51 or 52, characterized in that, The decoder is configured to decode the input bit value for each value of the second subset of the input bits placed on the two or more bit indices, for any one of the two or more bit indices.

54. The apparatus according to any one of claims 51 to 53, characterized in that, The plurality of bit indices are associated with a plurality of code blocks, and the second set of bit indices includes bit indices associated with a plurality of code blocks.

55. The apparatus according to claim 54, characterized in that, The input bit values ​​of the second subset of the input bits are placed on both the bit index associated with the first code block among the plurality of code blocks and the bit index associated with the second code block among the plurality of code blocks.

56. The apparatus according to claim 55, characterized in that, The encoded bits include a coupled codeword, which includes a combination of a first encoded bit obtained by encoding the first code block and a second encoded bit obtained by encoding the second code block.

57. The apparatus according to any one of claims 51 to 53, characterized in that, In multiple iterations, the input bit values ​​are recursively divided into multiple code blocks, wherein at each iteration the multiple code blocks include a shorter code block, which includes all the input bit values ​​of a longer code block, and the shorter code block is divided from the longer code block at the time of the iteration.

58. The apparatus according to claim 57, characterized in that, The plurality of code blocks include a single code block, wherein the corresponding input bit value is uniquely placed at the corresponding bit index in the plurality of bit indices.

59. The apparatus according to claim 57 or 58, characterized in that, The plurality of code blocks include a single code block, wherein corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a first portion of the code block, and corresponding input bit values ​​are uniquely placed at corresponding consecutive bit indices in a second portion of the code block. The corresponding input bit value placed at the corresponding consecutive bit index in the first part of the code block and the corresponding input bit value placed at the corresponding consecutive bit index in the second part of the code block each include: the value of the input bits of the second subset of the input bits placed at both the bit index in the first part of the code block and the bit index in the second part of the code block.

60. The apparatus according to claim 57 or 58, characterized in that, The plurality of code blocks include a single code block, wherein the values ​​of the input bits of the second subset of the input bits are placed on two or more bit indices among the plurality of bit indices.

61. The apparatus according to any one of claims 57 to 60, characterized in that, In each iteration, only the shorter code block is further divided into multiple shorter code blocks, each of which includes all the input bit values ​​of the longer code block, and the shorter code block is divided from the longer code block.

62. The apparatus according to any one of claims 57 to 60, characterized in that, In each iteration, the shorter code blocks derived from the longer code blocks in the previous iteration are each further divided into more even shorter code blocks. The plurality of shorter code blocks, which are derived from each shorter code block, include even shorter code blocks, each of which includes all the input bit values ​​of the shorter code block, and is further subdivided from the shorter code block.

63. The apparatus according to claim 51, characterized in that, A corresponding tag is associated with the plurality of bit indices, and the value of the input bit and the predetermined input bit value are placed on the plurality of bit indices in such a way that the value of the input bit and the predetermined bit value are assigned to the corresponding tag, and the value of the input bit and the predetermined bit value of the corresponding tag are assigned to the plurality of bit indices, wherein the tag includes a subset of tags associated with the second set of bit indices for assigning each corresponding value of the second subset of the input bit to the corresponding two or more bit indices of the second set of bit indices.

64. The apparatus according to claim 63, characterized in that, The tag is associated with the plurality of bit indices based on any one or more of the following: reliability order, bit index order, code bit interleaving sequence, transmission order, and a predefined order of a subset of the bit indices, the predefined order being based on the order of different subsets of the bit indices.

65. The apparatus according to claim 63 or 64, characterized in that, The tag also includes a single tag, the predetermined bit value is assigned to the single tag, and the single tag is associated with all bit indices in the third bit index set.

66. The apparatus according to any one of claims 63 to 65, characterized in that, Also used for: The corresponding tag is obtained from a mapping sequence that indicates the association between the corresponding tag and the plurality of bit indices.

67. A computer program product, characterized in that, Includes a non-transitory computer-readable medium storing a program for processor execution, the program comprising instructions for performing the following operations: Input bits are encoded using polar codes to obtain encoded bits. The polar codes include multiple bit indices for placing the values ​​of the input bits before encoding. These bit indices include: a first set of bit indices for placing values ​​of a first subset of the input bits; a second set of bit indices for placing values ​​of a second subset of the input bits; and a third set of bit indices for placing predetermined bit values. Wherein, each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set; Output the encoded bits.

68. A computer program product, characterized in that, Includes a non-transitory computer-readable medium storing a program for processor execution, the program comprising instructions for performing the following operations: Receive encoded bits encoded by a polar code, the polar code including a plurality of bit indices for placing the values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing the values ​​of a first subset of the input bits, a second set of bit indices for placing the values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values. Each value of the first subset of the input bits is placed at a bit index of the first bit index set, and each value of the second subset of the input bits is placed at two or more bit indices of the second bit index set; The encoded bits are decoded to obtain the decoded input bits.

69. A computer program product, characterized in that, The invention includes a non-transitory computer-readable medium storing a program for execution by a processor, the program comprising instructions for performing the method according to any one of claims 1 to 32.

70. A system, characterized in that, include: A first communication device is configured to transmit encoded bits encoded by a polar code, the polar code including bit indices for placing values ​​of input bits before encoding, the bit indices including: a first set of bit indices for placing values ​​of a first subset of the input bits, a second set of bit indices for placing values ​​of a second subset of the input bits, and a third set of bit indices for predetermined bit values, wherein each value of the first subset of the input bits is placed at one bit index of the first set of bit indices, and each value of the second subset of the input bits is placed at two or more bit indices of the second set of bit indices; A second communication device is configured to receive the encoded bits from the first communication device and decode the encoded bits to obtain decoded input bits.

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