Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to methods, devices, systems, and techniques for fabricating contact structures in semiconductor devices (e.g., 3D memory devices such as DRAM). An exemplary semiconductor device includes a first semiconductor structure and a second semiconductor structure connected together. The first semiconductor structure includes an array of memory cells and a first contact structure extending in a first direction. The first contact structure includes a first cross-section and a second cross-section both perpendicular to the first direction. The first cross-section is further away from the second semiconductor structure in the first direction than the second cross-section. The size of the first section is smaller than that of the second section.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] The demand for smaller, faster chips has driven the semiconductor industry. Manufacturers of memory devices and systems are also pushing for improvements in scaling technologies. Dynamic Random Access Memory (DRAM) is a common type of memory device widely used in computer systems. Therefore, advanced technologies are needed to mitigate problems and improve the scaling capabilities of DRAM devices. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for manufacturing contact structures in semiconductor devices, such as DRAM (e.g., 3D memory devices).

[0004] One aspect of this disclosure features a semiconductor device comprising a first semiconductor structure and a second semiconductor structure connected together. The first semiconductor structure includes an array of memory cells and a first contact structure extending along a first direction. The first contact structure includes a first cross-section and a second cross-section, both perpendicular to the first direction. Compared to the second cross-section, the first cross-section is further away from the second semiconductor structure along the first direction. The size of the first cross-section is smaller than the size of the second cross-section.

[0005] In some implementations, the second semiconductor structure includes peripheral circuitry associated with an array of memory cells, and the peripheral circuitry is coupled to the first contact structure.

[0006] In some embodiments, the size of the first cross section is the maximum size of the first cross section along a second direction perpendicular to the first direction, and the size of the second cross section is the maximum size of the second cross section along the second direction.

[0007] In some embodiments, the first contact structure extends through the semiconductor layer of the first semiconductor structure, and the first contact structure is spaced apart from the array of memory cells along a second direction perpendicular to the first direction.

[0008] In some embodiments, the semiconductor device further includes a bonding structure located between the first semiconductor structure and the second semiconductor structure. The second semiconductor structure is bonded to a first side of the first semiconductor structure via the bonding structure. The bonding structure includes conductive bonding pads and at least one dielectric material that isolates the conductive bonding pads in a second direction perpendicular to the first direction.

[0009] In some embodiments, the first semiconductor structure further includes an interconnect layer located between the first contact structure and the bonding structure along a first direction. A first end of the first contact structure is coupled to a conductive bonding pad of the conductive bonding pad of the bonding structure via the interconnect layer. A second end of the first contact structure is coupled to a first conductive contact structure located on a second side of the first semiconductor structure, the second side being opposite to the first side.

[0010] In some embodiments, the interconnect layer includes at least interconnect lines extending along a second direction and vertical interconnect channels (VIAs) extending along a first direction. Each VIA includes a third cross-section and a fourth cross-section, both perpendicular to the first direction. Compared to the fourth cross-section, the third cross-section is further away from the second semiconductor structure along the first direction. The size of the third cross-section is smaller than the size of the fourth cross-section.

[0011] In some embodiments, at least one memory cell in the array of memory cells includes a memory structure and a transistor extending along a first direction. A first end of the memory structure is coupled to the transistor. A second end of the memory structure is coupled to a second conductive contact structure that contacts a trench. The trench extends from a second side of the first semiconductor structure into the first semiconductor structure. Both the first and second conductive contact structures comprise aluminum.

[0012] In some embodiments, the second conductive contact structure includes a first portion, a second portion, and a third portion. The first portion and the second portion are connected via the third portion. The first portion and the second portion are perpendicular to a first direction. The first portion contacts the bottom of the trench. The third portion contacts the sidewall of the trench. The second portion contacts a portion of the second side that is connected to the sidewall of the trench.

[0013] In some embodiments, the ratio of the first dimension of the trench in the first direction to the second dimension of the trench in the second direction is less than 0.5.

[0014] In some embodiments, the first semiconductor structure further includes a second contact structure extending through a semiconductor layer of the first semiconductor structure along a first direction. The second contact structure is coupled to a peripheral circuit. The first contact structure is configured to transmit control signals to and from the peripheral circuit. The second contact structure is configured to provide power to the peripheral circuit.

[0015] Another aspect of this disclosure is a method comprising: forming a first semiconductor structure. The first semiconductor structure includes an array of memory cells. At least one memory cell in the array of memory cells includes a transistor extending along a first direction and a memory structure coupled to the transistor. The method further comprises: forming a contact structure in the first semiconductor structure. The contact structure extends along the first direction. The method further comprises: bonding the first semiconductor structure to a second semiconductor structure. The second semiconductor structure includes peripheral circuitry associated with the array of memory cells. The contact structure is coupled to the peripheral circuitry.

[0016] In some embodiments, forming a first semiconductor structure including an array of memory cells includes: a semiconductor body in which transistors are formed in a semiconductor layer of the first semiconductor structure, and forming a dielectric region extending through the semiconductor layer in a first direction.

[0017] In some embodiments, the first semiconductor structure includes a first side and a second side opposite to the first side. The first side is closer to the semiconductor layer along a first direction than the second side. Forming a contact structure in the first semiconductor structure includes: forming a contact hole in the first semiconductor structure by etching from the first side, wherein the contact hole extends through a dielectric region; and forming a contact structure in the contact hole by depositing a conductive material into the contact hole.

[0018] In some embodiments, the method further includes stacking a first semiconductor structure on a carrier wafer before forming a contact hole, wherein a second side contacts the carrier wafer.

[0019] In some embodiments, the method further includes forming an interconnect layer in a first semiconductor structure, wherein the interconnect layer is coupled to a contact structure and includes at least an interconnect line extending in a second direction perpendicular to the first direction and a VIA extending in the first direction.

[0020] In some embodiments, bonding the first semiconductor structure to the second semiconductor structure includes bonding the first semiconductor structure to the second semiconductor structure via a bonding structure. The bonding structure includes conductive bonding pads and at least one dielectric material isolating the conductive bonding pads in a second direction perpendicular to the first direction. The first side is located between the second side and the bonding structure.

[0021] In some embodiments, the method further includes: forming a trench extending from a second side of the first semiconductor structure into the first semiconductor structure; and forming a conductive contact structure in the trench by depositing a conductive material therein, wherein the conductive contact structure is coupled to the memory structure.

[0022] Another aspect of this disclosure features a memory system. The memory system includes a memory device and a memory controller coupled to and configured to control the memory device. The memory device includes a first semiconductor structure and a second semiconductor structure connected together. The first semiconductor structure includes an array of memory cells and a first contact structure extending along a first direction. The first contact structure includes a first cross-section and a second cross-section, both perpendicular to the first direction. Compared to the second cross-section, the first cross-section is further away from the second semiconductor structure along the first direction. The size of the first cross-section is smaller than the size of the second cross-section.

[0023] In some embodiments, the size of the first cross section is the maximum size of the first cross section along a second direction perpendicular to the first direction, and the size of the second cross section is the maximum size of the second cross section along the second direction. Attached Figure Description

[0024] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0025] Figure 1 A side view of a cross-section of an exemplary three-dimensional (3D) semiconductor device is shown.

[0026] Figures 2A-2G An exemplary manufacturing process for manufacturing semiconductor devices is shown.

[0027] Figure 3 A flowchart of an exemplary process for manufacturing a semiconductor device is shown.

[0028] Figure 4 A block diagram of an exemplary system is shown.

[0029] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0030] Contact structures in semiconductor devices (e.g., DRAM devices) can be configured to provide interconnections between components of the semiconductor device or to couple components of the semiconductor device to external circuitry (e.g., for pad take-off purposes). Fabrication of the contact structures may include forming contact holes in the semiconductor device via an etching process and depositing conductive material into the contact holes. In some embodiments, it may be difficult to form both longer (e.g., in the vertical direction) and shorter (e.g., in the vertical direction) contact structures using the same manufacturing process or cycle. One reason is that the etching process in the manufacturing cycle may cause loss of conductive material (e.g., tungsten (W)) in the semiconductor device when forming contact holes for shorter contact structures. However, using multiple etch masks and multiple etch processes to form both longer and shorter contact structures may increase manufacturing costs and reduce production yield.

[0031] Embodiments of this disclosure provide techniques for forming a semiconductor device including a first semiconductor structure and a second semiconductor structure connected together. Contact structures extending through the first semiconductor structure and vertical interconnect channel (VIA) contacts located in the interconnect layer of the first semiconductor structure can be formed in the same manufacturing cycle. For example, the contact structures and VIA contacts can be formed before the first semiconductor structure is bonded to the second semiconductor structure.

[0032] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. Contact structures of different dimensions along the vertical direction can be formed through different manufacturing cycles, thereby avoiding tungsten loss problems. The bottom-top metal (BTM) and the bottom-top VIA (BTV) coupled to the BTM can be combined into a single conductive structure, thereby reducing manufacturing costs and increasing production yield. Furthermore, the conductive structure replacing the BTM and BTV can be made of aluminum (Al) instead of W, further reducing manufacturing costs.

[0033] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), and others. It can also be applied to charge-trap-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-layer memory) devices, MLC (multi-layer memory) devices (e.g., 2-layer memory devices), TLC (triple-layer memory) devices, QLC (quadruple-layer memory) devices, or PLC (five-layer memory) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and others.

[0034] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0035] Figure 1 A side view of a cross-section of an exemplary 3D semiconductor device 100 is shown. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that... Figure 1 For illustrative purposes only and may not necessarily reflect actual device structures (e.g., interconnections) in practice. The 3D semiconductor device 100 includes semiconductor structures 102 and 104 connected together. In some embodiments, the 3D semiconductor device 100 is a bonded chip including semiconductor structure 104 stacked on top of semiconductor structure 102. Semiconductor structures 102 and 104 may be bonded at a bonding structure 103 located therebetween. Semiconductor structure 104 may have two sides 107 and 109. Side 107 (e.g., bottom surface) is closer to semiconductor structure 102. Side 109 (e.g., top surface) is further away from semiconductor structure 102 and opposite to side 107.

[0036] It should be noted that, in Figure 1The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of the various components in a semiconductor device. The substrate of the semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface located on the front side of the wafer on which components of the semiconductor device can be formed, and a bottom surface located on the back side of the wafer opposite the front side. The Z direction is perpendicular to both the X and Y directions. As used herein, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0037] like Figure 1 As shown, the semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The semiconductor structure 102 may include peripheral circuitry 112 located on and / or within the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., the well, source, and drain of the transistors 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or CMOS die 102.

[0038] In some embodiments, the semiconductor structure 102 further includes an interconnect layer 116 located above the peripheral circuitry 112 for transmitting electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect channel (VIA) contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which the interconnects and VIA contacts can be formed. That is, the interconnect layer 116 may include interconnects and VIA contacts located in a plurality of ILD layers. In some embodiments, the peripheral circuitry 112 is coupled to each other via interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to: W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric materials may be used to form the ILD layers, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0039] like Figure 1 As shown, bonding structure 103 may include bonding layer 118 (also referred to as bonding structure) and bonding layer 120 bonded at bonding interface 106 therebetween. Bonding layer 118 may be located above interconnect layer 116 and peripheral circuitry 112. Bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. Bonding contacts 119 may include a conductive material, such as Cu. A dielectric material (e.g., silicon oxide) may be used to form the remaining area of ​​bonding layer 118. The bonding contacts 119 in bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Bonding layer 120 may be located above bonding layer 118. Bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. Bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 can be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric can be used for hybrid bonding. The bonding contacts 121 can contact the bonding contacts 119 at the bonding interface 106. In some embodiments, such as Figure 1 As shown, the bonding layer 120 includes a dielectric layer opposite to a memory cell (e.g., a DRAM cell) 124, wherein bit lines 123 are located between the dielectric layer and the memory cell 124. The dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0040] In some embodiments, bonding layer 118 may be considered part of semiconductor structure 102, and bonding layer 120 may be considered part of semiconductor structure 104. Semiconductor structure 104 may be bonded face-to-face to the top of semiconductor structure 102 at bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), bonding interface 106 is disposed between bonding layers 120 and 118. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, bonding interface 106 is where bonding layers 120 and 118 meet and bond. In some examples, bonding interface 106 may be a layer of a specific thickness, comprising the top surface of bonding layer 118 and the bottom surface of bonding layer 120.

[0041] In some embodiments, the semiconductor structure 104 further includes an interconnect layer 122, which is located above the bonding layer 120 to transmit electrical signals. The interconnect layer 122 may include multiple interconnects, such as mid-stage (MEOL) interconnects and back-end stage (BEOL) interconnects. The multiple interconnects in the interconnect layer 122 may include lateral interconnects and VIA contacts. In some embodiments, the interconnects in the interconnect layer 122 may also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include interconnects and VIA contacts that can be formed in one or more ILD layers. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to: W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric materials may be used to form the ILD layers, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0042] In some embodiments, peripheral circuitry 112 includes a word line driver / row decoder coupled to word line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bit line driver / column decoder coupled to bit lines 123 and bit line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bit line 123 is a metallic bit line opposite to a semiconductor bit line (e.g., a doped silicon bit line). For example, bit line 123 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts instead of Schottky contacts. In some embodiments, bit line 123 is made of a composite conductive material, which may be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, composite conductive materials may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0043] In some embodiments, the semiconductor structure 104 includes a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122, including bit lines 123, may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to a string of DRAM cells 124. In some embodiments, the semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0044] In some embodiments, a semiconductor device may include a plurality of array dies (e.g., array die 104) and a CMOS die (e.g., CMOS die 102). The array dies and CMOS dies may be stacked and bonded together. A CMOS die may be coupled to each of the array dies individually and may drive each of the array dies individually to operate in a manner similar to that of the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer face-to-face bonded. Array dies may be disposed on the first wafer along with other array dies, and CMOS dies may be disposed on the second wafer along with other CMOS dies. The first and second wafers may be bonded together, so that an array die on the first wafer may be bonded to a corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least array dies and CMOS dies bonded together. In this example, the chip is diced from the bonded wafer. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a packaging substrate.

[0045] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a vertically (e.g., in the Z direction) extending semiconductor body 130 and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, for example, as... Figure 1 As shown, the semiconductor body 130 may have a cuboid or cylindrical shape, and the gate structure 136 may be adjacent to one side of the semiconductor body 130 in a plan view. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a two-gate structure, a three-gate structure, or a gate all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in the bit line direction (e.g., in the X direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the semiconductor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0046] like Figure 1As shown, in some embodiments, the semiconductor body 130 has two ends in the vertical direction (e.g., the Z direction). Figure 1 The semiconductor body 130 has two ends (upper and lower) extending in a vertical direction (e.g., the lower end) beyond the gate dielectric 132 into the ILD layer. In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (upper and lower) of the semiconductor body 130 extend in a vertical direction (e.g., the Z direction) beyond the gate electrode 134 into the ILD layer. That is, the semiconductor body 130 may have a vertical dimension (e.g., depth) larger than the vertical dimension of the gate electrode 134 (e.g., in the Z direction), and neither the upper nor lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. Therefore, short circuits between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 may also include a source and a drain disposed at opposite ends (upper and lower) of the semiconductor body 130 in a vertical direction (e.g., the Z direction). (Since their positions can be interchanged, both are referred to as 138.) In some embodiments, one of the source and drain 138 (e.g., in…) Figure 1 At the upper end of the middle) it is coupled to capacitor 128, and the other of the source and drain 138 (e.g., in the upper end of the middle) ... Figure 1 At the lower end of the line, it is coupled to line 123. That is to say, as... Figure 1 As shown, the vertical transistor 126 may have a first terminal in the positive Z direction and a second terminal opposite to the first terminal in the negative Z direction.

[0047] In some embodiments, the semiconductor structure 104 further includes a substrate 148 disposed above the interconnect layer 122. The semiconductor body 130 may be formed from the substrate 148 (e.g., by etching or epitaxy) and thus have the same semiconductor material as the substrate 148. The semiconductor body 130 may include semiconductor materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include monocrystalline silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or formed between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142, thereby reducing contact resistance. In some embodiments, the gate dielectric 132 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. In some embodiments, the gate electrode 134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the gate electrode 134 comprises multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 132 comprises silicon oxide and the gate electrode 134 comprises doped polysilicon. In another example, the gate structure 136 may be an HKMG, wherein the gate dielectric 132 comprises a high-k dielectric and the gate electrode 134 comprises a metal.

[0048] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in the word line direction (e.g., the Y direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each of which extends in the word line direction (e.g., the Y direction). Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit line 123 and the word line 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions in which the bit line 123 and the word line 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, including but not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, such as Figure 1 As shown, word line 134 includes multiple conductive layers, such as a W layer located above the TiN layer.

[0049] In some implementations, such as Figure 1 As shown, the vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 at its lower end contacts the bit line 123 (or, if any, a bit line contact). Accordingly, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically disposed between the bonding layer 120 and the word line 134, and the word line 134 is vertically disposed between the bit line 123 and the capacitor 128.

[0050] like Figure 1As shown, in some embodiments, capacitor 128 includes a first electrode 144 located above the source or drain 138 of vertical transistor 126 (e.g., the upper end of semiconductor body 130) and coupled to the source or drain 138 of vertical transistor 126 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact (e.g., a metal silicide contact) rather than a Schottky contact. For example, capacitor contact 142 may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric located above and in contact with the first electrode 144, and a second electrode located above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor, wherein the electrodes and capacitor dielectric are stacked vertically (in the Z direction), and the capacitor dielectric may be sandwiched between the electrodes. In some implementations, each first electrode 144 is coupled to the source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., a common ground). Figure 1 As shown, capacitor 128 may have a first end in the negative Z direction and a second end in the positive Z direction opposite to the first end. In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of metal silicide material).

[0051] It should be understood that the structure and construction of capacitor 128 are not limited to... Figure 1 Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to: Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes include a conductive material, including but not limited to: W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0052] like Figure 1As shown, the second semiconductor structure 104 may further include a contact structure 147 (also referred to as a pad lead-out contact structure or conductive contact structure) that contacts the common plate 146 for coupling the capacitor 128 to an external circuit, for example, for pad lead-out purposes. In some embodiments, such as Figure 1 As shown, contact structure 147 may be a conductive pad that contacts trench 149. Trench 149 may extend from side 109 into semiconductor structure 104 and expose common plate 146. In some embodiments, the ratio of a first dimension of trench 149 in the vertical direction (e.g., Z direction) to a second dimension of trench 149 in the horizontal direction (e.g., X direction) is less than 0.5. For example, this ratio may be 0.3. Contact structure 147 contacts the bottom surface of trench 149 (e.g., a portion of common plate 146) and sidewalls. Figure 1 As shown, the contact structure 147 may also cover a portion of the side 109. In some embodiments, such as Figure 1 As shown, the contact structure 147 includes a first portion 147a, a second portion 147b, and a third portion 147c. The first portion 147a and the second portion 147b are connected via the third portion 147c. The first portion 147a and the second portion 147b extend in the XY plane (e.g., perpendicular to the Z direction). The first portion 147a contacts the bottom of the trench 149. The third portion 147c contacts the sidewall of the trench 149. The second portion 147b contacts the portion of the sidewall 109 that connects to the sidewall of the trench 149. In some embodiments ( Figure 1 In (not shown), contact structure 147 may include one or more conductive pads (also referred to as bottom top metal (BTM)) disposed on side 109, and one or more conductive VIAs (also referred to as bottom top VIA (BTV)) extending along the Z direction and connecting the conductive pads and common board 146. In some embodiments, contact structure 147 includes a conductive material, including but not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

[0053] like Figure 1As shown, the semiconductor structure 104 may further include one or more contact structures 150 (also referred to as pad lead-out contact structures) extending along the Z-direction. Since each contact structure 150 extends from the side 109 into the semiconductor structure 104 and through the substrate 148, the contact structure 150 may also be referred to as a through-silicon contact (TSC). In some embodiments, the contact structures 150 may be spaced apart from the array of DRAM cells 124 in a horizontal direction (e.g., the X-direction). In some embodiments, the semiconductor structure 104 may include a dielectric spacer (e.g., having silicon oxide) located between each contact structure 150 and the substrate 148 to electrically isolate the contact structure 150 from the substrate 148. One end of the contact structure 150 may be connected to a conductive pad 152 disposed on the side 109, and the other end of the contact structure 150 may be coupled to an interconnect layer 122. Therefore, peripheral circuitry 112 can be coupled to DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and DRAM cell 124 can be coupled to external circuitry via contact structure 150 and conductive pad 152. Contact structure 150 and conductive pad 152 may include conductive materials, including but not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. Contact structure 150 and conductive pad 152 may include the same conductive material or different conductive materials. In some embodiments, contact structure 150 includes W, and conductive pad 152 includes Al. Contact structure 150 may be configured to transmit electrical signals between 3D semiconductor device 100 and external circuitry, for example, for pad lead-out purposes. For example, one contact structure 150 may be configured to transmit control signals to and from peripheral circuitry 112, and another contact structure 150 may be configured to provide power to peripheral circuitry 112.

[0054] In some embodiments, each contact structure in contact structure 150 may have, for example, a cylindrical or frustum-shaped form that tapers along the Z-direction. For example, the cross-section of the top portion of contact structure 150 may have a smaller dimension than another cross-section of the bottom portion of contact structure 150. Figure 1 As shown, the contact structure 150 may have cross sections 154 and 156, both perpendicular to the Z-direction. Compared to cross section 156, cross section 154 is further away from the semiconductor structure 102 along the Z-direction. In other words, compared to cross section 156, cross section 154 is closer to the side surface 109 of the semiconductor structure 104 along the Z-direction. The size of cross section 154 is smaller than the size of cross section 156. In some embodiments, the size of cross section 154 is the maximum size of cross section 154 along the horizontal direction (e.g., the X-direction), and the size of cross section 156 is the maximum size of cross section 156 along the same horizontal direction (e.g., the X-direction).

[0055] In some embodiments, the VIA (e.g., VIA 158) in interconnect layer 122 (which may also be referred to as a VIA contact or VIA contact structure) also has, for example, a cylindrical or frustum-shaped form that tapers along the Z direction. For example, VIA 158 may have a top section and a bottom section (not shown) both perpendicular to the Z direction. The top section of VIA 158 is further away from the semiconductor structure 102 along the Z direction than the bottom section of VIA 158. The size of the top section of VIA 158 is smaller than the size of the bottom section of VIA 158. In some embodiments, for example, as discussed later... Figure 2C In more detail, the VIA in interconnect layer 122 and the contact structure 150 are formed by the same manufacturing process or manufacturing cycle.

[0056] Figures 2A-2G This illustrates a method for manufacturing semiconductor devices (e.g., Figure 1 An exemplary manufacturing process for a semiconductor device 100 in the example.

[0057] like Figure 2A As shown, a semiconductor structure 200 can be formed. The semiconductor structure 200 can be... Figure 1 The example of semiconductor structure 104 differs in that some pads lead out contact structures (e.g., Figure 1 Contact structures 147, 150, and conductive pads 152 (as well as interconnect layers, e.g., Figure 1 At least a portion of the interconnect layer 122 in the semiconductor structure 200 has not yet been formed.

[0058] The semiconductor structure 200 can be formed using any suitable semiconductor manufacturing technology. The semiconductor structure 200 may include a semiconductor layer 201 and a DRAM cell 202 (e.g., Figure 1 An array of DRAM cells 124. The semiconductor layer 201 may be a substrate (e.g., ...). Figure 1 The substrate 148 in the DRAM cell 202 includes vertical transistors 204 (e.g., substrate 148). Figure 1 Vertical transistor 126) and capacitor 208 (e.g., Figure 1 (Capacitor 128 in the DRAM cell 202). Each DRAM cell 202 may include a vertical transistor 204 and a corresponding capacitor 208 coupled to the vertical transistor 204. Each vertical transistor 204 may be a MOSFET for switching the corresponding DRAM cell 202. In some embodiments, each vertical transistor 204 includes a corresponding semiconductor body 210 extending vertically (e.g., in the Z direction). Figure 1The semiconductor body 130 in the semiconductor body 210 and the corresponding gate structure (e.g., in contact with one side of the semiconductor body 210) Figure 1 Gate structure 136 in Figure 2A (Not shown in the image). The semiconductor body 210 can be formed from the substrate 201 (e.g., by etching or epitaxy) and therefore has the same semiconductor material as the substrate 201. For example, the semiconductor body 210 can be formed during an etching process by forming trenches extending in the lateral direction (e.g., the X and Y directions) in the substrate 201. The gate structure of the vertical transistor 204 can be formed by depositing a gate dielectric layer and a conductive layer on each semiconductor body 210.

[0059] like Figure 2A As shown, the semiconductor body 210 has two ends in the vertical direction (e.g., the Z direction). The vertical transistor 204 may also include a source and a drain respectively disposed at the two ends (upper and lower ends) of the semiconductor body 210 in the vertical direction (e.g., the Z direction) (both are referred to as 212 because their positions can be interchanged). In some embodiments, the source and drain 212 (e.g., Figure 1 The source and drain 138 in the transistor 204 can be formed by doping the semiconductor body 210 of each vertical transistor 204 with a dopant (e.g., a P-type dopant or an N-type dopant). In some embodiments, for each vertical transistor 204, one of the source and drain 212 (e.g., in the...) is formed by doping the semiconductor body 210 of each vertical transistor 204 with a dopant (e.g., in the...) Figure 2A At the lower end of the capacitor 208, the source and drain 212 are coupled to one of the capacitors in the capacitor 208, and the other of the source and drain 212 (e.g., in the lower end of the capacitor 208) is coupled to the other of the capacitors in the capacitor 208. Figure 2A At the upper end of the middle) it is coupled to bit line 214 extending along the X direction (e.g., at the upper end of the middle) to bit line 214 (e.g., Figure 1 (Bit line 123 in the middle). The array of DRAM cells 202 can be located between bit line 214 and capacitor 208 along the Z direction.

[0060] In some embodiments, each capacitor in capacitor 208 may be a vertical capacitor comprising a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric stacked vertically (e.g., in the Z direction). Capacitor 208 may be formed by forming vias extending in the Z direction and adjacent to the vertical transistor 204 (e.g., by etching). For each via, a first capacitor electrode (e.g., a first conductive layer) is formed on the inner surface of the via, and then a capacitor dielectric (e.g., a dielectric layer in contact with the first conductive layer) and a second capacitor electrode (e.g., a second conductive layer in contact with the dielectric layer) are formed. Each capacitor 208 includes a dielectric layer sandwiched between the first capacitor electrode and the second capacitor electrode. In some embodiments, each first capacitor electrode is connected via a corresponding capacitor contact 216 (e.g., Figure 1The capacitor contact 142) is coupled to the source or drain 212 of the corresponding vertical transistor 204 located in the same DRAM cell, while the second capacitor electrode is coupled to the common plate 218 (e.g., Figure 1 (The common board 146 in the middle). The semiconductor structure 200 may also include multiple word lines (e.g., Figure 1 The character line 134 in the middle Figure 2A (Not shown in the image), each of these multiple word lines extends in a word line direction (e.g., the Y direction). Each word line can be coupled to a row of DRAM cells 202.

[0061] The substrate 201 may include one or more isolation structures 220 extending through the substrate 201 in the Z direction. Each isolation structure 220 may include a dielectric material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Therefore, the isolation structure 220 may also be referred to as a dielectric region. In some embodiments, the isolation structure 220 may be formed by etching the substrate 201 (which may be performed in the same etching process used to fabricate the semiconductor body 210) to form a hole extending through the substrate 201 and then filling the hole with a dielectric material. Subsequently, one or more pad lead-out contact structures may be formed, each of the one or more pad lead-out contact structures extending through the corresponding isolation structure 220 in the Z direction (e.g., as per [reference to...]). Figures 2A-2C (As described). The isolation structure 220 may lead out contact structures around the pads and isolate the pad lead-out contact structures from the substrate 201. In some embodiments, the dielectric material of the isolation structure 220 (instead of the silicon of the substrate 201) is etched away when the pad lead-out contact structures are formed. The etching process of the isolation structure 220 may be faster than the etching process of the substrate 201, thereby improving the efficiency of the manufacturing process.

[0062] like Figure 2A As shown, the semiconductor structure 200 can be stacked on the carrier wafer 222. The semiconductor structure 200 can be bonded to the carrier wafer 222 using any suitable bonding technique. For example, the semiconductor structure 200 can be bonded to the carrier wafer 222 via an adhesive layer (not shown) disposed therebetween. The adhesive layer can include any suitable type of adhesive. In some embodiments, the semiconductor structure 200 can be bonded to the carrier wafer 222 using a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive). The carrier wafer 222 can provide physical support and protection for the semiconductor structure 200 during the manufacturing process.

[0063] like Figure 2BAs shown, contact holes 224 and VIA holes 226 extending along the Z-direction are formed. Contact holes 224 extend through the semiconductor structure 200. The semiconductor structure 200 may include a first side 228 and a second side 230 opposite to the first side 228. Compared to the second side 230, the first side 228 is closer to the substrate 201 along the Z-direction. The second side 230 may contact the carrier wafer 222. In some embodiments, contact holes 224 can be formed by etching away dielectric material in the isolation structure 220 of the semiconductor structure 200 from the first side 228. Contact holes 224 extend through the corresponding isolation structure 220 from the first side 228 to the second side 230. VIA holes 226 can also be formed by etching away semiconductor structure 200 from the first side 228. VIA holes 226 can extend from the first side 228 into the semiconductor structure 200. In some embodiments, each contact hole 224 may have a top cross-section 232 and a bottom cross-section 234, both perpendicular to the Z-direction. Compared to the bottom section 234, the top section 232 is closer to the first side 228 along the Z direction. The size of the top section 232 is larger than the size of the bottom section 234. In some embodiments, each VIA hole 226 may have a top section 236 and a bottom section 238, both perpendicular to the Z direction. Compared to the bottom section 238, the top section 236 is closer to the first side 228 along the Z direction. The size of the top section 236 is larger than the size of the bottom section 238.

[0064] like Figure 2C As shown, contact structure 240 can be formed by depositing conductive material into contact hole 224, and VIA 242 can be formed by depositing conductive material into VIA hole 226. In some embodiments, VIA 242 and contact structure 240 are formed through the same manufacturing process or the same manufacturing cycle. Conductive materials can include, but are not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. Contact structure 240 can be... Figure 1 Example of contact structure 150 in VIA 242. Figure 1 Example of VIA 158. VIA 242 can belong to interconnect layer 244 (e.g., Figure 1 Interconnect layer 122 in the middle.

[0065] like Figure 2DAs shown, semiconductor structure 256 can be formed from semiconductor structure 200 by forming other portions of interconnect layer 244 (e.g., interconnect lines 246 extending in a horizontal direction (e.g., X direction) and VIA 248 extending in a vertical direction (e.g., Z direction)) on top of semiconductor structure 200. Interconnect layer 244 can be coupled to contact structure 240. VIA 242 and VIA 248 can be made of different materials. For example, VIA 242 can be made of W, while VIA 248 can be made of Cu. In some embodiments, bonding layer (also referred to as bonding structure) 250 can be formed on top of interconnect layer 244. Figure 2D As shown, the top of the interconnect layer 244 can be considered as a side 245 of the semiconductor structure 256. Side 245 is opposite to side 230. Compared to side 230, side 245 is closer to the substrate 201 along the Z direction. The bonding layer 250 may include conductive bonding pads 252 and a dielectric material 254 that isolates the conductive bonding pads 252 in a horizontal direction (e.g., the X direction). The semiconductor structure 256 may be... Figure 1 Example of semiconductor structure 104 in the example.

[0066] like Figure 2E As shown, carrier wafer 222 can be removed or debonded from semiconductor structure 256. Semiconductor structure 256 can be flipped and bonded to semiconductor structure 258. For example, semiconductor structure 256 can be bonded to semiconductor structure 258 via bonding structure 266. Bonding structure 266 is formed by bonding layer 250 and bonding layer (also referred to as bonding structure) 260 joined at bonding interface 269. Bonding layer 260 is located between bonding layer 250 and semiconductor structure 258. Bonding layer 260 may include conductive bonding pads 262 and dielectric material 264 isolating conductive bonding pads 262 in a horizontal direction (e.g., X direction). In some embodiments, bonding layer 250 can be bonded to bonding layer 260 using direct bonding techniques (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and metal-to-metal bonding and dielectric-to-dielectric bonding can be obtained simultaneously. That is, the conductive bonding pads 252 in bonding layer 250 are bonded to the conductive bonding pads 262 in bonding layer 260, and the dielectric material 254 in bonding layer 250 is bonded to the dielectric material 264 in bonding layer 260. Bonding layer 250 can be... Figure 1 An example of bonding layer 120. Bonding layer 260 can be... Figure 1 Example of bonding layer 118 in the example.

[0067] In some embodiments, semiconductor structure 256 and semiconductor structure 258 can be fabricated in parallel. Semiconductor structure 258 can be... Figure 1An example of semiconductor structure 102. For example, semiconductor structure 258 may include substrate 267 and peripheral circuitry 268 located on and / or within substrate 267. Peripheral circuitry 268 may be... Figure 1 Examples of peripheral circuitry 112 are shown. In some embodiments, peripheral circuitry 268 includes a plurality of transistors 270 (e.g., planar transistors and / or 3D transistors). In some embodiments, semiconductor structure 258 also includes an interconnect layer 272 located above peripheral circuitry 268 for transmitting electrical signals to and from peripheral circuitry 268. In some embodiments, peripheral circuitry 268 may be configured to control an array of DRAM cells 202. For example, peripheral circuitry 268 may include word line drivers and / or bit line drivers for the array of DRAM cells 202. Peripheral circuitry 268 may be coupled to DRAM cells 202 via interconnect layer 272, bonding structure 266, and interconnect layer 244.

[0068] like Figure 2F As shown, trench 274 can be formed by an etching process. Trench 274 can extend from the side 230 of semiconductor structure 256 into semiconductor structure 256. Trench 274 can expose the common plate 218 coupled to capacitor 208. Trench 274 can be Figure 1 Example of groove 149 in the text.

[0069] like Figure 2G As shown, a semiconductor device 280 is formed. The semiconductor device 280 includes a semiconductor structure 256, a bonding structure 266, and a semiconductor structure 258. The semiconductor structure 256 includes conductive pads 276 and contact structures 278. The conductive pads 276 can be formed by depositing conductive material on the top of the side surface 230. Each conductive pad 276 can be connected to one end of a corresponding contact structure 240 (e.g., the top end). The contact structures 278 can be formed by depositing conductive material in a trench 274 and on the top of the side surface 230. The conductive pads 276 can be... Figure 1 Example of conductive pad 152. Contact structure 278 can be Figure 1 An example of contact structure 147 is shown. Each of the conductive pads 276 and contact structures 278 can be made of a conductive material, including but not limited to: W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the conductive pads 276 and contact structures 278 are made of Al instead of W, thereby reducing the cost of the manufacturing process. Although Figure 2GTwo conductive pads 276 and one contact structure 278 are shown; however, it should be understood that any suitable number of conductive pads and contact structures can be formed. For example, multiple contact structures 278 can be formed and coupled to a common board 218, thereby increasing the contact area between the contact structures 278 and the common board 218 and reducing the resistance caused by the contact structures 278. It should also be understood that, although Figure 2G The conductive pads 276 and contact structures 278 shown are merely examples, but any other suitable conductive pads and contact structures can be formed that are coupled to contact structures 240 and common board 218, respectively.

[0070] Figure 3 A flowchart of an exemplary process 300 is shown. Process 300 can be performed to form a semiconductor device (e.g., DRAM). For example, the semiconductor device may be... Figure 1 Semiconductor device 100 or Figure 2G The semiconductor device 280 in the middle. It can be based on... Figures 2A-2G To describe process 300. Process 300 may include forming Figures 2A-2G The semiconductor structure manufacturing process described in process 300. It should be understood that the operations shown in process 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in conjunction with... Figure 3 The different execution sequences are shown.

[0071] At operation 302, a first semiconductor structure is formed (e.g., Figure 2D-Figure 2G The semiconductor structure 256 in the image). The first semiconductor structure may include an array of memory cells (e.g., ...). Figure 2A An array of DRAM cells 202. At least one memory cell in the array of memory cells includes a transistor (e.g., a vertical transistor 204) extending along a first direction (e.g., the Z direction) and a memory structure coupled to the transistor (e.g., Figure 2A (Capacitor 208 in the middle).

[0072] In some embodiments, forming the first semiconductor structure includes forming a semiconductor body (e.g., a transistor) in a semiconductor layer (e.g., substrate 201) of the first semiconductor structure. Figure 2A Semiconductor body 210 in the middle.

[0073] In some embodiments, forming the first semiconductor structure further includes: forming a dielectric region extending through the semiconductor layer along a first direction (e.g., Figure 2A (Isolation structure 220 in the middle).

[0074] At operation 304, a contact structure is formed within the first semiconductor structure (e.g., ...). Figure 1 Contact structure 150 or Figure 2C The contact structure 240 extends along a first direction. In some embodiments, the first semiconductor structure includes a first side (e.g., Figure 2D Side 245) and the second side opposite to the first side (e.g., Figure 2D (230) of the side layer. Compared to the second side, the first side can be closer to the semiconductor layer along the first direction.

[0075] In some embodiments, forming a contact structure in the first semiconductor structure includes: forming a contact hole in the first semiconductor structure by etching from a first side (e.g., Figure 2B (Contact hole 224 in the first semiconductor structure). In some embodiments, the contact hole may extend through the dielectric region. In some embodiments, forming a contact structure in the first semiconductor structure further includes depositing a conductive material into the contact hole.

[0076] In some implementations, the first semiconductor structure may be stacked on the carrier wafer (e.g., before the contact holes are formed) Figure 2A The first semiconductor structure is mounted on a carrier wafer 222. The carrier wafer can provide physical support and protection to the first semiconductor structure during the manufacturing process. In some embodiments, a second side (e.g., side 230) of the first semiconductor structure is in contact with the carrier wafer.

[0077] In some implementations, the interconnect layer (e.g., Figure 2D Interconnect layer 244 can be formed in the first semiconductor structure. The interconnect layer can be coupled to a contact structure. The interconnect layer can include at least interconnect lines extending along a second direction perpendicular to the first direction (e.g., Figure 2D Interconnect 246) and VIA extending along the first direction (e.g., Figure 2D (VIA in VIA242 or 248).

[0078] At operation 306, the first semiconductor structure is bonded to the second semiconductor structure (e.g., ...). Figure 2E The second semiconductor structure may include peripheral circuitry associated with the array of memory cells (e.g., semiconductor structure 258). Figure 2E (External circuit 268 in the middle). Contact structures are coupled to the external circuits. In some embodiments, the carrier wafer can be removed or debonded from the first semiconductor structure. In some embodiments, the first semiconductor structure can be debonded through bonding structures (e.g., Figure 2EThe bonding structure 266 is bonded to the second semiconductor structure. The bonding structure includes conductive bonding pads (e.g., conductive bonding pads 252 and 262) and at least one dielectric material (e.g., dielectric materials 254 and 264) isolating the conductive bonding pads in a second direction perpendicular to the first direction. In some embodiments, the first side of the first semiconductor structure (e.g., ...) is... Figure 2E Side 245) is located on the second side of the first semiconductor structure (e.g., Figure 2E The side 230) is between the bonded structure.

[0079] In some embodiments, process 300 further includes: forming a trench (e.g., Figure 2F The trench 274 extends from a second side of the first semiconductor structure into the first semiconductor structure. In some embodiments, process 300 further includes forming a conductive contact structure (e.g., ...) in the trench. Figure 2G (Contact structure 278 in the example). For example, a conductive contact structure can be formed by depositing a conductive material (e.g., Al) in a trench. The conductive contact structure can be coupled to a storage structure.

[0080] Figure 4 A block diagram of an exemplary system 400 is shown. System 400 may have one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure. System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 4 As shown, system 400 may include a host device 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. The host device 408 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 408 may be configured to send data to or receive data from one or more memory devices 404.

[0081] Memory device 404 can be any memory device disclosed herein, such as... Figure 1 and Figures 2A-2GThe memory device shown is an example of a DRAM device. In some embodiments, memory device 404 includes NAND flash memory. A memory controller 406 (also referred to as controller circuitry) is coupled to memory device 404 and host device 408. Consistent with embodiments of this disclosure, memory device 404 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and memory controller 406 may be coupled to memory device 404 through at least one of the plurality of conductive interconnects. Memory controller 406 is configured to control memory device 404. For example, memory controller 406 may be configured to operate a plurality of channel structures via word lines. Memory controller 406 may manage data stored in memory device 404 and communicate with host device 408.

[0082] In some embodiments, the memory controller 406 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 406 may be configured to control the operation of the memory device 404 (e.g., read operations, erase operations, and programming (or write) operations). The memory controller 406 may also be configured to manage various functions regarding data stored or to be stored in the memory device 404, including but not limited to: bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 404. The memory controller 406 can also perform any other appropriate functions, such as formatting the memory device 404.

[0083] The memory controller 406 can communicate with external devices (e.g., host device 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0084] The memory controller 406 and one or more memory devices 404 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 402 can be implemented and packaged into different types of end electronic products. Figure 4 In one example shown, the memory controller 406 and the single memory device 404 can be integrated into the memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0085] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0086] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0087] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0088] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0089] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0090] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0091] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0092] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0093] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0094] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0095] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0096] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0097] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0098] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0099] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0100] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device comprising a first semiconductor structure and a second semiconductor structure connected together, wherein: The first semiconductor structure includes an array of memory cells and a first contact structure extending along a first direction; The first contact structure includes a first cross section and a second cross section, both of which are perpendicular to the first direction; Compared to the second cross section, the first cross section is further away from the second semiconductor structure along the first direction; and The size of the first cross section is smaller than the size of the second cross section.

2. The semiconductor device according to claim 1, wherein, The second semiconductor structure includes peripheral circuitry associated with the array of memory cells, and the peripheral circuitry is coupled to the first contact structure.

3. The semiconductor device according to claim 1 or claim 2, wherein, The dimension of the first cross section is the maximum dimension of the first cross section along a second direction perpendicular to the first direction, and the dimension of the second cross section is the maximum dimension of the second cross section along the second direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The first contact structure extends through the semiconductor layer of the first semiconductor structure, and the first contact structure is spaced apart from the array of memory cells along a second direction perpendicular to the first direction.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a bonding structure located between the first semiconductor structure and the second semiconductor structure, wherein: The second semiconductor structure is bonded to a first side of the first semiconductor structure via the bonding structure; and The bonding structure includes conductive bonding pads and at least one dielectric material that isolates the conductive bonding pads in a second direction perpendicular to the first direction.

6. The semiconductor device according to claim 5, wherein: The first semiconductor structure further includes an interconnect layer located between the first contact structure and the bonding structure along the first direction; The first end of the first contact structure is coupled to one of the conductive bonding pads of the bonding structure through the interconnect layer; and The second end of the first contact structure is coupled to a first conductive contact structure located on a second side of the first semiconductor structure, the second side being opposite to the first side.

7. The semiconductor device according to claim 6, wherein: The interconnect layer includes at least interconnect lines extending along the second direction and vertical interconnect channels (VIA) extending along the first direction; The VIA includes a third section and a fourth section, both perpendicular to the first direction; Compared to the fourth cross section, the third cross section is further away from the second semiconductor structure along the first direction; and The size of the third section is smaller than the size of the fourth section.

8. The semiconductor device according to claim 6, wherein: At least one memory cell in the array of memory cells includes a storage structure and a transistor extending along the first direction. The first end of the storage structure is coupled to the transistor; The second end of the storage structure is coupled to a second conductive contact structure that contacts a trench, the trench extending from the second side of the first semiconductor structure into the first semiconductor structure; and Both the first conductive contact structure and the second conductive contact structure comprise aluminum.

9. The semiconductor device according to claim 8, wherein: The second conductive contact structure includes a first part, a second part, and a third part; The first part and the second part are connected through the third part; The first part and the second part are perpendicular to the first direction; The first portion contacts the bottom of the trench; The third part contacts the sidewall of the trench; and The second portion contacts the portion of the sidewall of the second side that is connected to the trench.

10. The semiconductor device according to claim 8, wherein, The ratio of the first dimension of the groove in the first direction to the second dimension of the groove in the second direction is less than 0.

5.

11. The semiconductor device according to claim 2, wherein: The first semiconductor structure further includes a second contact structure extending through the semiconductor layer of the first semiconductor structure along the first direction; The second contact structure is coupled to the peripheral circuit; The first contact structure is configured to transmit control signals to and from the peripheral circuit; and The second contact structure is configured to provide power to the peripheral circuit.

12. A method comprising: A first semiconductor structure is formed including an array of memory cells, wherein at least one memory cell in the array of memory cells includes a transistor extending along a first direction and a memory structure coupled to the transistor. A contact structure is formed in the first semiconductor structure, wherein the contact structure extends along the first direction; and The first semiconductor structure is bonded to a second semiconductor structure, the second semiconductor structure including peripheral circuitry associated with the array of memory cells, wherein the contact structure is coupled to the peripheral circuitry.

13. The method according to claim 12, wherein, The first semiconductor structure forming an array of the memory cells includes: The semiconductor body of the transistor is formed in the semiconductor layer of the first semiconductor structure; and A dielectric region is formed that extends through the semiconductor layer along the first direction.

14. The method according to claim 13, wherein, The first semiconductor structure includes a first side and a second side opposite to the first side, wherein the first side is closer to the semiconductor layer along the first direction than the second side, and the contact structure is formed in the first semiconductor structure including: A contact hole is formed in the first semiconductor structure by etching from the first side, wherein the contact hole extends through the dielectric region; and The contact structure is formed in the contact hole by depositing conductive material into the contact hole.

15. The method according to any one of claims 12 to 14, further comprising: Before forming the contact hole, the first semiconductor structure is stacked on a carrier wafer, wherein the second side is in contact with the carrier wafer.

16. The method of claim 14, further comprising: An interconnect layer is formed in the first semiconductor structure, wherein the interconnect layer is coupled to the contact structure and includes at least an interconnect line extending in a second direction perpendicular to the first direction and a vertical interconnect channel (VIA) extending in the first direction.

17. The method of claim 14, wherein, Bonding the first semiconductor structure to the second semiconductor structure includes: The first semiconductor structure is bonded to the second semiconductor structure by a bonding structure, wherein the bonding structure includes conductive bonding pads and at least one dielectric material that isolates the conductive bonding pads in a second direction perpendicular to the first direction, and the first side is located between the second side and the bonding structure.

18. The method of claim 14, further comprising: Forming a trench extending from the second side of the first semiconductor structure into the first semiconductor structure; Conductive contact structures are formed in the trenches by depositing conductive material, wherein the conductive contact structures are coupled to the storage structure.

19. A memory system comprising: Memory devices; as well as A memory controller, coupled to the memory device and configured to control the memory device, wherein: The memory device includes a first semiconductor structure and a second semiconductor structure connected together. The first semiconductor structure includes an array of memory cells and a first contact structure extending along the first direction. The first contact structure includes a first cross section and a second cross section, both of which are perpendicular to the first direction; Compared to the second cross section, the first cross section is further away from the second semiconductor structure along the first direction; and The size of the first cross section is smaller than the size of the second cross section.

20. The memory system of claim 19, wherein, The dimension of the first cross section is the maximum dimension of the first cross section along a second direction perpendicular to the first direction, and the dimension of the second cross section is the maximum dimension of the second cross section along the second direction.

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