Display panel

Abstract

The invention discloses a display panel, the display panel comprises a substrate and a temperature sensing module, the temperature sensing module is arranged on the substrate, the temperature sensing module comprises a temperature-sensitive sensing unit, a voltage following unit and a voltage output unit, the temperature-sensitive sensing unit comprises a first oxide transistor and an amorphous silicon transistor, one of a source electrode and a drain electrode of the first oxide transistor is electrically connected with a first power supply voltage input end of the temperature sensing module, and the other one of the source electrode and the drain electrode of the first oxide transistor is electrically connected with one of a source electrode and a drain electrode of the amorphous silicon transistor. The other one of the source electrode and the drain electrode of the amorphous silicon transistor is electrically connected with a second power supply voltage input end of the temperature sensing module; the voltage following unit is electrically connected with the first power supply voltage input end, the other one of the source electrode and the drain electrode of the first oxidation transistor and the second power supply voltage input end; the voltage output unit is electrically connected with the voltage following unit.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] Because existing large-size display panels have long signal traces and require high driving voltages during operation, the display panels are prone to overheating, which can lead to reduced performance or even damage to the components in the display panel.

[0003] To address these issues, existing technologies integrate temperature sensing circuits into the display panel for real-time temperature monitoring. However, the existing temperature sensing circuits are affected by manufacturing process uniformity, resulting in significant errors in the real-time temperature output. Summary of the Invention

[0004] This application provides a display panel designed to improve the accuracy of temperature monitoring on the display panel.

[0005] On one hand, embodiments of this application provide a display panel, the display panel including: a substrate and a temperature sensing module, the temperature sensing module being disposed on the substrate, the temperature sensing module including: a temperature-sensitive sensing unit, a voltage follower unit, and a voltage output unit, the temperature-sensitive sensing unit including a first oxide transistor and an amorphous silicon transistor, one of the source and drain of the first oxide transistor being electrically connected to a first power supply voltage input terminal of the temperature sensing module, the other of the source and drain of the first oxide transistor being electrically connected to one of the source and drain of the amorphous silicon transistor, the other of the source and drain of the amorphous silicon transistor being electrically connected to a second power supply voltage input terminal of the temperature sensing module; the voltage follower unit being electrically connected to the first power supply voltage input terminal, the other of the source and drain of the first oxide transistor, and the second power supply voltage input terminal; the voltage output unit being electrically connected to the voltage follower unit.

[0006] Optionally, in some embodiments of this application, the gate of the first oxide transistor is electrically connected to the first power supply voltage input terminal, and the gate of the amorphous silicon transistor is electrically connected to the first control signal input terminal of the temperature sensing module.

[0007] Optionally, in some embodiments of this application, the first control voltage input to the first control signal input terminal is greater than the first power supply voltage input to the first power supply voltage input terminal.

[0008] Optionally, in some embodiments of this application, the voltage follower unit includes a second oxide transistor and a third oxide transistor. The gate of the second oxide transistor is electrically connected to the other of the source and drain of the first oxide transistor. One of the source and drain of the second oxide transistor is electrically connected to the first power supply voltage input terminal. The other of the source and drain of the second oxide transistor is electrically connected to the one of the source and drain of the third oxide transistor. The gate of the third oxide transistor is electrically connected to a second control signal input terminal. The other of the source and drain of the third oxide transistor is electrically connected to the second power supply voltage input terminal.

[0009] Optionally, in some embodiments of this application, the second control voltage input to the second control signal input terminal is less than the voltage received at the gate of the second oxide transistor.

[0010] Optionally, in some embodiments of this application, the display panel further includes a detection unit, the voltage output unit includes a fourth oxide transistor, one of the source and drain of the fourth oxide transistor is electrically connected to the other of the source and drain of the second oxide transistor, the gate of the fourth oxide transistor is electrically connected to the third control signal input terminal of the temperature sensing module, and the other of the source and drain of the fourth oxide transistor is electrically connected to the detection unit.

[0011] Optionally, in some embodiments of this application, the voltage output by the other of the source and drain of the fourth oxide transistor is between 0 volts and 15 volts.

[0012] Optionally, in some embodiments of this application, the display panel further includes multiple scan lines, and the third control signal input terminal is electrically connected to any of the scan lines.

[0013] Optionally, in some embodiments of this application, the display panel further includes a buffer layer disposed on the substrate; the first oxide transistor includes an oxide semiconductor layer, a first dielectric layer, a first gate, and a first source-drain layer, the oxide semiconductor layer is disposed on the side of the buffer layer away from the substrate, the first dielectric layer covers the oxide semiconductor layer and the buffer layer, and the first gate is disposed on the side of the first dielectric layer away from the substrate; the amorphous silicon transistor includes a second gate, a second dielectric layer, an amorphous silicon layer, and a second source-drain layer, the second gate is disposed on the same layer as the first gate and spaced apart, the second dielectric layer covers the first gate and the second gate, and the amorphous silicon layer is disposed on the side of the second dielectric layer away from the substrate; the display panel further includes a planarization layer, the planarization layer covers the second dielectric layer and the amorphous silicon layer, the first source-drain layer and the second source-drain layer are both disposed on the side of the planarization layer away from the substrate, the first source-drain layer is electrically connected to the oxide semiconductor layer, the second source-drain layer is connected to the amorphous silicon layer, and the first source-drain layer and the second source-drain layer are connected.

[0014] Optionally, in some embodiments of this application, the amorphous silicon layer includes a first step portion, a connecting portion, and a second step portion. The first step portion extends along the direction of the plane where the substrate is located and overlaps with the second gate. The second step portion extends along the direction of the plane where the substrate is located and is located on the side of the first step portion away from the first oxide transistor. The connecting portion is connected to the first step portion and the second step portion.

[0015] The display panel provided in this application includes a temperature sensing module disposed on a substrate. The temperature sensing module comprises a temperature-sensitive sensing unit, a voltage-following unit, and a voltage output unit. The temperature-sensitive sensing unit includes a first oxide transistor and an amorphous silicon transistor. One of the source and drain of the first oxide transistor is electrically connected to a first power supply voltage input terminal of the temperature sensing module. The other of the source and drain of the first oxide transistor is electrically connected to one of the source and drain of the amorphous silicon transistor. The other of the source and drain of the amorphous silicon transistor is electrically connected to a second power supply voltage input terminal of the temperature sensing module. The voltage-following unit is electrically connected to the first power supply voltage input terminal, the other of the source and drain of the first oxide transistor, and the second power supply voltage input terminal. The voltage output unit is electrically connected to the voltage-following unit. Because the resistance of amorphous silicon transistors decreases as the display panel temperature rises, while the resistance of oxide transistors remains constant, the higher the display panel temperature, the lower the resistance of the amorphous silicon transistors. This results in a larger current flowing through both the amorphous silicon and oxide transistors, leading to a greater voltage drop across the oxide transistors after the first power supply voltage is applied. Consequently, the current flowing through the voltage follower unit decreases, and thus the voltage output by the voltage output unit decreases. By establishing a relationship between the voltage output by the voltage output unit and the display panel temperature, the temperature of the amorphous silicon transistors can be inferred from the voltage output. This improves the accuracy of display panel temperature monitoring, prevents components in the display panel from operating at high temperatures for extended periods, and ultimately extends the lifespan of the display panel. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application;

[0017] Figure 2 yes Figure 1 A circuit diagram of a first embodiment of the temperature sensing module in the provided display panel;

[0018] Figure 3 yes Figure 2 A schematic diagram showing the relationship between the temperature at the amorphous silicon transistor in the provided temperature sensing module and the voltage output at the other end of the source and drain of the fourth oxide transistor.

[0019] Figure 4 yes Figure 1 A circuit diagram of a second embodiment of the temperature sensing module in the provided display panel;

[0020] Figure 5 yes Figure 1 A circuit diagram of a third embodiment of the temperature sensing module in the provided display panel;

[0021] Figure 6 This is a cross-sectional view of the display panel provided in an embodiment of this application along the AA' direction;

[0022] Figure 7 yes Figure 2 A schematic diagram of the temperature sensitivity curve of the amorphous silicon transistor in the provided temperature sensing module. Detailed Implementation

[0023] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0024] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.

[0025] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0026] In the various embodiments provided in this application, a transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that provides charge carriers to the transistor. Charge carriers flow into the transistor from the source. The drain is the electrode used to emit charge carriers within the transistor. For example, charge carriers flow from the source to the drain in the transistor. In the case of an N-type transistor, the charge carriers are electrons, therefore the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. Because electrons flow from the source to the drain in an N-type transistor, current flows from the drain to the source. In the case of a P-type transistor, the charge carriers are holes, therefore the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. Because holes flow from the source to the drain in a P-type transistor, current flows from the source to the drain.

[0027] like Figure 1 and Figure 2 As shown, an embodiment of this application provides a display panel 100, which includes a substrate 10 and a temperature sensing module 20 disposed on the substrate 10. The temperature sensing module 20 includes a temperature-sensitive sensing unit 21, a voltage follower unit 22, and a voltage output unit 23.

[0028] Specifically, the temperature-sensitive sensing unit 21 includes a first oxide transistor T1 and an amorphous silicon transistor T2. The gate and source of the first oxide transistor T1 are electrically connected to the first power supply voltage input terminal VDD of the temperature sensing module 20, and the drain of the first oxide transistor T1 is electrically connected to the source of the amorphous silicon transistor T2. The gate of the amorphous silicon transistor T2 is electrically connected to the first control signal input terminal Vin, and the drain of the amorphous silicon transistor T2 is electrically connected to the second power supply voltage input terminal VSS of the temperature sensing module 20. The first power supply voltage input terminal VDD can be set to have a voltage level higher than that of the second power supply voltage input terminal VSS.

[0029] Specifically, the voltage follower unit 22 is electrically connected to the first power supply voltage input terminal VDD, the drain of the first oxide transistor T1, the second power supply voltage input terminal VSS, and the second control signal input terminal Vsf.

[0030] Specifically, the voltage output unit 23 is electrically connected to the voltage follower unit 22 and the third control signal input terminal Vscan.

[0031] In the display panel 100 provided in this application, since the resistance of the amorphous silicon transistor T2 decreases as the temperature of the display panel increases, while the resistance of the first oxide transistor T1 does not change with temperature, the higher the temperature of the display panel, the lower the resistance of the amorphous silicon transistor T2, the larger the current flowing through the amorphous silicon transistor T2 and the first oxide transistor T1, and the greater the voltage drop between the source and drain of the first oxide transistor T1. This leads to a decrease in the voltage drop between the source and drain of the amorphous silicon transistor T2, thereby lowering the potential at the drain of the first oxide transistor T1. Consequently, the voltage output to the voltage follower unit 22 through the drain of the first oxide transistor T1 becomes smaller, resulting in a smaller conduction degree of the voltage follower unit 22. This reduces the current in the voltage follower unit 22 connected in series between the first power supply voltage input terminal VDD and the second power supply voltage input terminal VSS, and consequently reduces the voltage output by the voltage output unit 23.

[0032] In other words, as the temperature of the display panel increases, the resistance of the amorphous silicon transistor T2 decreases. This decrease in resistance leads to a decrease in the current flowing through the voltage follower unit 22, which in turn reduces the voltage output by the voltage output unit 23. Therefore, the temperature of the display panel is negatively correlated with the voltage output by the voltage output unit 23; that is, the higher the temperature of the display panel, the lower the voltage output by the voltage output unit 23, and vice versa.

[0033] By establishing the relationship between the voltage value output by the voltage output unit 23 and the temperature of the display panel, the specific temperature of the amorphous silicon transistor T2 can be deduced from the specific voltage value output by the voltage output unit 23. In other words, the specific temperature of the display panel can be deduced from the specific voltage value output by the voltage output unit 23. By obtaining the voltage value output by the voltage output unit 23, the specific temperature of the display panel can be accurately obtained, thereby improving the accuracy of temperature monitoring of the display panel, avoiding the devices in the display panel from working at high temperatures for a long time, and thus improving the service life of the display panel.

[0034] like Figure 1 As shown, the display panel 100 also includes multiple scan lines G. The display panel 100 also includes multiple pixels 11 arranged in an array and multiple data lines D. Each scan line G is electrically connected to a row of pixels 11. Each data line D is electrically connected to a column of pixels 11. Specifically, at least some of the pixels 11 are provided with a temperature sensing module 20. Preferably, each pixel 11 is provided with a temperature sensing module 20.

[0035] like Figure 2 As shown, since the gate of the first oxide transistor T1 is electrically connected to the first power supply voltage input terminal VDD and the gate of the amorphous silicon transistor T2 is electrically connected to the first control signal input terminal Vin of the temperature sensing module 20, the display panel 100 only needs to provide a control signal line configured to transmit the first control signal to the first control signal terminal Vin, without the need to provide a separate control signal line configured to transmit the corresponding control signal to the gate of the first oxide transistor T1. This reduces the number of control signal lines in the display panel 100, thereby reducing the layout space occupied by the control signal lines in the display panel 100, avoiding mutual interference between different signal lines (such as between control signal lines, between control signal lines and scan signal lines, and between control signal lines and data signal lines), and improving the stability of signal transmission.

[0036] In the embodiments of this application, the first control voltage input at the first control signal input terminal Vin is greater than the first power supply voltage input at the first power supply voltage input terminal VDD. The first power supply voltage is between 12 volts and 20 volts, and the first control voltage is between 25 volts and 35 volts. Specifically, the first power supply voltage includes values ​​of 12 volts, 13 volts, 14 volts, 15 volts, 16 volts, 17 volts, 18 volts, 19 volts, and 20 volts. The first control voltage includes values ​​of 25 volts, 26 volts, 27 volts, 28 volts, 29 volts, 30 volts, 31 volts, 32 volts, 33 volts, 34 volts, and 35 volts. Preferably, the first power supply voltage is 15 volts, and the first control voltage is 30 volts.

[0037] In an embodiment of this application, the voltage follower unit 22 includes a second oxide transistor T3 and a third oxide transistor T4. The gate of the second oxide transistor T3 is electrically connected to the drain of the first oxide transistor T1, the source of the second oxide transistor T3 is electrically connected to the first power supply voltage input terminal VDD, and the drain of the second oxide transistor T3 is electrically connected to the source of the third oxide transistor T4. The gate of the third oxide transistor T4 is electrically connected to the second control signal input terminal Vsf, and the drain of the third oxide transistor T4 is electrically connected to the second power supply voltage input terminal VSS.

[0038] In the embodiments of this application, the resistance value of the third oxide transistor T4 in the on state is greater than or equal to the resistance value of the second oxide transistor T3 in the on state, so that when the second oxide transistor T3 is fully on, the voltage at the drain of the second oxide transistor T3 is equal to the first power supply voltage input at the first power supply voltage input terminal VDD. That is, the magnitude of the voltage at the drain of the second oxide transistor T3 is related to the magnitude of the first power supply voltage input at the first power supply voltage input terminal VDD and the degree of conduction of the second oxide transistor T3.

[0039] In an embodiment of this application, the second control voltage input at the second control signal input terminal Vsf is less than the voltage received at the gate of the second oxide transistor T3.

[0040] Specifically, the voltage at the gate of the second oxide transistor T3 is equal to the first power supply voltage input at the first power supply voltage input terminal VDD minus the voltage drop across the first oxide transistor T1. The voltage drop across the first oxide transistor T1 is equal to the product of the resistance of the first oxide transistor T1 in the on-state and the current flowing through the first oxide transistor T1. The current flowing through the first oxide transistor T1 is inversely proportional to the resistance of the amorphous silicon transistor T2; that is, the smaller the resistance of the amorphous silicon transistor T2, the larger the current flowing through both the first oxide transistor T1 and the amorphous silicon transistor T2. The resistance of the amorphous silicon transistor T2 is inversely proportional to the temperature at which the amorphous silicon transistor T2 is located; that is, the higher the temperature at which the amorphous silicon transistor T2 is located, the smaller its resistance.

[0041] The setting that the second control voltage input at the second control signal input terminal Vsf is less than the voltage received at the gate of the second oxide transistor T3 ensures that the conduction level of the third oxide transistor T4 is always lower than that of the second oxide transistor T3, thereby making the resistance value of the third oxide transistor T4 larger. This ensures that the voltage at the drain of the second oxide transistor T3 is only related to the magnitude of the first power supply voltage input at the first power supply voltage input terminal VDD and the conduction level of the second oxide transistor T3. In other words, the second oxide transistor T3 and the third oxide transistor T4 form a source follower.

[0042] In embodiments of this application, the display panel further includes a detection unit, and the voltage output unit 23 includes a fourth oxide transistor T5. The source of the fourth oxide transistor T5 is electrically connected to the drain of the second oxide transistor T3, the gate of the fourth oxide transistor T5 is electrically connected to the third control signal input terminal Vscan of the temperature sensing module 20, and the drain of the fourth oxide transistor T5 is electrically connected to the detection unit to output voltage Vout to the detection unit.

[0043] In the embodiments of this application, the third control signal input terminal Vscan is electrically connected to any scan line G. Specifically, the third control signal input terminal Vscan is electrically connected to the scan line G to which the pixel 11 is connected, that is, each time the pixel 11 is charged, the fourth oxide transistor T5 in the temperature sensing module 20 is also turned on and outputs a voltage value detection unit to realize a temperature monitoring.

[0044] In embodiments of this application, the voltage output from the drain of the fourth oxide transistor T5 is between 0 volts and 15 volts. For example... Figure 3 As shown, when the temperature at the amorphous silicon transistor T2 is between 20 and 40 degrees (e.g., 25 degrees), the resistance of the amorphous silicon transistor T2 does not change. The voltage drop generated after the first power supply voltage flows through the first oxide transistor T1 is small. The second oxide transistor T3 is fully turned on, and the voltage at the drain of the second oxide transistor T3 is equal to the first power supply voltage. Therefore, the voltage Vout output by the drain of the fourth oxide transistor T5 is equal to the first power supply voltage (e.g., the value of the first power supply voltage is 15 volts).

[0045] Specifically, when the temperature at the amorphous silicon transistor T2 is between 40 and 60 degrees (e.g., 45 degrees), the resistance of the amorphous silicon transistor T2 decreases, the voltage drop generated after the first power supply voltage flows through the first oxide transistor T1 increases, the conduction degree of the second oxide transistor T3 decreases, and the first power supply voltage generates a voltage drop after flowing through the second oxide transistor T3. As a result, the voltage Vout output by the drain of the fourth oxide transistor T5 is less than the first power supply voltage. For example, the voltage Vout output by the drain of the fourth oxide transistor T5 is 11 volts.

[0046] Specifically, when the temperature at the amorphous silicon transistor T2 is between 60 and 80 degrees (e.g., 65 degrees), the resistance of the amorphous silicon transistor T2 is less than the resistance when the temperature at the amorphous silicon transistor T2 is 45 degrees. The voltage drop generated after the first power supply voltage flows through the first oxide transistor T1 further increases, and the conduction degree of the second oxide transistor T3 further decreases. The voltage drop generated after the first power supply voltage flows through the second oxide transistor T3 increases, so the voltage Vout output by the drain of the fourth oxide transistor T5 is less than the voltage Vout output by the drain of the fourth oxide transistor T5 when the temperature at the amorphous silicon transistor T2 is 45 degrees. For example, the voltage Vout output by the drain of the fourth oxide transistor T5 is 7 volts.

[0047] Specifically, when the temperature at the amorphous silicon transistor T2 is between 80 and 100 degrees (e.g., 85 degrees), the resistance of the amorphous silicon transistor T2 is less than the resistance when the temperature at the amorphous silicon transistor T2 is 65 degrees. The voltage drop generated after the first power supply voltage flows through the first oxide transistor T1 further increases, and the conduction degree of the second oxide transistor T3 further decreases. The voltage drop generated after the first power supply voltage flows through the second oxide transistor T3 increases, so the voltage Vout output by the drain of the fourth oxide transistor T5 is less than the voltage Vout output by the drain of the fourth oxide transistor T5 when the temperature at the amorphous silicon transistor T2 is 65 degrees. For example, the voltage Vout output by the drain of the fourth oxide transistor T5 is 1 volt.

[0048] In the embodiments of this application, the first oxide transistor T1, the second oxide transistor T3, the third oxide transistor T4, and the fourth oxide transistor T5 are made of the same material. Specifically, the first oxide transistor T1, the second oxide transistor T3, the third oxide transistor T4, and the fourth oxide transistor T5 are all made of indium gallium zinc oxide (IGZO). The amorphous silicon transistor T2 is made of low-temperature amorphous silicon.

[0049] like Figure 4As shown, an embodiment of this application provides another display panel 200. The difference between display panel 200 and display panel 100 is that the gate of the first oxide transistor T1 in display panel 200 is connected to a separate control signal V1 to avoid the first oxide transistor T1 being subjected to long-term stress, which would cause the threshold voltage of the first oxide transistor T1 to drift, thereby improving the stability of the performance of the temperature sensing module 20 and ensuring the accuracy of temperature monitoring of the display panel.

[0050] like Figure 5 As shown, an embodiment of this application provides another display panel 300. The difference between display panel 300 and display panel 100 is that the voltage follower unit 22 includes a second oxide transistor T3 and a first resistor R. The gate of the second oxide transistor T3 is electrically connected to the drain of the first oxide transistor, the source of the second oxide transistor T3 is electrically connected to the first power supply voltage input terminal VDD, and the drain of the second oxide transistor T3 is electrically connected to one end of the first resistor R. The other end of the first resistor R is electrically connected to the second power supply voltage input terminal VSS. The resistance value of the first resistor R is greater than the resistance value of the second oxide transistor T3 in the on-state. Therefore, the voltage at the drain of the second oxide transistor T3 is only related to the magnitude of the first power supply voltage input at the first power supply voltage input terminal VDD and the degree of conduction of the second oxide transistor T3; that is, the second oxide transistor T3 and the first resistor R together form a source follower.

[0051] like Figure 6As shown, the display panel 100 further includes a buffer layer 30, which is disposed on the substrate 10. The first oxide transistor T1 and the amorphous silicon transistor T2 are both disposed on the side of the buffer layer 30 away from the substrate 10. The first oxide transistor T1 includes an oxide semiconductor layer 211, a first dielectric layer 212, a first gate 213, and a first source / drain layer 214. The oxide semiconductor layer 211 is disposed on the side of the buffer layer 30 away from the substrate 10. The first dielectric layer 212 covers the oxide semiconductor layer 211 and the buffer layer 30. The first gate 213 is disposed on the side of the first dielectric layer 212 away from the substrate 10. The amorphous silicon transistor T2 includes a second gate 215, a second dielectric layer 216, an amorphous silicon layer 217, and a second source / drain layer 219. The second gate 215 and the first gate 213 are on the same layer and spaced apart. The second dielectric layer 216 covers the first gate 213 and the second gate 215. The amorphous silicon layer 217 is disposed on the side of the second dielectric layer 216 away from the substrate 10. The display panel also includes a planarization layer 218, which covers a second dielectric layer 216 and an amorphous silicon layer 217. A first source-drain layer 214 and a second source-drain layer 219 are both disposed on the side of the planarization layer 218 away from the substrate 10. The first source-drain layer 214 is electrically connected to the oxide semiconductor layer 211, and the second source-drain layer 219 is connected to the amorphous silicon layer 217. The first source-drain layer 214 and the second source-drain layer 219 are also connected.

[0052] In embodiments of this application, the first source-drain layer 214 includes the source and drain of the first oxide transistor T1. The second source-drain layer 219 includes the source and drain of the amorphous silicon transistor T2. The source and drain of the first oxide transistor T1 are disposed on opposite sides of the first gate 213 and electrically connected to opposite ends of the oxide semiconductor layer 211.

[0053] In embodiments of this application, the amorphous silicon layer 217 includes a first step portion 217a, a connecting portion 217b, and a second step portion 217c. The first step portion 217a extends along the plane of the substrate 10 and overlaps with the second gate 215. The second step portion 217c extends along the plane of the substrate 10 and is located on the side of the first step portion 217a away from the first oxide transistor T1. The connecting portion 217b extends along a direction perpendicular to the plane of the substrate 10 and is connected to the first step portion 217a and the second step portion 217c. One of the source and drain of the amorphous silicon transistor T2 is disposed on the side of the first step portion 217a away from the substrate 10 and is electrically connected to the end of the first step portion 217a away from the second step portion 217c. The other of the source and drain of the amorphous silicon transistor T2 is disposed on the side of the second step portion 217c away from the substrate 10 and is electrically connected to the end of the second step portion 217c away from the first step portion 217a.

[0054] In the embodiments of this application, the thickness of the connection portion 217b is equal to the sum of the thickness of the second dielectric layer 216 located between the second gate 215 and the first step portion 217a and the thickness of the first step portion 217a.

[0055] In embodiments of this application, the thickness of the first step portion 217a and the thickness of the second step portion 217c are equal. The thickness of the second dielectric layer 216 located between the second gate 215 and the first step portion 217a is greater than the thickness of the first step portion 217a. The thickness of the second dielectric layer 216 located between the second gate 215 and the first step portion 217a is greater than the thickness of the second step portion 217c.

[0056] In the embodiments of this application, the thickness of the first step portion 217a is less than the cross-sectional width of the connecting portion 217b from one of the source and drain of the amorphous silicon transistor T2 to the other of the source and drain of the amorphous silicon transistor T2. The bottom-gate gap type amorphous silicon transistor T2 provided in the embodiments of this application has advantages over existing amorphous silicon transistors T2, such as a wider operating window, faster response time to temperature changes, and a larger temperature-sensitive range.

[0057] In the embodiments of this application, the current increment caused by temperature change in the bottom-gate gap amorphous silicon transistor T2 accounts for a larger proportion than the current flowing through the amorphous silicon transistor T2 in the on-state. Therefore, the bottom-gate gap amorphous silicon transistor T2 provided in the embodiments of this application has strong temperature sensitivity, and the difference between the current value flowing through the amorphous silicon transistor T2 at different temperatures and the voltage value at the source or drain of the amorphous silicon transistor T2 is relatively large. Figure 7 The diagram shows the current value Ids flowing through the amorphous silicon transistor T2 at 25 degrees, 45 degrees, 65 degrees, 85 degrees and 105 degrees, and the voltage value Vgs at the source and drain of the amorphous silicon transistor T2.

[0058] In the embodiments of this application, the first oxide transistor T1, amorphous silicon transistor T2, second oxide transistor T3, third oxide transistor T4, and fourth oxide transistor T5 are all N-type transistors. N-type transistors are turned on when the gate is at a high potential and turned off when the gate is at a low potential. Specifically, in the embodiments of this application, the first oxide transistor T1, amorphous silicon transistor T2, second oxide transistor T3, third oxide transistor T4, and fourth oxide transistor T5 are all P-type transistors. P-type transistors are turned on when the gate is at a low potential and turned off when the gate is at a high potential; that is, different types of transistors have different turn-on and turn-off levels.

[0059] The display panel provided in this application includes a temperature sensing module 20 disposed on a substrate 10. The temperature sensing module 20 comprises a temperature-sensitive sensing unit 21, a voltage follower unit 22, and a voltage output unit 23. The temperature-sensitive sensing unit 21 includes a first oxide transistor T1 and an amorphous silicon transistor T2. The source of the first oxide transistor T1 is electrically connected to the first power supply voltage input terminal VDD of the temperature sensing module 20, and the drain of the first oxide transistor T1 is electrically connected to the source of the amorphous silicon transistor T2. The drain of the amorphous silicon transistor T2 is electrically connected to the second power supply voltage input terminal VSS of the temperature sensing module 20. The voltage follower unit 22 is electrically connected to the first power supply voltage input terminal VDD, the drain of the first oxide transistor T1, and the second power supply voltage input terminal VSS. The voltage output unit 23 is electrically connected to the voltage follower unit 22. Since the resistance of the amorphous silicon transistor T2 decreases as the display panel temperature rises, while the resistance of the oxide transistor remains constant, the higher the display panel temperature, the lower the resistance of the amorphous silicon transistor T2. This results in a larger current flowing through both the amorphous silicon transistor T2 and the oxide transistor, leading to a greater voltage drop across the first power supply voltage input to the first power supply terminal after passing through the oxide transistor. Consequently, the current flowing through the voltage follower unit 22 decreases, and thus the voltage output by the voltage output unit 23 decreases. By establishing the relationship between the voltage output by the voltage output unit 23 and the display panel temperature, the temperature of the amorphous silicon transistor T2 can be inferred from the voltage output by the voltage output unit 23. This improves the accuracy of display panel temperature monitoring, prevents components in the display panel from operating at high temperatures for extended periods, and ultimately extends the lifespan of the display panel.

[0060] The above provides a detailed description of a display panel provided by the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application, and the above description should not be construed as a limitation on the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: substrate; A temperature sensing module, wherein the temperature sensing module is disposed on the substrate, the temperature sensing module includes: A temperature-sensitive sensing unit includes a first oxide transistor and an amorphous silicon transistor. One of the source and drain of the first oxide transistor is electrically connected to the first power supply voltage input terminal of the temperature sensing module. The other of the source and drain of the first oxide transistor is electrically connected to one of the source and drain of the amorphous silicon transistor. The other of the source and drain of the amorphous silicon transistor is electrically connected to the second power supply voltage input terminal of the temperature sensing module. A voltage follower unit, wherein the voltage follower unit is electrically connected to the first power supply voltage input terminal, the other of the source and drain of the first oxide transistor, and the second power supply voltage input terminal; A voltage output unit, which is electrically connected to the voltage follower unit.

2. The display panel according to claim 1, characterized in that, The gate of the first oxide transistor is electrically connected to the first power supply voltage input terminal, and the gate of the amorphous silicon transistor is electrically connected to the first control signal input terminal of the temperature sensing module.

3. The display panel according to claim 2, characterized in that, The first control voltage input to the first control signal input terminal is greater than the first power supply voltage input to the first power supply voltage input terminal.

4. The display panel according to claim 1, characterized in that, The voltage follower unit includes a second oxide transistor and a third oxide transistor. The gate of the second oxide transistor is electrically connected to the other of the source and drain of the first oxide transistor. One of the source and drain of the second oxide transistor is electrically connected to the first power supply voltage input terminal. The other of the source and drain of the second oxide transistor is electrically connected to the one of the source and drain of the third oxide transistor. The gate of the third oxide transistor is electrically connected to a second control signal input terminal. The other of the source and drain of the third oxide transistor is electrically connected to the second power supply voltage input terminal.

5. The display panel according to claim 4, characterized in that, The second control voltage input to the second control signal input terminal is less than the voltage received at the gate of the second oxide transistor.

6. The display panel according to claim 5, characterized in that, The display panel further includes a detection unit, and the voltage output unit includes a fourth oxide transistor. One of the source and drain of the fourth oxide transistor is electrically connected to the other of the source and drain of the second oxide transistor. The gate of the fourth oxide transistor is electrically connected to the third control signal input terminal of the temperature sensing module, and the other of the source and drain of the fourth oxide transistor is electrically connected to the detection unit.

7. The display panel according to claim 6, characterized in that, The voltage output by the other of the source and drain terminals of the fourth oxide transistor is between 0 volts and 15 volts.

8. The display panel according to claim 6, characterized in that, The display panel also includes multiple scan lines, and the third control signal input terminal is electrically connected to any of the scan lines.

9. The display panel according to claim 1, characterized in that, The display panel further includes a buffer layer, which is disposed on the substrate; The first oxide transistor includes an oxide semiconductor layer, a first dielectric layer, a first gate, and a first source / drain layer. The oxide semiconductor layer is disposed on the side of the buffer layer away from the substrate. The first dielectric layer covers the oxide semiconductor layer and the buffer layer. The first gate is disposed on the side of the first dielectric layer away from the substrate. The amorphous silicon transistor includes a second gate, a second dielectric layer, an amorphous silicon layer, and a second source / drain layer. The second gate is on the same layer as the first gate and is spaced apart. The second dielectric layer covers the first gate and the second gate. The amorphous silicon layer is disposed on the side of the second dielectric layer away from the substrate. The display panel further includes a planarization layer, which covers the second dielectric layer and the amorphous silicon layer. The first source-drain layer and the second source-drain layer are both disposed on the side of the planarization layer away from the substrate. The first source-drain layer is electrically connected to the oxide semiconductor layer, and the second source-drain layer is connected to the amorphous silicon layer. The first source-drain layer and the second source-drain layer are also connected.

10. The display panel according to claim 1, characterized in that, The amorphous silicon layer includes a first step portion, a connecting portion, and a second step portion. The first step portion extends along the plane of the substrate and overlaps with the second gate. The second step portion extends along the plane of the substrate and is located on the side of the first step portion away from the first oxide transistor. The connecting portion is connected to the first step portion and the second step portion.

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