Temperature sensor sensing circuit architecture based on duty ratio modulation and temperature measurement method thereof

Abstract

The invention discloses a temperature sensor sensing circuit architecture based on duty ratio modulation and a temperature measurement method thereof, and belongs to the technical field of temperature sensors. The circuit architecture comprises a first current source, a second current source, a fourth current source, an amplifier, a comparator, a first resistor, a first triode, a second triode, a capacitor and a digital module. Compared with other temperature measurement schemes, the temperature sensing front-end circuit is greatly simplified, and temperature measurement can be completed only by using the common temperature sensing front-end part in all the schemes and the corresponding reading circuit. According to the invention, an extra circuit is not required to be used at a circuit end to generate a voltage or current signal in direct proportion to the temperature, but the temperature information in direct proportion to the temperature is read by reading the time difference of high and low signals output by the duty ratio of the circuit, and the analog signal is converted into the digital domain, so that the complexity of the actual circuit is reduced.

Description

Technical Field

[0001] This invention belongs to the field of temperature sensor technology, specifically relating to a temperature sensor sensing circuit architecture based on duty cycle modulation and its temperature measurement method. Background Technology

[0002] Temperature sensors play a crucial role in both everyday ambient temperature monitoring and thermal management within integrated circuits. Furthermore, to facilitate temperature readout, the design of a temperature sensor must consider its sensing scheme and readout method, enabling seamless connection to subsequent digital interfaces and temperature processing.

[0003] Figure 1 A general temperature sensor architecture [1] is shown, which uses DTΔΣADC for readout. First, currents I1, I2, I3, and I4, which are proportional to temperature, are generated through the temperature sensing front end (red box part). Then, the currents I3 and I4 bias diodes D3 and D4 (the diodes here are formed by connecting the base and collector of a transistor in parallel), thereby generating two voltages V that are inversely proportional to temperature. C (Voltage at point C) and V D (Voltage at point D), V C V D and V C -V D The input is quantized into a DTΔΣADC to generate a bitstream containing temperature information, thus enabling temperature measurement. The advantages of using a DTΔΣADC are its high accuracy, good resolution, and robustness. However, since the DTΔΣADC requires voltage sampling, additional I3 and I4 are needed to bias D3 and D4 to generate V. C and V D This is used to supply current to the subsequent DTΔΣ ADC, and V cannot be reused. A and V B Because points A and B have no output current capability. At the same time, the DTΔΣADC contains at least one operational amplifier, one comparator and a corresponding control signal generation circuit, which not only increases power consumption by 75 microamps[1], but also requires multiple clock cycles to complete temperature measurement due to the inherent time-for-accuracy characteristic of the ADC, which also increases the conversion time.

[0004] Figure 2 It is a temperature sensor with duty cycle modulation output [2]. First, the temperature sensing front end outputs a current I1 to I5 that is proportional to the temperature. I3 biases D3 to generate a voltage V that is inversely proportional to the temperature at point C. C Because the second amplifier creates negative feedback in the circuit, V E =V CThis makes the current flowing through M1 V C / R1 or V C / (R1 / / R2), this depends on the switching signal at SW1. Because V C It is inversely proportional to temperature, therefore V C / R1 and V C / The current magnitudes of (R1 / / R2) are inversely proportional to the temperature. Schmitt triggers are used to balance the two pairs of currents with temperature information (when OUT is high, I4 is balanced with the current flowing through M1; when OUT is low, I4+I5 is balanced with the current flowing through M1), thereby converting the temperature information into duty cycle information for temperature measurement. This readout architecture simplifies the timing design of the temperature sensor compared to using ADC readout, eliminates the need for an external clock signal, and shortens the temperature measurement time. However, as shown in the figure, the circuit still requires an additional operational amplifier to assist in temperature conversion, and the amplifier circuit is often the most power-consuming part in the analog circuit. Ultimately, the temperature sensor consumes 55uA of current [2]. Therefore, in order to further save power consumption, Figure 3 An alternative readout architecture is proposed.

[0005] Figure 3 This is a novel temperature sensor architecture based on duty cycle modulation output [3]. With Figure 1 , Figure 2 The temperature sensing front end is consistent with the temperature sensor, generating currents I1, I2, and I3 that are proportional to temperature. When Φ2 is in phase (i.e., Φ2 is high), SW1 is closed, I3 biases R2, and the voltage V at C... C It is also proportional to temperature; when Φ1 is in phase, I3 biases D3, and the voltage V at D is... D It is inversely proportional to temperature, thus at two different phases of Φ1 and Φ2, voltages V are generated at points C and D that are directly proportional to and inversely proportional to temperature, respectively. C and V D This will coordinate with the subsequent readout circuit. The subsequent digital module will generate an RST signal, which will be briefly enabled at the initial phase of Φ1 and Φ2, releasing the charge on capacitor Cap, i.e., the voltage across Cap is 0. When Φ1 is in phase, switches SW2, SW4, and SW6 are closed, and switches SW1, SW3, and SW5 are open. The positive and negative inputs of the comparator are connected to voltage V respectively. D and V E (As shown by the two yellow dashed lines of different types), since the voltage across capacitor Cap is 0 in the initial phase, therefore V D Initially, the voltage was greater than V. E The comparator outputs a high level, and as the current source I4 charges the capacitor, V E Gradually rise to V E >VD At this point, the comparator output jumps low, entering phase Φ2; in phase Φ2, switches SW1, SW3, and SW5 are closed, and switches SW2, SW4, and SW6 are open, connecting the positive and negative input terminals of the comparator to voltage V respectively. E and V C Since RST resets the voltage across capacitor Cap in each phase, V in the initial stage of Φ2... E <V C The comparator still outputs a low level, and as the current source I4 charges the capacitor Cap, V... E Gradually rise to V C <V E The comparator output flips to a high level, re-entering phase Φ1. The circuit continuously alternates between phases Φ1 and Φ2. In both phases Φ1 and Φ2, one of the comparator's inputs is connected to V. E This makes V E The capacitor Cap is charged by the current source I4, so that V E Rise to V C Or V D This causes the comparator output to flip, entering another phase. Therefore, V can be obtained by using the ratio of the time lengths of phases Φ1 and Φ2. C With V D The ratio. Because V C It is a voltage that is positively correlated with temperature, V D It is a voltage that is negatively correlated with temperature, therefore it can be expressed as V. C With V D The ratio is used to measure temperature, and V C With V D The ratio is converted into high and low level information of different durations by the subsequent capacitor Cap, comparator, and digital module, i.e., the output duty cycle, which can then be used to measure temperature. In this circuit, the comparison... Figure 1 The proposed scheme can save an amplifier, thereby further saving power consumption, requiring only 40 microamps of current [3]. However, the voltage V in this scheme is proportional to temperature. C It is generated by the current I3 flowing through resistor R2, which is proportional to the temperature. Because the resistor has a variable temperature coefficient and a large process diffusion in CMOS process (i.e. the resistance value is different in different chips), the temperature measurement accuracy and consistency will be reduced even for chips manufactured in the same batch.

[0006] Based on [3], this invention proposes a new temperature sensing scheme and corresponding circuit design for a temperature sensor based on duty cycle modulation output. It still adopts the output scheme in [3], but the two phases of the two fixed voltages detected by the comparator are no longer a voltage proportional to temperature plus a voltage inversely proportional to temperature, but two different voltages inversely proportional to temperature. The voltage proportional to temperature is no longer formed in the circuit, but is directly subtracted in the digital domain, i.e., the duty cycle output, thereby simplifying the circuit and reducing power consumption.

[0007] In summary, the existing technology has the following shortcomings:

[0008] 1. In existing solutions, if a DTΔΣADC is used for readout, a single temperature reading often requires multiple cycles to complete, resulting in high power consumption and long conversion time. Furthermore, the ΔΣADC also requires complex timing control and additional circuit design, leading to high complexity.

[0009] 2. In existing solutions, if the temperature sensor uses the circuit architecture in [2], the readout part requires an additional amplifier to convert the voltage with temperature information into current. The amplifier is an extremely energy-intensive unit, which not only increases power consumption but also increases circuit area. At the same time, the resistor adds a resistor unit when converting voltage into current. In CMOS technology, the resistance value often deviates greatly from the nominal value (>20%). In addition, the resistor also has a temperature coefficient, which deteriorates the temperature measurement accuracy and consistency.

[0010] 3. In the existing scheme, if the temperature sensor architecture in [3] is used, the readout scheme does not require the voltage node with temperature information to have the ability to output current, so an amplifier can be saved. However, it also introduces a resistor to generate a voltage proportional to the temperature for the next conversion. There is also a process deviation of the resistor, which affects the accuracy and consistency of temperature measurement.

[0011] The technical problems that existing temperature sensors need to solve can be summarized as follows:

[0012] 1. The temperature sensor can operate over a wide temperature range.

[0013] 2. When generating voltage / current signals that are directly proportional to temperature and inversely proportional to temperature, the circuit often requires additional components such as resistors and amplifiers. Could we consider generating one of the temperature-proportional or temperature-inverse signals in a digital domain manner, so that only the voltage / current information with the default temperature information needs to be generated in the circuit? This would greatly reduce the complexity, area and power consumption of the circuit.

[0014] 3. In standard CMOS processes, the resistance value of resistors varies with temperature and is affected by manufacturing process deviations, which greatly limits the accuracy of resistors. Therefore, the use of resistors should be minimized during the design process.

[0015] 4. Reduce the use of high-power circuit modules, such as amplifiers, to avoid high power consumption problems.

[0016] 5. Reduce chip area and design complexity to lower costs.

[0017] 6. It can be manufactured using standard CMOS processes, reducing process requirements and lowering costs.

[0018] The references are as follows:

[0019] [1]M.Pertijs,K.Makinwa and J.Huijsing,"A CMOS temperature sensor witha3 / spl sigma / inaccuracy of / spl plusmn / 0.1 / spl deg / C from-55 / spl deg / C to 125 / spl deg / C,"ISSCC.2005IEEE International Digest of Technical Papers.Solid-State Circuits Conference, 2005., San Francisco, CA, USA, 2005, pp.238-596Vol.1, doi:10.1109 / ISSCC.2005.1493957.

[0020] [2]Heidary,G.Wang,K.Makinwa and G.Meijer,"12.8A BJT-based CMOStemperature sensor with a 3.6pJ·K2-resolution FoM,"2014IEEE InternationalSolid-State Circuits Conference Digest of Technical Papers(ISSCC), San Francisco, CA, USA, 2014, pp.224-225, doi:10.1109 / ISSCC.2014.6757410.

[0021] [3]Z.Huang, Z.Tang, II: ExpressBriefs, vol.68, no.8, pp.2780-2784, Aug.2021, doi:10.1109 / TCSII.2021.3068283. Summary of the Invention

[0022] The purpose of this invention is to overcome the aforementioned deficiencies in the prior art, and to address the complexity of the coordination between the temperature sensing front-end circuit, readout circuit, and temperature sensing scheme in current temperature sensor circuit designs. It provides a temperature sensor sensing circuit architecture based on duty cycle modulation and its temperature measurement method. This invention proposes a novel temperature sensing scheme that eliminates the need for additional circuitry to generate a temperature-proportional voltage or current signal. Instead, it utilizes the time difference between the high and low signals output by the duty cycle of the readout circuit to read the temperature information proportional to the temperature. This process converts analog signal generation into digital processing, reducing the complexity of the actual circuit. Furthermore, this invention proposes a temperature sensing front-end circuit and a corresponding readout circuit adapted to the aforementioned temperature sensing scheme. Compared to other temperature measurement schemes, it significantly simplifies the temperature sensing front-end circuit, using only the common temperature sensing front-end portion shared by all schemes.

[0023] The specific technical solution adopted in this invention is as follows:

[0024] In a first aspect, the present invention provides a temperature sensor sensing circuit architecture based on duty cycle modulation, including a first current source, a second current source, a fourth current source, an amplifier, a comparator, a first resistor, a first transistor, a second transistor, a capacitor, and a digital module.

[0025] The inflow terminals of the first, second, and fourth current sources are all externally powered. The outflow terminal of the first current source is connected to the emitter of the first transistor via a line with a first resistor. The outflow terminal of the second current source is connected to the emitter of the second transistor. The outflow terminal of the fourth current source is connected to the upper plate of a capacitor. The collectors and bases of the first and second transistors are both grounded. The negative input terminal A of the amplifier is connected to the line connecting the first current source and the first resistor, and the positive input terminal B is connected to the line connecting the second current source and the second transistor. The positive input terminal of the amplifier is connected to the line with a first resistor. The circuit of the switch is connected to the positive input terminal of the comparator. The emitter H of the first transistor is connected to the negative input terminal of the comparator through a circuit with a second switch. The negative input terminal of the comparator is connected to the upper plate D of the capacitor through a circuit with a third switch. The positive input terminal of the comparator is connected to the upper plate of the capacitor through a circuit with a fourth switch. The upper plate of the capacitor is connected to the lower plate of the capacitor through a circuit with an RST switch. The lower plate of the capacitor is also grounded through a circuit. The output terminal of the comparator is connected to a digital module. The digital module outputs control signals for the switch, including Φ1, Φ2, RST, and duty cycle output.

[0026] Preferably, the first current source, the second current source, and the fourth current source are all PMOS current mirrors; wherein the width-to-length ratio of the first current source is 2u / 10u, the width-to-length ratio of the second current source is 10u / 10u, and the width-to-length ratio of the fourth current source is 2u / 10u.

[0027] Preferably, both the first transistor and the second transistor are composed of two PNP transistors with an area of ​​10u×10u connected in parallel.

[0028] Preferably, the first resistor is a three-terminal Poly resistor with a resistance of 370K ohms.

[0029] Preferably, the amplifier is a folded common-source common-gate amplifier with a gain greater than 90dB at room temperature and a unity-gain bandwidth of 500KHz.

[0030] Preferably, the comparator is composed of two cascaded operational amplifiers and an inverter buffer, with a delay of less than 100 ns.

[0031] Secondly, the present invention provides a temperature measurement method utilizing the temperature sensor sensing circuit architecture based on duty cycle modulation as described in any one of the first aspects, as follows:

[0032] The first current source, the second current source, the amplifier, the first resistor, the first transistor, and the second transistor together constitute the temperature sensing front end, while the fourth current source, the comparator, the capacitor, and the digital module together constitute the readout circuit.

[0033] In the temperature sensing front-end section, a positive and negative feedback current loop is constructed through an amplifier to make the voltages at points A and B the same. Since the current magnitude I2 of the second current source is N times the current magnitude I1 of the first current source, I1 and I2 are used to bias the first and second transistors, generating different voltages V at points H and B respectively. H and V B And there is V B –V H = k*T / q*ln(N), and V A =V B Therefore, there is V A –V H =k*T / q*ln(N); where k is Boltzmann constant, T is Kelvin temperature, and q is charge; the voltage difference between points A and H is proportional to the temperature, therefore, this voltage difference across resistor R1 can produce a current I1 = [k*T / q*ln(N)] / R1 that is proportional to the temperature;

[0034] The readout circuit includes clock phases Φ1 and Φ2 located at the first switch, the third switch, the second switch, and the fourth switch, respectively. The two clock phases alternate during normal operation of the readout circuit. The initial stage of each clock phase includes a very short period of RST being high. During this period, the two ends of the capacitor are shorted to reset the voltage across them to 0.

[0035] When the circuit is in the Φ1 high-level phase, the first and third switches are closed, and the second and fourth switches are open. At this time, the positive input terminal of the comparator is connected to point B and detects the voltage across the second transistor, while the negative input terminal of the comparator is connected to point D and detects the voltage across the capacitor. Since RST resets the voltage across the capacitor, the voltage at point D is V. D Starting from 0, and continuously increasing under the charging of the fourth current source, until V... D Just greater than V B When the comparator output flips from high to low, it enters the Φ2 phase. When the circuit is in the Φ2 high-level phase, the first and third switches are open, and the second and fourth switches are closed. At this time, the negative input terminal of the comparator is connected to point H and detects the voltage across the first transistor, while the positive input terminal is connected to point D and detects the voltage across the capacitor. Since RST resets the voltage across the capacitor, the voltage at point D is V. D Starting from 0, and continuously increasing under the charging of the fourth current source, until V... D Just greater than V H When the comparator output flips from low to high and enters phase Φ1, it completes one cycle of the duty cycle output.

[0036] Ignoring the brief RST duration, the high-level potential duration t1 and low-level potential duration t2 of the duty cycle output within one cycle are measured respectively. The duty cycle Duty_cycle is calculated according to the formula Duty_cycle=t1 / (t1+t2). Then, the temperature T is calculated according to the functional relationship T=k / (Duty_cycle-b)+a; where k, b, and a are all fixed coefficients obtained through calibration fitting.

[0037] Preferably, the high-level potential duration t1 and the low-level potential duration t2 are obtained by measuring using an FPGA or a logic analyzer.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] 1. In existing technologies, readout circuits calculate the ratio of two voltage / current signals with temperature information (one proportional to temperature and the other inversely proportional to temperature) to obtain readings. This means that in actual circuits, both a voltage / current signal proportional to temperature and an inversely proportional voltage / current signal must be generated simultaneously. However, in the temperature measurement method of this invention, two signals that are inversely proportional to temperature (but not exactly the same) are sent to the readout circuit. The readout circuit outputs the respective proportions of these two signals. Information directly related to temperature is obtained by subtracting the two signals output by the readout circuit. This eliminates the need to generate a voltage / current signal proportional to temperature in the actual circuit, greatly reducing circuit complexity.

[0040] 2. In existing technologies, using a DTΔΣADC as the readout circuit requires complex timing design. Furthermore, the large number of ADC modules significantly increases design complexity, power consumption, and area. This invention employs a duty cycle modulation output readout scheme, which requires only a comparator, a capacitor, a current source, and simple digital logic. While sacrificing some accuracy, it greatly reduces circuit complexity.

[0041] 3. In existing technologies, current-based readout requires an additional amplifier to convert the voltage signal into a current signal. Since amplifiers are energy-intensive circuit components, this increases circuit power consumption and area. This invention uses voltage-based readout and does not require the readout voltage node to have current output capability, meaning it does not significantly affect the preceding circuit (temperature sensing front-end). This reduces the driving requirements of the preceding circuit and also saves the need for an amplifier.

[0042] 4. In existing technologies, resistors are used to generate voltage / current signals with temperature information. However, in standard CMOS processes, the resistance value of resistors varies unevenly with temperature and is affected by manufacturing process deviations. This greatly limits the accuracy of the resistors, ultimately leading to reduced temperature measurement accuracy. This invention uses a newly proposed temperature sensing scheme that directly samples the voltage across a transistor (equivalent to a diode) connected by a diode. This eliminates the need for additional resistors to generate voltage / current signals with temperature information, reducing the use of resistors and mitigating their impact on temperature measurement accuracy. Attached Figure Description

[0043] Figure 1 The temperature sensor used in the existing technology is a DTΔΣADC as the readout circuit.

[0044] Figure 2 This is a temperature sensor based on current detection and duty cycle readout in the prior art;

[0045] Figure 3 This is a temperature sensor based on voltage detection and duty cycle readout in the prior art;

[0046] Figure 4 This invention presents a temperature sensor based on duty cycle readout.

[0047] Figure 5 This is a timing diagram of the key control signals and key voltage nodes in the temperature sensor proposed in this invention;

[0048] Figure 6 This is a graph showing the functional relationship between temperature T and duty cycle reading after using the sensing and temperature control scheme proposed in this invention. Detailed Implementation

[0049] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. Technical features in the various embodiments of the present invention can be combined accordingly without mutual conflict.

[0050] In the description of this invention, it should be understood that when an element is considered to be "connected" to another element, it can be a direct connection to the other element or an indirect connection, i.e., there is an intermediate element. Conversely, when an element is said to be "directly" connected to another element, there is no intermediate element.

[0051] In the description of this invention, it should be understood that the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features.

[0052] To better illustrate the improvements of the technical solution of this invention, the prior art will be briefly described first.

[0053] Figure 1 A general temperature sensor architecture [1] is shown, which uses a DTΔΣADC for readout, including a current source, amplifier, resistor, diode-connected transistor and DTΔΣADC. The specific connection method is as follows:

[0054] First, a circuit is formed by diode-connected transistors D1 and D2, current sources I1 and I2, resistor R1, and amplifier. The upper end of R1, point A, is connected to the output of current source I1 and the negative input of the amplifier. The lower end of R1 is connected to the positive input (emitter) of diode-connected transistor D1. The positive input of the amplifier, point B, is connected to the positive input of diode-connected transistor D2 and the output of current source I2. The output of the amplifier is connected to the grid of the current mirror (not shown in the diagram). The output points C and D of current mirrors I3 and I4 are connected to the positive inputs of diode-connected transistors D3 and D4, respectively. The input of the DTΔΣADC is the voltage at points C and D, and the output is a bit stream used for temperature measurement.

[0055] Figure 2 It is a duty cycle modulated output temperature sensor [2], which includes a current source, amplifier, resistor, diode-connected transistor, capacitor, Schmitt trigger, inverter, capacitor and switch. The specific connection method is as follows:

[0056] First, a circuit is formed by diode-connected transistors D1 and D2, current sources I1 and I2, resistor R1, and amplifier 1. The upper end of R1, point A, is connected to the output of current source I1 and the negative input of amplifier 1. The lower end of R1 is connected to the positive input (emitter) of diode-connected transistor D1. The positive input of amplifier 1, point B, is connected to the positive input of diode-connected transistor D2 and the output of current source I2. The output of amplifier 1 is connected to the gate of the current mirror (not shown in the diagram). The output node of current mirror I3, point C, is connected to the positive input of amplifier 2 and the positive input of D3. The output of amplifier 2 is connected to the gate of NMOS transistor M1. The negative input of amplifier 2, point E, is connected to the source of M1 and the upper ends of resistors R1 and R2. The two ends of switch SW1 are connected to the lower end of resistor R2 and ground; its control signal is the output port of a Schmitt trigger. The output port of current source I4, i.e., point D, is connected to the drain of M1, the upper plate of capacitor Cap, and the input of the Schmitt trigger. The two ends of switch SW2 are connected to the output of current source I5 and point D, respectively, and its control signal is generated by the output of the Schmitt trigger through an inverter.

[0057] Figure 3 It is a new temperature sensor architecture based on duty cycle modulation output [3], which includes a current source, amplifier, resistor, diode-connected transistor, capacitor, comparator, switch and simple digital module. The specific connection method is as follows:

[0058] First, a circuit is formed by diode-connected transistors D1 and D2, current sources I1 and I2, resistor R1, and amplifier. The upper end of R1, point A, is connected to the output of current source I1 and the negative input of the amplifier. The lower end of R1 is connected to the positive input (emitter) of diode-connected transistor D1. The positive input of the amplifier, point B, is connected to the positive input of diode-connected transistor D2 and the output of current source I2. The output of the amplifier is connected to the grid of the current mirror (not shown in the diagram). Switch SW1 is connected to the output of current mirror I3 and the upper end of resistor R2 (point C), with control signal Φ2. Switch SW2 is connected to the output of current mirror I3 and the positive input of diode D3 (point D), with control signal Φ1. Switch SW3 is connected to point C and the negative input of the comparator, with control signal Φ2. Switch SW4 is connected to point D and the positive input of the comparator, respectively, with a control signal of Φ1. Switch SW5 is connected to the output node (point E) of current mirror I4 and the positive input of the comparator, respectively, with a control signal of Φ2. Switch SW6 is connected to the output node (point E) of current mirror I4 and the negative input of the comparator, respectively, with a control signal of Φ1. The upper plate of the capacitor is connected to node E, and the lower plate is grounded. The upper and lower plates of the capacitor are connected by a switch with a control signal of RST. The comparator output is connected to a digital module, which outputs the control signals and output signals of this circuit: Φ1, Φ2, RST, and duty cycle output. The digital module is simple in structure and therefore not shown internally. Its main function is to buffer the comparator output to generate Φ1 and the duty cycle output, invert the comparator output to generate Φ2, and use a double-edge-detection comparator output to generate RST.

[0059] like Figure 4 As shown, this invention provides a temperature sensor sensing circuit architecture based on duty cycle modulation, mainly including a first current source, a second current source, a fourth current source, an amplifier, a comparator, a first resistor, a first transistor, a second transistor, a capacitor, and a digital module. The first current source, the second current source, the amplifier, the first resistor, the first transistor, and the second transistor together constitute the temperature sensing front-end section, while the fourth current source, the comparator, the capacitor, and the digital module together constitute the readout circuit section.

[0060] The connection methods and functions of each component will be explained in detail below.

[0061] In the temperature sensor sensing circuit architecture of this invention, the inflow terminals of the first current source, the second current source, and the fourth current source are all externally powered. The outflow terminal of the first current source is connected to the emitter of the first transistor through a line with a first resistor. The outflow terminal of the second current source is connected to the emitter of the second transistor. The outflow terminal of the fourth current source is connected to the upper plate of the capacitor. The collectors and bases of both the first and second transistors are grounded. The negative input terminal A of the amplifier is connected to the line connecting the first current source and the first resistor, and the positive input terminal B is connected to the line connecting the second current source and the second transistor. The positive input terminal of the amplifier is connected to the positive input terminal of the comparator through a line with a first switch. The emitter H of the first transistor is connected to the negative input terminal of the comparator through a line with a second switch. The negative input terminal of the comparator is connected to the upper plate D of the capacitor through a line with a third switch. The positive input terminal of the comparator is connected to the upper plate of the capacitor through a line with a fourth switch. The upper plate of the capacitor is connected to the lower plate via a circuit equipped with an RST switch, and the lower plate is also grounded via a circuit. The comparator output is connected to a digital module, which outputs control signals for the switches, including Φ1, Φ2, RST, and duty cycle output.

[0062] In embodiments of the present invention, such as Figure 4 As shown, a circuit is formed by diode-connected transistors D1 and D2, first current source I1, second current source I2, first resistor R1, and amplifier. The upper end of R1 (point A) is connected to the output of first current source I1 and the negative input of the amplifier. The lower end of R1 is connected to the positive input (emitter) of diode-connected transistor D1. The positive input (point B) of the amplifier is connected to the positive input of diode-connected transistor D2 and the output of second current source I2. The output of the amplifier is connected to the grid of the current mirror (not shown in the diagram). The two ends of the first switch SW1 are connected to node B of the current mirror and the positive input of the comparator, respectively, with a control signal of Φ1. The two ends of the second switch SW2 are connected to node H and the negative input of the comparator, respectively, with a control signal of Φ2. The two ends of the third switch SW3 are connected to the upper plate (node ​​D) of capacitor Cap and the negative input of the comparator, respectively, with a control signal of Φ1. The fourth switch SW4 is connected to point D and the positive input of the comparator, respectively. Its control signal is Φ2. The upper and lower plates of the capacitor are connected by a switch with a control signal of RST. The comparator's output is connected to a digital module, which outputs the circuit's control signals and output signals: Φ1, Φ2, RST, and the duty cycle output. The digital module is simple in structure and therefore not shown internally. Its main function is to buffer the comparator output to generate Φ1 and the duty cycle output, invert the comparator output to generate Φ2, and use a double-edge-detection comparator output to generate RST.

[0063] In a preferred embodiment of the present invention, the first current source, the second current source, and the fourth current source can all be PMOS current mirrors. Specifically, the width-to-length ratio of the first current source is 2u / 10u, the width-to-length ratio of the second current source is 10u / 10u, and the width-to-length ratio of the fourth current source is 2u / 10u.

[0064] In a preferred embodiment of the present invention, both the first transistor and the second transistor are composed of two PNP transistors with an area of ​​10u×10u connected in parallel.

[0065] In a preferred embodiment of the present invention, the first resistor is a three-terminal Poly resistor with a resistance of 370K ohms.

[0066] As a preferred embodiment of the present invention, the amplifier is a folded common-source common-gate amplifier with a gain greater than 90dB at room temperature and a unity-gain bandwidth of 500KHz.

[0067] As a preferred embodiment of the present invention, the comparator is a continuous-time comparator with hysteresis, which is composed of two cascaded operational amplifiers and an inverter buffer, with a delay of less than 100 ns.

[0068] In such Figure 4 As shown, in the temperature sensor sensing circuit architecture of the present invention, the temperature sensing front-end circuit exists in all reference designs, thus not increasing the design complexity. An amplifier is used in the temperature sensing front-end to construct a positive and negative feedback loop, thereby ensuring that the voltages at points A and B are the same, i.e., V. A =V B Since the magnitude of current I2 is N times that of I1, biasing D1 and D2 with I1 and I2 will produce different voltages V. H and V B And there is V B –V H = k*T / q*ln(N); where k is the Boltzmann constant, T is the Kelvin temperature, and q is the charge. Also, V A =V B Therefore, V A –V H = k*T / q*ln(N), we can see that this voltage difference is proportional to the temperature. When this voltage difference is across resistor R1, a current [k*T / q*ln(N)] / R1, i.e., I1, can be obtained, which is proportional to the temperature. The temperature sensing front-end circuit mainly provides bias current to D1 and D2, and this circuit has a self-holding function, requiring no other auxiliary circuits, thereby generating a voltage V with temperature information. H and V B The voltage that is proportional to temperature is obtained from the difference between these two voltages.

[0069] The subsequent readout circuit contains two clock phases, Φ1 and Φ2, which alternate during normal circuit operation. It should be noted that, as in the prior art [3], the initial stage of each clock phase includes a short period of RST being high. When the RST signal is high, the two ends of capacitor Cap are shorted, thereby resetting the voltage across the capacitor to 0. When the circuit is in phase Φ1 (i.e., Φ1 is high), SW1 and SW3 are closed, and SW2 and SW4 are open. At this time, the positive input terminal of the comparator is connected to point B (i.e., detecting the voltage across D2), and the negative input terminal of the comparator is connected to point D (i.e., detecting the voltage across capacitor Cap). The voltage at point D is V. D Starting from 0 (due to RST resetting Cap) and continuously rising under the charging of the fourth current source I4, until V... D Just greater than V B When the circuit is in phase Φ2 (i.e., Φ2 is low), SW1 and SW3 are open, SW2 and SW4 are closed, the negative input of the comparator is connected to point H (i.e., detecting the voltage across D1), and the positive input of the comparator is connected to point D (i.e., detecting the voltage across capacitor Cap). The voltage at point D is V. D Starting from 0 (due to RST resetting Cap) and continuously rising under the charging of the fourth current source I4, until V... D Just greater than V H When the comparator output flips from low to high, it enters phase Φ1.

[0070] Here, we assume that the duration of the high level in one cycle of the duty cycle output is t1, the duration of the low level is t2, and ignore the brief RST duration. The following equation applies to the charging and discharging of capacitor Cap (also with capacitance Cap) by the fourth current source I4:

[0071] t1*I4=Cap*V B V B =t1*I4 / Cap

[0072] t2*I4=Cap*V H V H =t2*I4 / Cap

[0073] The duty cycle output (the actual duty cycle output is the comparator output after passing through a buffer stage; the waveforms of the two are identical, only slightly different in phase) is calculated as follows:

[0074] Duty_cycle=t1 / (t1+t2)=V B / (V B +V H )

[0075] And: V H / (V B +V H )=t2 / (t1+t2)=1-Duty_cycle

[0076] From this, information with a positive temperature coefficient, namely V, can be calculated. B –V H = (t1-t2)*I4 / Cap. In the above-mentioned existing temperature measurement schemes [1][2][3], the temperature is measured by the ratio of a signal that is directly proportional to the temperature and a signal that is inversely proportional to the temperature, without needing to directly read V. B -V H The exact value. Therefore, an equation based on the same principle can be constructed: X = (V B -V H ) / V B This value can be expressed by the duty cycle of this scheme: X = [Duty_cycle – (1 – Duty_cycle)] / Duty_cycle = (2Duty_cycle – 1) / Duty_cycle. This allows for temperature measurement using a new readout scheme without needing to construct a temperature-proportional voltage signal in the actual circuit. Figure 3 In the temperature measurement scheme shown [3], the circuit reads Y = (R2 / R1) * (V B –V H ) / V D In X here (V) B -V H ) and Y in (R2 / R1)*(V B -V A Both are voltages proportional to temperature and are generated by the same temperature-sensing front end. The V in X... B With V in Y D Both are the voltage across the diodes (formed by connecting transistors with diodes) biased under currents proportional to temperature. Therefore, it can be seen that the principle of calculating temperature and reading the circuit reading in the present invention and the prior art [3] is the same in the end, which also verifies the feasibility of the present invention. However, the present invention transfers the analog circuit implementation to the digital domain for processing, thereby achieving the purpose of simplifying the circuit.

[0077] As a preferred embodiment of the present invention, the timing diagram of key control signals and key voltage nodes in the digital module is as follows: Figure 5 As shown, it includes Φ1, Φ2, RST, and V. D The waveform shows the duty cycle. As can be seen from the diagram, Φ1 and Φ2 are signals with opposite levels; the RST signal is briefly high initially when Φ1 and Φ2 are high, and low otherwise; V Dyes Figure 4 The voltage at node D, V, changes after each RST signal ends. D It begins to rise, and at the end of phase Φ1, it rises to V. B At the end of phase Φ2, it rises to V. H The duty cycle output is almost identical to the Φ1 waveform.

[0078] In actual temperature measurement, based on the aforementioned temperature sensor circuit architecture, the temperature measurement method of this invention needs to ignore the brief RST duration and measure the high-level potential duration t1 and low-level potential duration t2 of the duty cycle output within one cycle. The duty cycle Duty_cycle is calculated according to the formula Duty_cycle=t1 / (t1+t2). Since Duty_cycle has a definite relationship with X mentioned earlier, and X can be related to temperature T, a fixed functional relationship can be established between Duty_cycle and temperature T, i.e., T=k / (Duty_cycle-b)+a, to calculate the temperature T; where k, b, and a are fixed coefficients that can be obtained through calibration fitting. Once the coefficients k, b, and a, and the duty cycle reading at the current temperature (i.e., the value of Duty_cycle) are obtained, the temperature value T can be calculated using this known functional relationship, thus achieving temperature measurement.

[0079] In a preferred embodiment of the present invention, the duration of the high-level potential t1 and the duration of the low-level potential t2 can both be measured by an FPGA or a logic analyzer.

[0080] In one embodiment of the present invention, the functional relationship between temperature T and Duty_cycle obtained during the temperature measurement process is shown in the figure below. Figure 6 As shown in the figure, temperature T has a fixed functional relationship with Duty_cycle, and this functional relationship and the Duty_cycle at the current temperature can be used to measure the temperature.

[0081] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, all technical solutions obtained through equivalent substitution or transformation fall within the protection scope of the present invention.

Claims

1. A temperature sensor sensing circuit architecture based on duty cycle modulation, characterized in that, It includes a first current source, a second current source, a fourth current source, an amplifier, a comparator, a first resistor, a first transistor, a second transistor, a capacitor, and a digital module; The inflow terminals of the first, second, and fourth current sources are all externally powered. The outflow terminal of the first current source is connected to the emitter of the first transistor via a line with a first resistor. The outflow terminal of the second current source is connected to the emitter of the second transistor. The outflow terminal of the fourth current source is connected to the upper plate of a capacitor. The collectors and bases of the first and second transistors are both grounded. The negative input terminal A of the amplifier is connected to the line connecting the first current source and the first resistor, and the positive input terminal B is connected to the line connecting the second current source and the second transistor. The positive input terminal of the amplifier is connected to the line with a first resistor. The circuit of the switch is connected to the positive input terminal of the comparator. The emitter H of the first transistor is connected to the negative input terminal of the comparator through a circuit with a second switch. The negative input terminal of the comparator is connected to the upper plate D of the capacitor through a circuit with a third switch. The positive input terminal of the comparator is connected to the upper plate of the capacitor through a circuit with a fourth switch. The upper plate of the capacitor is connected to the lower plate of the capacitor through a circuit with an RST switch. The lower plate of the capacitor is also grounded through a circuit. The output terminal of the comparator is connected to a digital module. The digital module outputs control signals for the switch, including Φ1, Φ2, RST, and duty cycle output.

2. The temperature sensor sensing circuit architecture based on duty cycle modulation according to claim 1, characterized in that, The first current source, the second current source, and the fourth current source are all PMOS current mirrors; wherein, the width-to-length ratio of the first current source is 2u / 10u, the width-to-length ratio of the second current source is 10u / 10u, and the width-to-length ratio of the fourth current source is 2u / 10u.

3. The temperature sensor sensing circuit architecture based on duty cycle modulation according to claim 1, characterized in that, Both the first transistor and the second transistor are composed of two PNP transistors with an area of ​​10u×10u connected in parallel.

4. The temperature sensor sensing circuit architecture based on duty cycle modulation according to claim 1, characterized in that, The first resistor is a three-terminal Poly resistor with a resistance of 370K ohms.

5. The temperature sensor sensing circuit architecture based on duty cycle modulation according to claim 1, characterized in that, The amplifier is a folded common-source common-gate amplifier with a gain greater than 90dB at room temperature and a unity-gain bandwidth of 500KHz.

6. The temperature sensor sensing circuit architecture based on duty cycle modulation according to claim 1, characterized in that, The comparator is composed of two cascaded operational amplifiers and an inverter buffer, with a delay of less than 100ns.

7. A temperature measurement method using the temperature sensor sensing circuit architecture based on duty cycle modulation as described in any one of claims 1 to 6, characterized in that, Specifically as follows: The first current source, the second current source, the amplifier, the first resistor, the first transistor, and the second transistor together constitute the temperature sensing front end, while the fourth current source, the comparator, the capacitor, and the digital module together constitute the readout circuit. In the temperature sensing front-end section, a positive and negative feedback current loop is constructed through an amplifier to make the voltages at points A and B the same. Since the current magnitude I2 of the second current source is N times the current magnitude I1 of the first current source, I1 and I2 are used to bias the first and second transistors, generating different voltages V at points H and B respectively. H and V B And there is V B –V H = k*T / q*ln(N), and V A =V B Therefore, there is V A –V H =k*T / q*ln(N); where k is Boltzmann constant, T is Kelvin temperature, and q is charge; the voltage difference between points A and H is proportional to the temperature, therefore, this voltage difference across resistor R1 can produce a current I1 = [k*T / q*ln(N)] / R1 that is proportional to the temperature; The readout circuit includes clock phases Φ1 and Φ2 located at the first switch, the third switch, the second switch, and the fourth switch, respectively. The two clock phases alternate during normal operation of the readout circuit. The initial stage of each clock phase includes a very short period of RST being high. During this period, the two ends of the capacitor are shorted to reset the voltage across them to 0. When the circuit is in the Φ1 high-level phase, the first and third switches are closed, and the second and fourth switches are open. At this time, the positive input terminal of the comparator is connected to point B and detects the voltage across the second transistor, while the negative input terminal of the comparator is connected to point D and detects the voltage across the capacitor. Since RST resets the voltage across the capacitor, the voltage at point D is V. D Starting from 0, and continuously increasing under the charging of the fourth current source, until V... D Just greater than V B When the comparator output flips from high to low, it enters the Φ2 phase. When the circuit is in the Φ2 high-level phase, the first and third switches are open, and the second and fourth switches are closed. At this time, the negative input terminal of the comparator is connected to point H and detects the voltage across the first transistor, while the positive input terminal is connected to point D and detects the voltage across the capacitor. Since RST resets the voltage across the capacitor, the voltage at point D is V. D Starting from 0, and continuously increasing under the charging of the fourth current source, until V... D Just greater than V H When the comparator output flips from low to high and enters phase Φ1, it completes one cycle of the duty cycle output. Ignoring the brief RST duration, the high-level potential duration t1 and low-level potential duration t2 of the duty cycle output within one cycle are measured respectively. The duty cycle Duty_cycle is calculated according to the formula Duty_cycle=t1 / (t1+t2). Then, the temperature T is calculated according to the functional relationship T=k / (Duty_cycle-b)+a; where k, b, and a are all fixed coefficients obtained through calibration fitting.

8. The temperature measurement method according to claim 7, characterized in that, The duration of the high-level potential t1 and the duration of the low-level potential t2 are obtained by measuring using an FPGA or a logic analyzer.

Images