Device self-heating effect delay test structure and method
By connecting a temperature-sensitive device and a mode switching switch in series in a ring oscillator, the problem of inaccurate measurement of the self-heating delay of MOS transistors in the prior art is solved. This enables the testing of the self-heating delay and the extraction of model parameters, improves the accuracy of SPICE modeling, and saves oscillator area.
Patent Information
- Application Number
- CN202511232100.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-11-14
AI Technical Summary
Existing test structures are insufficient for measuring the delay caused by the self-heating effect of MOS transistors, and cannot accurately measure and extract the corresponding model parameters, thus affecting the accuracy of SPICE modeling.
A temperature-sensitive device, such as a diode-connected MOS transistor, is connected in series in the delay unit of the ring oscillator, and a mode switching switch is set in its path. By controlling the working mode of the mode switching switch, the device's self-heating effect delay can be tested and model parameters can be extracted.
It enables accurate testing of the device's self-heating effect delay, provides the test data required for SPICE modeling, and saves oscillator area through mode switching control.
Smart Images
Figure CN120948995A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a test structure for the delay of device self-heating effect. This invention also relates to a test method for the delay of device self-heating effect. Background Technology
[0002] As the size of MOS transistors continues to shrink, the impact of the self-heating effect of MOS transistors is becoming increasingly significant. Therefore, when performing SPICE modeling on MOS transistors, the delay caused by the self-heating effect must be considered as a model parameter. Thus, accurately measuring the delay caused by the self-heating effect is becoming increasingly important.
[0003] Currently, common test structures only include ring oscillators, which are insufficient for measuring the delay caused by self-heating effects. Summary of the Invention
[0004] The technical problem to be solved by this invention is to provide a test structure for the delay of device self-heating effect, which can test the delay caused by device self-heating effect and extract the corresponding model parameters of device self-heating effect delay, which is beneficial for SPICE modeling. To this end, this invention also provides a test method for device self-heating effect delay.
[0005] To solve the above-mentioned technical problems, the test structure for the device self-heating effect delay provided by the present invention includes: a ring oscillator.
[0006] The ring oscillator includes n stages of delay units, where n is an odd number.
[0007] Each stage of the delay unit includes a CMOS inverter. At least one stage of the delay unit has a temperature-sensitive device connected in series in the pull-up or pull-down path of the CMOS inverter. The temperature-sensitive device enhances the temperature sensitivity of the ring oscillator and causes the output signal of the ring oscillator to have a delay caused by the self-heating effect of the device.
[0008] A further improvement is that the temperature-sensitive device uses a diode-connected MOS transistor.
[0009] A further improvement is that a mode switching switch connected in parallel with the temperature-sensitive device is also provided in the pull-up or pull-down path of the CMOS inverter in which the temperature-sensitive device is provided.
[0010] The control terminal of the mode switching switch is connected to the mode control signal.
[0011] The ring oscillator has two operating modes: a test mode and a normal operating mode.
[0012] In the test mode, the mode control signal disconnects the mode switching switch, and the ring oscillator is used to test the device's self-heating effect delay.
[0013] Under the normal operating mode, the mode control signal turns on the mode switching switch.
[0014] A further improvement is that the temperature-sensitive device uses a first NMOS transistor connected to a diode.
[0015] The first NMOS transistor is connected in series in the pull-down path of the CMOS inverter of the corresponding delay unit.
[0016] A further improvement is that, in the pull-down path of the CMOS inverter equipped with the first NMOS transistor, the mode switching switch uses a second NMOS transistor.
[0017] A further improvement is that the first-stage delay unit uses a NAND gate, the first input of which is connected to the output of the nth-stage delay unit, and the second input of which is connected to an enable signal.
[0018] A further improvement is that the circuit structures of the second-level delay unit to the nth-level delay unit are the same.
[0019] A further improvement is that the circuit structure of the second-stage delay unit includes:
[0020] The CMOS inverter is formed by connecting a first PMOS transistor and a third NMOS transistor.
[0021] The source of the third NMOS transistor is connected to ground by the first NMOS transistor and the second NMOS transistor connected in parallel with the first NMOS transistor.
[0022] A further improvement is that multiple second PMOS transistors are connected in series between the first PMOS transistor and the power supply voltage, and the gate of each second PMOS transistor is connected to an inverting enable signal.
[0023] A further improvement is that the inverting enable signal is output from a first inverter, and the input of the first inverter is connected to the enable signal.
[0024] A further improvement is that the number of the second PMOS transistors includes three.
[0025] A further improvement is that the output of the nth stage delay unit is also connected to the input of the second delay unit, and the output of the second delay unit serves as the output of the ring oscillator.
[0026] To solve the above-mentioned technical problems, the test method for the device self-heating effect delay provided by the present invention includes the following steps:
[0027] The ring oscillator was tested at different temperatures, and the output signal of the ring oscillator at different temperatures was obtained. The self-heating effect of the temperature-sensitive device caused the delay of the output signal to be different at different temperatures.
[0028] A first relationship curve between the delay of the output signal and the temperature at different temperatures is obtained.
[0029] Further improvements include:
[0030] The self-heating effect parameters of the temperature-sensitive device are extracted based on the first relationship curve.
[0031] The self-heating effect parameters are used as modeling parameters for MOS transistors.
[0032] This invention, based on a conventional ring oscillator, connects a temperature-sensitive device in series in the pull-up or pull-down path of the CMOS inverter in at least part of the delay unit. The self-heating effect of the temperature-sensitive device at different temperatures can affect the clock output of the ring oscillator, thus enabling the testing of the delay caused by the device's self-heating effect. This allows for the extraction of model parameters corresponding to the device's self-heating effect delay, which is beneficial for SPICE modeling.
[0033] Furthermore, the first relationship curve between the delay of the output signal obtained by the ring oscillator of the present invention and the temperature corresponds to the curve of the threshold voltage of the MOS transistor changing with temperature. Therefore, the measurement of the self-heating effect by the ring oscillator of the present invention helps to provide accurate test data in SPICE modeling and facilitates the extraction of relevant self-heating effect parameters.
[0034] In addition, the present invention can also set a mode switching switch in parallel with the temperature-sensitive device. By controlling the mode switching switch, the mode control of the ring oscillator can be realized, so that the ring oscillator can be used to measure the device self-heating effect delay in test mode, and can also be used as a conventional oscillator, thereby maximizing the saving of the oscillator area. Attached Figure Description
[0035] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0036] Figure 1 This is a curve showing the threshold voltage of an existing NMOS transistor as a function of temperature.
[0037] Figure 2 This is a curve showing the threshold voltage of an existing PMOS as a function of temperature.
[0038] Figure 3 This is a circuit block diagram of the test structure for the self-heating effect delay of the device according to an embodiment of the present invention;
[0039] Figure 4 This is a circuit diagram of a delay unit with a temperature-sensitive device in the test structure for delaying the self-heating effect of the device according to an embodiment of the present invention.
[0040] Figure 5 This is a curve showing the self-heating effect delay as a function of temperature, obtained from testing the self-heating effect delay of the device in an embodiment of the present invention. Detailed Implementation
[0041] like Figure 3 The diagram shown is a circuit block diagram of the test structure for the self-heating effect delay of the device according to an embodiment of the present invention; as shown... Figure 4 The diagram shown is a circuit diagram of a delay unit with a temperature-sensitive device 202 in the test structure for the self-heating effect delay of the device according to an embodiment of the present invention; the test structure for the self-heating effect delay of the device according to an embodiment of the present invention includes: a ring oscillator 101.
[0042] The ring oscillator 101 includes n stages of delay units, where n is an odd number. Figure 3 In the diagram, the n-stage delay units are labeled as 1021, 1022, 1203 to 102n.
[0043] like Figure 4 As shown, each stage of the delay unit includes a CMOS inverter 201. A temperature-sensitive device 202 is connected in series in the pull-up or pull-down path of the CMOS inverter 201 in at least one stage of the delay unit. The temperature-sensitive device 202 enhances the temperature sensitivity of the ring oscillator 101 and causes the output signal CLKout of the ring oscillator 101 to have a delay caused by the self-heating effect of the device.
[0044] In this embodiment of the invention, the output terminal of the nth stage delay unit 102n is also connected to the input terminal of the second delay unit 103, and the output terminal of the second delay unit 103 serves as the output terminal of the ring oscillator 101.
[0045] The temperature-sensitive device 202 is a diode-connected MOS transistor.
[0046] like Figure 4 As shown, a mode switching switch 203 connected in parallel with the temperature-sensitive device 202 is also provided in the pull-up or pull-down path of the CMOS inverter 201 in which the temperature-sensitive device 202 is provided.
[0047] The control terminal of the mode switching switch 203 is connected to the mode control signal mode.
[0048] The operating modes of the ring oscillator 101 include a test mode and a normal operating mode.
[0049] In the test mode, the mode control signal mode causes the mode switching switch 203 to turn off, and the ring oscillator 101 is used to test the device self-heating effect delay.
[0050] Under the normal operating mode, the mode control signal mode turns on the mode switching switch 203.
[0051] In embodiments of the present invention, such as Figure 4 As shown, the temperature-sensitive device 202 uses a first NMOS transistor MN1 connected to a diode.
[0052] The first NMOS transistor MN1 is connected in series in the pull-down path of the CMOS inverter 201 of the corresponding delay unit.
[0053] In the pull-down path of the CMOS inverter 201 with the first NMOS transistor MN1, the mode switching switch 203 uses the second NMOS transistor MN2.
[0054] In other embodiments, the temperature-sensitive device 202 may be a PMOS transistor connected to a diode, and the PMOS transistor may be located in the pull-up path; the corresponding mode switching switch 203 may also be a PMOS transistor.
[0055] In this embodiment of the invention, the first-stage delay unit 1021 adopts a NAND gate, the first input terminal of the NAND gate is connected to the output terminal of the nth-stage delay unit 102n, and the second input terminal of the NAND gate is connected to the enable signal enable.
[0056] In this embodiment of the invention, the circuit structures of the second-stage delay unit 1022 to the nth-stage delay unit 102n are the same. Figure 4 The structure shown is the circuit structure diagram of any one of the delay units from the second-level delay unit 1022 to the nth-level delay unit 102n. Figure 4 The following description uses only the second-stage delay unit 1022 as an example: The circuit structure of the second-stage delay unit 1022 includes:
[0057] The CMOS inverter 201 is formed by connecting the first PMOS transistor MP1 and the third NMOS transistor MN3.
[0058] The source of the third NMOS transistor MN3 is connected to ground by the first NMOS transistor MN1 and the second NMOS transistor MN2 connected in parallel with the first NMOS transistor MN1.
[0059] A plurality of second PMOS transistors MP2 are connected in series between the first PMOS transistor MP1 and the power supply voltage VDD, and the gate of each second PMOS transistor MP2 is connected to an inverting enable signal enable. In some embodiments, the number of second PMOS transistors MP2 includes three. The series structure of the second PMOS transistors MP2 is shown in dashed box 204.
[0060] In this embodiment of the invention, the inverting enable signal is output by the first inverter 205, and the input terminal of the first inverter 205 is connected to the enable signal.
[0061] In this embodiment of the invention, a temperature-sensitive device 202 is connected in series in the pull-up or pull-down path of the CMOS inverter 201 of at least a portion of the delay unit, based on a conventional ring oscillator 101. In this way, the self-heating effect formed by the temperature-sensitive device 202 at different temperatures can affect the clock output of the ring oscillator 101, thus enabling the testing of the delay caused by the device's self-heating effect, and thereby enabling the extraction of the model parameters corresponding to the device's self-heating effect delay, which is beneficial for SPICE modeling.
[0062] Furthermore, the first relationship curve between the delay of the output signal CLKout obtained by the ring oscillator 101 in this embodiment of the invention and the temperature corresponds to the curve of the threshold voltage of the MOS transistor changing with temperature. Therefore, the measurement of the self-heating effect by the ring oscillator 101 of this invention helps to provide accurate test data when SPICE modeling and facilitates the extraction of relevant self-heating effect parameters.
[0063] In addition, embodiments of the present invention can also set a mode switching switch 203 connected in parallel with the temperature sensitive device 202. By controlling the mode switching switch 203, the mode control of the ring oscillator 101 can be realized, so that the ring oscillator can be used to measure the device self-heating effect delay in test mode, and can also be used as a conventional oscillator, thereby maximizing the saving of the oscillator area.
[0064] The test method for the device self-heating effect delay test structure of the present invention includes the following steps:
[0065] The ring oscillator 101 was tested at different temperatures, and the output signal CLKout of the ring oscillator 101 at different temperatures was obtained. The self-heating effect of the temperature-sensitive device 202 caused the delay of the output signal CLKout to be different at different temperatures.
[0066] A first relationship curve between the delay of the output signal CLKout at different temperatures and the temperature is obtained.
[0067] Also includes:
[0068] The self-heating effect parameters of the temperature-sensitive device 202 are extracted based on the first relationship curve.
[0069] The self-heating effect parameters are used as modeling parameters for MOS transistors.
[0070] like Figure 5 The figure shows the curve of the self-heating effect delay as a function of temperature, obtained from the test structure of the device self-heating effect delay according to an embodiment of the present invention. This is the first relationship curve. The vertical axis, T-sensor counts, corresponds to the time delay count related to temperature T, i.e., the device self-heating effect delay. The horizontal axis represents temperature. It can be seen that the device self-heating effect delay changes linearly with temperature.
[0071] and Figure 1 By comparing the corresponding threshold voltage curves of NMOS with temperature, it can be seen that... Figure 5 The first relation curve in and Figure 1 The curves are similar, both exhibiting linear changes. Therefore, the embodiments of the present invention... Figure 5 The first relationship curve shown can well reflect the self-heating effect of the device. Similar to the threshold voltage of the device, the self-heating effect parameter corresponding to the self-heating effect delay can also be used as the modeling parameter of the MOS transistor, i.e., the SPICE modeling parameter.
[0072] For MOS transistors, as the temperature increases, their threshold voltage will also change accordingly, and the trend of this change is as follows: Figure 1 , Figure 2 As shown, where Figure 1 This is the threshold voltage of an NMOS transistor as a function of temperature. Figure 2 This is a curve showing the threshold voltage of a PMOS transistor as a function of temperature. The threshold voltage changes of both NMOS and PMOS transistors are related to the self-heating effect of the devices. Based on the linear relationship between the threshold voltage of NMOS and PMOS transistors and temperature, and the correlation between the threshold voltage changes of NMOS and PMOS transistors and the self-heating effect of the devices, the applicant deduced that the signal delay caused by the self-heating effect of MOS transistors should also have a linear relationship with temperature. Based on this deduction, the applicant designed the results of this invention and achieved good technical effects.
[0073] In the ring oscillator of this invention, an NMOS device, namely the first NMOS transistor, is added to enhance its temperature sensitivity by acting as a diode, and an on switch, namely a mode switching switch, is added so that it can be used as a conventional oscillator at the same time. The use of the oscillator structure can save area to the greatest extent.
[0074] Simulation results of the circuit in the embodiment of the present invention reveal the relationship between signal delay caused by self-heating effect and temperature, which generally presents the following characteristics: Figure 5 The linear relationship shown corresponds to the change in its threshold voltage with temperature. Measuring the self-heating effect helps provide accurate test data during SPICE modeling, facilitating the extraction of parameters related to the self-heating effect.
[0075] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A test structure for the delay of device self-heating effect, characterized in that, include: Ring oscillator; The ring oscillator includes n stages of delay units, where n is an odd number; Each stage of the delay unit includes a CMOS inverter. At least one stage of the delay unit has a temperature-sensitive device connected in series in the pull-up or pull-down path of the CMOS inverter. The temperature-sensitive device enhances the temperature sensitivity of the ring oscillator and causes the output signal of the ring oscillator to have a delay caused by the self-heating effect of the device.
2. The test structure for the delay of device self-heating effect as described in claim 1, characterized in that: The temperature-sensitive device is a diode-connected MOS transistor.
3. The test structure for the delay of device self-heating effect as described in claim 2, characterized in that: In the pull-up or pull-down path of the CMOS inverter equipped with the temperature-sensitive device, a mode switching switch connected in parallel with the temperature-sensitive device is also provided. The control terminal of the mode switching switch is connected to the mode control signal; The ring oscillator has two operating modes: a test mode and a normal operating mode. In the test mode, the mode control signal disconnects the mode switching switch, and the ring oscillator is used to test the device's self-heating effect delay. Under the normal operating mode, the mode control signal turns on the mode switching switch.
4. The test structure for the delay of device self-heating effect as described in claim 3, characterized in that: The temperature-sensitive device is a first NMOS transistor connected to a diode; The first NMOS transistor is connected in series in the pull-down path of the CMOS inverter of the corresponding delay unit.
5. The test structure for the delay of device self-heating effect as described in claim 4, characterized in that: In the pull-down path of the CMOS inverter equipped with the first NMOS transistor, the mode switching switch uses a second NMOS transistor.
6. The test structure for the delay of device self-heating effect as described in claim 5, characterized in that: The first-stage delay unit uses a NAND gate. The first input of the NAND gate is connected to the output of the nth-stage delay unit, and the second input of the NAND gate is connected to an enable signal.
7. The test structure for the delay of device self-heating effect as described in claim 6, characterized in that: The circuit structures of the second-level delay unit to the nth-level delay unit are the same.
8. The test structure for the delay of device self-heating effect as described in claim 7, characterized in that: The circuit structure of the second-stage delay unit includes: The CMOS inverter is formed by connecting a first PMOS transistor and a third NMOS transistor; The source of the third NMOS transistor is connected to ground by the first NMOS transistor and the second NMOS transistor connected in parallel with the first NMOS transistor.
9. The test structure for the delay of device self-heating effect as described in claim 8, characterized in that: Multiple second PMOS transistors are connected in series between the first PMOS transistor and the power supply voltage, and the gate of each second PMOS transistor is connected to an inverting enable signal.
10. The test structure for the delay of device self-heating effect as described in claim 9, characterized in that: The inverting enable signal is output by the first inverter, and the input of the first inverter is connected to the enable signal.
11. The test structure for the delay of device self-heating effect as described in claim 9, characterized in that: The number of the second PMOS transistors includes three.
12. The test structure for the delay of device self-heating effect as described in claim 7, characterized in that: The output of the nth stage delay unit is also connected to the input of the second delay unit, and the output of the second delay unit serves as the output of the ring oscillator.
13. A test method using the test structure for the delay of device self-heating effect as described in any one of claims 1 to 12, characterized in that, Including the following steps: The ring oscillator was tested at different temperatures and the output signal of the ring oscillator at different temperatures was obtained. The self-heating effect of the temperature-sensitive device caused the delay of the output signal to be different at different temperatures. A first relationship curve between the delay of the output signal and the temperature at different temperatures is obtained.
14. The test method for the device self-heating effect delay as described in claim 13, characterized in that, Also includes: The self-heating effect parameters of the temperature-sensitive device are extracted based on the first relationship curve; The self-heating effect parameters are used as modeling parameters for MOS transistors.